NEC UPD753208

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD753204, 753206, 753208
4-BIT SINGLE-CHIP MICROCONTROLLERS
The µ PD753208 is one of the 75XL Series 4-bit single-chip microcontrollers and has a data processing
capability comparable to that of an 8-bit microcontroller.
The µ PD753208 has an on-chip LCD controller/driver and is based on the µ PD75308B of the 75X Series.
However, the µ PD75308B is supplied in an 80-pin package, whereas the µ PD753208 is supplied in a 48pin package (375 mils, 0.65-mm pitch) and therefore is suitable for small-scale application systems. In
addition, the µ PD753208 features expanded CPU functions and performs high-speed operations at a low
voltage of 1.8 V.
Detailed information about functions can be found in the following user’s manual. Be sure to read it
before designing. µ PD753208 User’s Manual: U10158E
Features
• Low-voltage operation: VDD = 1.8 to 5.5 V
• Variable instruction execution time for high-speed
– Can be driven by two 1.5-V batteries
operation and power saving operation
– 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation)
• Internal memory
– 0.67, 1.33, 2.67, 10.7 µ s (@ 6.0-MHz operation)
– Program memory (ROM):
4096 × 8 bits ( µ PD753204)
• Internal programmable LCD controller/driver
6144 × 8 bits ( µ PD753206)
• Small package:
8192 × 8 bits ( µ PD753208)
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
• One-time PROM version: µ PD75P3216
– Data memory (RAM):
512 × 4 bits
Applications
Remote controllers, Cameras, Sphygnomamometers, Compact-disc radio cassette player compo systems,
gas meters, etc.
Ordering Information
Part number
Package
ROM (× 8 bits)
µ PD753204GT-×××
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
4096
µ PD753206GT-×××
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
6144
µ PD753208GT-×××
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
8192
Remark ××× indicates ROM code suffix.
Unless otherwise specified, references in this data sheet to the µ PD753208 mean the
µ PD753204 and the µ PD753206.
The information in this document is subject to change without notice.
Document No. U10166EJ2V0DS00 (2nd edition)
Date Published March 1997 N
Printed in Japan
The mark
shows major revised points.
©
1996
µ PD753204, 753206, 753208
Function Outline
Parameter
Function
• 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation with system clock)
• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation with system clock)
Instruction execution time
Internal memory
ROM
4096 × 8 bits ( µPD753204)
6144 × 8 bits ( µPD753206)
8192 × 8 bits ( µPD753208)
RAM
512 × 4 bits
General-purpose register
• 4-bit operation: 8 × 4 banks
• 8-bit operation: 4 × 4 banks
Input/
output
port
6
Connecting on-chip pull-up resistors can be specified by software: 5
20
Connecting on-chip pull-up resistors can be specified by software: 20
Also used for segment pins: 8
CMOS input
CMOS input/output
N-ch open-drain
input/output
Total
LCD controller/driver
4
On-chip pull-up resistors can be specified by mask option
13-V withstand voltage
30
• Segment selection:
• Display mode selection:
4/8/12 segments (can be changed to CMOS input/
output port in 4-time units; max. 8)
Static
1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)
• On-chip split resistor for LCD drive can be specified by mask option
2
Timer
5 channels
• 8-bit timer/event counter: 1 channel
• 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier
generator, and timer with gate)
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
• SBI mode
Bit sequential buffer (BSB)
16 bits
Clock output (PCL)
• Φ, 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock)
• Φ, 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock)
Buzzer output (BUZ)
• 2, 4, 32 kHz (@ 4.19-MHz operation with system clock)
• 2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock)
Vectored interrupts
External: 2, Internal: 5
Test input
External: 1, Internal: 1
System clock oscillator
Ceramic or crystal oscillator for system clock oscillation
Standby function
STOP/HALT mode
Power supply voltage
VDD = 1.8 to 5.5 V
Package
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µPD753204, 753206, 753208
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) .................................................................................................... 5
2. BLOCK DIAGRAM ................................................................................................................................ 6
3. PIN FUNCTIONS .................................................................................................................................... 7
3.1 Port Pins ......................................................................................................................................7
3.2 Non-Port Pins .............................................................................................................................. 9
3.3 Pin Input/Output Circuits ......................................................................................................... 11
3.4 Recommended Connections for Unused Pins ....................................................................... 13
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 14
4.1 Difference Between Mk I and Mk II Modes .............................................................................. 14
4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 15
5. MEMORY CONFIGURATION ............................................................................................................. 16
6. PERIPHERAL HARDWARE FUNCTION ........................................................................................... 21
6.1 Digital I/O Port ........................................................................................................................... 21
6.2 Clock Generator ........................................................................................................................ 22
6.3 Clock Output Circuit ................................................................................................................. 23
6.4 Basic Interval Timer/Watchdog Timer ..................................................................................... 24
6.5 Watch Timer .............................................................................................................................. 25
6.6 Timer/Event Counter ................................................................................................................. 26
6.7 Serial Interface .......................................................................................................................... 30
6.8 LCD Controller/Driver ............................................................................................................... 32
6.9 Bit Sequential Buffer ................................................................................................................ 34
7. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 35
8. STANDBY FUNCTION ........................................................................................................................ 37
9. RESET FUNCTION ............................................................................................................................. 38
10. MASK OPTION ................................................................................................................................... 41
11. INSTRUCTION SET ............................................................................................................................ 42
12. ELECTRICAL SPECIFICATIONS ....................................................................................................... 56
13. CHARACTERISTIC CURVES (REFERENCE VALUES) ................................................................... 68
14. PACKAGE DRAWINGS ..................................................................................................................... 70
15. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 71
3
µ PD753204, 753206, 753208
APPENDIX A
µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST ............................................. 72
APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 74
APPENDIX C RELATED DOCUMENTS ................................................................................................ 77
4
µPD753204, 753206, 753208
1. PIN CONFIGURATION (TOP VIEW)
• 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µ PD753204GT-×××, µ PD753206GT-×××,
µ PD753208GT-×××
COM0
COM1
COM2
COM3
BIAS
VLC0
VLC1
VLC2
P30/LCDCL
P31/SYNC
P32
P33
VSS
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3
VDD
X1
X2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P10/INT0
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
RESET
IC Note
Note Connect IC (Internally Connected) pin directly to VDD.
Pin Identification
P00 to P03
P10, P13
P20 to P23
P30 to P33
P50 to P53
P60 to P63
P80 to P83
P90 to P93
KR0 to KR3
COM0 to COM3
SCK
SI
SO
SB0, SB1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Port0
Port1
Port2
Port3
Port5
Port6
Port8
Port9
Key Return 0 to 3
Common Output 0 to 3
Serial Clock
Serial Input
Serial Output
Serial Data Bus 0, 1
S12 to S23
:
V LC0 to VLC2
:
BIAS
:
LCDCL
:
SYNC
:
TI0
:
PTO0 to PTO2 :
BUZ
:
PCL
:
INT0, INT4
:
X1, X2
:
RESET
:
IC
:
V DD
:
V SS
:
Segment Output 12 to 23
LCD Power Supply 0 to 2
LCD Power Supply Bias Control
LCD Clock
LCD Synchronization
Timer Input 0
Programmable Timer Output 0 to 2
Buzzer Clock
Programmable Clock
External Vectored Interrupt 0, 4
System Clock Oscillation 1, 2
Reset
Internally Connected
Positive Power Supply
Ground
5
µ PD753204, 753206, 753208
2. BLOCK DIAGRAM
WATCH
TIMER
BUZ/P23
INTW
fLCD
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
INTBT
TI0/P13
CY
ALU
TOUT
PTO2/PCL/P22
GENERAL REG.
DECODE
AND
CONTROL
PROGRAM
Note
MEMORY
(ROM)
PORT2
4
P20 to P23
PORT3
4
P30 to P33
PORT5
4
P50 to P53
PORT6
4
P60 to P63
PORT8
4
P80 to P83
PORT9
4
P90 to P93
4
S12 to S15
4
S16/P93 to
S19/P90
4
S20/P83 to
S23/P80
4
COM0 to COM3
LCD
CONTROLLER/
DRIVER
INTCSI TOUT
INT4/P00
INTERRUPT
CONTROL
4
BIT SEQ
BUFFER (16)
fX/2N
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
PCL/PTO2/P22
Note The ROM capacity depends on the product.
6
P10,P13
CLOCKED
SERIAL
INTERFACE
INT0/P10
KR0/P60 to
KR3/P63
2
DATA
MEMORY
(RAM)
512 × 4 BITS
INTT2
SI/SB1/P03
SO/SB0/P02
SCK/P01
PORT1
BANK
INTT1
PTO1/P21
P00 to P03
SBS
INTT0 TOUT
8-BIT
TIMER
CASCADED
COUNTER #1 16-BIT
TIMER
8-BIT
COUNTER
TIMER
COUNTER #2
4
SP (8)
PROGRAM
COUNTER
8-BIT
TIMER/EVENT
COUNTER #0
TPO0/P20
PORT0
CPU CLOCK
Φ
SYSTEM
CLOCK
GENERATOR
X1 X2
fLCD
STANDBY
CONTROL
IC
VDD VSS RESET
VLC0
VLC1
VLC2
BIAS
LCDCL/P30
SYNC/P31
µPD753204, 753206, 753208
3. PIN FUNCTION
3.1 Port Pins (1/2)
Input/Output
Alternate
Function
P00
Input
INT4
P01
Input/Output
SCK
P02
Input/Output
SO/SB0
(F)-B
P03
Input/Output
SI/SB1
(M)-C
P10
Input
INT0
Pin Name
P13
TI0
P20
Input/Output
PTO0
P21
PTO1
P22
PCL/PTO2
P23
BUZ
P30
Input/Output
LCDCL
P31
SYNC
P32
–
P33
–
P50 to
P53 Note 2
Input/Output
–
Function
4-bit input port (PORT0).
For P01 to P03, on-chip pull-up resistors can
be specified by software in 3-bit units.
8-bit
I/O Circuit
After Reset
I/O
TYPE Note 1
No
Input
(B)
(F)-A
Input port in 1 bit unit (PORT1).
On-chip pull-up resistors can be specified by
software in 2-bit units.
Noise elimination circuit can be specified with
P10/INT0.
No
Input
(B)-C
4-bit input/output port (PORT2).
On-chip pull-up resistors can be specified by
software in 4-bit units.
No
Input
E-B
Programmable 4-bit input/output port (PORT3).
This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by software in 4-bit units.
No
Input
E-B
N-ch open-drain 4-bit input/output port (PORT5).
A pull-up resistor can be contained bit-wise
(mask option).
Withstand voltage is 13 V in open-drain mode.
No
High level
(when pullup resistors
are
provided) or
highimpedance
M-D
Notes 1. Characters in parentheses indicate the Schmitt-trigger input.
2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),
low level input leakage current increases when input or bit manipulation instruction is executed.
7
µ PD753204, 753206, 753208
3.1 Port Pins (2/2)
Pin Name
P60
Input/Output
Alternate
Function
Input/Output
KR0
P61
KR1
P62
KR2
P63
KR3
P80
Input/Output
S23
P81
S22
P82
S21
P83
S20
P90
Input/Output
S19
P91
S18
P92
S17
P93
S16
Function
8-bit
I/O Circuit
After Reset
I/O
TYPE Note 1
Programmable 4-bit input/output port (PORT6).
This port can be specified for input/output bitwise.
On-chip pull-up resistors can be specified by
software in 4-bit units.
No
Input
(F)-A
4-bit input/output port (PORT8).
On-chip pull-up resistors can be specified by
software in 4-bit units. Note 2
Yes
Input
H
Input
H
4-bit input/output port (PORT9).
On-chip pull-up resistors can be specified by
software in 4-bit units. Note 2
Notes 1. Characters in parentheses indicate the Schmitt-trigger input.
2. Do not connect on-chip pull-up resistors specified by software when using as segment signal output
pins.
8
µPD753204, 753206, 753208
3.2 Non-Port Pins (1/2)
After Reset
I/O Circuit
TYPE Note 1
Inputs external event pulses to the timer/event
counter.
Input
(B)-C
P20
Timer/event counter output
Input
E-B
PTO1
P21
Timer counter output
PTO2
P22/PCL
Input
(F)-A
Pin Name
TI0
PTO0
Input/Output
Alternate
Function
Input
P13
Output
Function
PCL
P22/PTO2
BUZ
P23
Optional frequency output (for buzzer output
or system clock trimming)
P01
Serial clock input/output
SO/SB0
P02
Serial data output
Serial data bus input/output
(F)-B
SI/SB1
P03
Serial data input
Serial data bus input/output
(M)-C
SCK
Input/Output
Clock output
INT4
Input
P00
Edge detection vectored interrupt input (both
rising edge and falling edge detection)
Input
(B)
INT0
Input
P10
Edge detection vectored
interrupt input (detection
edge can be selected).
Noise elimination circuit
can be specified.
Input
(B)-C
KR0 to KR3
Input/Output
P60 to P63
Input
(F)-A
S12 to S15
Output
–
Segment signal output
Note 2
G-A
S16 to S19
Output
P93 to P90
Segment signal output
Input
H
S20 to S23
Output
P83 to P80
Segment signal output
Input
H
COM0 to COM3
Output
–
Common signal output
Note 2
G-B
–
–
LCD drive power
On-chip split resistor is enable (mask option).
–
–
Output
–
Output for external split resistor disconnect
Note 3
–
Input/Output
P30
Clock output for externally expanded driver
Input
E-B
Input/Output
P31
Clock output for externally expanded driver sync
Input
E-B
VLC0 to V LC2
BIAS
LCDCL Note 4
SYNC
Note 4
With clock elimination
circuit/asynchronous
selectable
Falling edge detection testable input
Notes 1. Characters in parentheses indicate the Schmitt trigger input.
2. Each display output selects the following VLCX as input source.
S12 to S15: VLC1, COM0 to COM2: V LC2, COM3: VLC0.
3. When a split resistor is contained ....... Low level
When no split resistor is contained ...... High-impedance
4. These pins are provided for future system expansion.
At present, these pins are used only as pins P30 and P31.
9
µ PD753204, 753206, 753208
3.2 Non-Port Pins (2/2)
Input/Output
Alternate
Function
After Reset
I/O Circuit
TYPE Note 1
X1
Input
–
Crystal/ceramic connection pin for the system
clock oscillator. When inputting the external
clock, input the external clock to pin X1, and
the reverse phase of the external clock to pin
X2.
–
–
X2
–
Input
–
System reset input (low-level active)
–
(B)
IC
–
–
Internally connected. Connect directly to V DD.
–
–
V DD
–
–
Positive power supply
–
–
V SS
–
–
Ground potential
–
–
Pin Name
RESET
Function
Note Characters in parentheses indicate the Schmitt-trigger input.
10
µPD753204, 753206, 753208
3.3 Pin Input/Output Circuits
The µPD753208 pin input/output circuits are shown schematically.
(1/2)
TYPE A
TYPE D
VDD
VDD
data
P-ch
OUT
P-ch
IN
N-ch
output
disable
N-ch
CMOS specification input buffer.
Push-pull output that can be placed in output
high-impedance (both P-ch, N-ch off).
TYPE E-B
TYPE B
VDD
P.U.R.
P.U.R.
enable
IN
P-ch
data
Type D
IN/OUT
output
disable
Type A
Schmitt trigger input having hysteresis characteristic.
P.U.R. : Pull-Up Resistor
TYPE F-A
TYPE B-C
VDD
VDD
P.U.R.
P.U.R.
enable
P.U.R.
P-ch
P.U.R.
enable
P-ch
data
output
disable
IN/OUT
Type D
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
11
µ PD753204, 753206, 753208
(2/2)
TYPE F-B
TYPE H
VDD
P.U.R
P.U.R
enable
P-ch
output
disable
(P)
SEG
data
VDD
IN/OUT
P-ch
N-ch
TYPE G-A
P-ch
IN/OUT
data
output
disable
data
N-ch
output
disable
output
disable
(N)
TYPE E-B
P.U.R : Pull-Up Resistor
TYPE M-C
TYPE G-A
VDD
VLC0
P-ch
N-ch
P.U.R
P-ch
N-ch
VLC1
P.U.R.
enable
P-ch
P-ch
IN/OUT
N-ch
data
N-ch
OUT
SEG
data
VLC2
output
disable
N-ch
P-ch
N-ch
N-ch
P.U.R : Pull-Up Resistor
TYPE M-D
TYPE G-B
VDD
P-ch
N-ch
VLC0
P.U.R.
(Mask Option)
IN/OUT
N-ch
(+13-V
withstand)
data
VLC1
P-ch
output
disable
N-ch
OUT
input
instruction
VDD
P-ch
Note
P.U.R.
COM
data
N-ch
P-ch
N-ch
VLC2
N-ch
12
P-ch
Voltage
control
circuit
P.U.R. : Pull-Up Resistor
Note Pull-up resistor that only operates upon the execution
of an input instruction when the pull-up resistor is not
connected via the mask option (it is available during
low-voltage).
µPD753204, 753206, 753208
3.4 Recommended Connections for Unused Pins
Table 3-1. List of Recommended Connections for Unused Pins
Pin
Recommended Connection
P00/INT4
Connect to VSS or VDD
P01/SCK
Connect individually to VSS or VDD via a resistor
P02/SO/SB0
P03/SI/SB1
Connect to VSS
P10/INT0
Connect to VSS or VDD
P13/TI0
P20/PTO0
Input state: Connect individually to V SS or V DD via a resistor
P21/PTO1
Output state: No connection
P22/PCL/PTO2
P23/BUZ
P30/LCDCL
P31/SYNC
P32
P33
P50 to P53
Input state
: Connect to VSS
Output state : Connect to VSS (Do not connect pull-up
resistor in the mask option)
P60/KR0 to P63/KR3
Input state
: Connect individually to VSS or VDD via a
resistor
Output state : No connection
S0 to S15
No connection
COM0 to COM3
S16/P93 to S19/P90
Input state: Connect individually to V SS or V DD via a resistor
S20/P83 to S23/P80
Output state: No connection
VLC0 to VLC2
Connect to VSS
BIAS
Only if all of VLC0 to V LC2 are unused, connect to V SS.
In other cases, no connection.
IC
Connect to VDD directly
13
µ PD753204, 753206, 753208
4 SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Difference Between Mk I and Mk II Modes
The CPU of the µPD753208 has the following two modes: Mk I and Mk II, either of which can be selected.
The mode can be switched by bit 3 of the Stack Bank Select register (SBS).
• Mk I mode:
Upward compatible with the µ PD75308B. Can be used in the 75XL CPU with a ROM
capacity of up to 16 Kbytes.
• Mk II mode:
Incompatible with µ PD75308B. Can be used in all the 75XL CPU including those products
whose ROM capacity is more than 16 Kbytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I mode
Caution
Mk II mode
Number of stack bytes
for subroutine instructions
2 bytes
3 bytes
BRA ! addr1 instruction
CALLA ! addr1 instruction
Not available
Available
CALL ! addr instruction
3 machine cycles
4 machine cycles
CALLF ! faddr instruction
2 machine cycles
3 machine cycles
The MkII mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.
Software compatibility with products whose program memory exceeds 16 Kbytes can be raised
by using this mode.
When the MkII mode is selected, the number of stack bytes increases by one byte per stack
during subroutine call instruction execution compared with the MkI mode. When the !faddr
instruction is used, the length of each machine cycle increases by 1 machine cycle. Therefore,
if RAM efficiency or processing speed is emphasized over software compatibility, use of the MkI
mode is recommended.
14
µPD753204, 753206, 753208
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be
initialized to 100×B Note at the beginning of a program. When using the Mk II mode, it must be initialized to 000×B Note.
Note The desired numbers must be set in the × positions.
Figure 4-1. Stack Bank Select Register Format
Address
3
F84H
SBS3
2
1
SBS2 SBS1
0
Symbol
SBS0
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
Other than
above
0
Setting prohibited
0 must be set in the bit 2 position.
Mode switching specification
Caution
0
Mk II mode
1
Mk I mode
Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode.
When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode.
15
µ PD753204, 753206, 753208
5. MEMORY CONFIGURATION
• Program Memory (ROM)
.... 4096 × 8 bits (µ PD753204)
.... 6144 × 8 bits (µ PD753206)
.... 8192 × 8 bits (µ PD753208)
– Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET
signal is generated are written. Reset and start are possible at an arbitrary address.
– Addresses 0002H to 000DH
Vector table wherein the program start address and values set for the RBE and MBE by the vectored
interrupts are written. Interrupt execution can be started at an arbitrary address.
– Addresses 0020H to 007FH
Table area referenced by the GETI instruction Note.
Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the program steps.
• Data Memory (RAM)
– Data area ...
512 words × 4 bits (000H to 1FFH)
– Peripheral hardware area ... 128 words × 4 bits (F80H to FFFH)
16
µPD753204, 753206, 753208
Figure 5-1. Program Memory Map (1/3)
(a) µ PD753204
Address
7
6
0 0 0 H MBE RBE
0 0 2 H MBE RBE
0 0 4 H MBE RBE
5
4
0
0
0
0
0
0
0
Internal reset start address
(high-order 4 bits)
Internal reset start address
(low-order 8 bits)
INTBT/INT4
start address
(high-order 4 bits)
INTBT/INT4
start address
(low-order 8 bits)
INT0
start address
(high-order 4 bits)
INT0
start address
(low-order 8 bits)
INTCSI
start address
(high-order 4 bits)
INTCSI
start address
(low-order 8 bits)
INTT0
start address
(high-order 4 bits)
INTT0
start address
(low-order 8 bits)
BR $addr instruction
relative branch address
INTT1/INTT2
start address
(high-order 4 bits)
–15 to –1,
+2 to +16
INTT1/INTT2
start address
(low-order 8 bits)
006H
0 0 8 H MBE RBE
0 0 A H MBE RBE
0 0 C H MBE RBE
0
0
0
0
0
0
CALLF
! faddr
instruction
entry
address
Branch address of
BR BCXA, BR BCDE,
BR !addr, BRA !addr1Note or
CALLA !addr1Note
instructions
CALL !addr instruction
subroutine entry address
BRCB
! caddr instruction
branch address
020H
GETI instruction reference table
07FH
080H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
7FFH
800H
FFFH
Note Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
17
µ PD753204, 753206, 753208
Figure 5-1. Program Memory Map (2/3)
(b) µ PD753206
Address
7
6
0 0 0 0 H MBE RBE
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
5
0
0
0
0
Internal reset start address
(high-order 5 bits)
Internal reset start address
(low-order 8 bits)
INTBT/INT4
start address
(high-order 5 bits)
INTBT/INT4
start address
(low-order 8 bits)
INT0
start address
(high-order 5 bits)
INT0
start address
(low-order 8 bits)
INTCSI
start address
(high-order 5 bits)
INTCSI
start address
(low-order 8 bits)
INTT0
start address
(high-order 5 bits)
INTT0
start address
(low-order 8 bits)
INTT1/INTT2
start address
(high-order 5 bits)
INTT1/INTT2
start address
(low-order 8 bits)
0006H
0 0 0 8 H MBE RBE
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
0
0
0
CALLF
! faddr
instruction
entry
address
Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1Note or
CALLA ! addr1Note
instructions
CALL ! addr
instruction
subroutine entry
address
BR $ addr
instruction relative
branch address
–15 to –1,
+2 to +16
BRCB ! caddr
instruction
branch
address
0020H
GETI instruction reference table
007FH
0080H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
07FFH
0800H
0FFFH
1000H
BRCB ! caddr
instruction
branch
address
17FFH
Note Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
18
µPD753204, 753206, 753208
Figure 5-1. Program Memory Map (3/3)
(c) µ PD753208
Address
7
6
0 0 0 0 H MBE RBE
0 0 0 2 H MBE RBE
0 0 0 4 H MBE RBE
5
0
0
0
0
Internal reset start address
(high-order 5 bits)
Internal reset start address
(low-order 8 bits)
INTBT/INT4
start address
(high-order 5 bits)
INTBT/INT4
start address
(low-order 8 bits)
INT0
start address
(high-order 5 bits)
INT0
start address
(low-order 8 bits)
INTCSI
start address
(high-order 5 bits)
INTCSI
start address
(low-order 8 bits)
INTT0
start address
(high-order 5 bits)
INTT0
start address
(low-order 8 bits)
INTT1/INTT2
start address
(high-order 5 bits)
INTT1/INTT2
start address
(low-order 8 bits)
0006H
0 0 0 8 H MBE RBE
0 0 0 A H MBE RBE
0 0 0 C H MBE RBE
0
0
0
CALLF
! faddr
instruction
entry
address
Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1Note or
CALLA ! addr1Note
instructions
CALL ! addr
instruction
subroutine entry
address
BR $ addr
instruction relative
branch address
–15 to –1,
+2 to +16
BRCB ! caddr
instruction
branch
address
0020H
GETI instruction reference table
007FH
0080H
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
07FFH
0800H
0FFFH
1000H
BRCB ! caddr
instruction
branch
address
1FFFH
Note Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
19
µ PD753204, 753206, 753208
Figure 5-2. Data Memory Map
Data memory
000H
General-purpose
register area
Memory bank
(32 × 4)
01FH
020H
0
256 × 4
(224 × 4)
Stack area Note
Data area
static RAM
(512×4)
0FFH
100H
256 × 4
(236 × 4)
1
1EBH
1ECH
Display data
memory area
1F7H
1F8H
1FFH
(12 × 4)
(8 × 4)
Not incorporated
F80H
128 × 4
Peripheral hardware area
FFFH
Note As a stack area, either memory bank 0 or 1 can be selected.
20
15
µPD753204, 753206, 753208
6. PERIPHERAL HARDWARE FUNCTION
6.1 Digital I/O Port
There are three kinds of I/O ports.
•
CMOS input ports (Ports 0, 1)
•
CMOS input/output ports (Ports 2, 3, 6, 8, 9)
: 20
•
N-ch open-drain input/output ports (Port 5)
: 4
Total
: 6
30
Table 6-1. Types and Features of Digital Ports
Port
Function
Operation and features
Remarks
PORT0
4-bit input
The alternate function pins have an output function
with operation mode when using the serial interface
function.
Also used for the INT4, SCK,
SO/SB0, and SI/SB1 pins.
PORT1
1-bit input
2-bit input dedicated port
Also used for the INT0 and
TI0.
PORT2
4-bit I/O
Can be set to input mode or output mode in 4-bit
units.
Also used for the PTO0 to
PTO2, PCL, and BUZ pins.
Can be set to input mode or output mode bit-wise.
Also used for the LCDCL
and SYNC pins.
PORT3
PORT5
4-bit I/O (Nchannel opendrain, 13-V
withstand)
Can be set to input mode or output mode in 4-bit
units. On-chip pull-up resistor can be specified
by mask option bit-wise.
PORT6
4-bit I/O
Can be set to input mode or output mode bit-wise.
Also used for the KR0 to
KR3 pins.
Can be set to input mode
or output mode in 4-bit
units.
Also used for the S20 to
S23 pins.
PORT8
PORT9
Ports 8 and 9 are paired
and data can be input/
output in 8-bit units.
—
Also used for the S16 to
S19 pins.
21
µ PD753204, 753206, 753208
6.2 Clock Generator
The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is
shown in Figure 6-1.
The operation of the clock generator is determined by the Processor Clock Control Register (PCC).
The instruction execution time can also be changed.
• 0.95, 1.91, 3.81, 15.3 µ s (system clock: @ 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µ s (system clock: @ 6.0-MHz operation)
Figure 6-1. Clock Generator Block Diagram
· Basic interval timer (BT)
· Timer/event counter 0
· Timer counter 1, 2
· Watch timer
· LCD controller/driver
· Serial interface
· INT0 noise eliminator
· Clock output circuit









X1
VDD
fX
System clock
oscillator
X2
1/1 to 1/4096
Divider
1/2 1/4 1/16
Oscillation stop
Divider
Selector
1/4



PCC
Φ
· CPU
· INT0 noise eliminator
· Clock output circuit
Internal bus
PCC0
PCC1
HALT F/F
4
HALTNote
STOPNote
PCC2
S
PCC3
R
PCC2,
PCC3
Clear
STOP F/F
Q
Q
Wait release signal from BT
S
RESET Signal
R
Note Instruction execution
22
Standby release signal from
interrupt control circuit
µPD753204, 753206, 753208
Remarks 1. f X = System clock frequency
2. Φ = CPU clock
3. PCC: Processor Clock Control Register
4. One clock cycle (t CY) of the CPU clock is equal to one machine cycle of the instruction.
6.3 Clock Output Circuit
The clock output circuit is provided to output the clock pulses from the PCL pin (also functions as P22 or PTO2)
to the remote control wave outputs and peripheral LSIs.
• Clock Output (PCL) : Φ, 524, 262, 65.5 kHz (system clock: @ 4.19-MHz operation)
Φ, 750, 375, 93.8 kHz (system clock: @ 6.0-MHz operation)
Figure 6-2. Clock Output Circuit Block Diagram
From clock
generator
fX/23
Selector
fX/24
Selector
From timer counter
(channel 2)
Φ
Output buffer
PCL/PTO2/P22
fX/26
PORT2.2
CLOM3
0
CLOM1 CLOM0 CLOM
P22
output latch
Bit 2 of PMGB
Port 2 I/O mode
specification bit
4
Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output when
switching clock output enable/disable.
23
µ PD753204, 753206, 753208
6.4 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions.
• Interval timer operation to generate a reference time interrupt
• Watchdog timer operation to detect program runaway and reset the CPU
• Selects and counts the wait time when the standby mode is released
• Reads the contents of counting
Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram
From clock
generator
Clear
Clear
fX/25
fX/27
MPX
Basic interval timer
(8-bit frequency divider)
Set
fX/29
BT
fX/212
3
Wait release signal
when standby is
released.
BTM3 BTM2 BTM1 BTM0 BTM
SET1Note
4
24
Internal reset
signal
WDTM
SET1Note
8
Internal bus
Note Instruction execution
BT
interrupt
request flag Vectored
interrupt
IRQBT request signal
1
µPD753204, 753206, 753208
6.5 Watch Timer
The µPD753208 has one watch timer channel, whose functions are as follows.
• Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW.
• 0.5 sec interval can be created with the system clock (4.194304 MHz)
• Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the
fast feed mode.
• Outputs a frequency (2.048, 4.096, or 32.768 kHz) to the BUZ pin (P23), usable for buzzer and trimming
of system clock frequencies.
• Clears the frequency divider to make the clock start with zero seconds.
Figure 6-4. Watch Timer Block Diagram
fW
(512 Hz : 1.95 ms)
26
fW (256 Hz : 3.91 ms)
27
From
clock
generator
fX
128
(32.768 kHz)
Selector
fW
(32.768 kHz)
fW
214
Divider
2 Hz
0.5 sec
4 kHz 2 kHz
fW
fW
23
24
fLCD
Selector
INTW
IRQW
set signal
Clear
Selector
Output buffer
P23/BUZ
WM
PORT2.3
Note 2
Note 1
WM7
0
WM5
WM4
WM3
WM2
WM1
WM0
P23
output-latch
PMGB bit 2
Port 2 input/
output mode
8
Internal bus
Notes 1. WM3 is undefined while reading data.
2. Be sure to set WM0 to 0.
Remark The values enclosed in parentheses are applied when fX = 4.194304 MHz.
25
µ PD753204, 753206, 753208
6.6 Timer/Event Counter
The µ PD753208 provides one channel for timer/event counters and two channels for timer counters. Figures
6-5 to 6-7 show the block diagrams. Timer/event counter functions are as follows.
• Programmable interval timer operation
• Square wave output of any frequency to the PTO0 pin (n = 0 to 2).
• Event counter operation (Channel 0 only)
• Divides the frequency of signal input via the TI0 pin to 1-nth of the original signal and outputs the divided
frequency to the PTO0 pin (frequency divider operation).
• Supplies the shift clock to the serial interface circuit.
• Reads the counting status.
The timer/event counter operates in the following four modes as set by the mode register.
Table 6-2. Operation Modes of Timer/Event Counter
Channel
Channel 0 Channel 1
Channel 2
Mode
8-bit timer/event counter mode Note 1
Gate control function
A
N/A
Note 2
A
A
N/A
A
N/A
A
PWM pulse generator mode
N/A
16-bit timer counter mode
N/A
A
N/ANote 2
A
N/A
A
Gate control function
Carrier generator mode
Notes 1. Channel 0 only. 8-bit timer counter mode for channel 1 and channel 2
2. Used for gate control signal generation
Remark A:
N/A:
26
Available
Not available
Caution
SET1
6
From
fX/2
clock
fX/28
generator
fX/210
fX/24
–
Timer operation start
–
TM0
When data is set to TM0, always set bit 1 to 0.
MPX
TM06 TM05 TM04 TM03 TM02
Note Execution of instruction
TI0/P13
Input
buffer
PORT1.3
–
8
Note
8
CP
Clear
Count register (8)
8
Comparator (8)
8
T0
TMOD0
Modulo register (8)
8
Internal bus
Match
TOE0
TOUT0
T0
enable flag
RESET
IRQT0
clear signal
INTT0
IRQT0
set signal
Output buffer
PTO0/P20
PORT2.0
PMGB bit 2
Port 2
input/output
mode
To serial interface
P20
output latch
To timer counter (channel 2)
Reset
TOUT
F/F
Figure 6-5. Timer/Event Counter Block Diagram (channel 0)
µPD753204, 753206, 753208
27
28
SET1
TM1
MPX
Note Execution of instruction
fX/25
fX/26
From clock
fX/28
generator
fX/210
fX/212
8
Match
TOE1
INTT1
IRQT1
set signal
IRQT1 clear signal
RESET
Output buffer
P21/PTO1
PMGB bit 2
Port 2
input/output
mode
PORT2.1
P21
output latch
Timer counter reload signal (channel 2)
Reset
TOUT
F/F
T1
enable flag
Timer counter comparator (channel 2)
(During 16-bit timer counter mode)
Timer counter match signal (channel 2)
(During 16-bit timer counter mode)
Selector
Clear
Count register (8)
8
Comparator (8)
8
T1
TMOD1
Internal bus
Modulo register (8)
Timer operation start
CP
16 bit timer counter mode
Decoder
TM16 TM15 TM14 TM13 TM12 TM11 TM10
Timer counter
(channel 2) output
–
8
Note
Figure 6-6. Timer/Event Counter Block Diagram (channel 1)
µ PD753204, 753206, 753208
fX/2
fX/22
fX/24
fX/26
fX/28
fX/210
MPX
Note Execution of instruction
From clock
generator
TM2
SET1Note
8
Timer operation start
8
Match
TC2
RESET
INTT2
IRQT2
set signal
IRQT2 clear signal
Timer clock
input (channel 1)
Output buffer
P22/PCL/PTO2
PORT2.2 PMGB bit 2
P22
Port 2
output latch input/output
From clock generator
Carrier generator mode
Overflow
Reload
TOE2 REMC NRZB NRZ
8
Selector
Timer counter
match signal (channel 1)
(When carrier generator mode)
Timer counter
clear signal (channel 1)
(During 16-bit timer
counter mode)
Reset
TOUT
F/F
Timer counter
match signal (channel 1)
(During 16-bit timer
counter mode)
Clear
T2
Count register (8)
16-bit timer counter mode
CP
MPX (8)
8
8
Comparator (8)
8
8
TMOD2
Modulo register (8) TGCE
TMOD2H
High-level period setting
modulo register (8)
Timer event counter
TOUT F/F (channel 0)
Decoder
TM26 TM25 TM24 TM23 TM22 TM21 TM20
8
Internal bus
Selector Selector
Figure 6-7. Timer Counter Block Diagram (channel 2)
µPD753204, 753206, 753208
29
µ PD753204, 753206, 753208
6.7 Serial Interface
The µ PD753208 incorporates a clock-synchronous 8-bit serial interface and can be used in the following four
modes.
• Operation stop mode
• 3-wire serial I/O mode
• 2-wire serial I/O mode
• SBI mode (serial bus interface mode)
30
P01/SCK
P02/SO/SB0
P03/SI/SB1
P01
output Iatch
Selector
Selector
CSIM
Bit test
8
8
Serial clock control
circuit
Serial clock counter
Bus release/
command/
acknowledge
detection circuit
Shift register (SIO)
Address comparator
D
INTCSI
control circuit
Q
SO latch
CMDT
SET CLR
RELD
CMDD
ACKD
(8)
(8)
Match signal
RELT
Bit manipulation
Slave address register (SVA) (8)
8
SBIC
fX/23
fX/24
fX/26
TOUT0
(from timer/event counter
(channel 0))
IRQCSI
set signal
INTCSI
Bit test
External SCK
Serial clock
selector
Busy/
acknowledge
output circuit
ACKT
8/4
ACKE
Internal bus
BSYE
Figure 6-8. Serial Interface Block Diagram
µPD753204, 753206, 753208
31
µ PD753204, 753206, 753208
6.8 LCD Controller/Driver
The µ PD753208 incorporates a display controller which generates segment and common signals according
to the display data memory contents and incorporates segment and common drivers which can drive the panel
directly.
The µ PD753208 LCD controller/driver functions are as follows:
• Display data memory is read automatically by DMA operation and segment and common signals are
generated.
• Display mode can be selected from among the following five:
<1>
Static
<2>
1/2 duty (time multiplexing by 2), 1/2 bias
<3>
1/3 duty (time multiplexing by 3), 1/2 bias
<4>
1/3 duty (time multiplexing by 3), 1/3 bias
<5>
1/4 duty (time multiplexing by 4), 1/3 bias
• A frame frequency can be selected from among four in each display mode.
• A maximum of 12 segment signal output pins (S12 to S23) and four common signal output pins (COM0 to
COM3).
• The segment signal output pins (S16 to S23) can be changed to the I/O ports (PORT8 and PORT9).
• Split-resistor can be incorporated to supply LCD drive power. (Mask option)
–
Various bias methods and LCD drive voltages can be applicable.
–
When display is off, current flowing through the split resistor is cut.
• Display data memory not used for display can be used for normal data memory.
32
Port 8
output latch
3 2 1 0
4
Port 8
Input/Output buffer
0 1
2
3
4
8
Port 9
Port mode
output latch register group C
3 2 1 0
0
1
4
Port 9
Input/Output buffer
0 1
2
3
4
Decoder
LCD/port
selection
register
4
1F7H
S23/P80
Segment driver
3 2 1 0
3 2 1 0
1EFH
S16/P93
S15
1ECH
S0
3 2 1 0
3 2 1 0
Segment driver
3 2 1 0 3 2 1 0
3 2 1 0 3 2 1 0
1F0H
4
Internal bus
8
COM3 COM2 COM1 COM0
Common driver
fLCD
Display
control
register
4
VLC1
VLC0
LCD drive
voltage control
VLC2
Timing
controller
Display mode register
Figure 6-9. LCD Controller/Driver Block Diagram
1
0
Port mode
register group A
4
P31/SYNC P30/LCDCL
LCD drive
mode
switching
Port 3
output latch
1 0
4
µPD753204, 753206, 753208
33
µ PD753204, 753206, 753208
6.9 Bit Sequential Buffer ....... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be
easily performed by changing the address specification and bit specification in sequence, therefore it is useful
when processing large data bit-wise.
Figure 6-10. Bit Sequential Buffer Format
Address
Bit
FC3H
3
Symbol
L register
2
1
FC2H
0
3
2
BSB3
L = FH
1
FC1H
0
3
BSB2
L = CH L = BH
2
1
FC0H
0
3
BSB1
L = 8H L = 7H
L = 4H L = 3H
DECS L
2
1
0
BSB0
L = 0H
INCS L
Remarks 1. In pmem.@L addressing, the specified bit moves corresponding to the L register.
2. In pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification.
34
µPD753204, 753206, 753208
7. INTERRUPT FUNCTION AND TEST FUNCTION
There are seven interrupt sources and two test sources in the µ PD753208.
The interrupt control circuit of the µ PD753208 has the following functions.
(1) Interrupt function
• Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the
interrupt enable flag (IE×××) and interrupt master enable flag (IME).
• Can set any interrupt start address.
• Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register
(IPS).
• Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software.
• Release the standby mode. A release interrupt can be selected by the interrupt enable flag.
(2) Test function
• Test request flag (IRQ×××) generation can be checked by software.
• Release the standby mode. The test source to be released can be selected by the test enable flag.
35
36
Note
Selector
Falling edge
detector
IRQT1
IRQT2
IRQW
INTT1
INTT2
INTW
IM2
IRQ2
IRQT0
INTT0
Selector
IRQCSI
IRQ0
IRQ4
IRQBT
INTCSI
Both edge
detector
Edge
detector
Interruput enable flag (IE×××)
Note Noise eliminator (Standby release is disabled when noise eliminator is selected.)
KR3/P63
KR0/P60
INT0/P10
INT4/P00
IM0
IM2
INTBT
4
2
Internal bus
Figure 7-1. Interrupt Control Circuit Block Diagram
VRQn
IST1 IST0
Priority control
circuit
Decoder
IME IPS
Standby release
signal
Vector table
address
generator
µ PD753204, 753206, 753208
µPD753204, 753206, 753208
8. STANDBY FUNCTION
In order to save power dissipation while a program is in standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the µ PD753208.
Table 8-1. Operation Status in Standby Mode
Item
Mode
STOP mode
HALT mode
Set instruction
STOP instruction
HALT instruction
Operation
status
Clock generator
The system clock stops oscillation.
Only the CPU clock Φ halts (oscillation
continues).
Basic interval timer/
Watchdog timer
Operation stops.
Operable only when the system clock
is oscillated. (The IRQBT is set in the
reference interval).
Serial interface
Operable only when an external SCK
input is selected as the serial clock.
Operable
Timer/event counter
Operable only when a signal input to
the TI0 pin is specified as the count
clock.
Operable
Watch timer
Operation stops.
Operable
LCD controller/driver
Operation stops.
Operable
External interrupt
The INT4 is operable.
Only the INT0 is not operated
CPU
Release signal
Note
.
Operation stops.
Interrupt request signal sent from the operable hardware enabled by the
interrupt enable flag or RESET signal input.
Note Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register
(IM0).
37
µ PD753204, 753206, 753208
9. RESET FUNCTION
There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/
watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure
9-1 shows the circuit diagram of the above two inputs.
Figure 9-1. Configuration of Reset Function
RESET
Internal RESET signal
RESET signal sent from the
basic interval timer/watchdog timer
WDTM
Internal bus
Each hardware is initialized by the RESET signal generation as listed in Table 9-1. Figure 9-2 shows the
timing chart of the reset operation.
Figure 9-2. Reset Operation by RESET Signal Generation
Wait Note
RESET
signal
generated
Operation mode or
standby mode
HALT mode
Internal reset operation
Note The following two times can be selected by the mask option.
2 17/fX (21.8 ms: @ 6.0-MHz operation, 31.3 ms: @ 4.19-MHz operation)
2 15/fX (5.46 ms: @ 6.0-MHz operation, 7.81 ms: @ 4.19-MHz operation)
38
Operation mode
µPD753204, 753206, 753208
Table 9-1. Status of Each Device After Reset (1/2)
RESET signal generation
in the standby mode
RESET signal generation
during operation
Sets the low-order 4 bits of
program memory’s address
0000H to PC11 to PC8 and
the contents of address 0001H
to PC7 to PC0.
Sets the low-order 4 bits of
program memory’s address
0000H to PC11 to PC8 and
the contents of address 0001H
to PC7 to PC0.
µ PD753206, Sets the low-order 5 bits of
µ PD753208 program memory's address
0000H to PC12 to PC8 and
the contents of address 0001H
to PC7 to PC0.
Sets the low-order 5 bits of
program memory's address
0000H to PC12 to PC8 and
the contents of address 0001H
to PC7 to PC0.
Hardware
Program counter (PC)
PSW
µ PD753204
Carry flag (CY)
Held
Undefined
Skip flag (SK0-SK2)
0
0
Interrupt status flag (IST0, IST1)
0
0
Sets bit 6 of program memory’s
address 0000H to RBE and bit
7 to MBE.
Sets bit 6 of program memory’s
address 0000H to RBE and bit
7 to MBE.
Undefined
Undefined
1000B
1000B
Data memory (RAM)
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
0, 0
Undefined
Undefined
Bank enable flag (MBE, RBE)
Stack pointer (SP)
Stack bank select register (SBS)
Basic interval
Counter (BT)
timer/watchdog
Mode register (BTM)
0
0
timer
Watchdog timer enable flag (WDTM)
0
0
Timer/event
Counter (T0)
0
0
counter (T0)
Modulo register (TMOD0)
FFH
FFH
0
0
0, 0
0, 0
0
0
FFH
FFH
0
0
0, 0
0, 0
0
0
Mode register (TM0)
TOE0, TOUT F/F
Timer
Counter (T1)
counter (T1)
Modulo register (TMOD1)
Mode register (TM1)
TOE1, TOUT F/F
Timer
Counter (T2)
counter (T2)
Modulo register (TMOD2)
FFH
FFH
High-level period setting modulo
register (TMOD2H)
FFH
FFH
0
0
0, 0
0, 0
0, 0, 0
0, 0, 0
TGCE
0
0
Mode register (WM)
0
0
Mode register (TM2)
TOE2, TOUT F/F
REMC, NRZ, NRZB
Watch timer
39
µ PD753204, 753206, 753208
Table 9-1. Status of Each Device After Reset (2/2)
Serial interface
Hardware
RESET signal generation
in the standby mode
RESET signal generation
during operation
Shift register (SIO)
Held
Undefined
Operation mode register (CSIM)
0
0
SBI control register (SBIC)
0
0
Held
Undefined
Slave address register (SVA)
Clock generator,
Processor clock control register (PCC)
0
0
clock output circuit
Clock output mode register (CLOM)
0
0
LCD controller/
Display mode register (LCDM)
0
0
driver
Display control register (LCDC)
0
0
LCD/port selection register (LPS)
0
0
Reset (0)
Reset (0)
Interrupt
Interrupt request flag (IRQ×××)
function
Interrupt enable flag (IE×××)
0
0
Interrupt priority selection register (IPS)
0
0
INT0, 2 mode registers (IM0, IM2)
0, 0
0, 0
Output buffer
Off
Off
Output latch
Cleared (0)
Cleared (0)
I/O mode registers (PMGA, B, C)
0
0
Pull-up resistor setting register (POGA, B)
0
0
Held
Undefined
Digital port
Bit sequential buffer (BSB0 to BSB3)
40
µPD753204, 753206, 753208
10. MASK OPTION
The µPD753208 has the following mask options.
• P50 to P53 mask options
Selects whether or not to connect an internal pull-up resistor.
<1> Connect pull-up resistor internally bit-wise.
<2> Do not connect pull-up resistor internally.
• VLC0 to VLC2 pins, BIAS pins mask option
Selects whether or not to internally connect LCD-driving split resistors.
<1> Do not connect split resistor internally.
<2> Connect four 10-kΩ (typ.) split resistors simultaneously internally.
<3> Connect four 100-kΩ (typ.) split resistors simultaneously internally.
• Standby function mask option
Selects the wait time with the RESET signal.
<1> 2 17/fx (21.8 ms: When fX = 6.0 MHz, 31.3 ms: When f X = 4.19 MHz)
<2> 2 15/fx (5.46 ms: When fX = 6.0 MHz, 7.81 ms: When f X = 4.19 MHz)
41
µ PD753204, 753206, 753208
11. INSTRUCTION SET
(1) Expression formats and description methods of operands
The operand is described in the operand column of each instruction in accordance with the description
method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER
PACKAGE USERS’ MANUAL—LANGUAGE (EEU-1363)". If there are several elements, one of them
is selected. Capital letters and the + and – symbols are key words and are described as they are.
For immediate data, appropriate numbers and labels are described.
Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described.
However, there are restrictions in the labels that can be described for fmem and pmem. For details, see
the user's manual.
Representation
format
Description method
reg
reg1
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
rp
rp1
rp2
rp'
rp'1
XA,
BC,
BC,
XA,
BC,
rpa
rpa1
HL, HL+, HL–, DE, DL
DE, DL
n4
n8
4-bit immediate data or label
8-bit immediate data or label
mem
bit
8-bit immediate data or label
2-bit immediate data or label
fmem
pmem
FB0H-FBFH, FF0H-FFFH immediate data or label
FC0H-FFFH immediate data or label
addr
addr1
(Only in the
MKII mode)
caddr
faddr
000H-FFFH immediate data or label ( µ PD753204)
0000H-17FFH immediate data or label ( µ PD753206)
0000H-1FFFH immediate data or label ( µPD753208)
000H-FFFH immediate data or label ( µ PD753204)
0000H-17FFH immediate data or label ( µ PD753206)
0000H-1FFFH immediate data or label ( µPD753208)
12-bit immediate data or label
11-bit immediate data or label
taddr
20H-7FH immediate data (where bit 0 = 0) or label
PORTn
IE×××
RBn
MBn
PORT0-PORT3, PORT5, PORT6, PORT8, PORT9
IEBT, IET0-IET2, IE0, IE2, IE4, IECSI, IEW
RB0-RB3
MB0, MB1, MB15
BC,
DE,
DE
BC,
DE,
DE, HL
HL
DE, HL, XA', BC', DE', HL'
HL, XA', BC', DE', HL'
Note
Note mem can be only used for even address in 8-bit data processing.
42
µPD753204, 753206, 753208
(2) Legend in explanation of operation
A
: A register, 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: XA register pair; 8-bit accumulator
BC
: BC register pair
DE
: DE register pair
HL
: HL register pair
XA’
: XA’ expanded register pair
BC’
: BC’ expanded register pair
DE’
: DE’ expanded register pair
HL’
: HL’ expanded register pair
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag, bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn
: Port n (n = 0 to 3, 5, 6, 8, 9)
IME
: Interrupt master enable flag
IPS
: Interrupt priority selection register
IE×××
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Separation between address and bit
(××)
: Contents addressed by ××
××H
: Hexadecimal data
43
µ PD753204, 753206, 753208
(3) Explanation of symbols under addressing area column
*1
MB = MBE•MBS
(MBS = 0, 1, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (000H-07FH)
MB = 15 (F80H-FFFH)
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
*4
MB = 15, fmem = FB0H-FBFH, FF0H-FFFH
*5
MB = 15, pmem = FC0H-FFFH
*6
µ PD753204
addr = 000H-FFFH
µ PD753206
addr = 0000H-17FFH
µ PD753208
addr = 0000H-1FFFH
*7
addr, addr1 = (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
*8
µ PD753204
caddr = 000H-FFFH
µ PD753206
caddr = 0000H-0FFFH(PC12 = 0) or
1000H-17FFH(PC12 = 1)
µ PD753208
caddr = 0000H-0FFFH(PC12 = 0) or
1000H-1FFFH(PC12 = 1)
*9
faddr = 0000H-07FFH
*10
taddr = 0020H-007FH
*11
µ PD753204
addr1 = 000H-FFFH
µ PD753206
addr1 = 0000H-17FFH
µ PD753208
addr1 = 0000H-1FFFH
Data memory addressing
Program memory addressing
Remarks 1. MB indicates memory bank that can be accessed.
2. In *2, MB = 0 independently of how MBE and MBS are set.
3. In *4 and *5, MB = 15 independently of how MBE and MBS are set.
4. *6 to *11 indicate the areas that can be addressed.
(4) Explanation of number of machine cycles column
S denotes the number of machine cycles required by skip operation when a skip instruction is executed.
The value of S varies as follows.
• When no skip is made: S = 0
• When the skipped instruction is a 1- or 2-byte instruction: S = 1
• When the skipped instruction is a 3-byte instruction
Note
: S=2
Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of CPU clock (= t CY); time can be selected from among four types
by setting PCC.
44
µPD753204, 753206, 753208
Instruction
group
Transfer
instruction
Mnemonic
MOV
XCH
Number
of bytes
Number
of machine
cycles
A, #n4
1
1
A ← n4
reg1, #n4
2
2
reg1 ← n4
XA, #n8
2
2
XA ← n8
String effect A
HL, #n8
2
2
HL ← n8
String effect B
rp2, #n8
2
2
rp2 ← n8
A, @HL
1
1
A ← (HL)
*1
A, @HL+
1
2+S
A ← (HL), then L ← L+1
*1
L=0
A, @HL–
1
2+S
A ← (HL), then L ← L–1
*1
L = FH
A, @rpa1
1
1
A ← (rpa1)
*2
XA, @HL
2
2
XA ← (HL)
*1
@HL, A
1
1
(HL) ← A
*1
@HL, XA
2
2
(HL) ← XA
*1
A, mem
2
2
A ← (mem)
*3
XA, mem
2
2
XA ← (mem)
*3
mem, A
2
2
(mem) ← A
*3
mem, XA
2
2
(mem) ← XA
*3
A, reg
2
2
A ← reg
XA, rp'
2
2
XA ← rp'
reg1, A
2
2
reg1 ← A
rp'1, XA
2
2
rp'1 ← XA
A, @HL
1
1
A ↔ (HL)
*1
A, @HL+
1
2+S
A ↔ (HL), then L ← L+1
*1
L=0
A, @HL–
1
2+S
A ↔ (HL), then L ← L–1
*1
L = FH
A, @rpa1
1
1
A ↔ (rpa1)
*2
XA, @HL
2
2
XA ↔ (HL)
*1
A, mem
2
2
A ↔ (mem)
*3
XA, mem
2
2
XA ↔ (mem)
*3
A, reg1
1
1
A ↔ reg1
XA, rp'
2
2
XA ↔ rp'
Operand
Operation
Addressing
area
Skip condition
String effect A
45
µ PD753204, 753206, 753208
Instruction
group
Table
reference
Mnemonic
MOVT
Operand
XA, @PCDE
Number
of bytes
Number
of machine
cycles
1
3
Operation
Addressing
area
Skip condition
µPD753204
XA ← (PC11–8+DE) ROM
●
µPD753206, 753208
XA ← (PC12–8+DE) ROM
●
XA, @PCXA
1
3
µPD753204
XA ← (PC11–8+XA) ROM
●
µPD753206, 753208
XA ← (PC12–8+XA) ROM
●
Bit transfer
Operation
MOV1
ADDS
ADDC
SUBS
SUBC
XA, @BCDE
1
3
XA ← (BCDE)ROM
Note
*6
XA, @BCXA
1
3
XA ← (BCXA)ROM
Note
*6
CY, fmem.bit
2
2
CY ← (fmem.bit)
*4
CY, pmem.@L
2
2
CY ← (pmem 7–2+L3–2.bit(L1–0 ))
*5
CY, @H+mem.bit
2
2
CY ← (H+mem3–0 .bit)
*1
fmem.bit, CY
2
2
(fmem.bit) ← CY
*4
pmem.@L, CY
2
2
(pmem 7–2+L3–2.bit(L 1–0)) ← CY
*5
@H+mem.bit, CY
2
2
(H+mem3–0 .bit) ← CY
*1
A, #n4
1
1+S
A ← A+n4
carry
XA, #n8
2
2+S
XA ← XA+n8
carry
A, @HL
1
1+S
A ← A+(HL)
XA, rp'
2
2+S
XA ← XA+rp'
carry
rp'1, XA
2
2+S
rp'1 ← rp'1+XA
carry
A, @HL
1
1
A, CY ← A+(HL)+CY
XA, rp'
2
2
XA, CY ← XA+rp'+CY
rp'1, XA
2
2
rp'1, CY ← rp'1+XA+CY
A, @HL
1
1+S
A ← A–(HL)
XA, rp'
2
2+S
XA ← XA–rp'
borrow
rp'1, XA
2
2+S
rp'1 ← rp'1–XA
borrow
A, @HL
1
1
A, CY ← A–(HL)–CY
XA, rp'
2
2
XA, CY ← XA–rp'–CY
rp'1, XA
2
2
rp'1, CY ← rp'1–XA–CY
*1
carry
*1
*1
borrow
*1
Note Set "0" to register B if the µ PD753204 is used. Only the low-order one bit of register B will be valid if the
µ PD753206 or 753208 is used.
46
µPD753204, 753206, 753208
Instruction
group
Mnemonic
Operation
AND
OR
XOR
Number
of bytes
Number
of machine
cycles
A, #n4
2
2
A ← A ∧ n4
A, @HL
1
1
A ← A ∧ (HL)
XA, rp'
2
2
XA ← XA ∧ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∧ XA
A, #n4
2
2
A ← A ∨ n4
A, @HL
1
1
A ← A ∨ (HL)
XA, rp'
2
2
XA ← XA ∨ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∨ XA
A, #n4
2
2
A ← A v n4
A, @HL
1
1
A ← A v (HL)
XA, rp'
2
2
XA ← XA v rp'
rp'1, XA
2
2
rp'1 ← rp'1 v XA
Operand
Operation
Addressing
area
Skip condition
*1
*1
*1
Accumulator
manipulation
instructions
RORC
A
1
1
CY ← A0 , A3 ← CY, An–1 ← An
NOT
A
2
2
A←A
Increment
and
Decrement
instructions
INCS
reg
1
1+S
reg ← reg+1
reg=0
rp1
1
1+S
rp1 ← rp1+1
rp1=00H
@HL
2
2+S
(HL) ← (HL)+1
*1
(HL)=0
mem
2
2+S
(mem) ← (mem)+1
*3
(mem)=0
reg
1
1+S
reg ← reg–1
reg=FH
rp'
2
2+S
rp' ← rp'–1
rp'=FFH
reg, #n4
2
2+S
Skip if reg = n4
reg=n4
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2+S
Skip if A = reg
A=reg
XA, rp'
2
2+S
Skip if XA = rp'
XA=rp'
SET1
CY
1
1
CY ← 1
CLR1
CY
1
1
CY ← 0
SKT
CY
1
1+S
NOT1
CY
1
1
DECS
Comparison
instruction
Carry flag
manipulation
instruction
SKE
Skip if CY = 1
CY=1
CY ← CY
47
µ PD753204, 753206, 753208
Instruction
group
Mnemonic
Memory bit
SET1
manipulation
instructions
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
48
Number
of bytes
Number
of machine
cycles
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
pmem.@L
2
2
(pmem 7–2+L 3–2.bit(L1–0)) ← 1
*5
@H+mem.bit
2
2
(H+mem 3–0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
pmem.@L
2
2
(pmem 7–2+L 3–2.bit(L1–0)) ← 0
*5
@H+mem.bit
2
2
(H+mem 3–0.bit) ← 0
*1
mem.bit
2
2+S
Skip if (mem.bit)=1
*3
(mem.bit)=1
fmem.bit
2
2+S
Skip if (fmem.bit)=1
*4
(fmem.bit)=1
pmem.@L
2
2+S
Skip if (pmem 7–2+L3–2.bit(L 1–0))=1
*5
(pmem.@L)=1
@H+mem.bit
2
2+S
Skip if (H+mem3–0 .bit)=1
*1
(@H+mem.bit)=1
mem.bit
2
2+S
Skip if (mem.bit)=0
*3
(mem.bit)=0
fmem.bit
2
2+S
Skip if (fmem.bit)=0
*4
(fmem.bit)=0
pmem.@L
2
2+S
Skip if (pmem 7–2+L3–2.bit(L 1–0))=0
*5
(pmem.@L)=0
@H+mem.bit
2
2+S
Skip if (H+mem3–0 .bit)=0
*1
(@H+mem.bit)=0
fmem.bit
2
2+S
Skip if (fmem.bit)=1 and clear
*4
(fmem.bit)=1
pmem.@L
2
2+S
Skip if (pmem 7–2+L3–2.bit(L 1–0))=1 and clear
*5
(pmem.@L)=1
@H+mem.bit
2
2+S
Skip if (H+mem3–0 .bit)=1 and clear
*1
(@H+mem.bit)=1
CY, fmem.bit
2
2
CY ← CY ∧ (fmem.bit)
*4
CY, pmem.@L
2
2
CY ← CY ∧ (pmem7–2 +L3–2.bit(L1–0))
*5
CY, @H+mem.bit
2
2
CY ← CY ∧ (H+mem3–0.bit)
*1
CY, fmem.bit
2
2
CY ← CY ∨ (fmem.bit)
*4
CY, pmem.@L
2
2
CY ← CY ∨ (pmem7–2 +L3–2.bit(L1–0))
*5
CY, @H+mem.bit
2
2
CY ← CY ∨ (H+mem3–0.bit)
*1
CY, fmem.bit
2
2
CY ← CY v (fmem.bit)
*4
CY, pmem.@L
2
2
CY ← CY v (pmem 7–2+L3–2.bit(L 1–0))
*5
CY, @H+mem.bit
2
2
CY ← CY v (H+mem3–0 .bit)
*1
Operand
Operation
Addressing
area
Skip condition
µPD753204, 753206, 753208
Instruction
group
Branch
instructions
Mnemonic
BR Note
Operand
addr
Number
of bytes
Number
of machine
cycles
–
–
Operation
• µPD753204
PC11–0 ← addr
Select the most appropriate instruction from
among BR !addr, BRCB !caddr and BR $addr
according to the assembler being used.
Addressing
area
Skip condition
*6
• µPD753206, 753208
PC12–0 ← addr
Select the most appropriate instruction
from among BR !addr, BRCB !caddr
and BR $addr according to the
assembler being used.
addr1
–
–
• µPD753204
PC11-0 ← addr1
Select the most appropriate instruction
from among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.
*11
• µPD753206, 753208
PC12–0 ← addr1
Select the most appropriate instruction
from among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.
! addr
3
3
• µPD753204
PC11–0 ← addr
*6
• µPD753206, 753208
PC12–0 ← addr
$addr
1
2
• µPD753204
PC11–0 ← addr
*7
• µPD753206, 753208
PC12–0 ← addr
$addr1
1
2
• µPD753204
PC11–0 ← addr1
• µPD753206, 753208
PC12–0 ← addr1
Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
49
µ PD753204, 753206, 753208
Instruction
group
Branch
instruction
Mnemonic
BR
Operand
PCDE
Number
of bytes
Number
of machine
cycles
2
3
Operation
Addressing
area
Skip condition
• µPD753204
PC 11–0 ← PC11-8+DE
• µPD753206, 753208
PC 12–0 ← PC12-8+DE
PCXA
2
3
• µPD753204
PC 11–0 ← PC11-8+XA
• µPD753206, 753208
PC 12–0 ← PC12-8+XA
BCDE
2
3
• µPD753204
PC 11–0 ← BCDE
*6
Note 1
• µPD753206, 753208
PC 12–0 ← BCDE Note 2
BCXA
2
3
• µPD753204
PC 11–0 ← BCXA Note 1
*6
• µPD753206, 753208
PC 12–0 ← BCXA Note 2
BRA
Note 3
!addr1
3
3
• µPD753204
PC 11–0 ← addr1
*6
• µPD753206, 753208
PC 12–0 ← addr1
BRCB
!caddr
2
2
• µPD753204
PC 11–0 ← caddr11–0
*8
• µPD753206, 753208
PC 12–0 ← PC12+caddr 11–0
Subroutine
stack control
instructions
CALLA Note 3 !addr1
3
3
• µPD753204
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC 11–0
(SP–5) ← 0, 0, 0, 0
PC 11–0 ← addr1, SP ← SP–6
*11
• µPD753206, 753208
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC 11–0
(SP–5) ← 0, 0, 0, PC12
PC 12–0 ← addr1, SP ← SP–6
Notes 1. "0" must be set to the B register.
2. Only the low-order one bit is valid in the B register.
3. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
50
µPD753204, 753206, 753208
Instruction
group
Subroutine
stack control
instructions
Mnemonic
CALL Note
Operand
!addr
Number
of bytes
Number
of machine
cycles
3
3
Operation
• µPD753204
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC11–0
PC11–0 ← addr, SP ← SP–4
Addressing
area
Skip condition
*6
• µPD753206, 753208
(SP–3) ← MBE, RBE, 0, PC12
(SP–4) (SP–1) (SP–2) ← PC11–0
PC12–0 ← addr, SP ← SP–4
4
• µPD753204
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← addr, SP ← SP–6
• µPD753206, 753208
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
PC12–0 ← addr, SP ← SP–6
CALLF Note
!faddr
2
2
• µPD753204
(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC11–0
PC11–0 ← 0+faddr, SP ← SP–4
*9
• µPD753206, 753208
(SP–3) ← MBE, RBE, 0, PC12
(SP–4) (SP–1) (SP–2) ← PC11–0
PC12–0 ← 00+faddr, SP ← SP–4
3
• µPD753204
(SP–2)
×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, 0
PC11–0 ← 0+faddr, SP ← SP–6
←
• µPD753206, 753208
(SP–2)
×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
PC12–0 ← 00+faddr, SP ← SP–6
←
Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
51
µ PD753204, 753206, 753208
Instruction
group
Subroutine
stack control
instructions
Mnemonic
RET Note
Operand
Number
of bytes
Number
of machine
cycles
1
3
Operation
Addressing
area
Skip condition
• µPD753204
PC 11–0 ← (SP) (SP+3) (SP+2)
MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4
• µPD753206, 753208
PC 11–0 ← (SP) (SP+3) (SP+2)
MBE, RBE, 0, PC12 ← (SP+1), SP ← SP+4
• µPD753204
×, ×, MBE, RBE ← (SP+4)
0, 0, 0, 0, ← (SP+1)
PC 11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6
• µPD753206, 753208
×, ×, MBE, RBE ← (SP+4)
MBE, 0, 0, PC12 ← (SP+1)
PC 11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6
RETS Note
1
3+S
• µPD753204
MBE, RBE, 0, 0 ← (SP+1)
PC 11–0 ← (SP) (SP+3) (SP+2)
SP ← SP+4
then skip unconditionally
Unconditional
• µPD753206, 753208
MBE, RBE, 0, PC12 ← (SP+1)
PC 11–0 ← (SP) (SP+3) (SP+2)
SP ← SP+4
then skip unconditionally
• µPD753204
0, 0, 0, 0 ← (SP+1)
PC 11–0 ← (SP) (SP+3) (SP+2)
×, ×, MBE, RBE ← (SP+4)
SP ← SP+6
then skip unconditionally
• µPD753206, 753208
0, 0, 0, PC12 ← (SP+1)
PC 11–0 ← (SP) (SP+3) (SP+2)
×, ×, MBE, RBE ← (SP+4)
SP ← SP+4
then skip unconditionally
Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
52
µPD753204, 753206, 753208
Instruction
group
Subroutine
stack control
instructions
Mnemonic
Operand
RETI Note 1
Number
of bytes
Number
of machine
cycles
1
3
Addressing
area
Operation
Skip condition
• µPD753204
MBE, RBE, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD753206, 753208
MBE, RBE, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD753204
0, 0, 0, 0 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
• µPD753206, 753208
0, 0, 0, PC12 ← (SP+1)
PC11–0 ← (SP) (SP+3) (SP+2)
PSW ← (SP+4) (SP+5), SP ← SP+6
rp
1
1
(SP–1)(SP–2) ← rp, SP ← SP–2
BS
2
2
(SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2
rp
1
1
rp ← (SP+1) (SP), SP ← SP+2
BS
2
2
MBS ← (SP+1), RBS ← (SP), SP ← SP+2
2
2
IME (IPS.3) ← 1
2
2
IE××× ← 1
2
2
IME (IPS.3) ← 0
IE×××
2
2
IE××× ← 0
A, PORTn
2
2
A ← PORTn
XA, PORTn
2
2
XA ← PORTn+1, PORTn
PORTn, A
2
2
PORTn ← A
PORTn, XA
2
2
PORTn+1, PORTn ← XA
HALT
2
2
Set HALT Mode (PCC.2 ← 1)
STOP
2
2
Set STOP Mode (PCC.3 ← 1)
NOP
1
1
No Operation
RBn
2
2
RBS ← n
(n = 0-3)
MBn
2
2
MBS ← n
(n = 0, 1, 15)
PUSH
POP
Interrupt
control
instructions
EI
IE×××
DI
Input/output
instructions
IN Note 2
OUT Note 2
CPU control
instructions
Special
instructions
SEL
(n = 0-3, 5, 6, 8, 9)
(n = 8)
(n = 3, 5, 6, 8, 9)
(n = 8)
Notes 1. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and
MBS must be set to 15.
53
µ PD753204, 753206, 753208
Instruction
group
Special
instructions
Mnemonic
GET Notes 1, 2 taddr
Operand
Number
of bytes
Number
of machine
cycles
1
3
Operation
µPD753204
• When TBR instruction
PC 11–0 ← (taddr) 3–0 + (taddr+1)
•
Addressing
area
Skip condition
*10
––––––––––––––––––––––––––––––––––
–––––––––––––
• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC 11–0
(SP–3) ← MBE, RBE, 0, 0
PC 11–0 ← (taddr) 3–0 + (taddr+1)
SP ← SP–4
––––––––––––––––––––––––––––––––––
–––––––––––––
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
Depending on
the reference
instruction
• µPD753206, 753208
• When TBR instruction
PC 12–0 ← (taddr) 4–0 + (taddr+1)
––––––––––––––––––––––––––––––––––
–––––––––––––
• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC 11–0
(SP–3) ← MBE, RBE, 0, PC12
PC 12–0 ← (taddr) 4–0 + (taddr+1)
SP ← SP–4
––––––––––––––––––––––––––––––––––
–––––––––––––
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
3
• µPD753204
• When TBR instruction
PC 11–0 ← (taddr) 3–0 + (taddr+1)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –-
4
*10
–––––––––––––
• When TCALL instruction
(SP–6) (SP–3) (SP–4) ← PC 11–0
(SP–5) ← 0, 0, 0, 0
(SP–2) ← ×, ×, MBE, RBE
PC 11–0 ← (taddr) 3–0 + (taddr+1)
SP ← SP–6
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –-
3
Depending on
the reference
instruction
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
–––––––––––––
Depending on
the reference
instruction
Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI
instruction.
2. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
54
µPD753204, 753206, 753208
Instruction
group
Special
instructions
Mnemonic
GETI Notes 1, 2 taddr
Operand
Number
of bytes
Number
of machine
cycles
1
3
Operation
µPD753206, 753208
• When TBR instruction
PC12–0 ← (taddr) 4–0 + (taddr+1)
•
Addressing
area
*10
––––––––––––––––––––––––––––––––––––– ––––
4
–––––––––––––
• When TCALL instruction
(SP–6) (SP–3) (SP–4) ← PC11–0
(SP–5) ← 0, 0, 0, PC12
(SP–2) ← ×, ×, MBE, RBE
PC12–0 ← (taddr) 4–0 + (taddr+1)
SP ← SP–6
––––––––––––––––––––––––––––––––––––– ––––
3
Skip condition
• When instruction other than TBR and
TCALL instructions
(taddr) (taddr+1) instruction is executed.
–––––––––––––
Depending on
the reference
instruction
Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI
instruction.
2. The above operations in the double boxes can be performed only in the Mk II mode.
55
µ PD753204, 753206, 753208
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T A = 25˚C)
Parameter
Symbol
Test Conditions
Rating
Unit
–0.3 to +7.0
V
Supply voltage
VDD
Input voltage
VI1
Except port 5
–0.3 to VDD + 0.3
V
VI2
Port 5
On-chip pull-up resistor
–0.3 to VDD + 0.3
V
When N-ch open-drain
–0.3 to +14
V
–0.3 to VDD + 0.3
V
Per pin
–10
mA
Total for all pins
–30
mA
30
mA
220
mA
Output voltage
VO
Output current high
I OH
Output current low
Per pin
I OL
Total for all pins
–40 to +85
Operating ambient
temperature
TA
Storage temperature
Tstg
Note
˚C
–65 to +150
˚C
Note When LCD is driven in normal mode: TA = –10 to +85˚C
Caution
Product quality may suffer if the absolute maximum rating is exceeded for even a single
parameter or even momentarily. That is, the absolute ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be used
under conditions which ensure that the absolute maximum ratings are not exceeded.
CAPACITANCE (T A = 25˚C, V DD = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz
15
pF
Output capacitance
COUT
Unmeasured pins returned to 0 V.
15
pF
I/O capacitance
CIO
15
pF
56
µPD753204, 753206, 753208
SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Resonator
Recommended constant
Ceramic
resonator
C1
C2
VDD
Crystal
resonator
C1
TYP.
MAX.
6.0
After VDD reaches oscillation voltage range MIN.
Note 2
4
1.0
6.0
Note 2
Unit
MHz
ms
MHz
C2
Oscillation
stabilization time Note 3
VDD
External
clock
Oscillation
stabilization time Note 3
MIN.
1.0
Oscillator
frequency (fX) Note 1
X2
X1
Test conditions
Oscillator
frequency (fX) Note 1
X2
X1
Parameter
X1
X2
VDD = 4.5 to 5.5 V
10
ms
30
X1 input
frequency (fX) Note 1
1.0
X1 input
high/low level width
(t XH, tXL )
83.3
6.0
Note 2
500
MHz
ns
Notes 1. The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the
instruction execution time, refer to the AC characteristics.
2. When the oscillator frequency is 4.19 MHz < fx ≤ 6.0 MHz, setting the processor clock control register
(PCC) to 0011 results in 1 machine cycle being less than the required 0.95 µ s. Therefore, set PCC
to a value other than 0011.
3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing
the STOP mode.
Caution
When using the system clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as V DD.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
57
µ PD753204, 753206, 753208
RECOMMENDED OSCILLATOR CONSTANTS
Ceramic resonator (TA = –40 to 85 °C)
Manufacturer
TDK
Part number
Frequency
(MHz)
Oscillation voltage range (V DD)
C1
C2
MIN. (V)
MAX. (V)
5.5
CCR1000K2
1.0
100
100
1.8
CCR2.0MC33
2.0
—
—
2.0
CCR3.58MC3
3.58
CCR4.19MC3
4.19
FCR4.19MC5
CCR6.0MC3
FCR6.0MC5
Caution
Oscillator constant (pF)
Remark
—
On-chip
capacitor
2.2
6.0
2.5
The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency
precision, the oscillaiton frequency must be adjusted on the implementation circuit. For details,
please contact directly the manufacturer of the resonator you will use.
58
µPD753204, 753206, 753208
DC CHARACTERISTICS (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
Output voltage low
Symbol
IOL
Test conditions
MIN.
TYP.
Per pin
Sum of the all pins
Input voltage high
VIH1
VIH2
VIH3
Ports 2, 3, 8, and 9
VDD
V
1.8 ≤ VDD < 2.7 V
0.9V DD
VDD
V
0.8V DD
VDD
V
0.9V DD
VDD
V
When a pull-up register 2.7 ≤ VDD ≤ 5.5 V
is incorporated
1.8 ≤ VDD < 2.7 V
0.7V DD
VDD
V
0.9V DD
VDD
V
2.7 ≤ VDD ≤ 5.5 V
0.7V DD
13
V
1.8 ≤ VDD < 2.7 V
0.9V DD
13
V
VDD – 0.1
VDD
V
VIH4
X1
VIL1
Ports 2, 3, 5, 8, and 9
2.7 ≤ VDD ≤ 5.5 V
0
0.3VDD
V
1.8 ≤ VDD < 2.7 V
0
0.1VDD
V
2.7 ≤ VDD ≤ 5.5 V
0
0.2VDD
V
1.8 ≤ VDD < 2.7 V
0
0.1VDD
V
0
0.1
V
VIL3
X1
Output voltage high
VOH
SCK, SO, ports 2, 3, 6, 8, and 9 IOH = –1.0 mA
Output voltage low
VOL1
SCK, SO, ports 2, 3, 5, 6, 8,
and 9
VDD – 0.5
I OL = 15 mA,
VDD = 4.5 to 5.5 V
V
0.2
I OL = 1.6 mA
Output leakage
current high
mA
0.7V DD
Ports 0, 1, 6, RESET
Input leakage
current low
mA
2.7 ≤ VDD ≤ 5.5 V
VIL2
Input leakage
current high
15
150
2.7 ≤ VDD ≤ 5.5 V
When N-ch open-drain
Input voltage low
Unit
1.8 ≤ VDD < 2.7 V
Ports 0, 1, 6, RESET
Port 5
MAX.
VOL2
SB0, SB1
N-ch open-drain
pull-up resistor ≥ 1 kΩ
ILIH1
VIN = VDD
Other pins than X1
2.0
V
0.4
V
0.2VDD
V
3
µA
X1
20
µA
ILIH3
VIN = 13 V
Port 5 (When N-ch open-drain)
20
µA
ILIL1
VIN = 0 V
Other pins than port 5 and X1
–3
µA
–20
µA
ILIH2
ILIL2
X1
ILIL3
Port 5 (When N-ch open drain)
Other than when an input instruction
is executed
–3
µA
Port 5 (When N-ch open-drain)
When an input instruction VDD = 5.0 V
is executed
VDD = 3.0 V
–30
µA
–10
–27
µA
–3
–8
µA
3
µA
20
µA
–3
µA
ILOH1
VOUT = VDD
SCK, SO/SB0, SB1, ports 2, 3, 6, 8
and 9
Port 5 (When a pull-up resistor
is incorporated.)
ILOH2
VOUT = 13 V
Port 5 (When N-ch open-drain)
Output leakage
current low
ILOL
VOUT = 0 V
On-chip pull-up resistor
RL1
VIN = 0 V
RL2
Ports 0 to 3, 6, 8, and 9
(Excluding P00 pin)
50
100
200
kΩ
Port 5 (Mask option)
15
30
60
kΩ
59
µ PD753204, 753206, 753208
DC CHARACTERISTICS (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
Symbol
LCD drive voltage
VLCD
VAC0 = 0
Test conditions
MIN.
TA = –40 to +85˚C
TA = –10 to +85˚C
VAC0 = 1
VAC current
Note 1
LCD split resistor
I VAC
Note 2
MAX.
Unit
2.7
VDD
V
2.2
VDD
V
1.8
VDD
V
1
4
µA
VAC0 = 1, V DD = 2.0 V ± 10%
TYP.
RLCD1
50
100
200
kΩ
RLCD2
5
10
20
kΩ
0
±0.2
V
0
±0.2
V
1.9
6.0
mA
VODC
lO = ±1.0 µA
LCD output voltage
VODS
deviation Note 3 (segment)
lO = ±0.5 µA
Supply current Note 4
6.0 MHz
VDD = 5.0 V ± 10% Note 5
Crystal oscillation VDD = 3.0 V ± 10% Note 6
C1 = C2 = 22 pF
HALT mode V DD = 5.0 V ±10%
0.4
1.3
mA
0.72
2.1
mA
V DD = 3.0 V ±10%
0.27
0.8
mA
LCD output voltage
deviation Note 3 (common)
I DD1
I DD2
I DD1
I DD2
I DD3
VLCD0 = VLCD
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
1.8 V ≤ VLCD ≤ V DD
4.19 MHz
VDD = 5.0 V ± 10% Note 5
Crystal oscillation VDD = 3.0 V ± 10% Note 6
C1 = C2 = 22 pF
HALT mode V DD = 5.0 V ±10%
1.5
4.0
mA
0.25
0.75
mA
0.7
2.0
mA
V DD = 3.0 V ±10%
0.23
0.7
mA
VDD = 5.0 V ±10%
0.05
10
µA
VDD = 3.0 V
±10%
0.02
5
µA
0.02
3
µA
STOP mode
T A = 25˚C
Notes 1. Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1
µ A.
2. Either RLCD1 or RLCD2 can be selected by the mask option.
3. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (V LCDn; n = 0, 1, 2).
4. Not including currents flowing in on-chip pull-up resistors or LCD split resistors.
5. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode.
6. When PCC is set to 0000 and the device is operated in the low-speed mode.
60
µPD753204, 753206, 753208
AC CHARACTERISTICS (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
Symbol
CPU clock cycle
time Note 1
tCY
TI0 input frequency
fTI
TI0 input
high/low-level width
tTIH, t TIL
Interrupt input high/
low-level width
tINTH ,
tINTL
RESET low level width
Test conditions
MIN.
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
TYP.
MAX.
Unit
0.67
64
µs
0.95
64
µs
0
1.0
MHz
0
275
kHz
0.48
µs
1.8
µs
IM02 = 0
Note 2
µs
IM02 = 1
10
µs
INT4
10
µs
KR0 to KR3
10
µs
10
µs
VDD = 2.7 to 5.5 V
INT0
tRSL
Notes 1. The cycle time (minimum instruc-
tCY vs VDD
tion execution time) of the CPU
64
30
clock (Φ) is determined by the
oscillation frequency of the con-
6
clock) and the processor clock
5
control register (PCC). The figure
at the right indicates the cycle
time t CY versus supply voltage
V DD characteristic.
2. 2tCY or 128/f X is set by setting the
Cycle Time tCY [ µ s]
nected resonator (and external
Guaranteed Operation
Range
4
3
interrupt mode register (IM0).
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
61
µ PD753204, 753206, 753208
SERIAL TRANSFER OPERATION
2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (T A = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
t KCY1
t KL1, t KH1
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SINote 1 setup time
t SIK1
VDD = 2.7 to 5.5 V
(to SCK↑)
SI
Note 1
hold time
t KSI1
VDD = 2.7 to 5.5 V
(from SCK↑)
SONote 1 output delay
t KSO1
time from SCK↓
RL = 1 kΩ,
Note 2
VDD = 2.7 to 5.5 V
CL = 100 pF
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
t KCY1/2 – 50
ns
t KCY1/2 – 150
ns
150
ns
500
ns
400
ns
600
ns
0
250
ns
0
1000
ns
Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.
2. RL and C L are the load resistance and load capacitance of the SO output lines.
2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
t KCY2
t KL2, t KH2
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SINote 1 setup time
t SIK2
VDD = 2.7 to 5.5 V
(to SCK↑)
SI
Note 1
hold time
t KSI2
VDD = 2.7 to 5.5 V
(from SCK↑)
SONote 1 output delay
time from SCK↓
t KSO2
RL = 1 kΩ,
Note 2
VDD = 2.7 to 5.5 V
CL = 100 pF
MIN.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
400
ns
600
ns
0
300
ns
0
1000
ns
Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.
2. RL and C L are the load resistance and load capacitance of the SO output lines.
62
TYP.
µPD753204, 753206, 753208
SBI Mode (SCK...Internal clock output (master)): (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
tKCY3
tKL3 , tKH3
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
VDD = 2.7 to 5.5 V
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
t KCY3/2 – 50
ns
t KCY3/2 – 150
ns
150
ns
500
ns
t KCY3/2
ns
SB0, 1 setup time
(to SCK↑)
tSIK3
SB0, 1 hold time
(from SCK↑)
tKSI3
VDD = 2.7 to 5.5 V
SB0, 1 output delay
time from SCK↓
tKSO3
RL = 1 kΩ,
CL = 100 pF
SB0, 1↓ from SCK↑
tKSB
t KCY3
ns
SCK↓ from SB0, 1↑
tSBK
t KCY3
ns
SB0, 1 low-level width
tSBL
t KCY3
ns
SB0, 1 high-level width
tSBH
t KCY3
ns
Note
VDD = 2.7 to 5.5 V
0
250
ns
0
1000
ns
Note R L and C L are the load resistance and load capacitance of the SB0 and SB1 output lines.
SBI Mode (SCK...External clock input (slave)): (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high/low-level
Symbol
tKCY4
tKL4 , tKH4
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
VDD = 2.7 to 5.5 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
t KCY4/2
ns
SB0, 1 setup time
(to SCK↑)
tSIK4
SB0, 1 hold time
(from SCK↑)
tKSI4
VDD = 2.7 to 5.5 V
SB0, 1 output delay
time from SCK↓
tKSO4
RL = 1 kΩ,
CL = 100 pF
SB0, 1↓ from SCK↑
tKSB
t KCY4
ns
SCK↓ from SB0, 1↑
tSBK
t KCY4
ns
SB0, 1 low-level width
tSBL
t KCY4
ns
SB0, 1 high-level width
tSBH
t KCY4
ns
Note
VDD = 2.7 to 5.5 V
0
300
ns
0
1000
ns
Note R L and C L are the load resistance and load capacitance of the SB0 and SB1 output lines.
63
µ PD753204, 753206, 753208
AC Timing Test Point (Excluding X1 Input)
VIH (MIN.)
VIL (MAX.)
VIH (MIN.)
VIL (MAX.)
VOH (MIN.)
VOL (MAX.)
VOH (MIN.)
VOL (MAX.)
Clock Timing
1/fX
tXL
tXH
VDD–0.1 V
0.1 V
X1 Input
TI0 Timing
1/fTI
tTIL
TI0
64
tTIH
µPD753204, 753206, 753208
Serial Transfer Timing
3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
SI
tKSI1, 2
Input Data
tKSO1, 2
SO
Output Data
2-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SB0, 1
tKSO1, 2
65
µ PD753204, 753206, 753208
Serial Transfer Timing
Bus release signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
SB0, 1
tKSO3, 4
Command signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSIK3, 4
tSBK
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INTP0, 4
KR0 to 3
RESET input timing
tRSL
RESET
66
tKSI3, 4
tKSI3, 4
µPD753204, 753206, 753208
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(TA = –40 to +85˚C)
Parameter
Symbol
Release signal set time
t SREL
Oscillation stabilization
wait time Note 1
t WAIT
Test conditions
MIN.
TYP.
MAX.
Unit
µs
0
Release by RESET
Note 2
ms
Release by interrupt
Note 3
ms
Notes 1. The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
2. Either 2 17/fX or 215/fX can be selected by the mask option.
3. Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3
BTM2
BTM1
BTM0
—
—
—
—
0
0
1
1
0
1
0
1
0
1
1
1
Wait
When fx = 4.19-MHz operation
220/f X (approx. 250 ms)
217/f X (approx. 31.3 ms)
215/f X (approx. 7.81 ms)
213/f X (approx. 1.95 ms)
time
When fx = 6.0-MHz operation
220/f X (approx. 175 ms)
217/f X (approx. 21.8 ms)
215/f X (approx. 5.46 ms)
213/f X (approx. 1.37 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
Halt mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
Halt mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
67
µ PD753204, 753206, 753208
13. CHARACTERISTIC CURVES (REFERENCE VALUES)
IDD vs VDD (System Clock : 6.0-MHz Crystal Resonator)
(TA = 25 °C)
10
5.0
PCC = 0011
PCC = 0010
1.0
PCC = 0001
Supply Current IDD (mA)
PCC = 0000
System clock
HALT mode
0.5
0.1
0.05
X1
X2
Crystal
resonator
6.0 MHz
22 pF
22 pF
VDD
0.01
0
1
2
3
4
Supply Voltage VDD (V)
68
5
6
7
8
µPD753204, 753206, 753208
IDD vs VDD (System Clock : 4.19-MHz Crystal Resonator)
(TA = 25°C)
10
5.0
PCC = 0011
PCC = 0010
1.0
PCC = 0001
PCC = 0000
Supply Current IDD (mA)
System clock
HALT mode
0.5
0.1
0.05
X1
X2
Crystal
resonator
4.19 MHz
22 pF
22 pF
VDD
0.01
0
1
2
3
4
5
6
7
8
Supply Voltage VDD (V)
69
µ PD753204, 753206, 753208
14. PACKAGE DRAWINGS
48 PIN PLASTIC SHRINK SOP (375 mil)
48
25
3°+7°
–3°
detail of lead end
1
24
A
G
H
I
K
F
J
N
E
C
D
M M
L
B
P48GT-65-375B-1
NOTE
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
70
ITEM
MILLIMETERS
INCHES
A
16.21 MAX.
0.639 MAX.
B
0.63 MAX.
0.025 MAX.
C
0.65 (T.P.)
0.026 (T.P.)
D
0.30 ± 0.10
0.012+0.004
–0.005
E
0.125 ± 0.075
0.005 ± 0.003
F
2.0 MAX.
0.079 MAX.
G
1.7 ± 0.1
0.067 ± 0.004
H
10.0 ± 0.3
0.394 +0.012
–0.013
I
8.0 ± 0.2
0.315 ± 0.008
J
1.0 ± 0.2
0.039+0.009
–0.008
K
0.15+0.10
–0.05
0.006+0.004
–0.002
L
0.5 ± 0.2
0.020+0.008
–0.009
M
0.10
0.004
N
0.10
0.004
µPD753204, 753206, 753208
15. RECOMMENDED SOLDERING CONDITIONS
The µ PD753208 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 15-1. Surface Mounting Type Soldering Conditions
µPD753204GT-xxx
: 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µPD753206GT-xxx
: 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µPD753208GT-xxx
: 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
Soldering
Method
Soldering Conditions
Symbol
Infrared rays
reflow
Peak package's surface temperature: 235˚C, Reflow time: 30 seconds or less
(at 210˚C or higher), Number of reflow processes: Twice max.
IR35-00-2
VPS
Peak package's surface temperature: 215˚C, Reflow time: 40 seconds or less
(at 200˚C or higher), Number of reflow processes: Twice max.
VP15-00-2
Wave soldering
Solder temperature: 260˚C or below, Flow time: 10 seconds or less, Number of
flow process: 1, Preheating temperature: 120˚C or below (Package surface
temperature)
WS60-00-1
Partial heating
Pin temperature: 300˚C or below, Time: 3 seconds or less (per device side)
Caution
—
Use of more than one soldering method should be avoided (except for partial heating).
71
µ PD753204, 753206, 753208
APPENDIX A µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST
µ PD753108
Parameter
Program memory
µPD753208
Mask ROM
0000H-1FFFH
(8192 × 8 bits)
One-time PROM
0000H-3FFFH
(16384 × 8 bits)
Data memory
000H-1FFH
(512 × 4 bits)
CPU
75XL CPU
Instruction
execution
time
I/O port
µPD75P3216
When main system
clock is selected
• 0.95, 1.91, 3.81, 15.3 µ s (@ 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µ s (@ 6.0-MHz operation)
When subsystem
clock is selected
122 µ s (@ 32.768-kHz
operation)
None
CMOS input
8 (on-chip pull-up resistors can
be specified by software: 7)
6 (on-chip pull-up resistors can be specified by software: 5)
CMOS input/output
20 (on-chip pull-up resistors can be specified by software)
N-ch open drain
input/output
4 (on-chip pull-up resistors can be specified by software,
withstand voltage is 13 V)
Total
32
30
Segment selection: 16/20/24
(can be changed to CMOS
input/output port in 4 timeunit; max. 8)
Segment selection: 4/8/12 segments
(can be changed to CMOS input/output port in 4 time-unit;
max. 8)
LCD controller/driver
4 (no mask option, withstand
voltage is 13 V)
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)
On-chip split resistor for LCD driver can be specified by
using mask option.
Timer
5 channels
• 8-bit timer/event
counter: 3 channels
• Basic interval timer/
watchdog timer: 1 channel
• Watch timer: 1 channel
Clock output (PCL)
• Φ, 524, 262, 65.5 kHz
(Main system clock: @ 4.19-MHz operation)
• Φ, 750, 375, 93.8 kHz
(Main system clock: @ 6.0-MHz operation)
Buzzer output (BUZ)
• 2, 4, 32 kHz
(Main system clock: @
4.19-MHz operation or subsystem clock: @ 32.768-kHz
operation)
• 2.86, 5.72, 45.8 kHz
(Main system clock: @
6.0-MHz operation)
Serial interface
3
•
•
•
SCC register
Contained
None
5 channels
• 8-bit timer counter: 2 channels (can be used as the 16-bit
timer counter, carrier generator, and timer with gate)
• 8-bit timer/event counter: 1 channel
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
External: 3, internal: 5
External: 2, internal: 5
• 2, 4, 32 kHz
(Main system clock: @ 4.19-MHz operation)
• 2.93, 5.86, 46.9 kHz
(Main system clock: @ 6.0-MHz operation)
modes are available
3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit
2-wire serial I/O mode
SBI mode
SOS register
Vectored interrupt
72
No on-chip split resistor for
LCD driver
µPD753204, 753206, 753208
Parameter
µPD753108
Test input
External: 1, internal: 1
Operation supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
• 64-pin plastic QFP
(14 × 14 mm)
• 64-pin plastic QFP
(12 × 12 mm)
µ PD753208
µ PD75P3216
• 48-pin plastic shrink SOP
(375 mils, 0.65-mm pitch)
73
µ PD753204, 753206, 753208
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for system development using the µPD753208.
In 75XL series, the relocatable assembler which is common to the µ PD753208 Subseries is used in combination
with the device file of each product.
Language processor
RA75X relocatable assembler
OS
PC-9800 series
IBM PC/AT TM and
compatible machines
Distribution media
MS-DOSTM
3.5-inch 2HD
µ S5A13RA75X
Ver. 3.30 to
5-inch 2HD
µ S5A10RA75X
3.5-inch 2HC
µ S7B13RA75X
5-inch 2HC
µ S7B10RA75X
Ver. 6.2
Device file
Part number
(product name)
Host machine
Note
Refer to section
“OS for IBM PC”
Part number
(product name)
Host machine
OS
PC-9800 series
Distribution media
MS-DOS
Ver. 3.30 to
Ver. 6.2
IBM PC/AT and
compatible machines
3.5-inch 2HD
µ S5A13DF753208
5-inch 2HD
µ S5A10DF753208
3.5-inch 2HC
µ S7B13DF753208
5-inch 2HC
µ S7B10DF753208
Note
Refer to section
“OS for IBM PC”
PROM write tools
Hardware
Software
PG-1500
PG-1500 is a PROM programmer which enables you to program single chip microcomputers
including PROM by stand-alone or host machine operation by connecting an attached board
and optional programmer adapter to PG-1500. It also enables you to program typical PROM
devices of 256 Kbits to 4 Mbits.
PA-75P3216GT
PROM programmer adapter for the µ PD75P3216GT. Connect the programmer adapter to
PG-1500 for use.
PG-1500 controller
PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500
is controlled on the host machine.
Part number
(product name)
Host machine
OS
PC-9800 series
Distribution media
MS-DOS
Ver. 3.30 to
Ver. 6.2
IBM PC/AT and
compatible machines
3.5-inch 2HD
µ S5A13PG1500
5-inch 2HD
µ S5A10PG1500
3.5-inch 2HD
µ S7B13PG1500
5-inch 2HC
µ S7B10PG1500
Note
Refer to section
“OS for IBM PC”
Note Ver. 5.00 or later have the task swap function, but it cannot be used for this software.
Remarks 1. Operation of the assembler and device file is guaranteed only on the above host machine and OSs.
2. Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs.
74
µPD753204, 753206, 753208
Debugging tool
The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
µ PD753208.
The system configurations are described as follows.
Hardware
IE-75000-R
Note 1
IE-75001-R
In-circuit emulator for debugging the hardware and software when developing the
application systems that use the 75X series and 75XL series. When developing a
µPD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP753208GT-R which are sold separately must be used with the IE-75001-R.
It can debug the system efficiently by connecting the host machine and PROM
programmer.
IE-75300-R-EM
Emulation board for evaluating the application systems that use a µPD753208
subseries.
It must be used with the IE-75000-R or IE-75001-R.
EP-753208GT-R
Emulation probe for the µPD753208GT.
It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.
It is supplied with the 48-pin conversion adapter EV-9500GF-48 which facilitates
connection to a target system.
EV-9500GF-48
Software
In-circuit emulator for debugging the hardware and software when developing the
application systems that use the 75X series and 75XL series. When developing a
µPD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP753208GT-R that are sold separately must be used with the IE-75000-R.
By connecting with the host machine and the PROM programmer, efficient debugging
can be made.
It contains the emulation board IE-75000-R-EM which is connected.
IE control program
Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix
I/F and controls the above hardware on a host machine.
Host machine
OS
PC-9800 series
Distribution media
MS-DOS
Ver. 3.30 to
Ver. 6.2
IBM PC/AT and its
compatible machine
Part No.
(product name)
3.5-inch 2HD
µS5A13IE75X
5-inch 2HD
µS5A10IE75X
3.5-inch 2HC
µS7B13IE75X
5-inch 2HC
µS7B10IE75X
Note 2
Refer to section
“OS for IBM PC”
Notes 1. Maintenance parts.
2. Ver. 5.00 or later have the task swap function, but it cannot be used for this software.
Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs.
2. The µ PD753204, 753206, 753208, and 75P3216 are commonly referred to as the µ PD753208
Subseries.
75
µ PD753204, 753206, 753208
OS for IBM PC
The following IBM PC OS’s are supported.
OS
PC DOS
Ver. 5.02 to Ver. 6.3
J6.1/V Note to J6.3/V Note
MS-DOS
Ver. 5.0 to Ver. 6.22
5.0/V Note to 6.2/V Note
IBM DOS TM
J5.02/V
Note
Note
English version is supported.
Caution
76
Version
TM
Ver. 5.0 and later have the task swap function, but it cannot be used for this software.
µPD753204, 753206, 753208
APPENDIX C RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to device
Document No.
Document Name
Japanese
English
µPD753204, 753206, 753208 Data Sheet
U10166J
This manual
µPD75P3216 Data Sheet
U10241J
U10241E
µPD753208 User’s Manual
U10158J
U10158E
75XL Series Selection Guide
U10453J
U10453E
Documents related to development tool
Document No.
Document Name
Hardware
Software
Japanese
English
IE-75000-R/IE-75001-R User‘s Manual
EEU-846
EEU-1416
IE-75300-R-EM User’s Manual
U11354J
U11354E
EP-753208GT-R User’s Manual
U10739J
U10739E
PG-1500 User’s Manual
U11940J
EEU-1335
Operation
EEU-731
EEU-1346
Language
EEU-730
EEU-1363
PC-9800 Series
(MS-DOS) Base
EEU-704
EEU-1291
IBM PC Series
(PC DOS) Base
EEU-5008
U10540E
RA75X Assembler Package User’s Manual
PG-1500 Controller User’s Manual
Other related documents
Document No.
Document Name
Japanese
English
Semiconductor Device Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Electrostatic Discharge (ESD) Test
MEM-539
IEI-1201
Guide to Quality Assurance for Semiconductor Devices
C11893J
MEI-1202
Microcontroller – Related Product Guide – Third Party Products –
C11416J
–
Caution
The contents of the documents listed above are subject to change without prior notice to users.
Make sure to use the latest edition when starting design.
77
µ PD753204, 753206, 753208
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.
Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity.
Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry.
Each unused pin should be connected to VDD or GND with a resistor, if it is
considered to have a possibility of being an output pin. All handling related
to the unused pins must be judged device by device and related specifications
governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately
after power-on for devices having reset function.
78
µPD753204, 753206, 753208
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
79
µ PD753204, 753206, 753208
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be
prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country.
Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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