NEC UPD178076

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD178076,178078,178096,178098
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD178076, 178078, 178096, and 178098 are 8-bit single-chip CMOS microcontrollers containing hardware
for digital tuning systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit. In
addition, the µPD178076 and 178078 have an asynchronous serial interface (UART) mode, and the µPD178096 and
178098 have an IEBusTM controller.
Moreover, a flash memory model, the µPD178F098, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also under development.
For the detailed functional description, refer to the following User’s Manuals:
µPD178078, 178098 Subseries User’s Manual : U12790E
78K/0 Series User’s Manual - Instruction
: U12326E
FEATURES
• High-capacity ROM and RAM
Item Program Memory (ROM)
Part Number
µPD178076, 178096
48K bytes
µPD178078, 178098
60K bytes
• Instruction cycle:
Data Memory
Internal high-speed RAM Internal buffer RAM
1024 bytes
32 bytes
1024 bytes
2048 bytes
0.32 µs (with crystal resonator of fX = 6.3 MHz)
• Many internal hardware units
• Hardware for PLL frequency synthesizer
dual modulus prescaler, programmable divider,
phase comparator, charge pump
General-purpose I/O ports, A/D converter, serial
interface (UART mode: µPD178076 and 178078
only), IEBus controller (µPD178096 and 178098
only), timers, frequency counter, power-ON clear
circuit
Internal extension RAM
• Vectored interrupt sources
• µPD178076, 178078: 22
• µPD178096, 178098: 21
• Supply voltage
:VDD = 4.5 to 5.5 V (during PLL and CPU
operations)
:VDD = 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12885EJ3V0DS00
Date Published June 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 2000
µPD178076, 178078, 178096, 178098
APPLICATION FIELD
Car stereos
ORDERING INFORMATION
Part Number
Package
µPD178076GF-×××-3BA
100-pin plastic QFP (14 × 20)
µPD178078GF-×××-3BA
100-pin plastic QFP (14 × 20)
µPD178096GF-×××-3BA
100-pin plastic QFP (14 × 20)
µPD178098GF-×××-3BA
100-pin plastic QFP (14 × 20)
Remark ××× indicates ROM code suffix, which is E×× when the I2C bus is used.
2
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
DEVELOPMENT OF 8-BIT DTS SERIES
Models under mass production
Models under development
Flash memory model or
PROM model
80 pins
Mask ROM model
µ PD178F048
80 pins
Internal OSD controller
8-bit PWM × 4 channels
14-bit PWM × 1 channel
µ PD178048 subseries
Internal OSD controller
8-bit PWM × 4 channels
14-bit PWM × 1 channel
µ PD178098 subseries
100 pins
Internal IEBus controller
100 pins
µ PD178F098
Internal IEBus controller and UART
µ PD178078 subseries
100 pins
Internal UART
80 pins
µ PD178F134
Internal LCD and UART
80 pins
µ PD178F124
Internal LCD and UART
µPD178024 subseries
80 pins
Internal UART
80 pins
µPD178034 subseries
80 pins
Internal UART
80 pins
µPD178018A subseries
80 pins
µPD178003 subseries
µPD178P018A
Limits functions of µPD178018A subseries
Data Sheet U12885EJ3V0DS00
3
µPD178076, 178078, 178096, 178098
FUNCTIONAL OUTLINE
(1/2)
µPD178076
Item
Internal
ROM
48K bytes
memory
High-speed RAM 1024 bytes
Buffer RAM
32 bytes
Extension RAM
1024 bytes
µPD178078
µPD178096
µPD178098
60K bytes
48K bytes
60K bytes
2048 bytes
1024 bytes
2048 bytes
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
• 0.32 µs/0.64 µs/1.27 µs/2.54 µs/5.08 µs (with crystal resonator of fX = 6.3 MHz)
time
• 0.44 µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (with crystal resonator of fX = 4.5 MHz)Note 1
Instruction set
•
•
•
•
I/O port
Total
: 80 pins
• CMOS input
:
• CMOS I/O
: 64 pins
16-bit operation
Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulation (set, reset, test Boolean operation)
BCD adjustment, etc.
• N-ch open-drain output :
8 pins
8 pins
A/D converter
8-bit resolution × 8 channels
Serial interface
• 3-wire/SBI/2-wire/I2C bus Note 2 mode
selectable: 1 channel
• 3-wire mode: 1 channel
• 3-wire mode (with automatic transmit/
receive function of up to 32 bytes):
1 channel
• UART mode: 1 channel
IEBus controller
Not provided
Timer
•
•
•
•
Buzzer output
BEEP0 pin: 1 kHz, 1.5 kHz, 3 kHz, 4 kHz
• 3-wire/SBI/2-wire/I2C bus Note 2 mode
selectable: 1 channel
• 3-wire mode: 1 channel
• 3-wire mode (with automatic transmit/
receive function of up to 32 bytes):
1 channel
Provided
Basic timer (timer carry FF (10 Hz))
16-bit timer/event counter
8-bit timer/event counter
Watchdog timer
:
:
:
:
1
1
2
1
channel
channel
channels
channel
BUZ pin: 0.77 kHz, 1.54 kHz, 3.08 kHz, 6.15 kHz (with crystal resonator of fX = 6.3 MHz)
Notes 1. When using the IEBus controller of the µPD178096 or 178098, the 4.5-MHz crystal resonator cannot
be used. Use the 6.3-MHz crystal resonator.
2. When the I2C bus mode is used (including when the mode is implemented in software without using
the peripheral hardware), consult NEC when ordering a mask.
4
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
(2/2)
µPD178076
Item
Vectored
Maskable
interrupt
source
PLL
µPD178078
µPD178096
Internal : 13
Internal : 12
External: 8
External: 8
Non-maskable
Internal: 1
Software
1
Division mode
2 types
frequency
• Direct division mode (VCOL pin)
synthesizer
• Pulse swallow mode (VCOL and VCOH pins)
Reference
frequency
Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz)
Charge pump
Error out output: 2 pins
Phase
Unlock detectable in software
µPD178098
comparator
Frequency counter
Frequency measurement
• AMIFC pin: For 450-kHz counting
• FMIFC pin: For 450-kHz/10.7-MHz counting
Standby function
• HALT mode
• STOP mode
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Reset by power-ON clear circuit
• Detection of less than 4.5 VNote (Reset does not occur, however.)
• Detection of less than 3.5 VNote (during CPU operation)
• Detection of less than 2.3 VNote (in STOP mode)
Supply voltage
• VDD = 4.5 to 5.5 V (during CPU, PLL operation)
• VDD = 3.5 to 5.5 V (during CPU operation)
Package
• 100-pin plastic QFP (14 × 20)
Note
These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these.
Data Sheet U12885EJ3V0DS00
5
µPD178076, 178078, 178096, 178098
PIN CONFIGURATION (Top View)
• 100-pin plastic QFP (14 × 20)
µPD178076GF-×××-3BA, 178078GF-×××-3BA
GNDPORT
VDDPORT
P47
P46
P45
P44
P43
P42
P41
P40
P67
P66
P65
P64
P63
P62
P61
P60
GND1
P07/INTP7
µPD178096GF-×××-3BA, 178098GF-×××-3BA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P17/ANI7
AVSS
REGCPU
VDD
REGOSC
X2
X1
GND0
P100
GND2
P101/AMIFC
P102/FMIFC
VDDPLL
VCOH
VCOL
GNDPLL
EO0
EO1
IC
RESET
P00/INTP0
P01/INTP1
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P70/SI3
P71/SO3
P72/SCK3
P73
P50
P51
P52
P53
P54
P55
P56
P57
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
AVDD
P14/ANI4
P15/ANI5
P16/ANI6
6
Data Sheet U12885EJ3V0DS00
P06/INTP6
P05/INTP5
P04/INTP4
P124
P123
P122
P121 /RX0
P120 /TX0
P77
P76
P75[/TXD0]
P74[/RXD0]
P137
P136
P135
P134
P133
P132
P131/TO51
P130/TO50
P37/BUZ
P36/BEEP0
P35/TI51
P34/TI50
P33/TI01
P32/TI00
P31/TO0
P30/VM45
P03/INTP3
P02/INTP2
µPD178076, 178078, 178096, 178098
Cautions 1. Directly connect the IC (Internally Connect) pin to GND0, GND1, or GND2.
2. Keep the voltage at AVDD, VDDPORT, and VDDPLL pins same as that at the VDD pin.
3. Keep the voltage at AVSS, GNDPORT, and GNDPLL pins same as that at GND0, GND1, or
GND2.
4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-µF capacitor.
Remark [ ] : µPD178076 and 178078 only
{ }: µPD178096 and 178098 only
Pin Name
P130-P137
: Port 13
AMIFC
: AM intermediate frequency counter
REGCPU
: Regulator for CPU power supply
ANI0-ANI7
: A/D converter input
REGOSC
: Regulator for oscillation circuit
AVDD
: A/D converter power supply
RESET
: Reset input
AVSS
: A/D converter ground
RXD0Note 1
: UART0 serial data input
BUSY
: Busy output
RX0Note 2
: IEBus serial data input
BEEP0, BUZ
: Buzzer output
SB0, SB1
: Serial data bus input/output
EO0, EO1
: Error out output
SCK0, SCK1, SCK3 : Serial clock input/output
FMIFC
: FM intermediate frequency counter
SCL
SDA0, SDA1
: Serial data input/output
GNDPLL
: PLL ground
SI0, SI1, SI3
: Serial data input
GND0-GND2
: Ground
SO0, SO1, SO3
: Serial data output
IC
: Internally connected
STB
: Strobe output
INTP0-INTP7
: Interrupt input
TI00, TI01
: 16-bit timer capture trigger input
P00-P07
: Port 0
TI50, TI51
: 8-bit timer clock input
P10-P17
: Port 1
TO0
: 16-bit timer output
P20-P27
: Port 2
TO50, TO51
: 8-bit timer output
P30-P37
: Port 3
TXD0Note 1
: UART0 serial data output
P40-P47
: Port 4
TX0Note 2
: IEBus serial data output
P50-P57
: Port 5
VCOL, VCOH
: Local oscillation input
P60-P67
: Port 6
VDDPORT
: Port power supply
P70-P77
: Port 7
VDDPLL
: PLL power supply
P100-P102
: Port 10
VDD
: Power supply
P120-P124
: Port 12
VM45
: VDD = 4.5 V monitor output
X1, X2
: Crystal resonator
input
input
: Serial clock input/output
Notes 1. µPD178076 and 178078 only
2. µPD178096 and 178098 only
Data Sheet U12885EJ3V0DS00
7
µPD178076, 178078, 178096, 178098
BLOCK DIAGRAM
(1) µ PD178076, 178078
TO0/P31
TI00/P32
TI01/P33
16-bit TIMER/
EVENT COUNTER
PORT 0
8
P00-P07
TI50/P34
TO50/P130
8-bit TIMER/
EVENT COUNTER 50
PORT 1
8
P10-P17
TI51/P35
TO51/P131
8-bit TIMER/
EVENT COUNTER 51
PORT 2
8
P20-P27
WATCHDOG TIMER
PORT 3
8
P30-P37
BASIC TIMER
PORT 4
8
P40-P47
PORT 5
8
P50-P57
PORT 6
8
P60-P67
PORT 7
8
P70-P77
PORT10
3
P100-P102
PORT 12
5
P120-P124
PORT 13
8
P130-P137
8
ANI0/P10ANI7/P17
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
SERIAL
INTERFACE 1
SI3/P70
SO3/P71
SCK3/P72
SERIAL
INTERFACE 3
TXD0/P75
RXD0/P74
UART0
INTP0/P00INTP7/P07
INTERRUPT
CONTROL
BEEP0/P36
BUZ/P37
RESET
X1
X2
VDDPORT
GNDPORT
VDD
VM45/P30
REGOSC
REGCPU
GND0
78K/0
CPU
CORE
SERIAL
INTERFACE 0
8
ROM
µ PD178078
: 60 Kbyte
µ PD178076
: 48 Kbyte
RAM
µ PD178078
: 3 Kbyte
µ PD178076
: 2 Kbyte
A/D
CONVERTER
BUZZER OUTPUT
SYSTEM
CONTROL
VOLTAGE
REGULATOR
RESET
CPU
PERIPHERAL
VOSC
VCPU
FREQUENCY
COUNTER
PLL
PLL
VOLTAGE
REGULATOR
GND1
AVDD
AVSS
AMIFC/P101
FMIFC/P102
EO0
EO1
VCOL
VCOH
VDDPLL
GNDPLL
IC
GND2
8
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
(2) µ PD178096, 178098
TO0/P31
TI00/P32
TI01/P33
16-bit TIMER/
EVENT COUNTER
PORT 0
8
P00-P07
TI50/P34
TO50/P130
8-bit TIMER/
EVENT COUNTER 50
PORT 1
8
P10-P17
TI51/P35
TO51/P131
8-bit TIMER/
EVENT COUNTER 51
PORT 2
8
P20-P27
WATCHDOG TIMER
PORT 3
8
P30-P37
BASIC TIMER
PORT 4
8
P40-P47
PORT 5
8
P50-P57
PORT 6
8
P60-P67
PORT 7
8
P70-P77
PORT10
3
P100-P102
PORT 12
5
P120-P124
PORT 13
8
P130-P137
8
ANI0/P10ANI7/P17
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
SERIAL
INTERFACE 1
SI3/P70
SO3/P71
SCK3/P72
SERIAL
INTERFACE 3
RX0/P121
TX0/P120
IEBus0
INTP0/P00INTP7/P07
BEEP0/P36
BUZ/P37
RESET
X1
X2
VDDPORT
GNDPORT
VDD
VM45/P30
REGOSC
REGCPU
GND0
78K/0
CPU
CORE
SERIAL
INTERFACE 0
8
ROM
µ PD178098
: 60 Kbyte
µ PD178096
: 48 Kbyte
RAM
µ PD178098
: 3 Kbyte
µ PD178096
: 2 Kbyte
INTERRUPT
CONTROL
A/D
CONVERTER
BUZZER OUTPUT
SYSTEM
CONTROL
VOLTAGE
REGULATOR
RESET
CPU
PERIPHERAL
VOSC
VCPU
FREQUENCY
COUNTER
PLL
PLL
VOLTAGE
REGULATOR
GND1
AVDD
AVSS
AMIFC/P101
FMIFC/P102
EO0
EO1
VCOL
VCOH
VDDPLL
GNDPLL
IC
GND2
Data Sheet U12885EJ3V0DS00
9
µPD178076, 178078, 178096, 178098
CONTENTS
1.
PIN
1.1
1.2
1.3
FUNCTION LIST ......................................................................................................................
Port Pins ..................................................................................................................................
Pins Other Than Port Pins ......................................................................................................
I/O Circuits of Pins and Recommended Connections of Unused Pins ..............................
11
11
12
14
2.
MEMORY SPACE ............................................................................................................................ 18
2.1 Memory Size Select Register (IMS) ....................................................................................... 19
2.2 Internal Extension RAM Size Select Register (IXS) ............................................................. 20
3.
FEATURES OF PERIPHERAL HARDWARE FUNCTIONS .........................................................
3.1 Ports .........................................................................................................................................
3.2 Clock Generation Circuit ........................................................................................................
3.3 Timers ......................................................................................................................................
3.4 Buzzer Output Control Circuit ...............................................................................................
3.5 A/D Converter ..........................................................................................................................
3.6 Serial Interface ........................................................................................................................
3.7 IEBus Controller (µPD178096 and 178098 only) ..................................................................
3.8 PLL Frequency Synthesizer ...................................................................................................
3.9 Frequency Counter .................................................................................................................
4.
INTERRUPT FUNCTION ................................................................................................................. 37
5.
STANDBY FUNCTION .................................................................................................................... 43
6.
RESET FUNCTION.......................................................................................................................... 43
7.
INSTRUCTION SET ......................................................................................................................... 44
8.
ELECTRICAL SPECIFICATIONS ................................................................................................... 47
9.
PACKAGE DRAWING ..................................................................................................................... 63
21
21
22
22
26
27
28
32
35
36
10. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 64
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 65
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 67
10
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
1. PIN FUNCTION LIST
1.1 Port Pins (1/2)
Pin Name
P00-P07
I/O
I/O
Function
Port 0.
8-bit I/O port.
At Reset
Shared by:
Input
INTP0-INTP7
Can be set in input or output mode in 1-bit units.
P10-P17
Input
Port 1.
8-bit input port.
Input
ANI0-ANI7
P20
I/O
Port 2.
Input
SI1
P21
8-bit I/O port.
SO1
P22
Can be set in input or output mode in 1-bit units.
SCK1
P23
STB
P24
BUSY
P25
SI0/SB0/SDA0
P26
SO0/SB1/SDA1
P27
SCK0/SCL
P30
I/O
Port 3.
Input
P31
8-bit I/O port.
P32
Can be set in input or output mode in 1-bit units.
VM45
TO0
TI00
P33
TI01
P34
TI50
P35
TI51
P36
BEEP0
P37
P40-47
BUZ
I/O
Port 4.
Input
–
Input
–
Input
–
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P50-P57
I/O
Port 5.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P60-P67
I/O
Port 6.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P70
I/O
Port 7.
Input
SI3
P71
8-bit I/O port.
SO3
P72
Can be set in input or output mode in 1-bit units.
SCK3
P73
–
P74
RXD0Note 1
P75
TXD0Note 1
P76, P77
–
Data Sheet U12885EJ3V0DS00
11
µPD178076, 178078, 178096, 178098
1.1 Port Pins (2/2)
Pin Name
P100
I/O
I/O
Function
At Reset
Port 10.
P101
3-bit I/O port.
P102
I/O
Port 12.
TX0Note 2
RX0Note 2
5-bit I/O port.
P122-P124
Can be set in input or output mode in 1-bit units.
Output
FMIFC
Input
P121
P130
–
AMIFC
Can be set in input or output mode in 1-bit units.
P120
Shared by:
Input
Port 13.
–
Low-level
output
P131
8-bit output port.
P132-P137
N-ch open-drain output port (15 V withstand)
TO50
TO51
–
Notes 1. µPD178076 and 178078 only.
2. µPD178096 and 178098 only.
1.2 Pins Other Than Port Pins (1/2)
Pin Name
INTP0-INTP7
I/O
Input
Function
At Reset
External maskable interrupt input whose valid edge
Shared by:
Input
P00-P07
Input
P25/SB0/SDA0
(rising edge, falling edge, or both rising and falling edges)
can be specified.
SI0
Input
Serial data input to serial interface.
SI1
P20
SI3
P70
SO0
Output
Serial data output from serial interface.
Input
SO1
SO3
SB0
P26/SB1/SDA1
P21
P71
I/O
SB1
Serial data input/output to/from
N-ch open drain I/O
Input
serial interface.
P25/SI0/SDA0
P26/SO0/SDA1
SDA0
P25/SI0/SB0
SDA1
P26/SO0/SB1
SCK0
I/O
Serial clock input/output to/from serial interface.
Input
SCK1
P27/SCL
P22
SCK3
P72
SCL
N-ch open drain I/O
STB
Output
Strobe output for serial interface automatic transmission/
BUSY
Input
Busy input for serial interface automatic transmission/
VW45
Output
TI00
Input
P27/SCK0
Input
P23
Input
P24
V DD = 4.5 V monitor output
Input
P30
External count clock input to 16-bit timer 0.
Input
reception.
reception.
TI01
TI50
TI51
12
P32
P33
Input
External count clock input to 8-bit timer 50.
External count clock input to 8-bit timer 51.
Data Sheet U12885EJ3V0DS00
Input
P34
P35
µPD178076, 178078, 178096, 178098
1.2 Pins Other Than Port Pins (2/2)
Pin Name
TO0
I/O
Output
Function
At Reset
Shared by:
16-bit timer 0 output.
Input
P31
TO50
8-bit timer 50 output.
TO51
8-bit timer 51 output.
Low-level
output
P131
Buzzer output.
Input
BEEP0
Output
BUZ
P130
P36
P37
ANI0-ANI7
Input
Analog input to A/D converter.
EO0, EO1
Output
Error out output from charge pump of PLL frequency
VCOL
Input
Input
P10-P17
–
–
–
–
synthesizer.
Inputs local oscillation frequency of PLL (in HF and MF
modes).
VCOH
Input
Inputs local oscillation frequency of PLL (in VHF mode).
AMIFC
Input
Input to AM intermediate frequency counter.
Input
–
P101
–
FMIFC
Input
Input to FM intermediate frequency or AM intermediate
Input
P102
Input
P74
Input
P75
frequency counter.
RXD0
Input
Serial data input to asynchronous serial interface (UART0).
µPD178076 and 178078 only.
TXD0
Output
Serial data output from asynchronous serial interface
TX0
Output
IEBus controller data output. µPD178096 and 178098 only.
Input
P120
RX0
Input
IEBus controller data input. µPD178096 and 178098 only.
Input
P121
RESET
Input
System reset input.
X1
Input
Connection of crystal resonator for system clock oscillation.
(UART0). µPD178076 and 178078 only.
X2
–
REGOSC
–
Regulator for oscillation circuit. Connect this pin to GND via
–
–
–
–
–
–
–
–
–
–
0.1-µF capacitor.
REGCPU
–
Regulator for CPU power supply. Connect this pin to GND
VDD
–
Positive power supply.
–
–
GND0-GND2
–
Ground.
–
–
VDDPORT
–
Port power supply.
–
–
GNDPORT
–
Port ground.
–
–
AVDD
–
A/D converter positive power supply. Keep voltage at this
–
–
–
–
via 0.1-µF capacitor.
pin same as that at VDD.
AVSS
–
A/D converter ground. Keep voltage at this pin same as
that at GND0 through GND2.
VDDPLL Note
–
PLL positive power supply.
–
–
GNDPLLNote
–
PLL ground.
–
–
IC
–
Internally connected. Directly connect this pin to GND0,
–
–
GND1, or GND2.
Note
Connect a capacitor of about 1000 pF between the VDDPLL and GNDPLL pins.
Data Sheet U12885EJ3V0DS00
13
µPD178076, 178078, 178096, 178098
1.3 I/O Circuits of Pins and Recommended Connections of Unused Pins
Table 1-1 shows the types of the I/O circuits of the respective pins and the recommended connections of the pins
when they are not used.
For the configuration of the I/O circuit of each pin, refer to Figure 1-1.
Table 1-1. I/O Circuit Type of Each Pin (1/2)
Pin Name
I/O Circuit Type
I/O
Recommended Connection of Unused Pin
P00/INTP0-P07/INTP7
8
I/O
Input: Individually connect them to VDD, VDDPORT, GND0
to GND2, or GNDPORT via resistor.
Output: Leave open.
P10/ANI0-P17/ANI7
25
Input
Connect them to VDD, VDDPORT, GND0 to GND2, or
GNDPORT.
P20/SI1
5-K
I/O
Input: Individually connect them to VDD, VDDPORT, GND0
P21/SO1
5
P22/SCK1
5-K
P23/STB
5
P24/BUSY
5-K
P25/SI0/SB0/SDA0
10-D
to GND2, or GNDPORT via resistor.
Output: Leave open.
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/VM45
5
P31/TO0
P32/TI00
5-K
P33/TI01
P34/TI50
P35/TI51
P36/BEEP0
5
P37/BUZ
P40-P47
P50-P57
P60-P67
P70/SI3
5-K
P71/SO3
5
P72/SCK3
5-K
P73
5
P74/RXD0
5-K
P75/TXD0
5
P76, P77
P100
P101/AMIFC
P102/FMIFC
P120/TX0
P121/RX0
5-K
P122-P124
5
14
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Table 1-1. I/O Circuit Type of Each Pin (2/2)
Pin Name
P130/TO50
I/O Circuit Type
19
I/O
Output
Recommended Connection of Unused Pin
Open these pins.
P131/TO51
P132-P137
EO0
DTS-EO1
EO1
VCOL, VCOH
DTS-AMP2
REGOSC, REGCPU
RESET
AVDD
AVSS
Input
–
2
Disable PLL in software and select pull-down.
–
Connect these pins to GND0, GND1, or GND2 via 0.1-µF
capacitor.
–
Connect this pin to VDD or VDDPORT.
Input
–
–
Directly connect these pins to GND0 to GND2, or GNDPORT.
IC
Data Sheet U12885EJ3V0DS00
15
µPD178076, 178078, 178096, 178098
Figure 1-1. I/O Circuits of Respective Pins (1/2)
Type 5
Type 2
VDD
data
P-ch
IN/OUT
IN
output
disable
Schmitt trigger input with hysteresis characteristics
N-ch
input
enable
Type 8
Type 5-K
VDD
VDD
data
P-ch
data
P-ch
IN/OUT
IN/OUT
output
disable
N-ch
output
disable
N-ch
input
enable
Type 19
Type 10-D
VDD
data
P-ch
OUT
IN/OUT
open drain
output disable
N-ch
N-ch
input
enable
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as
VDDPORT and GNDPORT.
16
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Figure 1-1. I/O Circuits of Respective Pins (2/2)
Type 25
Type DTS-EO1
VDDPLL
P-ch
Comparator
+
DW
–
N-ch
VREF (Threshold voltage)
P-ch
IN
OUT
input
enable
UP
N-ch
GNDPLL
Type DTS-AMP
VDDPLL
IN
Note
GNDPLL
Note
This switch is selectable in software only for the VCOL and VCOH pins.
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as
VDDPORT and GNDPORT.
Data Sheet U12885EJ3V0DS00
17
µPD178076, 178078, 178096, 178098
2. MEMORY SPACE
Figure 2-1 shows the memory map of the µPD178076, 178078, 178096, and 178098.
Figure 2-1. Memory Map
FFFFH
Special function registers
(SFR)
FF00H
FEFFH
FEE0H
FEDFH
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
Cannot be used
FAE0H
FADFH
Data memory
space
Internal buffer RAM
nnnnH
Program area
32 × 8 bits
FAC0H
FABFH
1000H
0FFFH
Cannot be used
CALLF entry area
F800H
F7FFH
Internal extension
RAMNotes 1,3
mmmmH
mmmmH–1
0800H
07FFH
Program area
Cannot be usedNote 2
nnnnH+1
0080H
007FH
nnnnH
Program
CALLT table area
Internal ROMNotes 1, 3
0040H
003FH
memory space
Vector table area
0000H
0000H
Notes 1. The internal ROM and internal extension RAM capacities differ depending on the model (refer to the
table below).
Target Model Name
Internal ROM End Address
nnnnH
µPD178076, 178096
BFFFH
F400H
µPD178078, 178098
EFFFH
F000H
2. The µPD178078 and 178098 do not have this unusable area.
18
Internal Extension RAM First Address
mmmmH
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Note
3. The initial values of the memory size select register (IMS) and internal extension RAM size select
register (IXS) are CFH and 0CH, respectively. The following values must be set to the registers of
each model.
Part Number
IMS
IXS
µPD178076, 178096
CCH
0AH
µPD178078, 178098
CFH
08H
2.1 Memory Size Select Register (IMS)
This register is used to select the capacity of the internal memory.
Set CCH to this register of the µPD178076 and 178096. Set CFH to the IMS of the µPD178078 and 178098.
Use an 8-bit memory manipulation instruction to set the IMS.
This register is set to CFH at reset.
Figure 2-2. Format of Memory Size Select Register (IMS)
Symbol
7
6
5
4
IMS RAM2 RAM1 RAM0
RAM2
1
0
3
2
1
0
Address
At reset
R/W
FFF0H
CFH
R/W
Selects internal high-speed RAM capacity
1024 bytes
Setting prohibited
RAM3 RAM2
RAM1
RAM0
Selects internal ROM capacity
1
1
0
0
48K bytes
1
1
1
1
60K bytes
Others
0
ROM3 ROM2 ROM1 ROM0
RAM1 RAM0
Others
1
Setting prohibited
Data Sheet U12885EJ3V0DS00
19
µPD178076, 178078, 178096, 178098
2.2 Internal Extension RAM Size Select Register (IXS)
This register is used to select the capacity of the internal extension RAM.
Set 0AH of this register of the µPD178076 and 178096. Set 08H of the IXS of the µPD178078 and 178098.
Use an 8-bit memory manipulation instruction to set the IXS.
This register is set to 0CH at reset.
Figure 2-3. Format of Internal Extension RAM Size Select Register (IXS)
Symbol
7
6
5
IXS
0
0
0
4
3
2
1
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
20
Address
At reset
R/W
FFF4H
0CH
R/W
Selects internal extension RAM capacity
0
1
0
0
0
2048 bytes
0
1
0
1
0
1024 bytes
Others
0
Setting prohibited
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS
3.1 Ports
The following three types of ports are available:
• CMOS input (port 1)
: 8 pins
• CMOS I/O (ports 0, 2 through 7, 10, and 12)
: 64 pins
• N-ch open-drain output (port 13)
: 8 pins
Total
: 80 pins
Table 3-1. Port Functions
Name
Pin Name
Function
Port 0
P00-P07
I/O port. Can be set in input or output mode in 1-bit units.
Port 1
P10-P17
Input-only port.
Port 2
P20-P27
I/O port. Can be set in input or output mode in 1-bit units.
Port 3
P30-P37
I/O port. Can be set in input or output mode in 1-bit units.
Port 4
P40-P47
I/O port. Can be set in input or output mode in 1-bit units.
Port 5
P50-P57
I/O port. Can be set in input or output mode in 1-bit units.
Port 6
P60-P67
I/O port. Can be set in input or output mode in 1-bit units.
Port 7
P70-P77
I/O port. Can be set in input or output mode in 1-bit units.
Port 10
P100-P102
I/O port. Can be set in input or output mode in 1-bit units.
Port 12
P120-P124
I/O port. Can be set in input or output mode in 1-bit units.
Port 13
P130-P137
N-ch open-drain output port.
Data Sheet U12885EJ3V0DS00
21
µPD178076, 178078, 178096, 178098
3.2 Clock Generation Circuit
The instruction execution time can be changed as follows:
• 0.32 µs/0.64 µs/1.27 µs/2.54 µs/5.08 µs (system clock: 6.3-MHz crystal resonator)
• 0.44 µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (system clock: 4.5-MHz crystal resonator)Note
Note
When using the IEBus controller of the µPD178096 and 178098, the 4.5-MHz crystal resonator cannot
be used. Use the 6.3-MHz crystal resonator.
Figure 3-1. Block Diagram of Clock Generation Circuit
Prescaler
System
clock
oscillator
X2
Clock to other than
peripheral hardware
Prescaler
fX
fX
2
fX
22
fX
23
fX
24
Selector
X1
Standby
control
circuit
Wait
control
circuit
CPU clock
(fCPU)
3
STOP
0
0
0
0
0
PCC2 PCC1 PCC0
Processor clock control register (PCC)
Internal bus
3.3 Timers
Five timer channels are provided.
• Basic timer
: 1 channel
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watchdog timer
: 1 channel
Figure 3-2. Block Diagram of Basic Timer
6.3 MHz or
4.5 MHzNote
Note
Divider circuit
When using the IEBus controller of the µPD178096 and 178098, the 4.5-MHz crystal resonator cannot
be used. Use the 6.3-MHz crystal resonator.
22
INTBTM0
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Figure 3-3. Block Diagram of 16-Bit Timer/Event Counter
Internal bus
Noise
rejection
circuit
TI01/P33
Selector
CRC02 CRC01 CRC00
Selector
Capture/compare
control register 0
(CPU)
INTTM00
16-bit capture/compare
register 00 (CR00)
Coincidence
fX/23
Selector
fX/2
fX/22
fX/26
Noise
rejection
circuit
Clear
Output
control
circuit
Coincidence
2
TO0/P31
Output latch
(P31)
Noise
rejection
circuit
PM31
16-bit capture/compare
register 01 (CR01)
Selector
TI00/P32
16-bit timer counter 0
(TM0)
INTTM01
CRC02
PRM01PRM00
Prescaler mode
register 0 (PRM0)
TMC03 TMC02 TMC01 OVF0
16-bit timer
mode control
register 0 (TMC0)
Internal bus
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
Data Sheet U12885EJ3V0DS00
Timer output control
register 0 (TOC0)
23
µPD178076, 178078, 178096, 178098
Figure 3-4. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
Selector
S
Q
INV
8-bit timer counter OVF
50 (TM50)
R
INTTM50
Selector
Coincidence
Selector
TI50/P34
fX/2
fX/23
fX/25
fX/27
fX/29
fX/211
Mask circuit
8-bit compare
register 50 (CR50)
Clear
S
3
Selector
Output latch
(P130)
Level
inversion
R
TO50/P130
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
Timer mode control
register 50 (TMC50)
TCL502 TCL501 TCL500
Timer clock select
register 50 (TCL50)
Internal bus
Figure 3-5. Block Diagram of 8-Bit Timer/Event Counter 51
Coincidence
Selector
TI51/P35
fX/2
fX/23
fX/25
fX/27
fX/29
fX/211
Selector
S
Q
INV
8-bit timer counter OVF
51 (TM51)
R
Clear
S
3
R
Selector
Level
inversion
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
Timer clock select
register 51 (TCL51)
Timer mode control
register 51 (TMC51)
Data Sheet U12885EJ3V0DS00
TO51/P131
Output latch
(P131)
TCL512 TCL511 TCL510
Internal bus
24
INTTM51
Selector
8-bit compare
register 51 (CR51)
Mask circuit
Internal bus
µPD178076, 178078, 178096, 178098
Figure 3-6. Block Diagram of Watchdog Timer
fX/28
Clock input
control circuit
INTWDT
Divided clock
select circuit
Divider circuit
Output
control
circuit
RESET
RUN
Division mode
select circuit
3
WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation stabilization
time select register (OSTS)
WDCS2 WDCS1 WDCS0
Watchdog timer clock
select register (WDCS)
RUN
WDTM4 WDTM3
Watchdog timer mode
register (WDTM)
Internal bus
Data Sheet U12885EJ3V0DS00
25
µPD178076, 178078, 178096, 178098
3.4 Buzzer Output Control Circuit
Two types of buzzer output control circuits are provided.
• BEEP0 ... 1 kHz/1.5 kHz/3 kHz/4 kHz
• BUZ
... 0.77 kHz/1.54 kHz/3.08 kHz/6.15 kHz (system clock: 6.3-MHz crystal resonator)
Figure 3-7. Block Diagram of Buzzer Output Control Circuit (BEEP0)
1 kHz
1.5 kHz
Selector
BEEP0/P36
3 kHz
4 kHz
Output latch
(P36)
PM36
BEEP BEEP BEEP BEEP0 clock select
CL02 CL01 CL00 register (BEEPCL0)
Internal bus
Figure 3-8. Block Diagram of Buzzer Output Control Circuit (BUZ)
fX/210
fX/211
Selector
BUZ/P37
fX/212
fX/213
Output latch
(P37)
BZOE BCS1 BCS0
Clock output
select register (CKS)
Internal bus
Remark fX: System clock frequency
26
PM37
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
3.5 A/D Converter
An A/D converter with a resolution of 8 bits × 8 channels is provided.
Figure 3-9. Block Diagram of A/D Converter
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
Tap selector
Selector
Sample & hold circuit
Voltage comparator
AVSS
AVDD
ADCS3
Successive
approximation register
(SAR)
AVSS
INTAD
Control
circuit
A/D conversion result
register 3 (ADCR3)
4
ADS33 ADS32 ADS31 ADS30
ADCS3
0
Analog input channel specification
register 3 (ADS3)
FR32 FR31 FR30
0
0
0
Control Voltage
circuit comparator Power-fail compare threshold
value register 3 (PFT3)
PFEN3 PFCM3 PFHRM3
A/D converter mode register 3
(ADM3)
Power-fail compare mode register 3
(PFM3)
Internal bus
Data Sheet U12885EJ3V0DS00
27
µPD178076, 178078, 178096, 178098
3.6 Serial Interface
The µPD178076 and 178078 have four serial interface channels, and the µPD178096 and 178098 have three
channels.
• Serial interface 0
• Serial interface 1
• Serial interface 3
• Serial interface UART0: µPD178076 and 178078 only
Table 3-2. Types and Functions of Serial Interfaces
Function
3-wire serial I/O mode
3-wire serial I/O mode with
automatic transmit/receive
function
Serial interface 0
Serial interface 1
(MSB/LSB first
selectable)
(MSB/LSB first
selectable)
–
(MSB/LSB first
selectable)
Serial interface 3
(MSB first)
UART0Note
–
–
–
SBI (serial bus interface) mode
(MSB first)
–
–
–
2-wire serial I/O mode
(MSB first)
–
–
–
I2C bus mode
(MSB first)
–
–
–
–
–
UART (asynchronous serial
interface) mode
Note
28
–
µPD178076 and 178078 only.
Data Sheet U12885EJ3V0DS00
(Dedicated baud
rate generator)
Figure 3-10. Block Diagram of Serial Interface 0
Internal bus
Serial bus interface control
register 0 (SBIC0)
Serial operating mode register 0 (CSIM0)
CSIE0 COI WUP
CSIM CSIM CSIM CSIM
04
03
02
01
0
Slave address register 0
(SVA0)
Coincidence
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
SVAM
BSYE
Control circuit
SI0/SB0/SDA0/P25
Selector
P25
output latch
PM25
Serial I/O shift register
(SIO0)
CLR SET
D
Q
Output control
Note
SO0/SB1/SDA1/P26
Selector
Acknowledge
output circuit
PM26
P26 output latch
Note
Stop condition/
start condition/
acknowledge
detector
ACKD
CMDD
RELD
WUP
CLD
Interrupt request
signal generator
Serial clock
counter
SCK0/SCL/P27
INTCSI0
PM27
Output control
1/16
divider
Selector
Serial clock
control circuit
CSIM01
CSIM01
P27 output latch
Selector
2
CLD SIC SVAM CLC WREL WAT1 WAT0
4
SCL03 SCL02 SCL01 SCL00
Interrupt timing
specification register 0 (SINT0)
Internal bus
Note
Example in I2C bus mode operation.
Remark Output Control performs selection between CMOS output and N-ch open drain output.
fX/22-fX/29
Serial interface clock
select register 0 (SCL0)
29
µPD178076, 178078, 178096, 178098
Data Sheet U12885EJ3V0DS00
Output control
30
Figure 3-11. Block Diagram of Serial Interface 1
Internal bus
Automatic data transmit/
receive address pointer
register (ADTP)
Internal buffer RAM
Internal bus
Automatic data transmit/receive
interval specification register (ADTI)
ATE
Serial operating
mode register 1 (CSIM1)
DIR1
DIR1
ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Serial I/O shift register 1
(SIO1)
SI1/P20
Automatic data transmit/receive
control register (ADTC)
Coincidence
ADTI0-ADTI4
RE ARLD ERCE ERR TRF STRB BUSY1 BUSY0
CSIE1 DIR1
ATE LSCK1 SCL11 SCL10
TRF
P21 output latch
5-Bit counter
PM23
STB/P23
Handshake
BUSY/P24
ARLD
INTCSI1
SCK1/P22
PM22
SIO1 write
Clear
CSIE1
R
Selector
Selector
Serial clock counter
Q
S
LSCK1
P22 output latch
Selector
fX/24-fX/26
µPD178076, 178078, 178096, 178098
Data Sheet U12885EJ3V0DS00
Selector
PM21
SO1/P21
µPD178076, 178078, 178096, 178098
Figure 3-12. Block Diagram of Serial Interface 3
Internal bus
8
Serial I/O shift
register 3 (SIO3)
SI3/P70
PM71
SO3/P71
P71 output latch
SCK3/P72
PM72
Serial clock
counter
Interrupt request
signal generation
circuit
Serial clock
control circuit
Selector
INTCSI3
fX/24
fX/256
fX/2
P72 output latch
Figure 3-13. Block Diagram of Serial Interface UART0 (µPD178076 and 178078 only)
Internal bus
Asychronous serial interface
mode register 0 (ASIM0)
Receive buffer
register 0
(RXB0)
TXE0 RXE0 PS01 PS00 CL0
SL0 ISRM0
0
Asynchronous serial interface
status register 0 (ASIS0)
RXD0/P74
TXD0/P75
Receive shift
register 0
(RX0)
Reception
control circuit
PM75
(parity check)
P75 output latch
PE0
FE0 OVE0
Transmit shift
register
(TXS0)
INTSER0
INTSR0
Transmission
control circuit
(parity append)
INTST0
Baud rate
generator
fX/2-fX/28
TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00
Baud rate generator
control register 0 (BRGC0)
Internal bus
Data Sheet U12885EJ3V0DS00
31
µPD178076, 178078, 178096, 178098
3.7 IEBus Controller (µPD178096 and 178098 only)
The µPD178096 and 178098 have an IEBus controller. The functions of this IEBus controller are limited as
compared with the existing IEBus interface functions of the µPD78098 subseries.
Table 3-3 compares the interfaces of the µPD78098 subseries and µPD178098 subseries.
Table 3-3. Comparison of IEBus Interface (between µPD78098 Subseries and µPD178098 Subseries)
Item
µPD78098 Subseries IEBus
µPD178098 Subseries IEBus
Communication mode
Modes 0, 1, and 2
Fixed to mode 1
Internal system clock
fX = 6.0 (6.29) MHz
fX = 6.3 MHzNote
Internal buffer size
Transmit buffer: 33 bytes (FIFO)
Receive buffer: 40 bytes (FIFO)
Up to 4 frames can be received.
Transmit buffer: 1 byte
Receive buffer: 1 byte
CPU processing
Communication start processing
(data setting)
Setting and management of each
communication status
Writing data to transmit buffer
Reading data from receive buffer
Communication start processing
(data setting)
Setting and management of each
communication status
Writing data per 1 byte
Reading data per 1 byte
Management of transmission such as
slave status
Management of multiple frames, re-master
request processing
Hardware processing
Bit processing (modulation/demodulation,
error detection)
Field processing (generation/management)
Arbitration result detection
Parity processing (generation/error detection)
Automatic answering of ACK/NACK
Automatic data re-transmission processing
Automatic re-master processing
Transmission processing such as automatic
slave status
Multiple frame reception processing
Bit processing (modulation/demodulation,
error detection)
Field processing (generation/management)
Arbitration result detection
Parity processing (generation/error detection)
Automatic answering of ACK/NACK
Automatic data re-transmission processing
Note
The IEBus controller of the µPD178098 subseries operates at fX = 6.3 MHz, and not at fX = 4.5 MHz.
Remark fX: System clock frequency
32
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Figure 3-14. Block Diagram of IEBus Controller (µPD178096 and 178098 only)
CPU interface block
Internal registers
8
12
12
12
8
8
BCR0 (8)
UAR (12)
SAR (12)
PAR (12)
CDR (8)
DLR (8)
8
8
DR (8) USR (8)
8
8
12
12
12
8
8
8
8
8
8
ISR (8) SSR (8) SCR (8) CCR (8)
8
8
8
8
8
Internal bus
12
8
8
RX0/P121
NF
MPX
PSR (8 bits)
TX/RX
TX0/P120
MPX
12-bit latch
Interrupt
control
circuit
Comparator
Parity generation
error detection
Collision
detection
INT request
Interrupt control block
ACK
generation
IEBus interface block
5 Internal bus R/W
CLK
Bit processing block
Field processing block
Data Sheet U12885EJ3V0DS00
33
µPD178076, 178078, 178096, 178098
The IEBus mainly consists of the following six internal blocks:
• CPU interface block
• Interrupt control block
• Internal registers
• Bit processing block
• Field processing block
• IEBus interface block
<CPU interface block>
This block interfaces between the CPU (78K/0) and IEBus.
<Interrupt control block>
This block passes interrupt request signals from the IEBus to the CPU.
<Internal registers>
These are control registers that are used to control the IEBus and settings of each field.
<Bit processing block>
This block generates and disassembles bit timing, and mainly consists of a bit sequence ROM, 8-bit preset timer,
and decision unit.
<Field processing block>
This block generates each field in a communication frame and mainly consists of a field sequence ROM, 4-bit
down counter, and decision unit.
<IEBus interface block>
This is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register, collision
detector, parity detector, parity generation circuit, and ACK/NACK generation circuit.
34
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
3.8 PLL Frequency Synthesizer
Figure 3-15. Block Diagram of PLL Frequency Synthesizer
Internal bus
PLL mode
Select register
(PLLMD)
VCOH VCOL PLL PLL
DMD DMD MD1 MD0
PLL
data transfer
register (PLLNS)
2
2
fN
VCOH
Mixer
Input select
block
Programmable
divider
VCOL
Note 1
Voltage control
generator
PLL
NS0
PLL data register
(PLLRL, PLLRH, PLLR0)
6.3 MHz
or
4.5 MHzNote 2
fr
Phase
comparator
( φ - DET)
Reference
frequency
generator
EO1
Charge pump
EO0
Unlock
F/F
4
Note 1
Lowpass filter
PLL PLL PLL PLL
RF3 RF2 RF1 RF0
PLL reference
mode register
(PLLRF)
PLL
UL0
PLL unlock
F/F Judge register
(PLLUL)
Internal bus
Notes 1. These are external circuits.
2. When the IEBus controller of the µPD178096 and 178098 is used, the 4.5-MHz crystal resonator
cannot be used. Use the 6.3-MHz crystal resonator.
Data Sheet U12885EJ3V0DS00
35
µPD178076, 178078, 178096, 178098
3.9 Frequency Counter
Figure 3-16. Block Diagram of Frequency Counter
2
Gate time
control block
FMIFC/P102
IF counter
register
(IFCR)
block
Start/stop
control
block
Input select
block
AMIFC/P101
2
IFC IFC IFC IFC
MD1 MD0 CK1 CK0
IF counter
mode select
register (IFCMD)
IFC
JG0
IF counter
gate judge
register
Internal bus
36
Data Sheet U12885EJ3V0DS00
IFC IFC
ST RES
IF counter
control
register (IFCCR)
µPD178076, 178078, 178096, 178098
4. INTERRUPT FUNCTION
(1) µ PD178076 and 178078
The µPD178076 and 178078 have the following three types and 22 sources of interrupts:
• Non-maskable : 1Note
• Maskable
: 21Note
• Software
: 1
Note
Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and
either of them can be selected.
Table 4-1. Interrupt Sources (µPD178076 and 178078) (1/2)
Default
Interrupt Type PriorityNote 1
Interrupt Source
Name
Trigger
Internal/
External
Vector
Basic
Table
Configuration
Address TypeNote 2
Internal
0004H
Non-maskable
–
INTWDT
Overflow of watchdog timer
(when watchdog timer mode 1 is selected)
Maskable
0
INTWDT
Overflow of watchdog timer
(when interval timer mode is selected)
1
INTP0
Pin input edge detection
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTP6
0012H
8
INTP7
0014H
(A)
(B)
External
Internal
0006H
9
INTCSI0
End of transfer by serial interface 0
10
INTCSI1
End of transfer by serial interface 1
0016H
11
INTCSI3
End of transfer by serial interface 3
001AH
12
INTTM50
Generation of coincidence signal of 8-bit
timer/event counter 50
001CH
13
INTTM51 Generation of coincidence signal of 8-bit
timer/event counter 51
001EH
14
INTSER0 Reception error of serial interface UART0
0020H
15
INTSR0
End of reception by serial interface UART0
0022H
16
INTST0
End of transmission by serial interface
UART0
0024H
17
INTBTM0 Generation of coincidence signal of basic
timer
(C)
(B)
0018H
0026H
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1.
Data Sheet U12885EJ3V0DS00
37
µPD178076, 178078, 178096, 178098
Table 4-1. Interrupt Sources (µPD178076 and 178078) (2/2)
Default
Interrupt Type PriorityNote 1
Maskable
18
19
Internal/
External
Vector
Basic
Table
Configuration
Address TypeNote 2
Generation of signal indicating coincidence
between 16-bit timer counter (TM0) and
capture/compare register (CR00) (when
CR00 is used as compare register)
Internal
0028H
Detection of input edge of TI00/P32 pin
(when CR00 is used as capture register)
External
Interrupt Source
Name
INTTM00
Trigger
INTTM01 Generation of signal indicating coincidence
between 16-bit timer counter (TM0) and
capture/compare register (CR01) (when
CR01 is used as compare register)
Detection of input edge of TI01/P33 pin
(when CR01 is used as capture register)
Software
20
–
–
21
–
–
22
INTAD
End of conversion by A/D converter
–
BRK
Execution of BRK instruction
Internal
(D)
002AH
External
–
(B)
(B)
(D)
Note 3
–
Note 3
Internal
0030H
(B)
–
003EH
(E)
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1.
3. There are no interrupt sources corresponding to vector addresses 002CH and 002EH.
38
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
(2) µ PD178096 and 178098
The µPD178096 and 178098 have the following three types and 21 sources of interrupts:
• Non-maskable : 1Note
• Maskable
: 20Note
• Software
: 1
Note
Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and
either of them can be selected.
Table 4-2. Interrupt Sources (µPD178096 and 178098) (1/2)
Default
Interrupt Type PriorityNote 1
Interrupt Source
Name
Trigger
Non-maskable
–
INTWDT
Overflow of watchdog timer
(when watchdog timer mode 1 is selected)
Maskable
0
INTWDT
Overflow of watchdog timer
Internal/
External
Vector
Basic
Table
Configuration
Address TypeNote 2
Internal
0004H
(A)
(B)
(when interval timer mode is selected)
1
INTP0
Pin input edge detection
External
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTP6
0012H
8
INTP7
0014H
9
INTCSI0
End of transfer by serial interface 0
10
INTCSI1
End of transfer by serial interface 1
11
INTCSI3
End of transfer by serial interface 3
001AH
12
INTTM50
Generation of coincidence signal of 8-bit
timer/event counter 50
001CH
13
INTTM51
Generation of coincidence signal of 8-bit
timer/event counter 51
001EH
14
–
–
Internal
0006H
0016H
(C)
(B)
0018H
–
Note 3
15
–
–
Note 3
16
–
–
Note 3
17
INTBTM0
Generation of coincidence signal of basic
Internal
0026H
–
(B)
timer
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1.
3. There are no interrupt sources corresponding to vector addresses 0020H, 0022H, and 0024H.
Data Sheet U12885EJ3V0DS00
39
µPD178076, 178078, 178096, 178098
Table 4-2. Interrupt Sources (µPD178096 and 178098) (2/2)
Default
Interrupt Type PriorityNote 1
Maskable
18
19
Software
Internal/
External
Vector
Basic
Table
Configuration
Address TypeNote 2
Generation of signal indicating coincidence
between 16-bit timer counter (TM0) and
capture/compare register (CR00) (when
CR00 is used as compare register)
Internal
0028H
Detection of input edge of TI00/P32 pin
(when CR00 is used as capture register)
External
Interrupt Source
Name
INTTM00
Trigger
INTTM01 Generation of signal indicating coincidence
between 16-bit timer counter (TM0) and
capture/compare register (CR01) (when
CR01 is used as compare register)
Internal
Detection of input edge of TI01/P33 pin
(when CR01 is used as capture register)
External
Internal
(B)
(D)
002AH
(B)
(D)
20
INTIE1
IEBus0 data access request
21
INTIE2
IEBus0 communication error and start/end
of communication
002EH
22
INTAD
End of conversion by A/D converter AD1
0030H
(B)
–
BRK
Execution of BRK instruction
003EH
(E)
–
002CH
(B)
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1.
40
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Figure 4-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Interrupt
request
Vector table
address generation
circuit
Priority control
circuit
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR
ISP
Priority control
circuit
IF
Vector table
address generation
circuit
Standby release
signal
(C) External maskable interrupt (INTP0 through INTP7)
Internal bus
External interrupt
rising/falling edge enable
registers (EGP, EGN)
Interrupt
request
Edge detection
circuit
MK
IF
IE
PR
Priority control
circuit
ISP
Vector table
address generation
circuit
Standby release
signal
Data Sheet U12885EJ3V0DS00
41
µPD178076, 178078, 178096, 178098
Figure 4-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupts (INTTM00, INTTM01)
Internal bus
Prescaler mode register
(PRM0)
Interrupt
request
Edge detection
circuit
MK
IF
IE
PR
ISP
Priority control
circuit
Vector table
address generation
circuit
Standby release
signal
(E) Software interrupt
Internal bus
Interrupt
request
Priority control
circuit
Remark IF : Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
42
Data Sheet U12885EJ3V0DS00
Vector table
address generation
circuit
µPD178076, 178078, 178096, 178098
5. STANDBY FUNCTION
There are the following two standby functions to reduce the system power consumption.
• HALT mode : The CPU operating clock is stopped.
The average consumption current can be reduced by intermittent operation in combination with
the normal operating mode.
• STOP mode : The system clock oscillation is stopped. All operations by the system clock are stopped and
current consumption can be considerably reduced.
Figure 5-1. Standby Function
System Clock Operation
Interrupt
Request
HALT
Instruction
STOP
Instruction
Interrupt
Request
STOP Mode
(System clock
oscillation stopped)
HALT Mode
(Clock supply to CPU is
stopped, oscillation
continued)
6. RESET FUNCTION
There are the following three reset methods.
• External reset input by RESET pin
• Internal reset by watchdog timer hang-up time detection
• Internal reset by Power-On Clear (POC).
Data Sheet U12885EJ3V0DS00
43
µPD178076, 178078, 178096, 178098
7. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
Operand
[HL + byte]
#byte
First
Operand
A
r
Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B]
$addr16
1
None
[HL + C]
A
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
sfr
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
INC
DEC
DBNZ
B,C
!addr16
DBNZ
INC
DEC
MOV
PSW
MOV
MOV
PUSH
POP
MOV
ROR4
ROL4
[DE]
[HL]
[HL + byte]
[HL + B]
[HL + C]
MOV
X
MULU
C
DIVUW
Note
44
Except r = A
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
First Operand
AX
#word
AX
ADDW
SUBW
rp Note
MOVW
XCHW
sfrp
MOVW
saddrp
!addr16
MOVW
MOVW
SP
None
MOVW
CMPW
rp
MOVW
MOVW Note
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
SP
Note
MOVW
MOVW
MOVW
Only when rp = BC, DE or HL
Data Sheet U12885EJ3V0DS00
45
µPD178076, 178078, 178096, 178098
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
First Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
A.bit
CY
MOV1
sfr.bit
MOV1
$addr16
None
BT
SET1
BF
BTCLR
CLR1
BT
SET1
BF
CLR1
BTCLR
saddr.bit
MOV1
PSW.bit
MOV1
BT
SET1
BF
BTCLR
CLR1
BT
SET1
BF
CLR1
BTCLR
[HL].bit
CY
MOV1
MOV1
MOV1
MOV1
MOV1
SET1
AND1
AND1
AND1
AND1
AND1
CLR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
NOT1
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
First Operand
AX
BR
!addr16
CALL
BR
Compound
instruction
!addr11
CALLF
[addr5]
CALLT
$addr16
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
46
SET1
CLR1
MOV1
(4) Call instruction/branch instructions
Basic instruction
BT
BF
BTCLR
Data Sheet U12885EJ3V0DS00
µPD178076,178078,178096,178098
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T A = 25 °C)
Parameter
Rating
Unit
VDD
–0.3 to +6.0
V
VDDPORT
–0.3 to VDD + 0.3Note 1
V
AVDD
–0.3 to VDD + 0.3Note 1
V
VDDPLL
–0.3 to VDD + 0.3Note 1
V
Input voltage
VI
–0.3 to VDD + 0.3
V
Output voltage
VO
–0.3 to VDD + 0.3
V
Supply voltage
Output breakdown
Symbol
Conditions
Excluding P130 to P137
VBDS
P130-P137
N-ch open drain
16
V
Analog input voltage
VAN
P10-P17
Analog input pin
–0.3 to VDD + 0.3
V
High-level output
IOH
1 pin
–8
mA
Total of P00-P01, P20-P27, P50-P57, and P70-P73
–15
mA
Total of P02-P07, P30-P37, P40-P47, P60-P67,
–15
mA
–10
mA
Peak value
16
mA
r.m.s
8
mA
Total of P00-P01, P20-P27, P50-P57, Peak value
30
mA
and P70-P73
15
mA
Total of P02-P07, P30-P37, P40-P47, Peak value
30
mA
P60-P67, P74-P77, P120-P124, and
r.m.s
15
mA
Peak value
20
mA
r.m.s
10
mA
voltage
current
P74-P77, and P120-P124
Total of P100-P102
Low-level output
IOL Note 2 1 pin
current
r.m.s
P130-P137
Total of P100-102
Operating temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Notes 1. Keep the voltage at VDDPORT, AVDD, and VDDPLL same as that at the VDD pin.
2. Calculate the r.m.s as follows: [r.m.s] = [Peak value] x √Duty
Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality
of the product may be degraded. The absolute maximum ratings, therefore, are the values
exceeding which the product may be physically damaged. Be sure to use the product with these
ratings never being exceeded.
Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
Data Sheet U12885EJ3V0DS00
47
µPD178076,178078,178096,178098
Recommended Supply Voltage Ranges (TA = –40 to +85 °C)
Parameter
Supply voltage
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VDD1
When CPU and PLL are operating
4.5
5.0
5.5
V
VDD2
When CPU is operating and PLL is stopped
3.5
5.0
5.5
V
Data retention voltage
VDDR
When crystal oscillation stops
2.3
5.5
V
Output breakdown
VBDS
P130-P137 (N-ch open drain)
15
V
MAX.
Unit
voltage
DC Characteristics (TA = –40 to +85°C, V DD = 3.5 to 5.5 V)
Parameter
High-level input
voltage
Low-level input
Symbol
Test Conditions
MIN.
VIH1
P10-P17, P21, P23, P30, P31, P36, P37, P40-P47,
P50-P57, P60-P67, P71, P73, P75-P77, P100-P102,
P120, P122-P124
0.7 VDD
VDD
V
VIH2
P00-P07, P20, P22, P24-P27, P32-P35, P70, P72,
P74, P121, RESET
0.8 VDD
VDD
V
VIL1
P10-P17, P21, P23, P30, P31, P36, P37, P40-P47,
P50-P57, P60-P67, P71, P73, P75-P77, P100-P102,
P120, P122-P124
0
0.3 VDD
V
VIL2
P00-P07, P20, P22, P24-P27, P32-P35, P70, P72,
P74, P121, RESET
0
0.2 VDD
V
VOH1
P00-P07, P20-P24, P30-P37, 4.5 V ≤ VDD ≤ 5.5 V,
P40-P47, P50-P57, P60-P67, IOH = –1 mA
P70-P77, P100-P102,
3.5 V ≤ VDD < 4.5 V,
P120-P124
IOH = –100 µA
VDD – 1.0
V
VDD – 0.5
V
VDD – 1.0
V
voltage
High-level output
voltage
Low-level output
VOH2
EO0, EO1
VOH1
P00-P07, P20-P27, P30-P37, 4.5 V ≤ VDD ≤ 5.5 V,
P40-P47, P50-P57, P60-P67, IOL = 1 mA
P70-P77, P100-P102,
3.5 V ≤ VDD < 4.5 V,
P120-P124, P130-P137,
IOL = 100 µA
1.0
V
0.5
V
EO0, EO1
VDD = 4.5 to 5.5 V,
IOL = 3 mA
1.0
V
P00-P07, P10-P17,
P20-P24, P30-P37,
P40-P47, P50-P57,
P60-P67, P70-P77,
P100-P102, P120-P124,
VI = VDD
3
µA
voltage
VOL2
High-level input
leakage current
ILIH
VDD = 4.5 to 5.5 V,
IOH = –3 mA
TYP.
RESET
Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
48
Data Sheet U12885EJ3V0DS00
µPD178076,178078,178096,178098
DC Characteristics (TA = –40 to +85°C, V DD = 3.5 to 5.5 V)
Parameter
Symbol
Low-level input
Supply
currentNote
Unit
µA
ILOH1
P130-P137
VO = 15 V
–3
µA
ILOL1
P130-P137
VO = 0 V
3
µA
ILOH2
P25-P27
(at N-ch open drain I/O)
VO = VDD
–3
µA
ILOL2
P25-P27
(at N-ch open drain I/O)
VO = 0 V
3
µA
ILOH3
EO0, EO1
VO = VDD
–3
µA
ILOL3
EO0, EO1
VO = 0 V
3
µA
IDD1
When CPU is operating
and PLL is stopped.
Sine wave input to X1 pin
VI = VDD
fx = 4.5 MHz
(µPD178076, 178078)
2.5
15
mA
fx = 6.3 MHz
(µPD178076, 178078,
178096, 178098)
4.0
20
mA
In HALT mode with PLL
stopped.
Sine wave input to X1 pin
VI = VDD
fx = 4.5 MHz
(µPD178076, 178078)
0.2
0.8
mA
fx = 6.3 MHz
(µPD178076, 178078,
178096, 178098)
0.3
1.0
mA
5.5
V
IDD4
VDDR1
When crystal resonator is oscillating
3.5
VDDR2
When crystal oscillation is
stopped
Power-failure detection
function
2.2
V
Data memory retained
2.0
V
VDDR3
IDDR1
When crystal oscillation is
stopped
TA = 25°C,
VDD = 5 V
IDDR2
Note
MAX.
–3
IDD3
Data retention
current
TYP.
VI = 0 V
IDD2
Data retention
voltage
MIN.
P00-P07, P10-P17,
P20-P27, P30-P37,
P40-P47, P50-P57,
P60-P67, P70-P77,
P100-P102, P120-P124,
RESET
ILIL
leakage current
Output off
leakage current
Conditions
2.0
4.0
µA
2.0
20
µA
Excluding AVDD current and VDDPLL current.
Remarks 1. fX: System clock oscillation frequency
2. Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
Data Sheet U12885EJ3V0DS00
49
µPD178076,178078,178096,178098
Reference Characteristics (TA = –40 to +85°C, V DD = 4.5 to 5.5 V)
Parameter
Symbol
Supply current
IDD5
Conditions
MIN.
When CPU and PLL are operating.
Sine wave input to VCOH pin
At fIN = 160 MHz, VIN = 0.15 VP-P
TYP.
MAX.
5
Unit
mA
AC Characteristics
(1) Basic operation (T A = –40 to +85 °C, V DD = 3.5 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
(minimum instruction
execution time)
Conditions
At fX = 6.3 MHz
At fX = 4.5
TI00, TI01 input
high-/low-level
widths
tTIH0,
tTIL0
TI50, TI51 input
fTI5
MHzNote 1
MIN.
TYP.
MAX.
Unit
0.32
5.08
µs
0.44
7.11
µs
4/fsamNote 2
s
2
MHz
frequency
TI50, TI51 input
tTIH5,
high-/low-level
widths
tTIL5
Interrupt input
high-/low-level
widths
tINTH,
tINTL
RESET pin
low-level width
tRSL
INTP0-INTP7
200
ns
1
µs
10
µs
Notes 1. When the IEBus controller of the µPD178096 and 178098 is used, the 4.5-MHz crystal resonator
cannot be used. Use the 6.3-MHz crystal resonator.
2. fsam = fX/2, fX/4, f X/64 selectable by bits 0 and 1 (PRM00 and PRM01) of the prescaler mode register
0 (PRM0). However, fsam = f X/8 when the valid edge of TI00 is selected as the count clock.
50
Data Sheet U12885EJ3V0DS00
µPD178076,178078,178096,178098
(2) Serial interface (T A = –40 to +85°C, V DD = 3.5 to 5.5 V)
(a) Serial interface 0
(i) 3-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY1
tKH1,
Test Conditions
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKL1
SI0 setup time (to SCK0↑)
SI0 hold time (from SCK0↑)
SO0 output delay time from SCK0↓
Note
tSIK1
VDD = 4.5 to 5.5 V
tKSI1
tKSO1
C = 100 pF
MIN.
TYP.
MAX.
Unit
800
ns
1600
ns
tKCY1/2 – 50
ns
tKCY1/2 – 100
ns
100
ns
150
ns
400
ns
Note
300
ns
MAX.
Unit
C is the load capacitance of SCK0 and SO0 output line.
(ii) 3-wire serial I/O mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY2
tKH2,
Test Conditions
VDD = 4.5 to 5.5 V
TYP.
800
ns
1600
ns
400
ns
tKL2
800
ns
SI0 setup time (to SCK0↑)
tSIK2
100
ns
SI0 hold time (from SCK0↑)
tKSI2
400
ns
SO0 output delay time from SCK0↓
tKSO2
SCK0 at rising or falling edge time
tR2, tF2
Note
VDD = 4.5 to 5.5 V
MIN.
C = 100 pF
Note
300
ns
1000
ns
C is the load capacitance of SO0 output line.
Data Sheet U12885EJ3V0DS00
51
µPD178076,178078,178096,178098
(iii) SBI mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY3
tKH3,
Test Conditions
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKL3
SB0, SB1 setup time (to SCK0↑)
tSIK3
SB0, SB1 hold time (from SCK0↑)
tKSI3
SB0, SB1 output delay time from
tKSO3
VDD = 4.5 to 5.5 V
R = 1 kΩ
VDD = 4.5 to 5.5 V
C = 100 pF Note
SCK0↓
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
tKCY3/2 – 50
ns
tKCY3/2 – 150
ns
100
ns
300
ns
tKCY3/2
ns
0
250
ns
0
1000
ns
SB0, SB1↓ from SCK0↑
tKSB
tKCY3
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY3
ns
SB0, SB1 high-level width
tSBH
tKCY3
ns
SB0, SB1 low-level width
tSBL
tKCY3
ns
Note R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line.
(iv) SBI mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
tKCY4
tKH4,
Test Conditions
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKL4
SB0, SB1 setup time (to SCK0↑)
tSIK4
SB0, SB1 hold time (from SCK0↑)
tKSI4
SB0, SB1 output delay time from
tKSO4
VDD = 4.5 to 5.5 V
R = 1 kΩ
VDD = 4.5 to 5.5 V
C = 100 pF Note
SCK0↓
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
300
ns
tKCY4/2
ns
0
250
ns
0
1000
ns
SB0, SB1↓ from SCK0↑
tKSB
tKCY4
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY4
ns
SB0, SB1 high-level width
tSBH
tKCY4
ns
SB0, SB1 low-level width
tSBL
tKCY4
ns
SCK0 at rising or falling edge time
Note
52
tR4, tF4
1000
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
Data Sheet U12885EJ3V0DS00
ns
µPD178076,178078,178096,178098
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY5
SCK0 high-level width
tKH5
SCK0 low-level width
tKL5
SB0, SB1 setup time (to SCK0↑)
Test Conditions
R = 1 kΩ
C = 100 pF
Note
VDD = 4.5 to 5.5 V
tSIK5
VDD = 4.5 to 5.5 V
MIN.
TYP.
MAX.
Unit
1600
ns
tKCY5/2 – 160
ns
tKCY5/2 – 50
ns
tKCY5/2 – 100
ns
300
ns
350
ns
ns
SB0, SB1 hold time (from SCK0↑)
tKSI5
600
SB0, SB1 output delay time from
tKSO5
0
300
ns
SCK0↓
Note
R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line.
(vi) 2-wire serial I/O mode (SCK0 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY6
1600
ns
SCK0 high-level width
tKH6
650
ns
SCK0 low-level width
tKL6
800
ns
SB0, SB1 setup time (to SCK0↑)
tSIK6
100
ns
SB0, SB1 hold time (from SCK0↑)
tKSI6
tKCY6/2
ns
SB0, SB1 output delay time from
tKSO6
SCK0↓
C = 100 pF
SCK0 at rising or falling edge time
Note
R = 1 kΩ
VDD = 4.5 to 5.5 V
Note
0
300
ns
0
500
ns
1000
ns
tR6, tF6
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
Data Sheet U12885EJ3V0DS00
53
µPD178076,178078,178096,178098
(vii) I 2C Bus mode (SCL ... internal clock output)
Parameter
SCL cycle time
Symbol
tKCY7
Test Conditions
R = 1 kΩ
C = 100 pF
Note
MIN.
TYP.
MAX.
Unit
10
µs
tKCY7 – 160
ns
SCL high-level width
tKH7
SCL low-level width
tKL7
tKCY7 – 50
ns
SDA0, SDA1 setup time (to SCL↑)
tSIK7
200
ns
SDA0, SDA1 hold time
(from SCL↓)
tKSI7
0
ns
SDA0, SDA1 output delay time
tKSO7
VDD = 4.5 to 5.5 V
(from SCL↓)
0
300
ns
0
500
ns
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↑
tKSB
200
ns
SCL↓ from SDA0, SDA1↓
tSBK
400
ns
SDA0, SDA1 high-level width
tSBH
500
ns
Note
R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line.
(viii) I2 C Bus mode (SCL ... external clock input)
Parameter
SCL cycle time
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
tKCY8
1000
ns
tKH8, tKL8
400
ns
SDA0, SDA1 setup time (to SCL↑)
tSIK8
200
ns
SDA0, SDA1 hold time
(from SCL↓)
tKSI8
0
ns
SDA0, SDA1 output delay time
tKSO8
SCL high-/low-level width
from SCL↓
R = 1 kΩ
C = 100 pF
VDD = 4.5 to 5.5 V
Note
0
300
ns
0
500
ns
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↑
tKSB
200
ns
SCL↓ from SDA0, SDA1↓
tSBK
400
ns
SDA0, SDA1 high-level width
tSBH
500
ns
SCL at rising or falling edge time
Note
54
tR8, tF8
1000
R and C are the load resistance and load capacitance of SDA0 and SDA1 output line.
Data Sheet U12885EJ3V0DS00
ns
µPD178076,178078,178096,178098
(b) Serial interface 1
(i) 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY9
800
ns
SCK1 high/low-level width
tKH9,
tKL9
tKCY9/2 – 50
ns
SI1 setup time (to SCK1↑)
tSIK9
100
ns
SI1 hold time (from SCK1↑)
tKSI9
400
ns
SO1 output delay time (from SCK1↓)
tKSO9
Note
C = 100 pF Note
300
ns
MAX.
Unit
C is the load capacitance of SCK1 and SO1 output line.
(ii) 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
SCK1 cycle time
tKCY10
800
ns
SCK1 high/low-level width
tKH10,
tKL10
400
ns
SI1 setup time (to SCK1↑)
tSIK10
100
ns
SI1 hold time (from SCK1↑)
tKSI10
400
ns
SO1 output delay time (from SCK1↓)
tKSO10
C = 100 pF Note
SCK1 at rising or falling edge time tR10, tF10
Note
300
ns
1000
ns
C is the load capacitance of SO1 output line.
Data Sheet U12885EJ3V0DS00
55
µPD178076,178078,178096,178098
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock
output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY11
800
ns
SCK1 high/low-level width
tKH11,
tKL11
tKCY11/2 – 50
ns
SI1 setup time (to SCK1↑)
tSIK11
100
ns
SI1 hold time (from SCK1↑)
tKSI11
400
ns
SO1 output delay time (from SCK1↓)
tKSO11
C = 100 pF Note
300
ns
STB↑ from SCK1↑
tSBD
tKCY11/2 – 100
tKCY11/2 + 100
ns
Strobe signal high-level width
tSBW
tKCY11/2 – 30
tKCY11/2 + 30
ns
Busy signal setup time
tBYS
100
ns
Busy signal hold time
(from busy signal detection timing)
tBYH
100
ns
SCK1↓ from busy inactive
tSPS
200
ns
(to busy signal detection timing)
Note
C is the load capacitance of SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock
input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY12
800
ns
SCK1 high/low-level width
tKH12,
tKL12
400
ns
SI1 setup time (to SCK1↑)
tSIK12
100
ns
SI1 hold time (from SCK1↑)
tKSI12
400
ns
SO1 output delay time (from SCK1↓)
tKSO12
C = 100 pF Note
SCK1 at rising or falling edge time tR12, tF12
Note
56
C is the load capacitance of SO1 output line.
Data Sheet U12885EJ3V0DS00
300
ns
1000
ns
µPD178076,178078,178096,178098
(c) Serial interface 3
(i) 3-wire serial I/O mode (SCK3 ... internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK3 cycle time
tKCY13
800
ns
SCK3 high/low-level width
tKH13,
tKL13
tKCY13/2 – 50
ns
SI3 setup time (to SCK3↑)
tSIK13
100
ns
SI3 hold time (from SCK3↑)
tKSI13
400
ns
SO3 output delay time (from SCK3↓)
tKSO13
Note
C = 100 pF Note
300
ns
MAX.
Unit
C is the load capacitance of SCK3 and SO3 output line.
(ii) 3-wire serial I/O mode (SCK3 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
SCK3 cycle time
tKCY14
800
ns
SCK3 high/low-level width
tKH14,
tKL14
400
ns
SI3 setup time (to SCK3↑)
tSIK14
100
ns
SI3 hold time (from SCK3↑)
tKSI14
400
ns
SO3 output delay time (from SCK3↓)
tKSO14
C = 100 pF Note
SCK3 at rising or falling edge time tR14, tF14
Note
300
ns
1000
ns
MAX.
Unit
38400
bps
C is the load capacitance of SO3 output line.
(d) Serial interface UART0 (Dedicated baud rate generator output)Note
Parameter
Symbol
Test Conditions
Transfer rate
Note
MIN.
TYP.
µPD178076 and 178078 only.
Data Sheet U12885EJ3V0DS00
57
µPD178076,178078,178096,178098
AC Timing Test Point (Excluding X1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
TI Timing
tTIL0
tTIH0
TI00, TI01
1/fTI5
tTIL5
tTIH5
TI50,TI51
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP7
RESET Input Timing
tRSL
RESET
58
Data Sheet U12885EJ3V0DS00
µPD178076,178078,178096,178098
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tFn
tRn
SCK0, SCK1, SCK3
tSIKm
SI0, SI1, SI3
tKSIm
Input Data
tKSOm
SO0, SO1, SO3
Output Data
Remark m = 1, 2, 9, 10, 13, 14
n = 2, 10, 14
SBI mode (bus release signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tF4
tR4
SCK0
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
tKSI3, 4
SB0, SB1
tKSO3, 4
Data Sheet U12885EJ3V0DS00
59
µPD178076,178078,178096,178098
SBI mode (command signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tF4
tR4
SCK0
tSIK3, 4
tKSI3, 4
tSBK
tKSB
SB0, SB1
tKSO3, 4
2-wire serial I/O mode:
tKCY5, 6
tKL5, 6
tKH5, 6
tR6
tF6
SCK0
tSIK5, 6
tKSI5, 6
tKSO5, 6
SB0, SB1
I 2C bus mode:
tF8
tR8
tKCY7, 8
SCL
tKL7, 8
tKSI7, 8
tKH7, 8
tSIK7, 8
tKSO7, 8
SDA0, SDA1
tSBH
60
tSBK
Data Sheet U12885EJ3V0DS00
tKSB
tKSB
tSBK
µPD178076,178078,178096,178098
3-wire serial I/O mode with automatic transmit/receive function:
SO1
D2
SI1
D1
D2
D1
D0
D7
D0
D7
tKSI11, 12
tKH11, 12
tF12
tSIK11, 12
tKSO11, 12
SCK1
tR12
tSBD
tKL11, 12
STB
tSBW
tKCY11, 12
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
7
SCK1
8
9 Note
10 Note
tBYS
10 + n Note
tBYH
1
tSPS
BUSY
(Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
IEBus Controller CharacteristicsNote 1 (T A = –40 to +85°C, V DD = 3.5 to 5.5 V)
Parameter
IEBus system
clock frequency
Symbol
fs
Conditions
MIN.
TYP.
6.3Note 2
Fixed to mode 1
MAX.
Unit
MHz
Notes 1. µPD178096 and 178098 only.
2. Although the system clock frequency is 6.0 MHz in the IEBus standard, in these products, normal
operation is guaranteed at 6.3 MHz.
Remark 6.0 MHz and 6.3 MHz cannot both be used as the IEBus system clock frequency.
Data Sheet U12885EJ3V0DS00
61
µPD178076,178078,178096,178098
A/D Converter Characteristics (TA = –40 to +85°C, V DD = AV DD = 3.5 to 5.5 V)
Parameter
Symbol
Conditions
Resolution
Total conversion
MIN.
TYP.
MAX.
Unit
8
8
8
bit
±1.0
%FSR
±1.4
%FSR
VDD = 4.5 to 5.5 V
errorNotes 1, 2
Conversion time
tCONV
15.2
45.7
µs
Analog input voltage
VIAN
0
VDD
V
MAX.
Unit
Notes 1. Excluding quantization error (±0.2%FSR)
2. This value is indicated as a ratio to the full-scall value.
PLL Characteristics (T A = –40 to +85°C, V DD = 4.5 to 5.5 V)
Parameter
Operating
frequency
Symbol
Conditions
MIN.
TYP.
fIN1
VCOL pin, MF mode, sine wave input, VIN = 0.15 VP-P
0.5
3.0
MHz
fIN2
VCOL pin, HF mode, sine wave input, VIN = 0.15 VP-P
10
40
MHz
fIN3
VCOH pin, VHF mode, sine wave input, VIN = 0.15 VP-P
60
130
MHz
fIN4
VCOH pin, VHF mode, sine wave input, VIN = 0.3 VP-P
40
160
MHz
Remark The above values are the result of NEC’s evaluation of the device. If the device is likely to be affected
by noise in your application, it is recommended to use the device at a voltage higher than the above
values.
IFC Characteristics (T A = –40 to +85°C, V DD = 4.5 to 5.5 V)
Parameter
Operating
frequency
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
fIN5
AMIFC pin, AMIF count mode, sine wave input,
VIN = 0.15 VP-P
0.4
0.5
MHz
fIN6
FMIFC pin, FMIF count mode, sine wave input,
VIN = 0.15 VP-P
10
11
MHz
fIN7
FMIFC pin, AMIF count mode, sine wave input,
VIN = 0.15 VP-P
0.4
0.5
MHz
Remark The above values are the result of NEC’s evaluation of the device. If the device is likely to be affected
by noise in your application, it is recommended to use the device at a voltage higher than the above
values.
62
Data Sheet U12885EJ3V0DS00
µPD178076,178078,178096,178098
9. PACKAGE DRAWING
100-PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
S
C D
Q
R
31
30
100
1
F
G
J
H
I
M
P
K
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
23.6±0.4
B
20.0±0.2
C
14.0±0.2
D
17.6±0.4
F
0.8
G
H
0.6
0.30±0.10
I
0.15
J
K
L
0.65 (T.P.)
1.8±0.2
0.8±0.2
M
0.15+0.10
−0.05
N
0.10
P
2.7±0.1
Q
R
S
0.1±0.1
5°±5°
3.0 MAX.
P100GF-65-3BA1-4
Data Sheet U12885EJ3V0DS00
63
µPD178076,178078,178096,178098
10. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions.
For details of the recommended soldering conditions, refer to information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, consult NEC.
Table 10-1. Soldering Conditions for Surface-Mount Type
µPD178076GF-XXX-3BA: 100-pin plastic QFP (14 × 20)
µPD178078GF-XXX-3BA: 100-pin plastic QFP (14 × 20)
µPD178096GF-XXX-3BA: 100-pin plastic QFP (14 × 20)
µPD178098GF-XXX-3BA: 100-pin plastic QFP (14 × 20)
Soldering Method
Soldering Conditions
Recommended
Conditions Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 sec max. (210°C min.),
Number of times: 3 max.
IR35-00-3
VPS
Package peak temperature: 215°C, Time: 40 sec max. (200°C min.),
Number of times: 3 max.
VP15-00-3
Wave soldering
Solder bath temperature: 260°C max., Time: 10 sec max.,
Number of times: 1, Preheating temperature: 120°C max.,
(Package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max., Time: 3 sec max (per device side)
–
Caution Do not use two or more soldering methods in combination (except partial heating).
64
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD178078 and 178098
subseries.
Language processor software
RA78K/0Notes 1, 2, 3
Assembler package common to 78K/0 series
CC78K/0Notes 1, 2, 3
C compiler package common to 78K/0 series
DF178098Notes 1, 2, 3
Device file for µPD178078 subseries and µPD178098 subseries
CC78K0-LNotes 1, 2, 3
C compiler library source file common to 78K/0 series
Flash memory writing tools
Fashpro III
(Part number:
FL-PR3Note 4, PG-FL3)
Dedicated flash programmer
FA-100GF-3BANote 4
Flash programmer adapter
Debugging tools
• When in-circuit emulator IE-78K0-NS is used
IE-78K0-NS
In-circuit emulator common to 78K/0 series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PA
Performance board for enhancing and expanding the IE-78K0-NS function
IE-70000-98-IF-C
Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine
(C bus supported)
IE-70000-CD-IF-A
PC card and interface cable necessary when a notebook-type PC is used as host machine (PCMCIA
socket supported)
IE-70000-PC-IF-C
Interface adapter necessary when a IBM PC/ATTM compatible machine is used as host machine (ISA
bus supported)
IE-70000-PCI-IF
Interface adapter necessary when a PC with a PCI bus is used as host machine
IE-178098-NS-EM1
Emulation board to emulate µPD178078 and 178098 subseries
NP-100GFNote 4
Emulation probe for 100-pin plastic QFP (GF-3BA type)
EV-9200GF-100
Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type)
SM78K0Notes 1, 2
System simulator common to 78K/0 series
ID78K0-NSNotes 1, 2
Integrated debugger common to 78K/0 series
DF178098Notes 1, 2, 3
Device file for µPD178078 subseries and µPD178098 subseries
Notes 1. PC-9800 series (Japanese WindowsTM) based
2. IBM PC/AT compatible machine (Japanese/English windows) based
3. HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM, SolarisTM) based, NEWSTM
(NEWS-OSTM) based
4. Products of Naito Densei Machida Mfg. Co., Ltd. (Tel: 044-822-3813).
Remark Use the RA78K0, CC78K0, and SM78K0 in combination with the DF178098.
Data Sheet U12885EJ3V0DS00
65
µPD178076, 178078, 178096, 178098
• When in-circuit emulator IE-78001-R-A is used
IE-78001-R-A
In-circuit emulator common to 78K/0 series
IE-70000-98-IF-C
Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine
(C bus supported)
IE-70000-PC-IF-C
Interface adapter necessary when IBM PC/AT compatible machine is used as host machine (ISA
bus supported)
IE-70000-PCI-IF
Interface adapter necessary when a PC with a PCI bus is used as host machine
IE-78000-R-SV3
Interface adapter and cable necessary when EWS is used as host machine
IE-178098-NS-EM1
Emulation board to emulate µPD178078 and 178098 subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using IE-178098-NS-EM1 on IE-78001-R-A
EP-78064GF-R
Emulation probe for 100-pin plastic QFP (GF-3BA type)
EV-9200GF-100
Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type)
SM78K0Notes 1, 2
System simulator common to 78K/0 series
ID78K0Notes 1, 2
Integrated debugger common to 78K/0 series
DF178098Notes 1, 2, 3
Device file for µPD178078 subseries and µPD178098 subseries
Real-time OS
RX78K/0Notes 1, 2, 3
Real-time OS for 78K/0 series
MX78K0Notes 1, 2, 3
OS for 78K/0 series
Notes 1. PC-9800 series (Japanese Windows) based
2. IBM PC/AT compatible machine (Japanese/English windows) based
3. HP9000 series 700 (HP-UX) based, SPARCstation (SunOS, Solaris) based, NEWS (NEWS-OS)
based
Remark Use the SM78K0 in combination with the DF178098.
66
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Device Documents
Document No.
Title
Japanese
English
µPD178076, 178078, 178096, 178098 Data Sheet
U12885J
This document
µPD178F098 Data Sheet
U12920J
U12920E
µPD178078, 178098 Subseries User’s Manual
U12790J
U12790E
78K/0 Series User’s Manual - Instruction
U12326J
U12326E
U12704J
U12704E
78K/0 Series Application Note
Basics (I)
Development Tool Documents (User’s Manual)
Document No.
Title
Japanese
RA78K0 Assembler Package
English
Operation
U11802J
U11802E
Assembly Language
U11801J
U11801E
Structured Assembly
U11789J
U11789E
Operation
U11517J
U11517E
Language
U11518J
U11518E
IE-78001-R-A
U14142J
To be prepared
IE-78K0-NS
U13731J
U13731E
IE-178098-NS-EM1
U14013J
U14013E
EP-78064
EEU-934
EEU-1469
Language
CC78K0 C Compiler
SM78K0 System Simulator Windows Based
Reference
U10181J
U10181E
SM78K Series System Simulator
External Parts User
Open Interface
Specifications
U10092J
U10092E
ID78K0 Integrated Debugger EWS Based
Reference
U11151J
—
ID78K0 Integrated Debugger PC Based
Reference
U11539J
U11539E
ID78K0 Integrated Debugger Windows Based
Guide
U11649J
U11649E
ID78K0-NS Integrated Debugger Windows Based
Reference
U12900J
U12900E
Operation
U14379J
To be prepared
Caution The contents of the above documents are subject to change without notice. Please ensure that
the latest versions are used in design work, etc.
Data Sheet U12885EJ3V0DS00
67
µPD178076, 178078, 178096, 178098
Related Documents for Embedded Software (User’s Manual)
Document No.
Title
Japanese
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
English
Fundamental
U11537J
U11537E
Installation
U11536J
U11536E
Fundamental
U12257J
U12257E
Other Documents
Document No.
Title
Japanese
English
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Guides on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability and Quality Control
C10983J
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892J
C11892E
Semiconductor Device Quality/Reliability Handbook
C12769J
—
Microcomputer Product Series Guide
U11416J
—
Caution The contents of the above documents are subject to change without notice. Ensure that the
latest versions are used in design work, etc.
68
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
[MEMO]
Data Sheet U12885EJ3V0DS00
69
µPD178076, 178078, 178096, 178098
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material.
All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V DD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
Purchase of NEC I 2C components conveys a license under the Philips I2 C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
IEBus is a trademark of NEC Corporation.
Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT is a trademark of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
70
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U12885EJ3V0DS00
71
µPD178076, 178078, 178096, 178098
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4