NEC UPD9930G-22

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD9930
LINEAR CODEC FOR DIGITAL CELLULAR TELEPHONE
The µPD9930 is a +3 V single power operation, low power consumption linear CODEC LSI developed for digital
cellular telephone use.
CODEC has a wide dynamic use.
This IC also features a microphone/receiver amplifier, a tone generator, DAI (Digital Audio Interface: conforming
to GSM11.10), and a power-saving function. These functions can be controlled by microcontroller.
In addition, 21 mW (TYP.) low power consumption is enabled during 3 V operation.
FEATURES
• +3 V single power supply
• Low power consumption
In operation: 7 mA (TYP.) (VDD = 3 V)
In stand-by mode: 50 µA (TYP.) (VDD = 3 V)
• CODEC
• 13-bit precision linear coding
• Transmission level can be controlled by microcontroller.
• Analog input/output funciton
• Low noise microphone amplifier
• High output receiver amplifier
Piezo-electric receiver can be directly driven.
Gain canbe controlled by microcontroller.
• On-chip amplifier for accessory input/output
• Tone generator
• Frequency, generating pattern and gain can be controlled
by microcontroller.
• DTMF generation function
• Various service tone generation function
• GSM triple tone generation function
• Desired tone frequency can be registered (0.3 to 3.4 kHz)
• DAI
• Conforming to GSM11.10
• Test mode can be set by terminal or microcontroller
command.
• Stand-by mode
• Rise time at time of stand-by clearing: 30.5 ms (TYP.)
• Master clock generation PLL (external clock input: 8 kHz)
• Tone interrupt pattern output function
• Ringer output function
ORDERING INFORMATION
Part Number
µPD9930G-22
Package
44-pin plastic QFP (10 × 10 mm)
The information in this document is subject to change without notice.
Document No. S11616EJ2V0DS00 (2nd edition)
(Previous No. IC-3342)
Date Published November 1996 N
Printed in Japan
The mark
shows major revised points.
©
1994,1996
REQB
MICO
(15 to 33 dB)
MICI–
MICI+
(to XACOMO)
XAUXO
(0 to 10 dB)
XAUXI–
RAUXO
Digital signal processor
PLL
Microphone
amplifier
–
+
Pre-Filter
+ Mixer
0 or –3 dB
Voice send
Digital
Gain Cont.
0 to –2.8 dB
(0.4 dB steps)
A/D
REC2I–
DSP
INTERFACE
Receive
LPF
Post Filter 2
(Receiver amplifier 1)
0 to -31 dB
(1 dB steps)
Voice receive
Digital
Gain Cont.
0 to –2.4 dB
(0.8 dB steps)
Receiver drive amplifier
(Receiver amplifier 2)
–
+
MICROCONTROLLER
INTERFACE
Tone
Gain Cont.
0 to –30 dB
(1 dB steps)
–38.5 dB
Sign code
output
to Vref
DSPSEL
MSTR
MDAT
DCLK
DO
to Vref
XACOMI
XACOMO
Tone Interval
Generation
Vcombuff
MCLK
Tone
Generator
–
+
REC2O+
SO
SI
Post Filter 1
(Accessory output
amplifier)
0 dB fix
REC2O–
SCLK
(256 kHz)
SEN
Accessory input
amplifier
–
+
to Vref
D/A
REC1O
Transmit
BPF
FSYNC
(8 kHz)
BLOCK DIAGRAM
2
RESETB
MIXI
DAI
(GSM11. 10)
DI
TC1
TC2
Vref
RACOMO
RACOMI
DRSTB
µPD9930
TIMER
RINGER
Low-current drive LED
µPD9930
PIN CONFIGURATION (Top View)
REC2I–
ICNote
REC2O–
REC2O+
RACOMI
RACOMO
XACOMO
XACOMI
XAUXI–
XAUXO
MIXI
44-pin plastic QFP (10 x 10 mm)
33
32
31
30
29
28
27
26
25
24
23
MICI+
AVDD2
37
19
AGND4
DVDD
38
18
AGND3
SEN
39
17
AGND2
SI
40
16
AGND1
SO
41
15
DGND
SCLK
42
14
FSYNC
TEST
43
13
RESETB
MSTR
44
12
REQB
1
2
3
4
5
6
7
8
9
10
11
DSPSEL
20
RINGER
36
TIMER
AVDD1
TC2
MICI–
TC1
21
DCLK
35
DO
RAUXO
DI
MICO
DRSTB
22
MCLK
34
MDAT
REC1O
Note Internal connection; leave unconnected
3
µPD9930
Pin Name
AGND1-AGND4
4
: Analog Ground
AV DD1, AV DD2
: Analog Power Supply
DCLK
: DAI (Digital Audio Interface) Clock Output
DGND
: Digital Ground
DI
: DAI Serial Input
DO
: DAI Serial Output
DRSTB
: DAI Reset
DSPSEL
: Digital Signal Processor Select
DV DD
: Digital Power Supply
FSYNC
: Frame Synchronization Signal Input
IC
: Internally Connected
MCLK
: Microcontroller Synchronous Clock
MDAT
: Microcontroller Serial Data
MICI+
: Microphone Amplifier Input Non-Inverted
MICI–
: Microphone Amplifier Input Inverted
MICO
: Microphone Amplifier Output
MIXI
: Mixer Input
MSTR
: Microcontroller Strobe
RACOMI
: Receive Common Reference Voltage Input
RACOMO
: Receive Common Reference Voltage Output
RAUXO
: Receive Auxiliary Amplifier Output
REC1O
: Receive Amplifier 1 Output
REC2I–
: Receive Amplifier 2 Input Inverted
REC2O+
: Receive Amplifier 2 Output Non-Inverted
REC2O–
: Receive Amplifier 2 Output Inverted
REQB
: Request
RESETB
: Reset
RINGER
: Ringer
SCLK
: Serial Data Synchronous Clock Output
SEN
: Serial Data Output Enable
SI
: Serial Data Input
SO
: Serial Data Output
TC1, TC2
: DAI Mode Control
TEST
: Test
TIMER
: Timer
XACOMI
: Transmit Common Reference Voltage Input
XACOMO
: Transmit Common Reference Voltage Output
XAUXI–
: Transmit Auxiliary Amplifier Input Inverted
XAUXO
: Transmit Auxiliary Amplifier Output
µPD9930
CONTENTS
1. PIN FUNCTIONS ........................................................................................................................... 6
1.1 LIST OF PIN FUNCTIONS ..................................................................................................................... 6
1.2 PIN EQUIVALENT CIRCUIT .................................................................................................................. 8
2. BLOCK FUNCTIONS ..................................................................................................................... 9
2.1 CODEC .................................................................................................................................................... 9
2.1.1 Audio Codec .............................................................................................................................. 9
2.1.2 Audio Analog Input .................................................................................................................. 9
2.1.3 Audio Analog Output ............................................................................................................. 10
2.1.4 Audio Digital Accessory Output ........................................................................................... 11
2.1.5 Audio Digital Signal Processor ............................................................................................ 11
2.1.6 Power Up/Down Control ........................................................................................................ 12
2.1.7 Microcontroller Interface ....................................................................................................... 18
2.1.8 DSP Interface .......................................................................................................................... 19
2.1.9 DAI (Digital Audio Interface) ................................................................................................. 22
3. TONE INTERVAL OUTPUT FUNCTION (TIMER TERMINAL) ................................................. 29
4. INTERNAL CONTROL FUNCTIONS ...........................................................................................30
4.1 SEND/RECEIVE GAIN CONTROL ...................................................................................................... 30
4.1.1 Voice Send Analog Gain/Receiver Amplifier 2 Control Register (TXGCR) .................... 32
4.1.2 Voice Receive Analog Gain Control Register (RXGCR) ................................................... 33
4.1.3 Voice Send/Receive Digital Gain Control Register (DGGSR) .......................................... 35
4.2 DIGITAL INPUT/OUTPUT CONTROL ................................................................................................. 37
4.2.1 Digital Signal Processing Control Register (DSPCR) ....................................................... 38
4.3 TONE CONTROL .................................................................................................................................. 40
4.3.1 Tone Frequency Selection Register (FRQSR) .................................................................... 43
4.3.2 Expanded Tone Registers (EXPR1, EXPR2) ....................................................................... 45
4.3.3 Tone Control Register (TONCR) ........................................................................................... 47
4.3.4 Tone Gain Control Register (TNGCR) ................................................................................. 48
4.4 TEST MODE CONTROL ...................................................................................................................... 50
4.4.1 Test Control Register (TSTCR) ............................................................................................. 52
5. ELECTRICAL CHARACTERISTICS ............................................................................................53
6. APPLIED CIRCUIT EXAMPLE .................................................................................................... 73
7. PACKAGE DRAWINGS ............................................................................................................... 74
8. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 75
5
µPD9930
1. PIN FUNCTIONS
1.1 LIST OF PIN FUNCTIONS
Table 1-1 List of Pin Functions (1/2)
Pin No.
Pin Name
Input/Output
1
MDAT
Input
Microcontroller interface serial input
Function
2
MCLK
Input
Microcontroller interface clock input
3
DRSTB
Input
DAI (Digital Audio Interface) reset input
This is reset at low level. Internally pulled high.
4
DI
Input
DAI serial input
Internally pulled high.
5
DO
Output
6
DCLK
Output
7
TC1
Input
DAI serial output
Hi-Z in normal operation (TC1 = TC2 = low level)
8
TC2
Input
DAI clock output (104 kHz)
Hi-Z in normal operation
DAI mode control
Selection of test mode specified by
GSM11.10 in combination with TC1
and TC2
TC2
TC1
L
L
Normal operation
L
H
Speech encoder test mode
H
L
Speech decoder test mode
H
H
Acoustic device test mode
L: Low level
H: High level
Test mode specification
TC1 and TC2 pins are internally pulled down.
6
9
TIMER
Output
Timer output. Output of rectangular wave synchronized with tone intermittent
pattern.
10
RINGER
Output
Ringer tone output. Output of rectangular wave synchronized with tone frequency.
11
DSPSEL
Input
Selection of DSP interface input/output timing mode.
Connect to VDD or GND. (VDD = mode 1, GND = mode 2)
12
REQB
Input
Input of DSP interface data transmit request signal.
Serial data can be input/output at low level.
13
RESETB
Input
System reset input. This is reset at low level. Initializes all control registers.
Reset when turning power on.
14
FSYNC
Input
Send/receive frame synchronization signal (8 kHz) input
15
DGND
—
Digital ground. Connect to a digital ground line near µPD9930 pins.
16
AGND1
—
Analog ground. Connect to an analog ground line near µPD9930 pins.
17
AGND2
—
18
AGND3
—
19
AGND4
—
20
MICI+
Input
Microphone amplifier non-inverted input
21
MICI–
Input
Microphone amplifier inverted input
22
MICO
Output
23
MIXI
Input
24
XAUXO
Output
Microphone amplifier output. Connect microphone amplifier gain adjust resistor.
Outputs sidetone signal to REC2I- pin.
Pre-filter + mixer input
Accessory input amplifier output. Connect accessory input amplifier gain adjust
resistor.
µPD9930
Table 1-1 List of Pin Functions (2/2)
Pin No.
Pin Name
Input/Output
Function
25
XAUXI–
Input
Accessory input amplifier inverted input
26
XACOMI
Input
Voice send internal reference voltage input
27
XACOMO
Output
Voice send internal reference voltage (1.2 V) output
28
RACOMO
Output
Voice receive internal reference voltage (1.2 V) output
29
RACOMI
Input
30
REC2O+
Output
31
REC2O–
Output
32
IC
—
33
REC2I–
Input
34
REC1O
Output
35
RAUXO
Output
36
AVDD1
—
37
AVDD2
—
38
DVDD
—
39
SEN
Output
40
SI
Input
Voice receive internal reference voltage input
Receiver amplifier 2 non-inverted output
Receiver amplifier 2 inverted output
Internal connection; leave unconnected
Receiver amplifier 2 inverted input
Connect sidetone gain adjust resistor.
Receiver amplifier 1 output
Accessory output amplifier output
Analog power. Connect to an analog power supply line near µPD9930 pins.
Digital power. Connect to a digital power supply line near µPD9930 pins.
DSP interface enable signal output
DSP interface serial input
41
SO
Output
DSP interface serial output
42
SCLK
Output
DSP interface clock output (256 kHz)
43
TEST
Input
Set at high level
44
MSTR
Input
Microcontroller interface strobe signal input
Caution Short-circuit the XACOMI and XACOMO pins at a location as close to the pins of the µPD9930 as
possible. Connect a capacitor (chip capacitor or electrolytic capacitor) between this short-circuited
portion and analog ground.
The same applies to the RACOMI and RACOMO pins.
The transmission/reception level is determined by these reference pins. Therefore, make sure that
these pins are not affected by noise or fluctuation of ground potential due to current.
7
µPD9930
1.2 PIN EQUIVALENT CIRCUIT
Type 1
Type 2
AVDD
AVDD
Analog input
Analog input
To internal circuit
To internal circuit
AGND
AGND
Pin Name MICI+, MICI–, XAUXI–, REC2I–
Pin Name MIXI, XACOMI, RACOMI
AVDD
Type 3
DVDD
Type 4
Analog output
CMOS input
From internal circuit
To internal
circuit
AGND
DGND
Pin Name MICO, XAUXO, XACOMO, RACOMO,
REC2O+, REC2O–, REC1O, RAUXO
Type 6
DVDD
Type 5
Pin Name MDAT, MCLK, DSPSEL, REQB,
RESETB, FSYNC, TEST, MSTR
Note
DVDD
Mask input
CMOS input
To internal
circuit
CMOS input
To internal
circuit
DGND
DGND
Pin Name SI
Type 7 Note
Pin Name TC1, TC2
Type 8
DVDD DVDD
DVDD
P
CMOS output
CMOS input
To internal
circuit
N
DGND
DGND
Pin Name DRSTB, DI
Type 9
From internal
circuit
Pin Name TIMER, RINGER, SEN, SO, SCLK
DVDD
Enable signal
P
CMOS output
From internal
circuit
N
DGND
Pin Name DO, DCLK
Note In normal mode, set the output of drive IC side to high impedance for reducing power consumption.
8
µPD9930
2. BLOCK FUNCTIONS
2.1 CODEC
2.1.1 Audio Codec
Audio analog signal and linear code conversion.
• Input/output format: 16 bits (2's complement)
• Accuracy: 13 bits
2.1.2 Audio Analog Input
Includes microphone input and accessory input.
(1) Microphone amplifier
Amplifiers differential input signals from the microphone to the required gain.
(2) Accessory input amplifier
Amplifiers the accessory input signal to the required gain.
(3) Pre-filter + mixer
Selects the output signal of microphone amplifier and accessory input amplifier, and inputs these to A/D converter
after controlled gain.
Table 2-1 Analog Input Function
Amplifier
Microphone Amplifier
Function
Accessory Input Amplifier
Pre-filter + Mixer
Gain setting method
External resistor
External resistor
Microcontroller
command
Gain setting range
15 to 33 dB
R2
20 log
(dB)
R1
0 to 10 dB
R3
20 log
(dB)
R4
0 or –3 dB
Minimum resistive load
50 kΩ
(Including gain setting resistance)
300 kΩ
(Including gain setting resistance)
—
Maximum capacitive load
20 pF
20 pF
—
Maximum output level
0.6 V0-p
0.6 V0-p
—
Figure 2-1 Analog Input Block
MIXI
MICO
(15 to 33 dB)
R2
R1
MICI–
Microphone
amplifier
MICI+
–
+
R1
(to XACOMO)
(0 to 10 dB)
R3
Pre-filter +
mixer
0 or –3 dB
XAUXO
XAUXI–
R4
–
+
Accessory input amplifier
to Vref
9
µPD9930
2.1.3 Audio Analog Output
Includes receiver output and accessory output. Sidetone addition is also possible.
(1) Post filter 2 (receiver amplifier 1)
This circuit adjusts the gain of D/A differential output signal (volume control), and then converts it to single output
signal.
(2) Receiver drive amplifier (receiver amplifier 2)
This is differential output amplifier that can directly drive a piezo-electric receiver (when using a dynamic receiver,
an additional external amplifier is necessary). The sidetone is added in this circuit.
(3) Post filter 1 (accessory output amplifier)
This circuit converts D/A differential output signal to single output signal. Connected to the earphone of the head
set (capacitance load), etc.
Table 2-2 Analog Output Functions
Amplifier
Function
Receiver Amplifier 1
Receiver Amplifier 2
Accessory Output Amplifier
Gain setting method
Microcontroller command
External resistor
—
Gain setting range
0 to –31 dB (1 dB steps)
Voice receive signal gain:
– ∞ to + 10 dB
—
20 log R3 (dB) + 6 dBNote
R2
Sidetone signal gain:
– ∞ to + 3 dB
R3
20 log
(dB) + 6 dBNote
R1
Minimum resistive load
100 kΩ
2 kΩ
100 kΩ
Maximum capacitive load
20 pF
60 nF
100 pF
Maximum output level
0.6 V0-p
4 Vp-p (Differential output)
0.6 V0-p
Note Conversion result (single output → differential output)
Figure 2-2 Analog Output Block
RAUXO
REC1O
R2
Sidetone signal
R1
REC2I–
R3
REC2O–
REC2O+
Post filter 1
(accessory output
amplifier)
0 dB fix
Post filter 2
(receive amplifier 1)
0 to –31 dB
(1 dB steps)
Receiver drive amplifier
(receiver amplifier 2)
–
+
to Vref
–
+
to Vref
10
µPD9930
2.1.4 Audio Digital Accessory Output
(1) Ringer output (RINGER pin)
• Outputs rectangular waves of the same signal frequency as tone signal frequency.
• The output is controlled by turning off power to the output buffer with a control register.
Figure 2-3 RINGER Output
RAUXO
(Tone output)
RINGER
The RINGER signal tends to bounce when the tone output (RAUXO) signal crosses its zero level, and this
tendency increases as the tone output gain decreases (lower than 0 dB).
When using RINGER pin, tune the tone output gain by TNGCR (Tone gain control register) to 0 dB.
(2) Timer (tone interval) output (TIMER pin)
Outputs rectangular waves of the same pattern as the tone signal interrupt pattern. This is used to make the
LED blink in synchronization with the ringer tone.
Figure 2-4 Digital Accessory Output Waveform
REC10
RAUXO
(Tone output)
RINGER
TIMER
2.1.5 Audio Digital Signal Processor
Send signal digital BPF processing, receive signal digital LPF processing, transmission level (digital gain)
control, and tone generation processing.
(1) Voice send signal digital gain fine adjustment function
Performs gain fine adjustment for voice send signal by digital coefficient multiplication. Together with prefilter
gain adjustment, fine adjustment is possible at a width of 5.8 dB.
(2) Voice receive signal digital gain fine adjustment function
Performs fine adjustment of gain for voice receive signal by digital coefficient multiplication.
(3) Tone generation function
Generates single-tone and dual-tone audible signals. Tone frequency, interrupt pattern, gain, generation/stop
can be controlled by microcontroller command. GSM triple tone can be generated by special command.
11
µPD9930
Table 2-3 Digital Gain Control Functions
Voice Send Signal Gain Control Voice Receive Signal Gain Control
Tone Gain Control
Gain setting method
Microcontroller command
Microcontroller command
Microcontroller command
Gain setting range
0 to –2.8 dB (0.4 dB steps)
0 to –2.4 dB (0.8 dB steps)
0 to –30 dB (1 dB steps), –38.5 dB
2.1.6 Power Up/Down Control
The µ PD9930 includes a power down function for reducing power consumption. Power down control is by
the two methods described below.
(1) Input/output amplifier power up/down control
Power up/down for both the input and output amplifiers can be controlled.
When the power down function is used for all input amplifiers, both pre-filter and A/D enter the power down state.
When the power down function is used for the accessory output amplifier and the receiver 1 amplifier, the D/A
also enters power down state.
(2) Stand-by mode
Low power consumption can be realized in the mode in which all chip operation is stopped. The stand-by mode
is set by power down command. Operation restarts by power up command.
The following control registers are used to enable the control described above.
Control Method
Registers Used
Power up/down control of input/output amplifier
(not including receiver amplifier 2)
Input/output amplifier control register (AMPCR)
Power up/down control of receiver amplifier 2
Send analog gain/receiver amplifier 2 control register (TXGCR)
Set/clear of standby mode
Power up control command (PUPCMD)
Power down control command (PDWCMD)
An outline diagram of power down control is shown in Figure 2-5.
12
µPD9930
Figure 2-5 Power Down Control
Register address
0
0
AMPCR
0
MICPDB XAUXPDB REC1PDB RAUXPDB RINGPDB
Register address
0
0
0
TXGCR
1
1
0
REC2PDB
TXAG
HEXNote
Power up command
0
1
1
1
1
0
—
M
L
—
78H
1EH
—
M
70H
HEXNote
Power down command
0
1
1
1
0
0
—
L
0EH
Note M: HEX value with MSB first L: HEX value with LSB first
PLL
Microphone input
–
+
Stand-by
Stand-by
"1" = Power ON
MICPDB
Pre-filter
+ mixer
A/D
to XACOMI
Accessory input
–
+
"1" = Power ON
XAUXPDB
to Vref
Accessory output
When all input amplifiers are
in the power down state,
these also enter power
down state.
Digital signal
processor
Stand-by
–
+
"1" = Power ON
RAUXPDB
D/A
Receiver 1
–
+
Stand-by
"1" = Power ON
REC1PDB
Receiver 2
–
+
When both accessory output
and receiver 1 amplifiers are
in the power down state, these
also enter power down state.
Stand-by
to Vref
"1" = Power ON
–
+
REC2PDB
to Vref
Ringer output
Stand-by
"1" = Ringer output
RINGPDB
Caution MICPDB and XAUXPDB cannot enter the power up state at the same time (MICPDB = XAUXPDB =
"1").
13
µPD9930
(3) Input/output amplifier control register (AMPCR)
This is a 5-bit register for power up/down control of each input/output amplifier (not including receiver amplifier
2), and for ringer output ON/OFF control.
Remark For information on power up/down control of receiver amplifier 2, refer to 4.1.1 Voice Send Analog Gain/
Receiver Amplifier 2 Control Register (TXGCR).
Figure 2-6 Input/Output Amplifier Control Register
Register address
MICPDB
AMPCR
D7
D6
D5
0
0
0
D4
D3
D2
D1
D0
MICPDB XAUXPDB REC1PDB RAUXPDB RINGPDB
Microphone amplifier power control
0
Power down
1
Power up
XAUXPDB Accessory input amplifier power control
0
Power down
1
Power up
REC1PDB Receiver amplifier 1 power control
0
Power down
1
Power up
RAUXPDB Accessory output amplifier power control
0
Power down
1
Power up
RINGPDB Ringer output control
0
Sets output at low level.
1
Output enable
Remarks 1. In the stand-by mode, all amplifiers enter the power down state regardless of input/output control register
settings. However, register contents are held unless reset or written, so when the stand-by mode is
cleared by power up command, the command prior to the stand-by mode is resumed.
2. The microphone and accessory amplifiers cannot enter the power up (D4 = D3 = "1") state at the same
time.
14
µPD9930
Table 2-4 Function Specification by Input/Output Amplifier Control Register
Register address
AMPCR
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
Microphone Accessory
Receiver
Accessory
amplifier input amplifier amplifier 1 output amplifier Ringer output
HEXNote
M
L
0
0
0
0
0
X
X
X
X
Stop
00H 00H
0
0
0
0
1
X
X
X
X
Output
01H 80H
0
0
0
1
0
X
X
X
O
Stop
02H 40H
0
0
0
1
1
X
X
X
O
Output
03H C0H
0
0
1
0
0
X
X
O
X
Stop
04H 20H
0
0
1
0
1
X
X
O
X
Output
05H A0H
0
0
1
1
0
X
X
O
O
Stop
06H 60H
0
0
1
1
1
X
X
O
O
Output
07H E0H
0
1
0
0
0
X
O
X
X
Stop
08H 10H
0
1
0
0
1
X
O
X
X
Output
09H 90H
0
1
0
1
0
X
O
X
O
Stop
0AH 50H
0
1
0
1
1
X
O
X
O
Output
0BH D0H
0
1
1
0
0
X
O
O
X
Stop
0CH 30H
0
1
1
0
1
X
O
O
X
Output
0DH B0H
0
1
1
1
0
X
O
O
O
Stop
0EH 70H
0
1
1
1
1
X
O
O
O
Output
0FH F0H
1
0
0
0
0
O
X
X
X
Stop
10H 08H
1
0
0
0
1
O
X
X
X
Output
11H 88H
1
0
0
1
0
O
X
X
O
Stop
12H 48H
1
0
0
1
1
O
X
X
O
Output
13H C8H
1
0
1
0
0
O
X
O
X
Stop
14H 28H
1
0
1
0
1
O
X
O
X
Output
15H A8H
1
0
1
1
0
O
X
O
O
Stop
16H 68H
1
0
1
1
1
O
X
O
O
Output
17H E8H
Remarks
At reset
Note M: HEX value with MSB first
L: HEX value with LSB first
Remark O: Power up
X: Power down
15
µPD9930
(4) Power up/down command (PUPCMD/PDWCMD)
The stand-by mode is set and cleared by the following two special commands. When resetting, the stand-by
mode is set.
Figure 2-7 Power Down Command (Sets to stand-by mode)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
X
X
PDWCMD
Remark X: Don't Care
Figure 2-8 Power Up Command (Clears stand-by mode)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
1
0
X
X
PUPCMD
Remark X: Don't Care
Power up/down timing
Power up command
Power down command
FSYNC
COUNT
0
1
2
3
238
239
240
241
0
ANAPWD
CLKPWD
DSPPWD
Remarks COUNT:
Internal counter (counts with an 8-kHz internal clock)
ANAPWD: Analog power down (power down when high)
CLKPWD: Clock power down (power down when high)
DSPPWD: Signal processing power down (power down when high)
16
0
µPD9930
(5) Power up/down sequence
(a) Power down sequence
Power down command execution
Digital signal processing (filter operation,
tone generation operation) operation stop
Clock (internal clock, serial clock) power down
Analog (PLL, all amplifiers) power down
(b) Power up sequence
Power up command execution
Analog and PLL operation start
PLL clock stabilization
Clock operation start
Digital signal operation start
Remarks 1. The DSP interface serial input/output operation does not stop or start when switching to power up/down.
2. Rising time from standby mode to normal operation mode is about 30.5 ms after execution of the power
up command.
3. FSYNC can be stopped at power down. However, input of the FSYNC clock is necessary during
operation and in the above sequence.
17
µPD9930
2.1.7 Microcontroller Interface
The µ PD9930 can control internal functions by microcontroller command. A clock synchronous serial I/O is
incorporated to receive command.
A clocked serial interface is provided to receive microcontroller commands. A microcontroller connection
example is shown in Figure 2-9. 8-bit length data is received by the serial clock (MCLK), serial input (MDAT),
and strobe input (MSTR) lines Note.
The timing chart is shown in Figure 2-10. By reading data to the internal shift register and setting MSTR
to high level at the MCLK rising point, it is latched to the internal control register. Data transfer must be made
with LSB first.
Note When 8 bits or more (9 MCLK clocks or more) data is input, the last 8-bit which is input immediately before
the active edge of MSTR is recognized as a control command.
Figure 2-9 Example of Connection with Microcontroller
µ PD9930
Microcontroller
Microcontroller I/F
Serial I/O
SO
MDAT
SCK
MCLK
PORT
MSTR
Figure 2-10 Microcontroller Interface Timing Chart
MCLK
MDAT
MSTR
18
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
µPD9930
2.1.8 DSP Interface
A clock synchronous serial I/O is built-in to exchange voice send/receive coding data with an external DSP.
16-bit data is transferred at 8 kHz by the serial clock (SCLK = 256 kHz), serial input (SI), serial output (SO),
and enable output (SEN) lines. The REQB is a terminal for allowing/inhibiting data transmission. There are
two modes for data input and output timing, and either can be selected by the DSPSEL terminal. Select the
mode matching the DSP serial interface input/output timing. Data format is as follows: Both SO output and SI
input are in 2's complement format with MSB first.
Figure 2-11 Data Format in DSP Interface
SO output
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Coding data (13 bits)
Sign bit
Invalid data
Remark A full code is output when the SO pin is +3.17 dBm0 (A/D 1.2 Vp-p).
SI input
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Coding data (15 bits)
Sign bit
Remark When a full code is input to the SI pin, the accessory output is 1.2 Vp-p.
Table 2-5 DSP Input/Output Timing Mode Selection
Pin input
Mode
DSPSEL
H
MODE1
L
MODE2
Table 2-6 Allowing Data Transmission
REQB pin Input
Data Transmission
L
Data transmission is allowed. Enable signal (SEN) is output at rising edge of FSYNC (8 kHz), and
data input/output is started.
H
Enable signal is not output and data are not input or output.
19
µPD9930
Figure 2-12 Example of Connection with DSP (Mode 1)
µ PD9930
DSP
DSP I/F
Serial I/O
SCK
SCLK
enable
SEN
SI
SO
SO
SI
PORT
REQB
VDD
DSPSEL Note
Note When using with mode 2, connect DSPSEL to GND.
20
FSYNC
8 kHz
µPD9930
Figure 2-13 DSP Interface Timing Chart
(a) Mode 1 (DSPSEL = VDD)
REQB
125 µ s
FSYNC
(8 kHz)
SEN
SCLK
(256 kHz)
SO
SI
don't care
D15
D14
D2
D1
D0
D15
D14
D2
D1
D0
don't care
D15
D14
D13
D15
D14
D13
D15
D14
D13
(b) Mode 2 (DSPSEL = GND)
REQB
125 µ s
FSYNC
(8 kHz)
SEN
SCLK
(256 kHz)
D15
SO
SI
don't care
D14
D15 D14
D13
D2
D2
D1
D1
D0
D0
don't care
D15
D14
D13
D12
21
µPD9930
2.1.9 DAI (Digital Audio Interface)
Has a on-chip circuit enabling DAI functions specified in GSM11.10. The receive system has a on-chip LPF
only. If a BPF is necessary, it should be mounted externally. System configuration at the time of DAI test mode
is shown in Figure 2-15. The DAI terminal is connected to the system simulator via the pin 25 DSUB socket.
The test mode can be selected by terminals TC1 or TC2, or by microcontroller command. DAI mode should be
set after completing power-up operation (30.5 ms after executing power-up command).
When changing the modes from DAI to normal, either of the following operations should be executed.
• After specifying normal mode, input the DAI reset signal (DRSTB = low).
• Input reset signal (RESETB = low).
When specifying by command, test control register mode specification bits (ITC1, ITC2) are used (Refer to
4.4.1 Test Control Register (TSTCR).).
Timing for each mode is shown in Figures 2-16 through 2-20.
For operation at the time of each mode, refer to Figure 4-13 Test Mode Operation.
Table 2-7 DAI Test Mode Specification
TC2
TC1
(ITC2) (ITC1)
Test mode
specification
Function
0
0
Normal operationNote
Normal operation.
This mode is set at system reset (when RESETB = low) regardless of status of TC1
and TC2.
0
1
Speech encoder
test mode
Outputs data input from DI pin to DSP (speech encoder) from SO pin.
Input is started at rising edge of first FSYNC (8-kHz external clock input) after
execution of mode specification, and outputting data to DSP is started at next rising
edge of FSYNC.
1
0
Speech decoder
test mode
Outputs speech decoder output data input from SI pin from DO pin.
Inputting data from DSP is started at rising edge of first FSYNC (8-kHz external
clock input) after execution of mode specification, and data is output from DO pin at
next rising edge of FSYNC.
1
1
Acoustic device, A/D, Outputs audio data converted into digital signal from DO pin.
D/A test mode
Also inputs audio data input from DI pin to D/A converter. Inputting/outputting data
is started at rising edge of first FSYNC (8-kHz external clock input) after execution
of mode specification. At this time, clock output to DSP (SCLK) is stopped.
Note In the normal mode, do not set DRSTB to low level (during low period, serial interface with DSP is disabled).
As well, set the output pins of driver IC to high-impedance state, because DRSTB input pin is connected with
a pull-up resistor.
Remark Analog loop back mode and DAI test mode cannot be specified at the same time.
DAI test mode is set with TC1, TC2 (or ITC1, ITC2) and DRSTB pins. DAI test mode is entered at the rising
edge of the DRSTB signal when both TC1 and TC2 pins (or ITC1 and ITC2 pins) are set as shown in Figure
2-14.
22
µPD9930
Figure 2-14 Latch Timing of TC1, TC2 (or ITC1, ITC2)
TC1 (ITC1)
TC2 (ITC2)
DRSTB
Figure 2-15 Example of System Configuration at Time of DAI Test Mode
Mobile equipment
µ PD9930
System simulator
FSYNC
25-Pin DSUB socket
DAI
DCLK
MCLK
MSTR
MDAT
8 kHz
Test command
Microcontroller
DO
DAI
DI
TC2
SCLK
SEN
SO
DRSTB
SI
REQB
TC1
DSP
(SP-CODEC)
Remark In the acoustic device test mode, REQB is ignored (both high and low levels). When DSPSEL = VDD (mode
1), SCLK and SEN are fixed to low, and when DSPSEL = GND (mode 2), fixed to high.
23
24
Figure 2-16 Speech Encoder Test Mode (DSP Interface = MODE 1) (TC1 = 1, TC2 = 0)
TC1 (ITC1)
TC2 (ITC2)
"L"
DRSTB
REQB
FSYNC
(8 kHz)
DCLK
(104 kHz)
DI
don't care
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D11
D10
D9
D8
D7
D6
D5
SCLK
(256 kHz)
SEN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
µPD9930
SO
Figure 2-17 Speech Encoder Test Mode (DSP Interface = Mode 2) (TC1 = 1, TC2 = 0)
TC1 (ITC1)
TC2 (ITC2)
"L"
DRSTB
REQB
FSYNC
(8 kHz)
DCLK
(104 kHz)
DI
don't care
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D11
D10
D9
D8
D7
D6
D5
SCLK
(256 kHz)
SEN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
25
µPD9930
SO
26
Figure 2-18 Speech Decoder Test Mode (DSP Interface = Mode 1) (TC1 = 0, TC2 = 1)
TC1 (ITC1)
"L"
TC2 (ITC2)
DRSTB
REQB
FSYNC
(8 kHz)
SCLK
(256 kHz)
SEN
SI
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DCLK
(104 kHz)
D12
D11
D10
D9
D8
D7
D6
D5
µPD9930
DO
Figure 2-19 Speech Decoder Test Mode (DSP Interface = Mode 2) (TC1 = 0, TC2 = 1)
TC1 (ITC1)
"L"
TC2 (ITC2)
DRSTB
REQB
FSYNC
(8 kHz)
SCLK
(256 kHz)
SEN
SI
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DCLK
(104 kHz)
D12
D11 D10
D9
D8
D7
D6
D5
27
µPD9930
DO
28
Figure 2-20 Acoustic Device Test Mode (DSP Interface = Mode 1) (TC1 = 1, TC2 = 1)
TC1 (ITC1)
TC2 (ITC2)
DRSTB
REQB
FSYNC
(8 kHz)
SCLK
(256 kHz)
Note
DCLK
(104 kHz)
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D11
D10
D9
D8
D7
D6
D5
DO
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D11
D10
D9
D8
D7
D6
D5
Note In DSP Interface = Mode 2, SCLK is fixed to high.
µPD9930
DI
µPD9930
3. TONE INTERVAL OUTPUT FUNCTION (TIMER TERMINAL)
When a tone is generated, an interval signal that indicates the tone intermittent state is output. The function
is used, for example, to make the LED blink in synchronization with the ringer tone.
Figure 3-1 Tone Interval Output Waveform
Tone generation
(1) Continuous tone
Tone generation Tone stop
(31.25 ms) (31.25 ms)
(2) Intermittent tone
(when 31.25 ms on/off)
Tone generation
(200 ms)
(3) One-shot tone
(200 ms one-shot)
Tone generation Tone stop
(1 s)
(1 s)
(4) GSM triple tone
29
µPD9930
4. INTERNAL CONTROL FUNCTIONS
The µ PD9930 can control internal functions by commands from a microcontroller. Commands consist of 8bit data (D7 to D0) consisting of register address and setting data, and are written in the following internal
registers.
Register name
Control
(1)
(2)
(3)
Voice send analog gain/receiver amplifier 2 control register (TXGCR)
Voice receive analog gain control register (RXGCR)
Voice send/receive digital gain control register (DGGSR)
Voice send/receive gain control
(4)
Digital signal processing control register (DSPCR)
Digital input/output control
(5)
Tone frequency selection register (FRQSR)
Tone control
(6)
(7)
(8)
Expanded tone register (EXPR1/EXPR2)
Tone control register (TONCR)
Tone gain control register (TNGCR)
(9) Input/output amplifier control register (AMPCR)
(10) Power up control command (PUPCMD)
(11) Power down control command (PDWCMD)
Power up/down control
(12) Test control register (TSTCR)
Test mode control
Remarks 1. In the case of registers (1), (2), and (9) to (11), written contents are executed instantly.
2. For registers (3) to (8) and (12), since fetch execution is made by the internal clock (125 µs interval),
keep 125 µs or more interval for write-in to the same register.
If the write-in to the same register is executed continuously, the previous command may be ignored.
3. Even when in the stand-by mode, write-in to each internal register is possible (can be held), but the
command written in the register is executed only after clearing the stand-by mode.
4.1 SEND/RECEIVE GAIN CONTROL
An outline of send/receive gain control is shown in Figure 4-1.
With the µ PD9930, the following send and receive gain control is possible.
Send/receive gain control
Voice send gain
control
Voice receive gain
control
30
Register used
Pre-filter analog gain adjustment
(0, –3 dB)
Voice send analog gain/receiver amplifier 2
control register (TXGCR)
Digital gain fine adjustment
(0 to –2.8 dB, 0.4 dB steps)
Voice send/receive digital gain control register
(DGGSR)
Receiver amplifier 1 analog gain adjustment
(volume control) (0 to –31 dB, 1 dB steps)
Voice receive analog gain control register
(RXGCR)
Digital gain fine adjustment
(0 to –2.4 dB, 0.8 dB steps)
Voice send/receive digital gain control register
(DGGSR)
µPD9930
Figure 4-1 Send/Receive Gain Control
Register address
0
0
0
TXGCR
1
1
0
REC2PDB
TXAG
Digital signal-processor
0 to –2.8 dB
(0.4 dB steps)
Pre-filter/mixer
Microphone input
or
Accessory input
Voice send analog
gain control
Voice send digital
gain control
A/D
BPF
SO
0, –3 dB
Register address
0
1
DGGSR
0
RXDG1
RXDG0
TXDG2
TXDG1
TXDG0
Receiver amplifier 1
Voice receive analog
gain control
Receiver output
D/A
LPF
0 to –31 dB
(1 dB steps)
0
SI
0 to –2.4 dB
(0.8 dB steps)
Register address
0
Voice receive digital
gain control
RXGCR
1
RXAG4
RXAG3
RXAG2
RXAG1
RXAG0
31
µPD9930
4.1.1 Voice Send Analog Gain/Receiver Amplifier 2 Control Register (TXGCR)
This register controls pre-filter gain. It also controls receiver amplifier 2 power up/down as shown in Table
4-1 (Refer to 2.1.6 Power Up/Down Control).
When power is down, the contents of the register area retained. After power is up, control continues as before
power was down.
Figure 4-2 Voice Send Analog Gain/Receiver Amplifier 2 Control Register
Register address
REC2PDB
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
0
REC2PDB
TXAG
Receiver amplifier 2 power up/down specification
0
Power down
1
Power up
TXAG
TXGCR
Pre-filter analog gain specification
0
Sets to 0 dB
1
Sets to –3 dB
Table 4-1 Function Specification by Send Analog Gain/Receiver Amplifier 2 Control Register
Register address
HEXNote
TXGCR
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
1
1
Voice send analog gain
M
L
0
0
0
Power down
0 dB
18H 18H
0
0
1
Power down
–3 dB
19H 98H
0
1
0
Power up
0 dB
1AH 58H
0
1
1
Power up
–3 dB
1BH D8H
Note M: HEX value with MSB first
L: HEX value with LSB first
32
Receiver amplifier 2
Remarks
At reset
µPD9930
4.1.2 Voice Receive Analog Gain Control Register (RXGCR)
This is a 5-bit register for controlling the analog gain (volume) of receiver amplifier 1.
Figure 4-3 Voice Receive Analog Gain Control Register
Register address
RXGCR
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
RXAG4
RXAG3
RXAG2
RXAG1
RXAG0
RXAG4 to RXAG0 Receiver amplifier 1 gain specification
00000 to 11111 0 to –31 dB (1 dB steps)
33
µPD9930
Table 4-2 Function Specifications by Voice Receive Analog Gain Control Register
Register address
HEXNote
RXGCR
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
M
L
0
0
0
0
0
0 dB
20H 04H
0
0
0
0
1
–1 dB
21H 84H
0
0
0
1
0
–2 dB
22H 44H
0
0
0
1
1
–3 dB
23H C4H
0
0
1
0
0
–4 dB
24H 24H
0
0
1
0
1
–5 dB
25H A4H
0
0
1
1
0
–6 dB
26H 64H
0
0
1
1
1
–7 dB
27H E4H
0
1
0
0
0
–8 dB
28H 14H
0
1
0
0
1
–9 dB
29H 94H
0
1
0
1
0
–10 dB
2AH 54H
0
1
0
1
1
–11 dB
2BH D4H
0
1
1
0
0
–12 dB
2CH 34H
0
1
1
0
1
–13 dB
2DH B4H
0
1
1
1
0
–14 dB
2EH 74H
0
1
1
1
1
–15 dB
2FH F4H
1
0
0
0
0
–16 dB
30H 0CH
1
0
0
0
1
–17 dB
31H 8CH
1
0
0
1
0
–18 dB
32H 4CH
1
0
0
1
1
–19 dB
33H CCH
1
0
1
0
0
–20 dB
34H 2CH
1
0
1
0
1
–21 dB
35H ACH
1
0
1
1
0
–22 dB
36H 6CH
1
0
1
1
1
–23 dB
37H ECH
1
1
0
0
0
–24 dB
38H 1CH
1
1
0
0
1
–25 dB
39H 9CH
1
1
0
1
0
–26 dB
3AH 5CH
1
1
0
1
1
–27 dB
3BH DCH
1
1
1
0
0
–28 dB
3CH 3CH
1
1
1
0
1
–29 dB
3DH BCH
1
1
1
1
0
–30 dB
3EH 7CH
1
1
1
1
1
–31 dB
3FH FCH
Note M: HEX value with MSB first
L: HEX value with LSB first
34
Voice receive analog gain
Remarks
At reset
µPD9930
4.1.3 Voice Send/Receive Digital Gain Control Register (DGGSR)
This is a 5-bit register for adjusting the gain of the digital signal processor. The gain of the send system and
receive system can be fine-adjusted independently.
Figure 4-4 Send/Receive Digital Gain Control Register
Register address
DGGSR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
RXDG1
RXDG0
TXDG2
TXDG1
TXDG0
RXDG1 to RXDG0 Receive digital gain specification
00 to 11
0 to –2.4 dB (0.8 dB steps)
TXDG2 to TXDG0 Send digital gain specification
000 to 111
0 to –2.8 dB (0.4 dB steps)
35
µPD9930
Table 4-3 Function Specifications by Voice Send/Receive Digital Gain Control Register
Register address
DGGSR
D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
Voice send
HEXNote
digital gain
digital gain
M
Remarks
L
0
0
0
0
0
0 dB
0 dB
40H 02H
0
0
0
0
1
0 dB
–0.4 dB
41H 82H
0
0
0
1
0
0 dB
–0.8 dB
42H 42H
0
0
0
1
1
0 dB
–1.2 dB
43H C2H
0
0
1
0
0
0 dB
–1.6 dB
44H 22H
0
0
1
0
1
0 dB
–2.0 dB
45H A2H
0
0
1
1
0
0 dB
–2.4 dB
46H 62H
0
0
1
1
1
0 dB
–2.8 dB
47H E2H
0
1
0
0
0
–0.8 dB
0 dB
48H 12H
0
1
0
0
1
–0.8 dB
–0.4 dB
49H 92H
0
1
0
1
0
–0.8 dB
–0.8 dB
4AH 52H
0
1
0
1
1
–0.8 dB
–1.2 dB
4BH D2H
0
1
1
0
0
–0.8 dB
–1.6 dB
4CH 32H
0
1
1
0
1
–0.8 dB
–2.0 dB
4DH B2H
0
1
1
1
0
–0.8 dB
–2.4 dB
4EH 72H
0
1
1
1
1
–0.8 dB
–2.8 dB
4FH F2H
1
0
0
0
0
–1.6 dB
0 dB
50H 0AH
1
0
0
0
1
–1.6 dB
–0.4 dB
51H 8AH
1
0
0
1
0
–1.6 dB
–0.8 dB
52H 4AH
1
0
0
1
1
–1.6 dB
–1.2 dB
53H CAH
1
0
1
0
0
–1.6 dB
–1.6 dB
54H 2AH
1
0
1
0
1
–1.6 dB
–2.0 dB
55H AAH
1
0
1
1
0
–1.6 dB
–2.4 dB
56H 6AH
1
0
1
1
1
–1.6 dB
–2.8 dB
57H EAH
1
1
0
0
0
–2.4 dB
0 dB
58H 1AH
1
1
0
0
1
–2.4 dB
–0.4 dB
59H 9AH
1
1
0
1
0
–2.4 dB
–0.8 dB
5AH 5AH
1
1
0
1
1
–2.4 dB
–1.2 dB
5BH DAH
1
1
1
0
0
–2.4 dB
–1.6 dB
5CH 3AH
1
1
1
0
1
–2.4 dB
–2.0 dB
5DH BAH
1
1
1
1
0
–2.4 dB
–2.4 dB
5EH 7AH
1
1
1
1
1
–2.4 dB
–2.8 dB
5FH FAH
Note M: HEX value with MSB first
L: HEX value with LSB first
36
Voice receive
At reset
µPD9930
4.2 DIGITAL INPUT/OUTPUT CONTROL
An outline of digital input/output control is shown in Figure 4-5.
The µ PD9930 can control input and output of the digital signal processor as follows.
Digital input/output control
Registers used
Voice send data BPF operation processing execution/stop
Connection and disconnection to tone output Voice send/
receive system
Digital signal processing control register
(DSPCR)
Serial output terminal (SO) control
Serial input terminal (SI) control
Caution You must not connect nor disconnect tone output voice send/receive system in the tone operation.
It causes malfunction.
Figure 4-5 Digital Input/Output Control
DSPCR
Register address
0
1
1
0
TXACT
TNACT SOACT
Digital signal processor
DSP I/F
SOACT
TXACT
A/D
SIACT
BPF
1 = ON
SO
1
0
DGND
SIACT
LPF
D/A
0
1 = ON
SI
DGND
Note
TNACT
1
Tone
generator
Note Connected when TXACT = 0 and TNACT = 1.
37
µPD9930
4.2.1 Digital Signal Processing Control Register (DSPCR)
This is a 4-bit register for controlling digital signal processor input/output.
Figure 4-6 Digital Signal Processing Control Register
Register address
TXACT
DSPCR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
TXACT
TNACT
SOACT
SIACT
Voice send data processing control
0
Stops voice send data digital BPF processing.
1
Executes voice send data digital BPF processing.
TNACT
Tone output control
0
Disconnects tone output from voice send/receive systems.
1
Connects tone output to voice send/receive systems.
SOACT
DSP interface output control
Note
0
Sets serial output (SO) at low level
1
Outputs send data (or tone data) to the serial output (SO).
SIACT
.
DSP interface input control
Note
0
Sets serial input (SI) at low level
1
Inputs receive data to serial input (SI).
.
Note Test Control Register can set serial input/output terminal at low level, too (refer to 4.4.1 Test Control Register
(TSTCR)).
Caution Before specification of SOACT bit, be sure to write "0" for SIOOFF bit of Test Control Register.
If "0" isn't written for SIOOFF bit, serial output terminal is set at low level, regardless of SOACT bit.
38
µPD9930
Table 4-4 Function Specification by Digital Signal Processing Control Register
Register address
HEXNote
DSPCR
Serial output control
D7 D6 D5 D4 D3 D2 D1 D0
0
1
1
0
Control of output to D/A
M
L
0
0
0
0
Note 2
Note 3
60H 06H
0
0
0
1
Note 2
Voice receive signal output
61H 86H
0
0
1
0
0
0
1
1
0
1
0
0
Note 2
0
1
0
1
Note 2
0
1
1
0
Tone output
0
1
1
1
Tone output
1
0
0
0
1
0
0
1
1
0
1
0
Voice send signal output
Note 3
6AH 56H
1
0
1
1
Voice send signal output
Voice receive signal output
6BH D6H
1
1
0
0
Inhibiting command
—
—
1
1
0
1
Inhibiting command
—
—
1
1
1
0
Voice send signal output
1
1
1
1
Voice send signal output
Inhibiting command
Inhibiting command
Tone output
—
—
—
—
Remarks
At reset
64H 26H
Voice receive signal + tone output 65H A6H
Tone output
66H 66H
Voice receive signal + tone output 67H E6H
Inhibiting command
Inhibiting command
Tone output
—
—
—
—
6EH 76H
Voice receive signal + tone output 6FH F6H
Notes 1. M: HEX value with MSB first
L: HEX value with LSB first
2. Stops voice send data processing and serial output.
3. Stops voice receive data serial input and tone output.
39
µPD9930
4.3 TONE CONTROL
An outline diagram of the tone generator is shown in Figure 4-7. Tone generation is by the tone 1 oscillation
circuit and the tone 2 oscillation circuit.
The tone 1 oscillation circuit generates high group frequency for DTMF and four types of single tones (tone
1 frequency).
The tone 2 oscillation circuit generates low group frequency (tone 2 frequency) for DTMF. Dual tone is output
by adding tone 1 frequency.
In addition to registered tones, other frequencies can be registered. Also, GSM triple tone can be generated
by special command. Examples of tone generation are shown in Figure 4-8.
Tone control items are shown below.
Tone control
Tone frequency
Registered tone
User registration
tone
Registers used
Specification of DTMF
Tone frequency selection register
Single tone: 400 Hz, 425 Hz, 2 kHz, 2.6 kHz
(FRQSR)
Selection of GSM triple tone
Tone control register (TONCR)
Registration of desired tone in 0.3 to 3.4 kHz
range.
Tone frequency selection register
(FRQSR)
(Single tone, dual tone)
Expanded tone register 1
(EXPR1)
Expanded tone register 2
(EXPR2)
Generation pattern Registered
pattern
Desired pattern
Gain
40
31.25 ms intermittence, 200 ms intermittence,
250 ms intermittence, 500 ms intermittence,
1s intermittence, 200 ms one-shot tone
Tone control register
(TONCR)
Interrupted at desired interval by START/STOP
command
Control of tone output gain
0 to –30 dB (1 dB steps), –38.5 dB
Tone gain control register
(TNGCR)
Figure 4-7 Tone Control
FRQSR
Register address
1
0
0
FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
TNGCR
Register address
Tone 1 oscillation circuit
1
1
1
TNGAIN4 TNGAIN3 TNGAIN2 TNGAIN1 TNGAIN0
Tone 1 frequency
1209 Hz
1336 Hz
1477 Hz
1633 Hz
400 Hz
425 Hz
2000 Hz
2600 Hz
–6 dB
0 to –30 dB
(1-dB steps)
–38.5 dB
3.1 dBm0
LPF output (receive signal) (Only sign code)
Expanded tone register 1
Ringer output
Expanded tone 1 frequency
TNACTNote
To D/A
START/
STOP
Serial output
Tone 2 oscillation circuit
Timer output
Tone 2 frequency
697 Hz
852 Hz
Expanded tone 2 frequency
1
–9 dB
0
1
TNMODE
TNP2
TNP1
TNP0
START/
STOP
41
µPD9930
TONCR
Register address
1
Note Digital signal processing control
register bit 2 (Refer to Figure 4-6).
0
3.1 dBm0
Expanded tone register 2
Tone interval
generation
– ∞ dB
770 Hz
941 Hz
µPD9930
Figure 4-8 Tone Generation Examples
(a) When generating a busy tone
(b) When generating DTMF "7" with continuous tone
(400 Hz single tone, 500 ms intermittence)
Busy tone generation
Tone gain control register
DTMF "7" generation
Tone gain control register
Set tone gain.
Set tone gain.
Tone frequency selection register
Tone frequency selection register
Set frequency to 400 Hz.
Set frequency to DTMF "7".
Tone control register
Tone control register
Select single tone
Select 500 ms intermittent pattern.
START/STOP = "1" (start)
Select dual tone.
Select continuous tone.
START/STOP = "1" (start)
END
END
(c) When generating GSM triple tone
(d) When generating 200 ms intermittent user register tone (480 Hz single tone; coefficient =
0111011100B)
GSM triple tone generation
User register tone generation
Tone gain control register
Tone gein control register
Set tone gain.
Tone control register
Select single tone
Select GSM triple tone
START/STOP = "1" (start)
Set tone gain.
Tone frequency selection register
Specify "user register"
Expanded tone register 1
END
"100110" (registration command) +
registration data
(lower order 2 bits) setting
Expanded tone register 1
Registration data
(higher-order 8 bits) setting
Tone control register
Select single tone.
Select 200 ms intermittent pattern.
START/STOP = "1" (start)
42
END
µPD9930
4.3.1 Tone Frequency Selection Register (FRQSR)
This is a 5-bit register for specifying tone 1 (high group frequency for DTMF and four types of single tones)
and tone 2 (low group frequency for DTMF) frequency combinations.
Figure 4-9 Tone Frequency Selection Register
Register address
FRQSEL4 to FRQSEL0
00000 to 10100
FRQSR
D7
D6
D5
1
0
0
D4
D3
D2
D1
D0
FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
Tone frequency selection
Refer to Table 4-5 Function Specification by Tone Frequency Selection Register.
Write operation in this register is instantaneously executed and retained when a command is received, but
change of tone generation or generating tone is executed only when "1" is written for START/STOP control bit
of the tone control register (refer to Figure 4-11 Tone Control Register).
When a user registration tone is selected, the tone specified by the expanded tone register (refer to Figure
4-10 Expanded Tone Frequency Registration Procedure) is generated.
Caution Do not input a command that sets a tone oscillation frequency after inputting a tone oscillation
command (writing "1" to the START/STOP control bit of the tone control register).
43
µPD9930
Table 4-5 Function Specification by Tone Frequency Selection Register
Register address
HEXNote 1
FRQSR
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
DTMF function
Tone 1 frequency
Tone 2 frequency
M
L
0
0
0
0
0
DTMF “1”
1209 Hz
697 Hz
80H 01H
0
0
0
0
1
DTMF “2”
1336 Hz
697 Hz
81H 81H
0
0
0
1
0
DTMF “3”
1477 Hz
697 Hz
82H 41H
0
0
0
1
1
DTMF “A”
1633 Hz
697 Hz
83H C1H
0
0
1
0
0
DTMF “4”
1209 Hz
770 Hz
84H 21H
0
0
1
0
1
DTMF “5”
1336 Hz
770 Hz
85H A1H
0
0
1
1
0
DTMF “6”
1477 Hz
770 Hz
86H 61H
0
0
1
1
1
DTMF “B”
1633 Hz
770 Hz
87H E1H
0
1
0
0
0
DTMF “7”
1209 Hz
852 Hz
88H 11H
0
1
0
0
1
DTMF “8”
1336 Hz
852 Hz
89H 91H
0
1
0
1
0
DTMF “9”
1477 Hz
852 Hz
8AH 51H
0
1
0
1
1
DTMF “C”
1633 Hz
852 Hz
8BH D1H
0
1
1
0
0
DTMF “∗”
1209 Hz
941 Hz
8CH 31H
0
1
1
0
1
DTMF “0”
1336 Hz
941 Hz
8DH B1H
0
1
1
1
0
DTMF “#”
1477 Hz
941 Hz
8EH 71H
0
1
1
1
1
DTMF “D”
1633 Hz
941 Hz
8FH F1H
1
0
0
0
0
400 HzNote 2
Indefinite value
90H 09H
1
0
0
0
1
425 HzNote 2
Indefinite value
91H 89H
2 kHz
Note 2
Remarks
1
0
0
1
0
Indefinite value
92H 49H
1
0
0
1
1
2.6 kHzNote 2
Indefinite value
93H C9H At reset
1
0
1
0
0
User registration
User registration
94H 29H
1
0
1
0
1
Inhibiting command
—
—
1
0
1
1
0
Inhibiting command
—
—
1
0
1
1
1
Inhibiting command
—
—
Notes 1. M: HEX value with MSB first
L: HEX value with LSB first
2. This is single tone. When specifying this tone, be sure to specify the tone control register in the single tone
mode (refer to Figure 4-11 Tone Control Register).
Remark For DTMF tone generation, specify the tone control register in the dual tone mode (refer to Figure 4-11
Tone Control Register). If the register is specified in the single tone mode, only the high group tone (tone
1 frequency) is generated.
44
µPD9930
4.3.2 Expanded Tone Registers (EXPR1, EXPR2)
(1) Expanded Tone Frequency Registration Procedure
The µPD9930 can register desired tone frequencies (expanded tone frequencies) in 0.3 to 3.4 kHz range.
Expanded tone register 1 (EXPR1) is for registering expanded tone 1 frequency (high group frequency for DTMF
and single tone). Expanded tone register 2 (EXPR2) is for registering expanded tone 2 frequency (low frequency
for DTMF). The frequency must be specified by 10-bit coefficient (2's complement).
Registration of single tone is done with EXPR1 (single-tone generation is impossible by EXPR2) (refer to Figure
4-10 (a)).
When registering dual tone, set high group in EXPR1 and low group in EXPR2.
Write operation in this register can be executed by continuously writing the expanded tone registration command
and expanded tone data command (refer to Figure 4-10).
Once registered, the frequency is valid until reset or updated.
Figure 4-10 Expanded Tone Frequency Registration Procedure
(a) Expanded tone 1 frequency registration procedure
<1> Set expanded tone 1 registration command in EXPR1.
Expanded tone 1 registration command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
0
EA1
EA0
EXPR1
<2> Set higher-order 8 bits of expanded tone coefficient (expanded tone 1 data command) in EXPR1.
Expanded tone 1 data command
D7
D6
D5
D4
D3
D2
D1
D0
EA9
EA8
EA7
EA6
EA5
EA4
EA3
EA2
EXPR1
Remark EA9 to EA0: Tone 1 frequency 10-bit coefficient
(b) Expanded tone 2 frequency registration procedure
<1> Set expanded tone 2 registration command in EXPR2.
Expanded tone 2 registration command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
1
EB1
EB0
EXPR2
<2> Set higher-order 8 bits of expanded tone coefficient (expanded tone 2 data command) in EXPR2.
Expanded tone 2 data command
D7
D6
D5
D4
D3
D2
D1
D0
EB9
EB8
EB7
EB6
EB5
EB4
EB3
EB2
EXPR2
Remark EB9 to EB0: Tone 2 frequency 10-bit coefficient
Caution After executing the expanded tone registration command, the next command is written as expanded
tone data, so continuously execute the expanded tone data command.
45
µPD9930
(2) Expanded Tone Data Determination Method
The coefficient E of the tone frequency fe (0.3 to 3.4 kHz) to be generated is determined by the following formula.
E = COS (2π fe/fs)
fs = 8 kHz
Coefficient E: Sign bit 1 bit + 9 bits below the decimal point (Coefficient: 2's complement)
Example When specifying 400 Hz single tone
COS (2π x 400/8000)
= COS (π x 0.1)
= COS (0.3141592653......)
= 0.951056516......
= (0.11110011X) b
(Higher-order 9 bits are determined.)
Next, the least significant bit is determined.
When (0.111100110) b = 0.94921875
2π fe' x fs = COS–1 (0.94921875) = 0.320052983
fe' = 0.320052983 x fs/(2π)
fe' = 407.504115
When (0.111100111) b = 0.951071875
2π fe" x fs = COS–1 (0.951071875) = 0.314109559
fe" = 0.314109559 x fs/(2π)
fe" = 399.524415
Since fe" is nearest to 400 Hz, the coefficient to be registered is (0.111100111) b = (1E7) H.
0
1
1
1
1
0
0
1
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
EA9
EA8
EA7
EA6
EA5
EA4
EA3
EA2
EA1
EA0
The error of oscillation frequency by rounding 10-bit coefficient is below ±5 Hz (MAX. at 300 Hz → ±1.7 %) for
all frequencies.
About ±1.67 % near 300 Hz (±5 Hz)
About ±1.00 % near 500 Hz (±5 Hz)
About ±0.40 % near 1 kHz (±5 Hz)
About ±0.25 % near 2 kHz (±5 Hz)
About ±0.16 % near 3 kHz (±5 Hz)
Coefficient is negative number in fe > 2.0 kHz.
46
µPD9930
4.3.3 Tone Control Register (TONCR)
This is a 5-bit register for controlling single tone/dual tone specification, generation pattern selection, and
generation and stopping.
Figure 4-11 Tone Control Register
Register address
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
TNMODE
TNP2
TNP1
TNP0
START
/STOP
TNMODE Single tone/dual tone specification
0
Single tone mode
1
Dual tone mode
TONCR
Remarks
At reset
TNP2
TNP1
TNP0 Generation pattern selection
0
0
0
Continuous tone generation
0
0
1
31.25 ms tone, 31.25 ms no tone repeated
0
1
0
200 ms tone, 200 ms no tone repeated
0
1
1
250 ms tone, 250 ms no tone repeated
1
0
0
500 ms tone, 500 ms no tone repeated
1
0
1
1 s tone, 1s no tone repeated
1
1
0
GSM triple tone generated Note 1
1
1
1
200 ms interval tone generated (one shot tone)
Remarks
At reset
START/STOP Tone generation/stop control
0
Stop ("1" → "0", "0" → "0" both valid) Note 2
1
Validation of tone ferquency selection register setting data, start of
generation ("1" → "1", "0" → "1" both valid)
Remarks
At reset
Notes 1. 950 Hz tone 333 ms, 1400 Hz tone 333 ms, 1800 Hz tone 333 ms, 1 s no tone repeated.
2. Do not input a command that sets a tone oscillation frequency after inputting a tone oscillation command
(writing "1" to the START/STOP control bit of the tone control register).
Remark When the regeneration pattern is specified as "110", it becomes GSM triple tone command, so tone
generation forcibly enters single tone mode.
Tone generation and change of a tone that is being generated is executed only when "1" is written for START/
STOP control bit (D0 bit) (refer to Figure 4-11 and Table 4-6).
47
µPD9930
Table 4-6 Function Specification by Tone Control Register
Register address
HEXNote
TONCR
Tone control conditions
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
M
X
X
X
X
0
Tone stop
A0H 05H
0
0
0
0
1
Continuous single tone generation
A1H 85H
0
0
0
1
1
31.25 ms intermittent single tone generation
A3H C5H
0
0
1
0
1
200 ms intermittent single tone generation
A5H A5H
0
0
1
1
1
250 ms intermittent single tone generation
A7H E5H
0
1
0
0
1
500 ms intermittent single tone generation
A9H 95H
0
1
0
1
1
1 s intermittent single tone generation
ABH D5H
0
1
1
0
1
GSM triple tone generation
ADH B5H
0
1
1
1
1
200 ms one-shot single tone generation
AFH F5H
1
0
0
0
1
Continuous dual tone generation
B1H 8DH
1
0
0
1
1
31.25 ms intermittent dual tone generation
B3H CDH
1
0
1
0
1
200 ms intermittent dual tone generation
B5H ADH
1
0
1
1
1
250 ms intermittent dual tone generation
B7H EDH
1
1
0
0
1
500 ms intermittent dual tone generation
B9H 9DH
1
1
0
1
1
1 s intermittent dual tone generation
BDH BDH
1
1
1
1
1
200 ms one-shot dual tone generation
BFH FDH
Note M: HEX value with MSB first
L: HEX value with LSB first
Remark X: Don't care
4.3.4 Tone Gain Control Register (TNGCR)
This is a 5-bit register for controlling the tone output gain.
Figure 4-12 Tone Gain Control Register
Register address
TNGAIN4 to TNGAIN0
00000 to 11111
48
L
TNGCR
D7
D6
D5
1
1
1
D4
D3
D2
D1
D0
TNGAIN4 TNGAIN3 TNGAIN2 TNGAIN1 TNGAIN0
Tone gain selection (Refer to Table 4-7 Function
Specification by Tone Gain Control Register).
0 to –30 dB (1 dB steps), –38.5 dB
µPD9930
Table 4-7 Function Specification by Tone Gain Control Register
Register address
HEXNote
TNGCR
D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
Tone gain
M
L
0
0
0
0
0
0 dB
E0H 07H
0
0
0
0
1
–1 dB
E1H 87H
0
0
0
1
0
–2 dB
E2H 47H
0
0
0
1
1
–3 dB
E3H C7H
0
0
1
0
0
–4 dB
E4H 27H
0
0
1
0
1
–5 dB
E5H A7H
0
0
1
1
0
–6 dB
E6H 67H
0
0
1
1
1
–7 dB
E7H E7H
0
1
0
0
0
–8 dB
E8H 17H
0
1
0
0
1
–9 dB
E9H 97H
0
1
0
1
0
–10 dB
EAH 57H
0
1
0
1
1
–11 dB
EBH D7H
0
1
1
0
0
–12 dB
ECH 37H
0
1
1
0
1
–13 dB
EDH B7H
0
1
1
1
0
–14 dB
EEH 77H
0
1
1
1
1
–15 dB
EFH F7H
1
0
0
0
0
–16 dB
F0H 0FH
1
0
0
0
1
–17 dB
F1H 8FH
1
0
0
1
0
–18 dB
F2H 4FH
1
0
0
1
1
–19 dB
F3H CFH
1
0
1
0
0
–20 dB
F4H 2FH
1
0
1
0
1
–21 dB
F5H AFH
1
0
1
1
0
–22 dB
F6H 6FH
1
0
1
1
1
–23 dB
F7H EFH
1
1
0
0
0
–24 dB
F8H 1FH
1
1
0
0
1
–25 dB
F9H 9FH
1
1
0
1
0
–26 dB
FAH 5FH
1
1
0
1
1
–27 dB
FBH DFH
1
1
1
0
0
–28 dB
FCH 3FH
1
1
1
0
1
–29 dB
FDH BFH
1
1
1
1
0
–30 dB
FEH 7FH
1
1
1
1
1
–38.5 dB
FFH FFH
Remarks
At reset
Note M: HEX value with MSB first
L: HEX value with LSB first
49
µPD9930
4.4 TEST MODE CONTROL
The µ PD9930 has the following test functions.
Test function
DAI test function
This test function is stipulated in GSM11.10. Test mode selection can be
controlled by external terminal (TC1 or TC2) or internal register (ITC1,
ITC2).
Analog loopback function
Send data after BPF processing is input to LPF.
DSP interface input/
output control function
SO, SI, SCLK and SEN terminals can be set at low level.
An outline of test mode control is shown in Figure 4-13.
50
Registers used
Test control
register (TSTCR)
µPD9930
Figure 4-13 Test Mode Operation
(a) DAI (speech encoder test mode)
(b) DAI (speech decoder test mode)
Mobile Station
Mobile Station
µ PD9930
µ PD9930
DSP
DSP I/F
SO
DSP
DSP I/F
speech
encoder
SI
TX
DAI
speech
decoder
RX
DAI
DI
DO
System
simulator
1
TC1
0
TC2
0
TC1
1
TC2
(c) DAI (A/D, D/A test mode)
System
simulator
(d) Analog loopback mode
µ PD9930
Mobile Station
µ PD9930
DAI
A/D
D/A
BPF
LPF
A/D
BPF
D/A
LPF
DO
System
simulator
DI
TC1
TC2
1
1
51
µPD9930
4.4.1 Test Control Register (TSTCR)
This is a 5-bit control register for selecting the test mode.
ITC1, ITC2 become valid at the rising edge of DRSTB. For the precautions when using DAI, refer to 2.1.9
DAI (Digital Audio Interface).
Figure 4-14 Test Control Register
Register address
TSTCR
D7
D6
D5
D4
D3
D2
D1
1
1
0
TCMODE
ITC2
ITC1
LOOPBK
0
Specification of test mode by external terminals TC1 and TC2 At reset
1
Specification of test mode by test control registers ITC1 and ITC2
DAI test mode specification
Remarks
0
Normal operation
At reset
0
1
Speech encoder test mode
1
0
Speech decoder test mode
1
1
Acoustic device, A/D, D/A test mode
ITC1
0
Analog loopback specification
Remarks
0
Normal operation
At reset
1
Analog loopback
LOOPBK
SIOOFF
DSP interface input/output terminal control
SIOOFF
Remarks
TCMODE DAI test mode control method selection
ITC2
D0
Remarks
0
Normal operation
1
Setting of terminals SO, SI, SCLK, and SEN to low level At reset
Remark The analog loopback mode and the DAI test mode cannot be specified at the same time.
52
µPD9930
5. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (T A = 25˚C, DGND = AGND1 to AGND4 = 0 V)
Item
Symbol
Conditions
Ratings
Unit
Supply Voltage
VDD
AVDD1, AVDD2, DVDD
–0.3 to +5.5
V
Analog Input Voltage
VAIN
All analog input pins
–0.3 to VDD +0.3
V
Digital Input Voltage
VDIN
All digital input pins
–0.3 to VDD +0.3
V
Analog Output Pin Applied Voltage
VAOUT
All analog output pins
–0.3 to VDD +0.3
V
Digital Output Pin Applied Voltage
VDOUT
All digital output pins
–0.3 to VDD +0.3
V
Operating Ambient Temperature
TA
–30 to +85
˚C
Storage Temperature
Tstg
–65 to +150
˚C
Cautions 1. Connect the AGND1 through AGND4 pins and DGND pin to an analog ground line near µPD9930
pins. Connect the DVDD, AVDD1, AVDD2 pins to an analog power supply line near µPD9930 pins.
2. Do not connect output (and bidirectional) pins each other. Do not connect output (or bidirectional) pins directly to the VDD, VCC, or GND line. However, open drain pin and open collector
pin can be directly connected to VDD, VCC, or GND line. If timing design is made so that no signal
conflict occurs, three-state pins can also be connected directly to three-state pins of external
circuit.
3. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
The device should be operated within the limits specified under DC and AC Characteristics.
53
µPD9930
RECOMMENDED OPERATING RANGE (T A = –30 to +85˚C)
(1) DC Condition
Item
Symbol
Conditions
MIN.
TYP.
3.0
MAX.
Unit
Supply Voltage
VDD
AVDD1, AVDD2, DVDD
2.7
3.6
V
High Level Input Voltage
VIH
All digital input pins
0.7 VDD
VDD
V
Low Level Input Voltage
VIL
All digital input pins
0
0.3 VDD
V
Analog Input Voltage
VIA
All analog input pins
0.6
1.8
V
VMIC
Differential: MICI+, MICI–
1.2
Vp-p
Gain Setting Range
GMIC
Set with external resistor
15
Load Resistance
RLMIC
Includes gain setting resistance
50
Load Capacitance
CLMIC
Microphone Input
Analog Input Voltage
33
dB
kΩ
20
pF
1.2
Vp-p
10
dB
Accessory Input
Analog Input Voltage
VAUXI
XAUXI–
Gain Setting Range
GAUXI
Set with external resistor
Load Resistance
RLAUXI
Includes gain setting resistance
Load Capacitance
CLAUXI
0
300
kΩ
20
pF
1.2
Vp-p
Pre-filter + Mixer Input
Analog Input Voltage
VMIXI
MIXI
Accessory Output
Load Resistance
RLAUXO
Load Capacitance
CLAUXO
100
kΩ
100
pF
Receiver 1 Output
Load Resistance
RLREC1
Load Capacitance
CLREC1
100
kΩ
20
pF
1.2
Vp-p
Receiver 2 Output
Analog Input Voltage
VREC2
REC2I-
Gain Setting Range
GREC2
Set with external resistor
Load Resistance
RLREC2
60 nF series
Load Capacitance
CLREC2
2 kΩ series
CLACOM
XACOMO, RACOMO
–∞
+10
2
dB
kΩ
60
nF
10
µF
Reference Voltage Output
Load Capacitance
0.2
(2) Frame Signal (FSYNC) and Reset Signal (RESETB)
Item
MIN.
TYP.
fs
7.995
8.000
FSYNC High Level Width
tWHS
2.0
µs
FSYNC Low Level Width
tWLS
2.0
µs
FSYNC Frequency
Symbol
Conditions
MAX.
8.005
Unit
kHz
FSYNC Rise Time
tr
20
ns
FSYNC Fall Time
tf
20
ns
RESETB Low Level Width
54
tRSL
260
ns
µPD9930
(3) Microcontroller Interface
Item
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
MCLK Cycle Time
tMCY
240
ns
MCLK High Level Width
tMCH
100
ns
MCLK Low Level Width
tMCL
100
ns
MCLK Rise Time
tMR
20
ns
MCLK Fall Time
tMF
20
ns
MDAT Setup Time to
MSTR ↑
tSUMDA
50
ns
MDAT Hold Time from
MCLK ↑
tHMDA
50
ns
MSTR High Level Width
tWMST
320
ns
MCLK Setup Time to
MSTR ↑
tSUMCK
0
ns
MSTR Setup Time to
MCLK ↑
tSUMST
100
ns
(4) DSP Interface
Item
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SI Setup Time to SCLK ↓
tSUSI
200
ns
SI Hold Time from SCLK ↓
tHSI
200
ns
(5) DAI
Item
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
DI Setup Time to DCLK ↑
tSUDI
200
ns
DI Hold Time from DCLK ↑
tHDI
200
ns
TC1, TC2 Rise Time
tTR
50
ns
TC1, TC2 Fall Time
tTF
50
ns
DRSTB Low Level Width
tDRSL
130
µs
DRSTB Rise Time
tDRR
20
ns
DRSTB Fall Time
tDRF
20
ns
DAI Mode Setting Time 1
tTCF
60
ms
DAI Mode Setting Time 2
tTCR
260
µs
REQB Low Level Width
tDRQL
130
µs
REQB High Level Width
tDRQH
130
µs
REQB Rise Time
tDRQR
20
ns
REQB Fall Time
tDRQF
20
ns
55
µPD9930
CAPACITANCE (TA = 25˚C)
Item
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Digital Output Pin
Capacitance
COD
f = 1 MHz
20
pF
Digital Input Pin
Capacitance
CID
f = 1 MHz
20
pF
DC CHARACTERISTICS (TA = 25˚C, V
DD
= 2.7 to 3.6 V (GND standard))
(1) Current Consumption
Item
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Circuit Current in Normal
Mode
IDD1
Microphone input
(1020 Hz: –10 dBm0)
Accessory input: Power down
serial input (1020 Hz: –10 dBm0)
Accessory output: Power up
Receiver 1, 2: Power up
7.0
9.0
mA
Circuit Current in DAI
Operation
IDD2
Microphone input
(1020 Hz: –10 dBm0)
Accessory input: Power down
serial input (1020 Hz: –10 dBm0)
Accessory output: Power up
Receiver 1, 2: Power up
7.5
10.0
mA
Circuit Current in Standby
Mode
IDD3
DI, DRSTB, TC1, TC2: Open
FSYNC: 8 kHz
Other digital input pins: 0 or VDD
50
100
µA
TYP.
MAX.
Unit
1.0
µA
(2) Digital Part
Item
Digital Input Leak Current
Pull-Up/Down Current
Symbol
Conditions
ILH
VI = VDD
ILL
VI = 0
IIL
VDD = 3.3 V, 0 ≤ VI ≤ VDD
100
µA
0.4
V
Low Level Output Voltage
VOL
IOL = 2.0 mA
High Level Output Voltage
VOH
IOH = –2.0 mA
56
MIN.
µA
–1.0
2.4
V
µPD9930
(3) Analog Part
Item
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
0
dB
–3.0
–2.8
dB
Pre-filter + Mixer
Volume Range
GPRF
–3
Volume Accuracy
∆GPRF
Volume 0 dB standard
Cross-Talk 1 between
Input Channels
CTIN1
Microphone input amplifier: Power down
MICI = 1.2 Vp-p
XAUXI– = 0 Vp-p
Accessory input gain setting: 0 dB
–45
dB
Cross-Talk 2 between
Input Channels
CTIN2
Accessory input amplifier: Power down
MICI = 0 Vp-p
XAUXI– = 1.2 Vp-p
Accessory input gain setting: 0 dB
–45
dB
VAMAX
1.2
Vp-p
Maximum Output
Voltage
VR1MAX
1.2
Vp-p
Volume Range
GREC1
0
dB
–3.2
Accessory Output
Maximum Output
Voltage
Receiver 1 Output
Volume Accuracy
∆GREC1
–31
Volume: 0 to –16 dB
–1.5
–1.0
–0.5
dB
VolumeNote: –17 to –31 dB
–2.0
–1.0
0.0
dB
4
Vp-p
Receiver 2 Output
Maximum Output
Voltage
VR2MAX
Distortion factor 4 % (MAX.)
VACOM
XACOMO, RACOMO
Reference Voltage Output
Output Voltage
1.2
V
Note Simple decrease in the gain due to drop of volume is guaranteed.
(4) Tone Generator
Item
Output Signal Level
Frequency Deviation
Distortion Factor
Tone Volume Range
Tone Volume Accuracy
Symbol
Conditions
MIN.
TYP.
MAX.
VTN1
Tone 1
–2.93
–2.73
VTN2
Tone 2
–5.93
–5.73
∆FTN
0.3 to 3.4 kHz
–5
+5
Accessory output
30
TNSD
GTN
∆GTN
–1.4
dBm0
Hz
dB
–38.5
Volume: 0 to –30 dB (1 dB steps)
Unit
–1.0
0
dB
–0.8
dB
57
µPD9930
AC CHARACTERISTICS
(1) DSP Interface (TA = –30 to +85˚C, V
Item
DD
= 2.7 to 3.6 V, CL = 100 pF)
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCLK Cycle Time
tSCY
3906
ns
SCLK High Level Width
tSCH
1953
ns
SCLK Low Level Width
tSCL
1953
ns
SCLK Rise Time
tSR
20
ns
SCLK Fall Time
tSF
20
ns
SCLK Delay Time from
FSYNC ↑
tDSCLK
1.0
µs
SEN ↑ Delay Time from
FSYNC ↑
tDSENR
80
ns
SEN ↓ Delay Time from
SCLK ↑: Mode 1
SEN ↓ Delay Time from
SCLK ↓: Mode 2
tDSENF
80
ns
SO Output Delay Time
tDSO
40
ns
from SCLK ↑: Mode 1
SO Output Delay Time
from SCLK ↓: Mode 2
(2) DAI (TA = –30 to +85˚C, V
Item
DD
= 2.7 to 3.6 V, CL = 100 pF)
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
DCLK Cycle Time
tDCY
9615
ns
DCLK High Level Width
tDCH
4808
ns
DCLK Low Level Width
tDCL
4808
ns
DCLK Rise Time
tDR
20
ns
DCLK Fall Time
tDF
20
ns
DCLK Delay Time from
FSYNC ↑
tDDCLK
200
ns
DO Output Delay Time
from DCLK ↓
tDDO
200
ns
(3) Others (Digital Output) (TA = –30 to +85˚C, V
Item
Symbol
DD
= 2.7 to 3.6 V, CL = 100 pF)
Conditions
MIN.
TYP.
MAX.
Unit
TIMER/RINGER Rise Time
tDDR
TIMER pin and RINGER pin
50
ns
TIMER/RINGER Fall Time
tDDF
TIMER pin and RINGER pin
50
ns
58
µPD9930
Frame signal (FSYNC)
1/fs
tWHS
tr
FSYNC
tf
tWLS
Remark During normal operation or the power up/down sequence, be sure to input the frame signal.
Reset signal (RESETB)
RESETB
tRSL
Remarks 1. The reset signal is input as it is without shaping, so take full precautions against noise.
2. A power on reset circuit is not incorporated, so be sure to set RESET to low after turning the power on.
Microcontroller interface timing
tWMST
MSTR
tMCY
tMCH
tSUMCK
tSUMST
MCLK
tMR
tSUMDA
MDAT
D0
tMCL
tMF
tHMDA
D1
D2
D6
D7
D0
Remark D0 to D7: Microcontroller command (LSB first)
59
µPD9930
DSP interface timing (mode 1)
SCLK
tDSCLK
tSCY
tSCL
tSF
tSCH
tSR
FSYNC
tDSENR
tDSENF
SEN
tDSO
SO
D15
D14
tSUSI
SI
don't care
D15
D13
D1
D0
tHSI
D14
D13
don't care
D0
DSP interface timing (mode 2)
SCLK
tSCY
tDSCLK
tSCH
tSR
tSCL
tSF
FSYNC
tDSENF
tDSENR
SEN
tDSO
D15
SO
tSUSI
SI
60
don't care
D15
D14
D13
D1
D0
tHSI
D14
D13
D0
don't care
µPD9930
DAI input timing
FSYNC
tDDCLK
tDCH
tDCY
tDR
DCLK
tSUDI
DI
D12
tHDI
tDCL
D11
D10
tDF
D9
D8
D7
Remark D12 to D0: Input data (MSB first)
DAI output timing
FSYNC
tDCY
tDDCLK
tDCH
tDR
DCLK
tDCL
tDDO
DO
D12
D11
D10
tDF
D9
D8
D7
Remark D12 to D0: Output data (MSB first)
61
µPD9930
TC1, TC2, DRSTB input timing
TC1, TC2
tTR, tTF
tTCR
tTCF
tDRF
tTR, tTF
tDRR
DRSTB
tDRSL
TIMER, RINGER output timing
tDDR
tDDF
TIMER,
RINGER
REQB input timing
tDRQF
tDRQR
tDRQH
REQB
tDRQL
62
µPD9930
TRANSMISSION CHARACTERISTICS
Transmission characteristics are as indicated below unless otherwise specified.
• Analog input
Analog input signal (–10 dBm0, 1020 Hz) → accessory input part
Accessory input: Set gain 0 dB
Microphone input: Power down
Pre-filter + mixer: Set gain 0 dB
• Analog output
Analog output signal → accessory output part
Receiver output: Power down
• Digital gain set
Send and receive: 0 dB
• Digital input signal level: 0 dBm0
• TA = 25˚C, V
DD
= 2.7 to 3.6 V (GND standard)
(1) Send/Receive Zero Transmission Level (0 dBm0 level)
Item
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Send Zero Transmission
Level
V0TLPX
600 Ω standard
–8.4
dBm
Receive Zero Transmission
V0TLPR
600 Ω standard
–8.4
dBm
Level
(2) Gain Characteristics
Item
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Send Gain Deviation
GX
–0.5
+0.5
dB
Receive Gain Deviation
GR
–0.5
+0.5
dB
Send Gain Deviation
Temperature Power
Fluctuation
∆GX
–0.4
+0.4
dB
Receive Gain Deviation
Temperature Power
Fluctuation
∆GR
–0.4
+0.4
dB
MAX.
Unit
(3) Transmission Loss Level
Item
Send Transmission Loss
Level
Receive Transmission Loss
Level
Symbol
GTX
GTR
Conditions
MIN.
TYP.
+3 to –40 dBm0
–0.4
+0.4
dB
–40 to –50 dBm0
–0.6
+0.6
dB
–50 to –55 dBm0
–1.2
+1.2
dB
+3 to –40 dBm0
–0.4
+0.4
dB
–40 to –50 dBm0
–0.6
+0.6
dB
–50 to –55 dBm0
–1.2
+1.2
dB
63
µPD9930
(4) Transmission Gain Frequency Characteristics
Item
Send Transmission Gain
Frequency Characteristics
Receive Transmission Gain
Frequency Characteristics
Symbol
Conditions
MIN.
TYP.
MAX.
–23
Unit
GRX1
60 Hz
dB
GRX2
200 Hz
–2.5
0
dB
GRX3
0.3 to 3.0 kHz
–0.3
+0.3
dB
GRX4
3.2 kHz
–0.65
+0.3
dB
GRX5
3.4 kHz
–0.8
0
dB
GRX6
4.0 kHz
–14
dB
GRX7
4.6 kHz or more
–28
dB
GRR3
0.3 to 3.0 kHz
–0.3
+0.3
dB
GRR4
3.2 kHz
–0.65
+0.3
dB
GRR5
3.4 kHz
–0.8
0
dB
GRR6
4.0 kHz
–14
dB
GRR7
4.6 kHz or more
–28
dB
(5) Noise Characteristics
Item
Send Noise
Symbol
MIN.
Microphone power down, XAUXI– →
ACOM, gain 0 dB, C message filter
TYP.
MAX.
Unit
25
dBrnc0
–65
dBm0c
25
dBrnc0
–65
dBm0c
Send input → Receive output
–50
dBm0
CTTR
No sidetone pass, microphone power down
input 0 dBm0 and 1020 Hz from XAUXI–
input +0 code from SI
–60
dB
Cross-Talk between Receive
and Send Channels
CTRT
No sidetone pass, microphone power down
XAUXI– → ACOM
input 0 dBm0 and 1020 Hz from SI
–60
dB
Power Supply Voltage
Variation Rejection
PSRR
VDD ±100 mV0-p signal application
f = 0 to 3.4 kHz
Receive Noise
Single Frequency Noise
Cross-Talk between Send
NXC
Conditions
NRC1
NSF
and Receive Channels
64
C message filter, input +0 code from SI
30
dB
µPD9930
(6) Distortion Factor Characteristics
Item
Symbol
Send Channel Total Power
Distortion Factor
SDX
Receive Channel Total
SDR
Power Distortion Factor
Conditions
MIN.
0 to –10 dBm0
35
–40 dBm0
25
–45 dBm0
20
0 to –10 dBm0
35
–40 dBm0
25
–45 dBm0
20
Absolute Delay
DA
XAUXI– → RAUXO
Delay Distortion Frequency
Characteristics
DO
XAUXI– → RAUXO
TYP.
MAX.
Unit
dB
dB
550
µs
500 Hz
1.40
ms
600 Hz
0.70
1 kHz
0.20
2.6 kHz
0.20
2.8 kHz
1.40
Send Transmission Gain Frequency Characteristics 1 (GRX)
5
0
–5
–10
Send transmission gain (dB)
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Frequency (kHz)
65
µPD9930
Send Transmission Gain Frequency Characteristics 2 (GRX)
0.1
0
–0.1
Send transmission gain (dB)
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
Frequency (kHz)
Receive Transmission Gain Frequency Characteristics 1 (GRR)
5
0
–5
–10
–15
Receive transmission gain (dB)
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
0
66
1
2
3
4
5
6
7
8
9
Frequency (kHz)
10
11
12
13
14
15
16
µPD9930
Receive Transmission Gain Frequency Characteristics 2 (GRR)
0.1
0
–0.1
Receive transmission gain (dB)
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
Frequency (kHz)
67
µPD9930
Send/receive zero transmission level (0 dBm0 level) is explained below for your reference.
(a) Send zero transmission level
Analog output signal level at which the digital input signal level of the D/A converter becomes 0 dBm0.
(b) Receive zero transmission level
Analog input signal level at which the digital output signal level of the A/D converter becomes 0 dBm0.
(c) Analog signal level (dBm)
The conversion expression of the amplitude voltage of a signal and an analog signal level is as follows:
X = 10 logW
X: analog signal level (dBm)
W: analog signal power (mW)
W = (V2/R) x 103
V: effective value of analog signal (AC) (Vrms)
R: resistance (Ω)
With the µPD9930, the signal voltage (effective value) can be calculated if R = 600 Ω and X = –8.4 dBm are
substituted.
W = 0.1445 (mW)
V = 0.294 (Vrms)
To calculate V0-p, multiply the signal voltage (effective value) by √2.
V0-p = 0.416 (V)
(d) Digital signal level (dBm0)
Signal level where the level of the full swing of the digital output value of the A/D converter and the digital input
value of the D/A converter is considered to be 3.17 dBm0 (the amplitude of the analog signal is 1.2 Vp-p where
the gain of the microphone input or accessory input is 0 dB).
<Level diagram>
This diagram indicates the range in which adjustments can be made by using each amplifier and gain control
function.
Example: Input level at which digital output of linear codec is –10 dBm0 is –33 dBm.
(Conditions)
Microphone amplifier gain during microphone input: 15 dB
Analog gain control: 0 dB
Digital gain control: 0 dB
Output level at which digital input of linear codec is –10 dBm0 is –18.4 dBm.
(Conditions)
During receiver output
Analog gain control: 0 dB
Digital gain control: 0 dB
68
µPD9930
Voice send level diagram (microphone input)
+
Vref –
Analog
gain control
A/D
Digital
gain control
[dBm]
0
[dBm0]
15 to 33 dB
0 dB or –3 dB
–10
0 to –2.8 dB
(0.4 dB steps)
0
–10 dBm0
–10
–20
–30
–33.4 dBm
–15.8 dBm0
–20
–30
–40
–41.4 dBm
–40
–50
–50
–60
–60
Remarks 1. Thick line: Indicates case where gain of microphone amplifier is set to 15 dB, gain of analog gain control
to 0 dB, and gain of digital gain control to 0 dB.
Thin line:
Indicates case where gain of microphone amplifier is set to 33 dB, gain of analog gain control
to –3 dB, and gain of digital gain control to –2.8 dB.
2. Overload level: 3.17 dBm0.
69
µPD9930
Voice receive level diagram (receiver output)
Receiver 1
[dBm]
0
Analog
gain control
0 to –31 dB (1 dB steps)
D/A
Digital
gain control
0 to –2.4 dB
(0.8 dB steps)
[dBm0]
0
–10
–18.4 dBm
–10 dBm0
–10
–20
–20
–30
–30
–40
–40
–50
–51.8 dBm
–50
–60
–60
Remarks 1. Thick line: Indicates case where gain of analog gain control is set to 0 dB and gain of digital gain control
to 0 dB.
Thin line:
Indicates case where gain of analog gain control is set to –31 dB and gain of digital gain
control to –2.4 dB.
2. Overload level: 3.17 dBm0.
70
µPD9930
Voice send level diagram (accessory input)
+
Vref –
Analog
gain control
A/D
Digital
gain control
[dBm]
0
[dBm0]
0 to 10 dB
0 dB or –3 dB
–10
–18.4 dBm
0 to –2.8 dB
(0.4 dB steps)
–10 dBm0
–10
–20
–15.8 dBm0
–30
0
–20
–28.4 dBm
–30
–40
–40
–50
–50
–60
–60
Remarks 1. Thick line: Indicates case where gain of microphone amplifier is set to 0 dB, gain of analog gain control
to 0 dB, and gain of digital gain control to 0 dB.
Thin line:
Indicates case where gain of microphone amplifier is set to 10 dB, gain of analog gain control
to –3 dB, and gain of digital gain control to –2.8 dB.
2. Overload level: 3.17 dBm0.
71
µPD9930
Voice receive level diagram (accessory output)
Accessory
output
[dBm]
0
0 dB (fix)
D/A
Digital
gain control
0 to –2.4 dB
(0.8 dB steps)
[dBm0]
0
–10
–18.4 dBm
–10 dBm0
–10
–20
–20.8 dBm
–20
–30
–30
–40
–40
–50
–50
–60
–60
Remarks 1. Thick line: Indicates case where gain of digital gain control is set to 0 dB.
Thin line:
Indicates case where gain of digital gain control is set to –2.4 dB.
2. Overload level: 3.17 dBm0.
72
1 µF
8 kHz
From
RESET
circuit
From DSP
12 kΩ
100 kΩ to 500 kΩ
21
20
19
18
17
16
15
14
13
MICI–
MICI+
AGND4
AGND3
AGND2
AGND1
DGND
FSYNC
RESETB
23 MIXI
300 kΩ
12
REQB
22
MICO
0.1 µF
DSPSEL 11
24 XAUXO
100 kΩ
to 300 kΩ
Accessory
input
VDD (mode 1)
or GND (mode 2)
RINGER 10
6. APPLIED CIRCUIT EXAMPLE
1 µF
25 XAUXI–
2.2 µ F
Low-current drive LED
26 XACOMI
+
TIMER
9
TC2
8
TC1
7
DCLK
6
DO
5
DI
4
DRSTB
3
MCLK
2
MDAT
1
0.1 µ F
–
27 XACOMO
+
2.2 µF
–
28 RACOMO
0.1 µF
Note
µ PD9930G-22
29 RACOMI
30 REC2O+
31 REC2O–
100 kΩ to 900 kΩ
DSUB
socket
(25 pin)
32 IC
0.1 µF
33 REC2I–
REC1O
RAUXO
AVDD1
AVDD2
DVDD
SEN
SI
SO
SCLK
TEST
MSTR
100 kΩ to
300 kΩ
34
35
36
37
38
39
40
41
42
43
44
Microcontroller
300 kΩ
Accessory output +
4.7 µF
–
+
4.7 µ F
–
0.1 µ F
0.1 µ F
73
Note When connecting a dynamic receiver, use a drive amplifier.
DSP
To REQB
µPD9930
0.1 µF
µPD9930
7. PACKAGE DRAWINGS
44 PIN PLASTIC QFP (
10)
A
B
Q
F
G
H
I
M
5˚±5˚
12
11
S
44
1
detail of lead end
D
23
22
C
33
34
J
M
P
K
N
L
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
74
P44G-80-22-2
ITEM
MILLIMETERS
INCHES
A
13.6 ± 0.4
0.535+0.017
–0.016
B
10.0 ± 0.2
0.394+0.008
–0.009
C
10.0 ± 0.2
0.394+0.008
–0.009
D
13.6 ± 0.4
0.535+0.017
–0.016
F
1.0
0.039
G
1.0
0.039
H
0.35 ± 0.10
0.014+0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071+0.008
–0.009
L
1.0 ± 0.2
0.039+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.15
0.006
P
1.45 ± 0.1
0.057+0.005
–0.004
Q
0.05 ± 0.05
0.002 ± 0.002
S
1.65 MAX.
0.065 MAX.
µPD9930
8. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the µPD9930.
For more details, refer to our document "Semiconductor Device Mounting Technology Manual" (C10535E).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under
different conditions.
Type of Surface Mount Device
µPD9930G-22: 44-pin plastic QFP (10 x 10 mm)
Soldering process
Soldering conditions
Symbol
Infrared ray reflow
Peak temperature of package surface: 235˚C or below,
Reflow time: 30 seconds or below (210˚C or higher),
Number of reflow processes: MAX. 2
Exposure limitNote: 7 days
(10 hours pre-baking is required at 125˚C afterwards)
IR35-107-2
VPS
Peak temperature of package surface: 215˚C or below,
Reflow time: 40 seconds or below (200˚C or higher),
Number of reflow processes: MAX. 2
Exposure limitNote: 7 days
VP15-107-2
(10 hours pre-baking is required at 125˚C afterwards)
Wave soldering
Soldering bath temperature: 260˚C or below,
Reflow time: 10 seconds or below, Number of reflow processes: 1
Preheating temperature: 120˚C MAX. (package surface temperature)
Exposure limitNote: 7 days
(10 hours pre-baking is required at 125˚C afterwards)
Partial heating method Terminal temperature: 300˚C or below,
Time: 3 seconds or below (Per one side of the device).
WS60-107-1
—
Note Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25˚C and relative humidity at 65 % or less.
Caution Do not apply more than one soldering method at any one time, except for "Partial heating method".
75
µPD9930
[MEMO]
76
µPD9930
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
77
µPD9930
[MEMO]
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
78