FUJITSU MB86437

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-23005-3E
ASSP
CMOS
3 V Single Power Supply Audio
Interface Unit (AIU)
MB86437
■ DESCRIPTION
The FUJITSU MB86437 is an AIU (audio interface unit) LSI for +3 V single-power source digital telephone devices,
manufactured using CMOS process technology. The codec transmission filter characteristics meet G.712 standards,
and can handle input and output in A-Law, µ-Law and linear conversion modes. The MB86437 also contains the
necessary DTMF, microphone and receiver amps for telephone devices.
■ FEATURES
• +3 V single power supply
• Low power consumption: muting settings for each operating mode
Normal operation : 5.0 mA TYP
Standby mode
: 0.5 µA TYP
• On-chip codec filter meets G.712 standards
• Selection of codec companding law (A-law, µ-law, 14 bit linear)
• On-chip low-noise microphone amp (2-channel) (0 to 35 dB amplification)
• On-chip receiver speaker amps (32 Ω BTL type: 10 mW MIN)
• On-chip earphone speaker amps (32 Ω single type: 5 mW MIN)
(Continued)
■ PACKAGE
48 pin, Plastic LQFP
(FPT-48P-M05)
MB86437
(Continued)
•
•
•
•
•
On-chip electronic volume gain adjustments (sending, receiving, tone)
On-chip accessory input/output circuits
DTMF generator function
Service tone generation
CMOS compatible input/output
■ PIN ASSIGNMENT
(TOP VIEW)
48
1
37
36
Index
25
12
24
13
(FPT-48P-M05)
2
MB86437
■ PIN DESCRIPTION
Pin No.
Symbol
I/O
A/D
Description
1
SWI
I/O
A/D
I/O pin for analog switch SW12
The standard on resistance for the analog switch is 500 Ω.
2
SWO
I/O
A/D
I/O pin for analog switch SW12
Connected to pin 1 via switch SW12.
3
RAUD
O
A
Output pin for the received audio signal to the external speaker or for
testing.
4
VD1
P
A
Power supply pin for reception. Supply a voltage between 2.7 V and 3.6 V.
5
JEAR
O
A
Amplifier output pin for the earphone speaker.
Can output 5 mW for a 32 Ω load.
6
EAR
O
A
Amplifier output pin for the receiver speaker. Internal BTL connection to
XEAR. The maximum output for a 32 Ω load between EAR and XEAR is 10
mW.
7
XEAR
O
A
Amplifier output pin for the receiver speaker.
BTL connection to XEAR.
8
VS1
G
A
Ground pin for reception. Set to 0 V.
9
TONE
O
A
Amplifier output pin for the tone speaker. The output can be set to normal
mode, ground, or high impedance.
10
TBO
O
A
AMP4 output pin. Pair high pass filter with TBI so that there is no DC offset
at the speaker.
11
TBI
I
A
AMP4 inverted (–) input pin
12
PTBO
O
A
PCM reception, tone addition output
13
MDI
I
A
Pin used to add an analog input signal to the tone section or apply an
envelope to the tone. Required functions can be selected by controlling
SW16. Setting SW16 off sets the input impedance to approximately 140 kΩ
and setting SW16 on sets the input impedance to approximately 210 kΩ.
14
VD2
P
A
Power supply pin for reception. Supply a voltage between 2.7 V and 3.6 V.
15
DSCK
I/O
A
Can be connected to EXSD and TAUD by path switching.
16
EXSD
I/O
A
Can be connected to DSCK and TAUD by path switching.
17
TAUD
I/O
A
Can be connected to EXSD and DSCK by path switching.
18
MICO
O
A
Output pin for mike amplifier [1]
19
MIC
I
A
Inverted input pin (–) for mike amplifier [1]
20
XMIC
I
A
Non-inverted input pin (+) for mike amplifier [1]
21
JMIC
I
A
Inverted input pin (–) for mike amplifier [2]
22
JMICO
O
A
Output pin for mike amplifier [2]
23
VS2
G
A
Ground pin for transmission. Set to 0 V.
24
SGC
O
A
Pin for connecting the bypass capacitor for the signal ground potential
generation circuit.
Connect a capacitor between SGC and VS2.
25
VS4
G
A
Ground pin for A/D and D/A. Set to 0 V.
26
SGI
I
A
General-purpose amplifier. To use, connect to SGO.
(Continued)
3
MB86437
(Continued)
4
Pin No.
Symbol
I/O
A/D
Description
27
SGO
O
A
General-purpose amplifier output pin. The signal can also go to JEAR via
SW15.
28
STA
O
A
Transmission analog signal output via SW1. Connect to AMP4 when
performing sidetone addition for reception. The standard on resistance for
the analog switch is 500 Ω.
29
BBO
O
A
Transmission analog signal output pin
30
BTPI
I
A
Inverted input pin (–) for the PCM ENCODE section input op-amp
31
BTPO
O
A
Output pin for the PCM ENCODE section input op-amp
32
VD3
P
D
Power supply pin for transmission. Supply a voltage between 2.7 V and 3.6 V.
33
DIN
I
D
PCM signal input pin. The signal is clocked in on the falling edge of CLK.
CMOS interface.
34
DOUT
O
D
PCM signal output pin. The signal is clocked out on the rising edge of CLK.
After data output, becomes fixed at the "H" level if PLL synchronization is
lost or a power-down occurs. CMOS interface.
35
SYNC
I
D
Transmission and reception sync signal input pin for the PCM CODEC
section. The operating clock frequency is 8 kHz. CMOS interface.
Fixing at "H" or "L" causes part of the CODEC section to power-down.
36
CLK
I
D
Input pin for setting the bit rate for the transmission and reception PCM
signals. The data rate can be selected from 64 kHz to 3.152 MHz for µ-law
or A-law operation, or from 128 kHz to 3.152 MHz for linear operation. Fixing
at "H" or "L" causes part of the CODEC section to power-down. CMOS
interface.
37
TCLK
I
D
Clock input pin for tone generation. The internal clock divided by one or two
(set by D4D3 of address 01110) can be used as the tone CLK. CMOS
interface.
38
VD4
P
D
Digital power supply pin. Supply a voltage between 2.7 V and 3.6 V.
39
SRD
I
D
10-bit serial data input pin. CMOS interface. This data sets the electronic
volume, path, and tone settings.
40
SRC
I
D
Write clock input pin for the 10-bit serial data. CMOS interface.
SRD is clocked in the rising edge.
41
STB
I
D
Strobe signal for the serial data latch. Latches on "L". CMOS interface.
42
XPRST
I
D
Reset signal input pin for the digital circuits. CMOS interface.
L: Initialize internal latches. H: Normal
43
LO0
O
D
Latch output pin for external control. Outputs D0 of address 01000. CMOS
interface.
44
LO1
O
D
Latch output pin for external control. Outputs D1 of address 01000. CMOS
interface.
45
LO2
O
D
Latch output pin for external control. Outputs D2 of address 01000. CMOS
interface.
46
LO3
O
D
Latch output pin for external control. Outputs D3 of address 01000. CMOS
interface.
47
PS
I
D
Power-down control signal input pin. CMOS interface. Powers down all
circuits regardless of register settings.
48
VS3
G
D
Digital ground pin. Set to 0 V.
MB86437
■ BLOCK DIAGRAM
SGC (24) BTPO (31) BTPI (30)
SGI
(26)
SGO
(27)
–
BBO (29)
VS 1 (8)
VS 2 (23)
VS 3 (48)
VS 4 (25)
SW1
VREF
+
STA (28)
generator
AMP5
AO
SGC
SGC
VREF generator block
–
+
EV0
(Invert)
4bit
SW3
0 dB
0 dB (RST)
Microphone amp (1)
–
+
AMP1
SGC
DOUT
(34)
A/D
+
MDI
(13)
Transmitting block
SGC
Microphone amp (2)
SGC
SW5
512 K
0 dB (RST)
0 dB SW13
4bit
SINGLE: –14 dBv Tone generator
block
DUAL: –14 dBv
–15 dB
15 dB
(RST)
(RST)
DUAL
TONE
EV4
EV3
(Invert)
+
3bit
4bit
ATT
SW16
–30 to 0 dB 8 to 23 dB
–15 dB 5 dB step 1 dB step
–7 to 8 dB
1 dB step
EV2
(Invert)
–
SW11
+
3bit
AMP3
SGC
–15 to 15 dB, 5 dB step
–14 dB
(RST)
0 dB SW8b
SW12
–
+
PD
SGC SW8a
EV5
3bit 0 dB
SW10
0 dB (RST)
LPF
D/A
–18 to –11dB
1 dB step
3bit
–
+
0 dB SW6b
Receiver speaker drive block
–
AMP4
SW15
–
+
CONTROL
LOGIC
SGC
Earphone speaker drive block
10 dB (RST)
0 dB, 10 dB
6 dB (RST)
0 dB, 6 dB
PSAVE
SW7b
EV8
1bit
EV9
1bit
XEAR
(7)
–
+
AO
Control
block
0 dB
EAR
(6)
PD
SGC
–3 dB (RST)
–9 to 0 dB
3 dB step
EV7
2bit
Receiving
block
PD
0 dB
+
SGC
TAUD
(17)
EXSD
(16)
DSCK
(15)
PTBO
(12)
SWI
(1)
SWO
(2)
RAUD
(3)
–8 dB (RST)
–14 to 0 dB
EV6
2 dB step
SW 2
SGC
SW6a
TBO
(10)
TBI
(11)
SRD
(39)
SRC
(40)
STB
(41)
JMIC
(21)
–
+
Codec block
PLL
EV1
TCLK
(37)
SW4
AMP2
SYNC
(35)
CLK
(36)
DIN
(33)
–7 to 8 dB
1 dB step
–
BPF
MICO
(18)
MIC
(19)
XMIC
(20)
JMICO
(22)
PD
JEAR
(5)
SW7a
0 dB SW9b
–
0 dB
SW9c
+
PD
SW14
TONE
(9)
SGC SW9a
Tone speaker drive block
XPRST LO0 LO1 LO2 LO3
(42) (43) (44) (45) (46)
: Digital input
PS (47)
: Digital output
VD1 (4) VD2 (14) VD3 (32) VD4 (38)
: Analog input
: Analog output
Electronic volume:
• (RST) indicates the value for reset
• (inverting) indicates the inverted phase
between input and output.
: Input/output
: VDD
: GND
5
MB86437
■ FUNCTIONAL DESCRIPTION
1. Register Settings
The MB86437 IC chip controls all electronic volume, switch, tone generator circuit and power-down control circuit
by means of the SRD, STB and SRC input.
(1) Mode setting
The data format consists of 10 bits of serial data. The first 5 bits (A4 to A0) are the address and the next 5 bits (D4
to D0) are data. SRD is clocked in on the rising edge of SRC and latched when STB is "L". During power-down, the
register is not reset and writing to the register is possible. A reset and data initialization occurs when XPRST is "L".
Data Address
Meaning
Data Setting
After a Reset
D4 D3 D2 D1 D0
Data Meaning
D4
D3
D2
D1
D0
A00 00000
Test mode
0
0
0
0
A01 00001
EV0 gain
0
1
1
1 X EV0 [0000: –7 dB to 1111: 8 dB, step 1 dB,
Reset: 0 dB]
X
A02 00010
EV1 gain
0
1
1
1 X EV1 [0000: –7 dB to 1111: 8 dB, step 1 dB,
Reset: 0 dB]
X
A03 00011
EV2 gain
X X 0
A04 00100
Transmit mute 1
(SW3, 4, 5)
Receive mute 1
(SW6b, 7b, 8b,
9b, 9c)
X
0 X X X 0 Receive
mute
(SW6b, 7b,
8b, 9b, 9c)
1: Mute 1
0: No mute
X
A05 00101
SW8, 3, 4, 5
mute 2
1 X 1
1 SW8
X
1: Mute 2
0: No mute
Valid when
D4 of A04 is
"0"
SW4
SW5
SW3
1: Mute 2 1: Mute 2 1: Mute 2
0: No mute 0: No mute 0: No mute
1 EV7
[00: –9 dB to 11: 0 dB,
step 3 dB, Reset: –3
dB]
SW9b9c
SW6b
SW7b
1: Mute 2 1: Mute 2 1: Mute 2
0: No mute 0: No mute 0: No mute
A06 00110
EV7 gain/SW7b, 1
9b, 9c, 6b mute
2
0
1
1
1
1
0 00000: Normal operation (writing prohibited)
1 X
X
EV2 [000: –15 dB to 111: 15 dB,
step 5 dB, Reset: 0 dB]
X
Transmit
mute
(SW3, 4,
5)
1: Mute 1
0: No mute
Valid when D0 of A04 is "0"
Valid when D4 of A04 is "0"
A07 00111
SW2, 11, 12, 10 X 1
control
0
0
0 X
SW2
1: ON
0: OFF
SW11
1: ON
0: OFF
SW12
1: ON
0: OFF
SW10
1: ON
0: OFF
A08 01000
Digital parallel
output
X 0
0
0
0 X
L03
L02
L01
L00
A09 01001
EV3 gain
0
1
1 X EV3 [0000: 8 dB to 1111: 23 dB, step 1 dB,
Reset: 15 dB]
1
X
(Continued)
6
MB86437
(Continued)
Data Address
Meaning
Data Setting
After a Reset
Data Meaning
D4 D3 D2 D1 D0
A0A 01010
Tone [1] setting
0
0
0
0
D4
D3
D2
D1
D0
0 Tone 1
na = a7 × 27 + a6 × 26 + … + a1 × 2 + a0
waveform
1: Square
wave a7
a6
a5
a4
0: Sine wave
A0B 01011
A0C 01100
Tone [2] setting
X 0
0
1
0 X
0
0
0
0 Tone 2
nb = b7 × 2 + b6 × 2 + … + b1 × 2 + b0
waveform
1: Square
b6
b5
b4
wave b7
0
a3
a2
7
a1
a0
6
0: Sine wave
A0D 01101
X 0
0
1
0 X 0
0 X
b2
Divide ratio Division X
ratio
(TCLK/N)
(M)
00 TCLK/1 12 divisions
01 TCLK/1 24 divisions
10 TCLK/2 24 divisions
11 Use prohibited
b1
b0
Tone [1]
control
1:
Generate
0: Stop
Tone [2]
control
1:
Generate
0: Stop
A0E 01110
Tone waveform
setting
(for tones [1]
and [2])
0
A0F 01111
CODEC
compression
rule
X X X 0
A10 10000
PD control and
0
SW14 control for
CODEC, TONE,
SGO, and
transmission
(TX)
0
0
0 CODEC PD TONE PD SGO PD Transmit1: PD
1: PD
1: PD
ter PD
0: Operate 0: Operate 0: Operate 1: PD
0: Operate
SW14
1: TONE
output 0 V
0: Operate
A11 10001
PD control for
0 X 0
RAUD, JEAR,
TONE, and EAR
0
0 RAUD PD X
(SW8a)
1: Independent
0: Linked
EAR PD
(SW6a)
1: Independent
0: Linked
0
0
b3
0 X
X
X
JEAR PD
(SW7a)
1: Independent
0: Linked
CODEC companding law
00: µ-LAW
01: Linear
10: A-LAW
11: Use prohibited
TONE PD
(SW9a)
1: Independent
0: Linked
Independent: Do not power-down corresponding amplifier in
conjunction with mute.
Linked: Power-down corresponding amplifier in conjunction
with mute.
A12 10010
DOUT/SW1, 13,
9b, 9c
0
0
0
1
1 DOUT
1: Fixed at
"H"
0: Operate
SW1 mute SW13
1: Mute
mute
0: No mute 1: Mute
0: No mute
SW9b
mute
0: Mute
1: No mute
SW9c
mute
0: Mute
1: No mute
The tone frequencies are as follows. (fa and fb are the frequencies of tones [1] and [2] respectively.)
(fin = TCLK input frequency (512 kHz recommended when N = 1, M = 12, 1024 kHz recommended when N = 1,
M = 24 → fin/(N × M) = 42.667 kHz), N: Divide ratio (1 or 2), M: Number of divisions (12 or 24))
fa = (fin/(N × M))/(na + 1), fb = (fin/(N × M))/(nb + 1)
(Continued)
7
MB86437
(Continued)
Data Address
Meaning
Data Setting
After a Reset
D4 D3 D2 D1 D0
Data Meaning
D4
D3
D2
D1
D0
A13 10011
EV8, EV6 gain
1 X 0
1
1 EV8 gain
1: 10 dB
0: 0 dB
X
EV6 [000: –14 dB to 111: 0 dB,
step 2 dB, Reset: –8 dB]
A14 10100
EV4 gain
X X 0
1
1 X
X
EV4 [000: –30 dB to 111: 0 dB,
step 5 dB, Reset: –15 dB]
A15 10101
EV9, EV5 gain
1 X 0
1
1 EV9 gain
1: 6 dB
0: 0 dB
X
EV5 [000: –11 dB to 111: –18 dB,
step 1 dB, Reset: –14 dB]
A16 10110
SW15, 16
control
X X X 0
0 X
X
X
SW15
1: AMP5
0: AMP4
SW16 * 1
1:
Envelope
0: ATT
A17 10111
All PD
X X X X 1 X
X
X
X
All circuits
PD
1: Normal
0: PD
Notes: 1. When unused, connect the MDI input to OPEN or SGC. When using ATT, an SGC-centered signal or
capacitive coupling is required (to prevent an offset).
2. Set X to 0.
3. Set to initial value by a reset (____ section).
8
MB86437
(2) Transmitting audio mute settings
Switches SW1, SW3, SW4, SW5, SW10, and SW11 have the following functions. Address 00100 signals have
priority.
Setting
Address
Data bit
: ON,
A4 to A0
A4 to A0
A4 to A0
A4 to A0
Switching setting
00100
00101
00111
10010
D4 to D0
D4 to D0
D4 to D0
D4 to D0
–* * *1
–*–––
*––––
–––––
—
–* * *0
–*01–
*––––
–––––
—
–* * *0
–*10–
*––––
–––––
—
–* * *0
–*––0
*–0–0
–––––
—
—
—
–* * *0
–*––1
*–0–1
–––––
—
—
—
–* * *0
–*––1
*–1–0
–––––
—
—
—
–* * *–
–*–––
*––––
–1–––
—
—
SW1 SW3 SW4 SW5
Remarks
SW1 SW1
0
1
—
—
—
—
—
—
—
—
—
—
—
Microphone amp
[1], [2] mute
Microphone amp
[2] mute
Microphone amp
[1] mute
: OFF, — : not determined
(3) Receiving audio mute settings
Switches SW6b, SW7b, SW8b, SW9b, SW9c, and SW12 have the following functions. Address 00100 signals have
priority.
Setting
Address
Data bit
: ON,
A4 to A0
A4 to A0
A4 to A0
A4 to A0
A4 to A0
00100
00101
00110
00111
10010
D4 to D0
D4 to D0
D4 to D0
D4 to D0
D4 to D0
1* * *–
–*–––
–––––
*––––
–––––
0* * *–
1*–––
–––––
*––––
–––––
—
0* * *–
0*–––
––1––
*––––
–––––
—
0* * *–
–*–––
––01–
*––––
–––––
—
0* * *–
–*–––
–––0–
*––––
–––01
—
0* * *–
–*–––
–––0–
*––––
–––10
—
0* * *–
–*–––
––––1
*––––
0* * *–
–*–––
––––0
0* * *–
–*–––
–––––
Switching setting
Remarks
SW6 SW7 SW8 SW9 SW9 SW1
b
b
b
b
c
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–––––
—
—
—
—
*0–––
–––––
—
—
—
—
*1–––
–––––
—
—
—
—
—
—
: OFF, — : not determined
9
MB86437
(4) Electronic volume controls
There are ten different electronic volume controls, EV0 through EV9, with the following specifications. Electronic
volume control settings are made by the SRD, SRC and STB signals, and setting values are reset by the XPRST
signal.
Table 1 Relation of Volume Control Data bit Values to Gain
Address 00001
Data
EV0
Code
D4 D3 D2 D1
D0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00010
00011
01001
10100
10101
10011
00110
10011
10101
EV1
EV2
EV3
EV4
EV5
EV6
EV7
EV8
EV9
NonNonNonNonNonNonNonInverte Inverte
Inverte
Inverte Inverte Inverte Inverte Inverte Inverte Unit
Inverte
d
d
d
d
d
d
d
d
d
d
D4 to
D1
D4 to
D1
D2 to
D0
D4 to
D1
D2 to
D0
D2 to
D1
D2 to
D0
D4 to
D3
–7
–7
8
–6
–6
–5
–5
–4
–4
–15
–10
–5
0
5
10
15
15
–30
–25
–20
–15
–10
–5
0
0
–11
–12
–13
–14
–15
–16
–17
–18
–14
–12
–10
–8
–6
–4
–2
0
–3
–3
12
–2
–2
13
–1
–1
14
0
0
15
1
1
16
2
2
17
3
3
18
4
4
19
–11
–12
–13
–14
–15
–16
–17
–18
–14
–12
–10
–8
–6
–4
–2
0
5
5
20
6
6
21
7
7
22
8
8
23
–9
–9
–9
–9
–9
–9
–9
–9
–6
–6
–6
–6
–6
–6
–6
–6
–3
–3
–3
–3
–3
–3
–3
–3
0
0
0
0
0
0
0
0
9
10
11
Notes: • Each setting value is determined in relation to the initial setting value.
• Returns to initial value at reset (
parts)
• The "Inverted" and "Non-Inverted" columns indicate the I/O phase.
• Settings with no gain figure listed are undefined.
10
D4
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
10
10
10
10
10
10
10
10
6
6
6
6
6
6
6
6
dB
MB86437
(5) Tone generation circuit
This section describes the frequency settings and output control.
• Tone frequency control register
The clock used to generate tones is the clock input from TCLK divided by 1 or 2. The divide ratio is set by the data
at address 01110. Also, 12 division and 24 division modes are available to generate a smooth frequency even at
low frequencies.
Table 2 Register Control for the TONE Clock Frequency
Address 01110
D4
D3
0
0
1
1
0
1
0
1
Tone Generation Clock (fIN)
Waveform Division
Frequency input to TCLK
Frequency input to TCLK
Frequency input to TCLK divided by 2
Prohibited
12 divisions
24 divisions
24 divisions
The following formula specifies the frequencies that can be set by the tone frequency control register.
Set frequency f = fIN/(M × (1 + n)), M = division mode (12 or 24)
n = 4, 5, ..., 255 (fIN: Tone generation clock)
fIN = 4 MHz max.
Therefore, the range of available frequencies in 12 division mode and fIN = 512 kHz, and in 24 division mode and
fIN = 1024 kHz is:
fmin = 167 Hz, fmax = 8533 Hz
Table 3 lists the frequency settings for all the standard DTMF frequencies.
Table 3 Tone Frequency Register Control
(Setting: 12 divisions and fIN = 512 kHz, or 24 divisions and fIN = 1024 kHz)
Tone Type
Service tones
(Single tone)
Low tones
D
T
M
F
High tones
Standard
Frequency
(Example of
generated
frequency)
Set
Frequency
400 Hz
Address
01010/01100
Address
01011/01101
n
Error
0
106
–0.32%
0
0
20
1.56%
1
0
0
60
0.34%
0
1
1
0
54
0.74%
∗
0
0
0
1
49
0.15%
0
∗
1
1
0
0
44
0.75%
1
0
∗
0
0
1
0
34
0.82%
0
0
1
∗
1
1
1
1
31
–0.20%
0
0
0
1
∗
1
1
0
0
28
–0.38%
0
0
0
1
∗
1
0
0
1
25
0.48%
D4
Data
D3 D2 D1 D0
D4
Data
D3 D2 D1 D0
398.7 Hz
—
0
1
1
0
∗
1
0
1
2000 Hz
2031.7 Hz
—
0
0
0
1
∗
0
1
697 Hz
699.4 Hz
—
0
0
1
1
∗
1
770 Hz
775.7 Hz
—
0
0
1
1
∗
852 Hz
853.3 Hz
—
0
0
1
1
941 Hz
948.1 Hz
—
0
0
1
1209 Hz
1219.0 Hz
—
0
0
1336 Hz
1333.3 Hz
—
0
1477 Hz
1471.3 Hz
—
1633 Hz
1641.0 Hz
—
Notes: • Settings are shown in binary notation.
• Error is the error between the set frequency and standard frequency.
• Set n to 4 or higher and set a frequency of 5 kHz or less.
11
MB86437
• Tone output waveform
The D4 data bit at address 01010, 01100 may be used to select either sine-wave or trapezoidal waveforms for tone
output.
VH
D4 = 0
Sine wave
output
VL
1
2
3
4
5
6
7
8
9 10 11 12
1
2
3
4
5
VH
D4 = 1
Trapezoidal wave
output
VL
• Tone output control
Tone output is controlled by addresses 01110 and 00111. Provided TCLK does not stop, sine wave output always
halts close to zero. Also, SW2 controls output muting.
Address 01110
DATA – – – D1 –
(Tone [1] control)
Address 01110
DATA – – – – D0
(Tone [2] control)
Address 00111
DATA – – – D1 –
(SW2 control)
PTBO output
(sine wave mode)
Mute set by
SW2
SGC
Waveform halts at zero
crossover point.
Tone section output SGC
(sine wave mode)
Single tone
Dual tone
Waveform halts at zero
crossover point.
Single tone
: Disable
12
MB86437
• Tone envelope
Even if the tone halts at close to zero, changes in the DC voltage can still occur can be audible. Using SW16 for
tone control enables the voltage level for tone generation to be controlled. The waveform amplitude characteristics
have the following general relationships.
Va = 2 × (0.47 – 0.12 × Vl) (Vl: MDI voltage, Va = Tone amplitude)
R5
Control clock
R4
210 kΩ
V1
MDI
C1
SW 16
130 kΩ
Tone
output
25 kΩ
Vl
Vh
VR
–
MDI
+
AMP 3
SGC
For a cut off frequency of 8.3 Hz, control clock of 0 to 3 V, and SGC = 1.5 V, the envelope ratio and resistor and
capacitor values are as follows.
Recommended Values
Vh, Vl Voltages
Envelope Ratio
Aim Value
R4
R5
C1
Max. (Vh)
Min. (Vl)
Envelope Ratio
Calculated Value
–3 dB
33 kΩ
22 kΩ
1.5 µF
0.828 V
0.584 V
–3.13 dB
–4 dB
47 kΩ
18 kΩ
1.5 µF
0.824 V
0.516 V
–4.05 dB
–5 dB
82 kΩ
15 kΩ
1.5 µF
0.810 V
0.448 V
–5.15 dB
–6 dB
270 kΩ
15 kΩ
1.5 µF
0.790 V
0.400 V
–5.91 dB
13
MB86437
(6) CODEC I/O
Code companding for µ-law and A-law is in accordance with CCITT Recommendation G.711.
Linear coding uses 14-bit, two's complement code which is output MSB-first.
Address 01111 is used to control µ-law, A-law, and linear code I/O.
SYNC
Din, Dout
MSB
12
11
10
1
LSB
Table 4 Table of Linear Code vs. Voltage
MSB
Code
0 1 1 1 1 1 1 1
to
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
to
1 0 0 0 0 0 0 0
LSB
PTBO Standard Voltage (V)
1 1 1 1 1 1
2.2647
to
1.5009
1.5000
1.4991
to
0.7354
0 0 0 0 0 1
0 0 0 0 0 0
1 1 1 1 1 1
0 0 0 0 0 1
(7) Parallel output
LO0 to 3 are general-purpose latch outputs for external control. LO0 to 3 output the data written to address 01000.
The outputs are CMOS outputs. Data output continues during power-down.
D3
D2
D1
D0
Address 01000
LO0
LO1
LO2
LO3
(Inside IC)
14
MB86437
2. Analog Input
Analog inputs in the MB86437 include the two microphone inputs and the three accessory input.
(1) Microphone amps
The microphone amps take the incoming signal from the microphones and amplify it to any desired level of gain.
The microphone amps are low-noise types for use with capacitor microphones, and are capable of a wide range of
amplification. All microphone amps must be AC coupling with capacitors to prevent amplification of DC offset level.
Mike amplifier characteristics (open loop characteristics)
Gain (dB)
80
40
0
–40
10
1K
1M
Frequency (Hz)
V DD
MICO
–
+
Capacitor type
Mike
MIC
XMIC
(Inside IC)
SGC
AG
(2) Accessory input
Direct input from the TAUD to the codec unit is possible through SW5, without passing through the microphone
amp. Care must be taken with the input signal in this case, however, because input resistance is not at highimpedance level.
Microphone amp output may be added to the signal by using switching controls.
In this case, the result will be at the additional output level.
In addition, SW10 and SW11 may be used to transmit digital data from the TAUD to EXSD and DSCK, allowing the
sending of fax or PC data without modification.
Approximately 100 kΩ
0 dB
SW5
TAUD
SW10
–
CODEC
EXSD
+
SW11
SGC
DSCK
(Inside IC)
Note: TAUD, EXSD, and DSCK contain no buffers. If not used,
TAUD, EXSD and DSCK should be connected to SGC.
15
MB86437
3. Analog Output Relationships
The four analog outputs consist of three speaker drivers (for receiver, earphone, and tone) and an accessory output.
(1) Speaker driver amps
The speaker driver amps consist of one BTL output (the receiver output) and one single output (the earphone
output). Also, the sounder driver consists of one single output and the sounder output can be obtained via a transistor.
As the speaker amps have high power consumption, separate power-down control is available for each speaker amp.
Parameter
Output type
Load resistance *1
Load capacitance *2
Maximum output power
*1:
*2:
Receiver Speaker Amp
(EAR, XEAR)
Earphone Speaker Amp
(JEAR)
Tone Amp
(TONE)
BTL
32 Ω (typ.)
0.1 µF
10 mW (min.)
Single
32 Ω (typ.)
0.1 µF
5 mW (min.)
Single
600 Ω (typ.)
Dynamic speaker
A capacitor is required to prevent oscillation.
• Analog output connection example
EV6
EAR
_
+
C1
SGC
Receiver speaker
Dynamic type: 32 Ω (typ)
–
TBO
+
C1
XEAR
SGC
JEAR
EV7
–
+
C2
Earphone speaker
Dynamic type: 32 Ω (typ)
C1
SGC
EV8
Sounder
EV9
TONE
–
EV4
+
SGC
SW 14
(Inside IC)
Note: Insert C1 capacitors of approximately 0.1 µF to prevent oscillation. C2 is to cut DC.
16
MB86437
4. Reception Connections
This section describes reception connections, sidetone addition, and melody IC connection.
(1) Reception connections
This describes the connection to the speaker amp for the reception signal.
Provide a high-pass filter at AMP4 to prevent a DC offset being applied to the speaker amp.
• First-order high-pass filter
EV2
PTBO
C1
R1
TBI
R2
–
+
AMP4
TBO
SGC
To speaker amplifier
(2) Sidetone addition
Sidetone addition is implemented by connecting the STA output and AMP4. In this case, use of a resistor of
approximately 100 kΩ at AMP4 is recommended as the SW1 on resistance affects the sidetone gain.
PTBO
sw1
STA
C1
R1
TBI
R2
C1
R1: Use a resistor of approximately 100 kΩ.
–
+
AMP4
TBO
SGC
To speaker amplifier
17
MB86437
(3) Melody IC connection
A melody IC can be connected using AMP4. However, the level can be made to vary in the same way as the tone
if the MDI pin is used. MDI has an input impedance of approximately 140 kΩ and is not high impedance.
(–14 dBv typ)
DUAL TONE
(–15 dB)
Melody
IC
MDI
SW16 Approximately
140 kΩ
–
To EV4
+
SGC
(4) JEAR signal selection
JEAR can receive a signal from AMP4 or AMP5. This enables a range of applications to be implemented depending
on the AMP4 and AMP5 circuit structures.
• Example of switching EAR and JEAR
PTBO
TBO
TBI
–
To EAR
+
AMP4
SGC
SGO
To JEAR
SW15
SGI
–
+
AMP5
SGC
(5) Preventing a clicking sound when the electronic volume gain is changed or when muting
Changing the gain of the electronic volume or muting may result in a clicking sound due to fluctuation in the DC
level. In such cases, the following setting is recommended.
Set the mode in which powering down the speaker amplifier is not linked with SW6b, 7b, 8b, and 9b (ADDRESS:
10001, DATA: 10111) and mute using SW6b, 7b, 8b, and 9b.
18
MB86437
5. Power-Save Mode
This section describes the setting methods and states.
(1) Mode setting
Power-save mode can be controlled by an external control signal and register setting.
The various modes set each block to a power-save state, enabling the power consumption to be reduced.
• Power-save mode setting table
Address
TONE
EV2 AMP3, 4
Accessory
Ear Phone
TONE
Receiver
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VREF
operation
1
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SGO PD
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
TONE
operation
1
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CODEC,
TONE PD
1
–
–
–
–
–
–
1
1
–
–
–
–
–
–
–
–
–
CODEC
operation
1
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CODEC
SYNC PD
1
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Transmission
operation
1
–
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
Transmission
PD
1
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
–
1
1
1
1
0
1
–
–
0
1
0
0
–
–
–
–
1
0
–
1
1
1
0
0
1
–
–
0
1
0
0
–
–
–
–
1
0
–
1
1
0
1
0
1
–
–
0
0
0
1
–
–
–
–
1
1
–
0
0
0
0
0
1
–
–
1
1
0
0
–
–
–
–
1
0
–
1
1
1
1
0
1
–
–
1
1
1
1
–
–
–
–
PS
or
00100 00101
00110
10000
10001
Address
10111
Reception
operation
D4 D0
D4
D2 D1 D0 D4 D3 D2 D1 D4 D2 D1 D0 STOP
: Operation enabled,
: Changes depending on address 10001,
AMP5
All PD
Mode
VREF
CODEC
Reception
Transmission
SYNC
or
CLK
: Power-down
Note: Powering down the CODEC or TONE generator powers down the entire reception block.
19
00101
00110
1
1
1
1
CODEC
operation
TONE
operation
TONE
mute
TONE
GND
0
1
1
1
1
CODEC
SYNC
PD
Transmission
mute
1 1 1
0
0
0
0
0
0
1
1
0
1
1 1
–
Transmission
halt
1
1
Transmission
PD
1 1
1
CODEC,
TONE
PD
1
R
R
–
1
– – –
– H –
– –
–
S S –
S
– – – –
– – –
– – – G – – – – –
– – – S – – – – –
– – – –
– – – –
STO
– – – – – – – – –
P
– – – – –
– – – – –
–
– – –
– – –
– – –
–
– H –
– – –
– – –
– – – – – – – – – – – H –
– – – – –
R – – – R
– – – – – – – – –
– – –
1
S – – – – –
S – – – –
SGO PD
0 0 1 1
S
S
JEAR
0
1 1 1
RAUD
S
EAR, XEAR
1
1
TONE
– – –
1 1 0 0
TBO, PTBO
1
SYNC
or
CLK
MICO, JMICO
1
1
10010
SGC
Reception mute
1
10001
D4 D3 D2 D1 D0 D4 D2 D1 D0 D4 D3 D2 D1 D0
10000
SGO
H *
D3
00111
DOUT
0
D4 D0 D4 D2 D1 D0 D2 D1 D0
PS
00100
or
Address
10111
LO0 to 3
All PD
Mode
STA
Output Pin State
BBO
20
BTPO
Address
MB86437
(2) Output pin states in each mode
: High impedance, S: Signal ground, R: Connected to signal ground via high resistance, : Normal operation
* : Depends on value of address 01000, G: Ground output, R1: Connected to signal ground via high resistance
when SW1 is on.
H : High level output
MB86437
■ TIMING CHART
(1) Codec-Related Signals
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[13]
[14]
CLK
fC
fS*
SYNC
i
ii
iii
iv
v
vi
vii
viii
Xiii Xiv
1
2
3
4
5
6
7
8
13 14
DOUT
DIN
(1)
(2)
(3)
(3)
A-Iaw
( µ-law
)
(14bit-linear)
[Enlarged view]
(1)
[1]
[2]
CLK
t XS
t SX
SYNC
t WSH
i
ii
DOUT
t CO
(2)
[5]
t ZD
[6]
CLK
tF
tR
t DR
5
t RD
6
DIN
(3)
( [13] )
[7]
( [14] )
[8]
CLK
tWCH
t WCL
t DZ
t CO
vii
viii
DOUT
t DF
*: From first CLK Down to second CLK Down, SYNC = H.
21
MB86437
(2) Microcomputer Data-Related Signals
XPRST
t WRE
A4
A3
A2
A1
A0
D4
D3
D2
D1
D0
SRD
SRC
f SC
STB
LO 0 to 3
(1)
[Enlarged view]
t SSC
(1)
t HSC
SRD
D1
D0
t HCB
SRC
t WL
t SCB
STB
t DS
LO 0 to 3
t LD
22
t WH
MB86437
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter
Rating
Symbol
Min.
Max.
Unit
Power supply voltage
VDD
–0.3
+6.0
V
Analog input voltage
VAIN
–0.3
VDD + 0.3
V
Digital input voltage
VDIN
–0.3
VDD + 0.3
V
Storage temperature
Tstg
–55
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Pin name
Operating temperature
Ta
—
Power supply voltage
VDD
"H" level digital input voltage
VH
"L" level digital input voltage
VL
Analog output load resistance
RLB
Value
Unit
Min.
Typ.
Max.
–20
25
80
°C
2.7
3.0
3.6
V
VDD × 0.7
—
VDD
V
0.0
—
VDD × 0.3
V
*2
50
—
—
kΩ
CLB
BTPO, BBO, PTBO, TBO,
SGO
—
—
20
pF
CLS
Between SGC-VS4
—
10
—
µF
RLE
Between EAR-XEAR
28
32
—
Ω
Analog output load capacity*1
CLE
EAR,
Between XEAR-GND
0.1
—
—
µF
Analog output load resistance*1
RLJ
JEAR
28
32
—
Ω
Analog output load capacity*1
CLJ
Between JEAR-GND
0.1
—
—
µF
Analog output load resistance
RLT
600
—
—
Ω
Analog output load capacity
CLT
—
—
100
pF
Analog output load resistance
RLM
10
—
—
kΩ
Analog output load capacity
CLM
—
—
20
pF
Analog output load resistance
RLM
5
—
—
kΩ
Analog output load capacity
CLM
—
—
20
pF
All Amp. output pins
0.45
—
VDD–0.45
V
Analog output load capacity
Analog output load resistance*
Analog output voltage
1
VAOUT
VD1, VD2, VD3
All digital input pins
TONE
MICO, JMICO
RAUD
Analog input voltage
VAIN
All Amp. input pins
1.2
1.5
1.8
V
TCLK frequency
FTCLK
TCLK
—
—
4.0
MHz
*1:
*2:
Dynamic typ speakers
BTPO, BBO, PTBO, TBO, SGC, SGO
23
MB86437
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
Power supply current at
full power-down mode
IPD
Power supply current for
normal operation
(all operation)
Digital input current
Digital output voltage
Pin
All VDP pins
IVD2
IIH
IIL
VOH
VOL
Conditions
Typ.
Max.
PS = 0
Digital input = GND
—
0.5
50
µA
All blocks operating, CLK =
2048, SYNC = 8 kHz,
no signal
—
5.0
10
mA
—
—
—
10
µA
—
—
—
10
µA
VDD×0.8
—
VDD
V
IOL = 1.5 mA
0.0
—
VDD×0.2
V
IOH = –1.5 mA
Input offset voltage
VFM
Between
MIC-XMIC
MICO-MIC short
–10
—
10
mV
Output offset voltage
VFE
Between
EAR-XEAR
TBO-TBI short EV6 = 0 dB
–20
—
20
mV
SGC output voltage
VSGC
SGC
—
1.40
1.50
1.60
V
RSW
Between
SWI-SWO
SW12 = on
—
—
2
kΩ
RTE
Between
TAUD-EXSD
SW10 = on, SW11 = off,
SW5 = off
—
—
2
kΩ
RTD
Between
TAUD-DSCK
SW10 = off, SW11 = on,
SW5 = off
—
—
2
kΩ
RTG
Between
TONE-VS
SW14 = on
—
—
2
kΩ
RBS
Between
BBO-STA
SW1 = on
—
—
2
kΩ
RITA
TAUD
Operating
70
100
140
kΩ
RIMDA
MDI
Operating, SW16 = ATT
100
140
200
kΩ
RIMD
MDI
Operating,
SW16 = envelope
150
210
300
kΩ
IOFH
RAUD, TONE
SW8a, SW9a, b, c,
14 = off, Vin = 0 to VDD
–10
—
10
µA
Inter-pin resistance
Input resistance
Analog output off leak
Note: Measurement conditions: ■ Standard Test Circuit
24
Unit
Min.
All digital input
pins
All digital
output pins
Value
MB86437
2. AC Characteristics
(1) Codec-Related Signals
Parameter
Symbol
Digital input rise time
tR
Digital input fall time
tF
Shift clock frequency
fC
Conditions
Value
Unit
Min.
Typ.
Max.
—
—
50
ns
—
—
50
ns
µ-law, A-law
64
—
3152
kHz
Linear
128
—
3152
kHz
VS × 0.3 → VS × 0.7
Shift clock pulse width (H)
tWCH
VIH = VS × 0.7
1/fC×0.3
—
1/fC×0.7
ns
Shift clock pulse width (L)
tWCL
VIL = VS × 0.3
1/fC×0.3
—
1/fC×0.7
ns
Sync frequency
fS
—
—
8
—
kHz
Sync pulse width
tWSH
—
1/fC
—
62
µs
SYNC to CLK setup time
tSX
—
100
—
—
ns
CLK to SYNC hold time
tXS
—
50
—
—
ns
CLK to DIN hold time
tRD
—
50
—
—
ns
DIN to CLK setup time
tDR
—
50
—
—
ns
SYNC to DOUT delay time
tZD
BIT 1
—
—
200
ns
CLK to DOUT delay time
tCO
BIT 2 to 8
—
—
200
ns
CLK to DOUT disable time
tDZ
“H”
—
—
200
ns
(2) Microcomputer Data-Related Signals
Parameter
Symbol
Pin
Value
Unit
Min.
Typ.
Max.
50
—
—
ns
50
—
—
ns
50
—
—
ns
200
—
—
ns
200
—
—
ns
SRC to SRD data setup time
tSSC
SRC to SRD data hold time
tHSC
SRC to STB setup time
tSCB
SRC pulse width (H)
tWH
SRC pulse width (L)
tWL
STB pulse width
tDS
STB
50
—
—
ns
STB to SRC hold time
tHCB
STB, SRC
50
—
—
ns
LO0 to 3 delay time
tLD
LO0 to 3
—
—
200
ns
Shift clock frequency
fSCLK
SRC
—
—
2048
kHz
Reset pulse width
tWRE
XPRST
1
—
—
µs
SRD, SRC
SRC, STB
SRC
25
MB86437
3. Transmission Characteristics
(1) Microphone Amp System
Parameter
Symbol
Gain
(between MICO and BBO)
GMB
Gain
(between JMICO and BBO)
Conditions
Value
Unit
Min.
Typ.
Max.
MICO = –20 dBV, 1020 Hz
SW3 = on, SW1 = SW4 = SW5 = off
EV0 = 0 dB
–1.5
—
1.5
dB
GJB
JMICO = –20 dBV, 1020 Hz
SW4 = on, SW1 = SW3 = SW5 = off
EV0 = 0 dB
–1.5
—
1.5
dB
Gain
(between TAUD and BBO)
GTB
TAUD = –20 dBV, 1020 Hz
SW5 = on, SW1 = SW3 = SW4 = off
EV0 = 0 dB
–1.5
—
1.5
dB
Signal to noise ratio
(Microphone amp [1])
SMB
Ain1 = –40 dBV (+20 dBgain), 1020 Hz
SW3 = on, SW1 = SW4 = SW5 = off
C message, Measured at MICO
40
—
—
dB
Signal to noise ratio
(Microphone amp [2])
SJB
Ain2 = –40 dBV (+20 dBgain), 1020 Hz
SW4 = on, SW1 = SW3 = SW5 = off
C message, Measured at JMICO
40
—
—
dB
STB
TAUD = –40 dBV, 1020 Hz, SW5 = on,
SW1 = SW3 = SW4 = SW10 = SW11 =
off, EV0 = 0 dB, C message,
Measured at BBO
40
—
—
dB
Signal to noise ratio
(BBO)
Note: Measurement conditions: ■ Standard Test Circuit
(2) Reception
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
GTR
Measured at RAUD
–1
0
1
Gain
GTE
EV6 = 0 dB,
Measured between EAR and XEAR
5
6
7
Conditions:
TBO = –20 dB, 1020 Hz
GTJ
EV7 = 0 dB, Measured at JEAR
–1
0
1
GTT
EV8 = 0 dB, SW9b = on,
SW9c = off, Measured at TONE
–1
0
1
PE
R = 32 Ω, Between EAR and XEAR,
EV6 = 0 dB, THD = 10%, 1020 Hz
10.0
—
—
mW
PJ
R = 32 Ω, JEAR, EV7 = 0 dB,
THD = 10%, 1020 Hz
5.0
—
—
mW
STR
TBO = –40 dBV, 1020 Hz,
SW6b = SW7b = SW8b = SW9b = on,
SW15 = AMP4, EV6, 7, 8 = 0 dB
C message, RAUD, EAR-XEAR,
Measured at JEAR
40
—
—
dB
STJ
SGO = –40 dBV, 1020 Hz, SW7b = on,
SW15 = AMP5, C message, Measured
at JEAR
40
—
—
dB
Output power
Signal to noise ratio
Note: Measurement conditions: ■ Standard Test Circuit
26
Value
dB
MB86437
(3) TONE
Parameter
Symbol
TONE output level
Conditions
Value
Unit
Min.
Typ.
Max.
GT1
Generating 1 tone, f1 = 948.1 kHz, sine wave
SW2 = off, SW9b = off, SW9c = on, MDI = OPEN
–12.0
EV3 = 15 dB, EV4 = –15 dB, EV9 = 0 dB,
Measured at TONE
–14.0
–16.0
dBV
GT2
Generating 2 tones, f1 = 948.1 kHz,
f2 = 1219.1 kHz, simultaneous sine wave
generation
–12.0
SW2 = off, SW9b = off, SW9c = on, MDI = OPEN
EV3 = 15 dB, EV4 = –15 dB, EV9 = 0 dB,
Measured at TONE
–14.0
–16.0
dBV
GT3
MDI = 1020 Hz, –10 dBV input
SW2 = on, SW13 = off, DUAL TONE = off
EV2 = 0 dB, EV3 = 15 dB, EV4 = –15 dB,
EV5 = –14 dB, Measured at PTBO
–27.0
–29.0
–31.0
dB
HTT
EV3 = 15 dB, EV4 = –15 dB, EV9 = 0 dB,
SW9c = on
SW2 = SW9b = off, MDI = OPEN, Generating a
single tone, Measured at TONE, nth harmonic
level (n = 2 to 5)
—
—
–38
dB
HTP
EV3 = 15 dB, EV4 = –15 dB, EV5 = –15 dB, EV2
= 15 dB
SW2 = on, SW9c = SW13 = off, MDI = OPEN,
Generating a single tone, Measured at PTBO,
nth harmonic level (n = 2 to 5)
—
—
–38
dB
Harmonic level
(4) Reception and transmission (CODEC, Analog section)
Parameter
Symbol
Conditions
Value
Min.
Typ.
Max.
Unit
Crosstalk
(Transmission →
reception)
CTX
Ain1 = 1020 Hz, –8.5 dBV (0 dBgain)
DIN = "H"
Measurement: RAUD 1020 Hz
—
—
–50
dB
Crosstalk
(Reception →
transmission)
CTR
DIN = 1020 Hz, 0 dBm 0
AIN = SGC
Measurement: DOUT 1020 Hz
—
—
–50
dB
PSRR
0 < f < 50 kHz, VDD + 30 mVOP
C message
AIN = SGC, DIN = ICN
—
22
—
dB
EV0, EV1, EV3, EV5
Gain error relative to reset value
Input = 1020 Hz, –20 dBV
–0.7
—
0.7
dB
EV2, EV4, EV6, EV7, EV8, EV9
Gain error relative to reset value
Input = 1020 Hz, –20 dBV
–1.0
—
1.0
dB
Power supply noise
rejection ratio
Electronic volume gain
error
GEV
(Continued)
27
MB86437
(Continued)
Parameter
Symbol
Gmsw2
Conditions
SW2 = SW3 = off, EV4 = –15 dB
EV2 = 0 dB, EV3 = 15 dB
MDI = 1020 Hz, –30 dBV Measured at PTBO
SW1, 3, 4, 5 = off, EV0 = 0 dB
Gmsw34 AIN1 or AIN2 = 1020 Hz, –30 dBV
Measured at BBO
Gmsw5
Mute level
Electronic volume
offset variation
(amount of change
for 1 step)
Electronic volume
offset variation
(amount of change
for 1 step)
SW1, 3, 4, 5 = off, EV0 = 0 dB
TAUD = 1020 Hz, –30 dBV, Measured at BBO
SW6b = SW7b = SW8b = SW9b = SW9c = off
EV6, 7, 8, 9 = 0 dB, TBO = 1020 Hz, –30 dBV
Gmsw69
MDI = 1020 Hz-30 dBV, EV4 = 0 dB
RAUD, EAR, XEAR, JEAR, Measured at TONE
Value
Unit
Min.
Typ.
Max.
—
—
–40
dB
—
—
–40
dB
—
—
–40
dB
—
—
–40
dB
Gmsw13
SW13 = SW2 = off, EV1, 2 = 0 dB,
DIN = 1020 Hz, 0 dBm0, Measured at PTBO
—
—
–40
dB
Gmsw15a
SW15 = AMP4, TBI-TBO = short
SGO = 1020 Hz, –30 dBV, Measured at JEAR
—
—
–40
dB
Gmsw15b
SW15 = AMP5, SGI-SGO = short
TBO = 1020 Hz, –30 dBV, Measured at JEAR
—
—
–40
dB
VEV0off
(EV0)
SW3 = on, SW4 = SW5 = off
MIC-MICO, SGC-XMIC = short
Measured between SGC and BBO when EV0
variable
–10
—
10
mV
VEV1off
(EV1)
SW2 = off, SW13 = on, EV2 = 0 dB
SYNC = 8 kHz, CLK = 2048 kHz, DIN = ICN
Measured between SGC and PTBO when EV1
variable
–25
—
25
mV
VEV2off
(EV2)
SW2 = off, SW13 = on, EV1 = 0 dB
SYNC = 8 kHz, CLK = 2048 kHz, DIN = ICN
Measured between SGC and PTBO when EV2
variable
–25
—
25
mV
VEV3off
(EV3)
Tone generation = off, SW9a, 9b = off,
SW9c = on, EV4 = –15 dB, EV9 = 0 dB,
MDI = open
Measured between SGC and TONE when EV3
variable
–70
—
70
mV
VEV4off
(EV4)
Tone generation = off, MDI = open,
EV3 = 15 dB, EV9 = 0 dB, SW9a = 9b = off,
SW9c = on
Measured between SGC and TONE when EV4
variable
–300
—
300
mV
VEV5off
(EV5)
Tone generation = off, MDI = open,
EV3 = 15 dB, EV2 = 0 dB
EV4 = –15 dB, SW2 = on, SW13 = off
Measured between SGC and PTBO when EV5
variable
–5
—
5
mV
(Continued)
28
MB86437
(Continued)
Parameter
Electronic volume
offset variation
(amount of change
for 1 step)
Change in DC offset
during mute
Symbol
Conditions
VEV6off
(EV6)
Value
Unit
Min.
Typ.
Max.
SW6b = on, SW6a = off
TBI-TBO = short
Measured between SGC and EAR when EV6
variable
–5
—
5
mV
VEV7off
(EV7)
SW7b = on, SW7a = off, SW15 = AMP4
TBI-TBO = short
Measured between SGC and JEAR when
EV7 variable
–5
—
5
mV
VEV8off
(EV8)
SW9b = on, SW9a, 9c = off
TBI-TBO = short
Measured between SGC and TONE when
EV8 variable
–50
—
50
mV
VEV9off
(EV9)
Tone generation = off, MDI = open,
EV3 = 15 dB
EV4 = –15 dB, SW9c = on, SW9a, 9b = off
Measured between SGC and TONE
–140
—
140
mV
SW13 = off, EV2 = 0 dB, EV3 = 15 dB,
VSW2off EV4 = –15 dB
(SW2) EV5 = –14 dB, Tone = off, MDI = open
Measured at PTBO for SW2 on and off
–30
—
30
mV
SW1, 4, 5 = off, EV0 = 0 dB
VSW3off
MIC-MICO = short
(SW3)
Measured at BBO for SW3 on and off
–20
—
20
mV
SW1, 3, 5 = off, EV0 = 0 dB
VSW4off
JMIC-JMICO = short
(SW4)
Measured at BBO for SW4 on and off
–20
—
20
mV
SW1, 3, 4, 10, 11 = off, EV0 = 0 dB
VSW5off
TAUD = SGC
(SW5)
Measured at BBO for SW5 on and off
–10
—
10
mV
SW7a, 8a, 9a = off, EV6 = –8 dB
VSW6off
TBI-TBO = short, EV7 = –3 dB
(SW6b)
Measured at EAR, XEAR for SW6b on and off
–10
—
10
mV
SW6a, 8a, 9a = off, SW15 = AMP4
VSW7off
EV7 = –3 dB, TBI-TBO = short
(SW7b)
Measured at JEAR for SW7b on and off
–10
—
10
mV
SW6a, 7a, 9a = off
VSW8off
TBI-TBO = short
(SW8b)
Measured at RAUD for SW8b on and off
–20
—
20
mV
SW6a, 7a, 8a, 9c = off, EV8 = 10 dB
VSW9boff
MDI = open, TBI-TBO = short
(SW9b)
Measured at TONE for SW9b on and off
–65
—
65
mV
SW6a, 7a, 8a, 9b = off, EV9 = 6 dB
VSW9off
MDI = open, TBI-TBO = short
(SW9c)
Measured at TONE for SW9c on and off
–300
—
300
mV
SW2 = off, EV1, 2 = 0 dB, DIN = ICN
VSWDoff
SYNC = 8 kHz, CLK = 2048 kHz
(SW13)
Measured at PTBO for SW13 on and off
–90
—
90
mV
29
MB86437
(5) Codec
Parameter
Symbol
Gain tracking
(A to D)
BTPO → DOUT
1020 Hz, –10 dBm0
Reference value
(µ-law)
GTX
Gain tracking
(D to A)
DIN → PTBO
1020 Hz, –10 dBm0
Reference value
(µ-law)
EV1 = EV2 = 0 dB
GTR
Gain tracking
(A to D) (Linear)
BTPO → DOUT
1020 Hz, AFST–13 dB
Reference value
GTXL
Gain tracking
(D to A) (Linear)
DIN → PTBO
0 dBm0
1020 Hz
Reference value
FRX
Typ.
Max.
+3 to –40 dBm0
–0.3
—
0.3
dB
–40 to –50 dBm0
–0.5
—
0.5
dB
–50 to –55 dBm0
–1.0
—
1.0
dB
+3 to –40 dBm0
–0.3
—
0.3
dB
–40 to –50 dBm0
–0.5
—
0.5
dB
–50 to –55 dBm0
–1.0
—
1.0
dB
AFST to AFST–43 dB
–0.3
—
0.3
dB
AFST–43 to AFST–53 dB
–0.5
—
0.5
dB
AFST–53 to AFST–58 dB
–1.0
—
1.0
dB
AFSR to AFSR–43 dB
–0.3
—
0.3
dB
–0.5
—
0.5
dB
AFSR–53 to AFSR–58 dB
–1.0
—
1.0
dB
0 to 60 Hz
24.0
—
—
dB
60 to 300 Hz –0.20
—
—
dB
300 to 3000 Hz –0.20
—
0.20
dB
3000 to 3400 Hz –0.20
—
0.8
dB
3400 to 4600 Hz
*
—
—
dB
32.0
—
—
dB
0 to 300 Hz –0.30
—
—
dB
300 to 3000 Hz –0.30
—
0.30
dB
3000 to 3400 Hz –0.30
—
1.10
dB
3400 to 4600 Hz
*
—
—
dB
32.0
—
—
dB
4600 to 12 kHz
Receiving frequency
characteristics
(D to A)
DIN → PTBO
0 dBm0
1020 Hz
Reference value
EV1 = EV2 = 0 dB
FRR
Unit
Min.
1020 Hz, AFSR–13 dB
AFSR–43 to AFSR–53 dB
Reference value
EV1 = EV2 = 0 dB
GTRL
Transmitting
frequency
characteristics
(A to D)
BTPO → DOUT
Value
Conditions
4600 to 12 kHz
Transmitting absolute
gain
GAX
(A to D)
BTPO → DOUT
1020 Hz, 0 dBm0 (Linear: AFST–3 dB)
VS = 3.0 V, Ta = +25°C
–1.0
0
1.0
dB
Receiving absolute
gain
(D to A)
DIN → PTBO
1020 Hz, 0 dBm0 (Linear: AFSR–3 dB)
EV1 = EV2 = 0 dB, VS = 3.0 V, Ta = +25°C
–1.20
0
1.20
dB
*: 14.5 × {1 – Sin
GAR
π (4000 – f)
1200
}
(Continued)
30
MB86437
(Continued)
Parameter
Symbol
Transmitting signal to
noise ratio
SDX
(A to D)
BTPO → DOUT
1020 Hz
C message
(µ-law)
Receiving signal to
noise ratio
(D to A)
DIN → PTBO
1020 Hz
C message
EV1 = EV2 = 0 dB
(µ-law)
SDR
Value
Conditions
Unit
Min.
Typ.
Max.
0 to –30 dBm0
34.0
—
—
dB
–40 dBm0
28.0
—
—
dB
–45 dBm0
23.0
—
—
dB
0 to –30 dBm0
34.0
—
—
dB
–40 dBm0
28.0
—
—
dB
–45 dBm0
23.0
—
—
dB
AFST–3 to AFST–33 dB
34.0
—
—
dB
AFST–43 dB
28.0
—
—
dB
AFST–48 dB
23.0
—
—
dB
AFSR–3 to AFSR–33 dB
34.0
—
—
dB
AFSR–43 dB
28.0
—
—
dB
AFSR–48 dB
23.0
—
—
dB
Transmitting signal to
noise ratio
(A to D)
SDXL
BTPO → DOUT
(Linear)
1020 Hz
C message
Recieving signal to
noise ratio
(D to A) SDRL
DIN → PTBO
(Linear)
SDRL
1020 Hz
C message
EV1 = EV2 = 0 dB
Transmitting no-talk
noise
BTPO → DOUT
ICNX
C message
—
–72
–69
dBm0C
Receiving no-talk
noise
DIN → PTBO
ICNR
C message
EV1 = EV2 = 0 dB
—
–75
–70
dBm0C
Analog input level
BTPO
AILU
1020 Hz, 0 dBm0, Ta = +25°C
VS = 3.0 V
µ-law
0.3290 0.3739 0.4195 Vrms
Analog output level
PTBO
AOLU
1020 Hz, 0 dBm0, Ta = +25°C
VS = 3.0 V
µ-law
EV1 = EV2 = 0 dB
0.3290 0.3739 0.4195 Vrms
Analog input fullscale
level
AFST
BTPO
VS = 3.0 V, Ta = +25°C Linear
0.6729 0.7647 0.8581
VOP
Analog output
fullscale level
PTBO
VS = 3.0 V, Ta = +25°C Linear
EV1 = EV2 = 0 dB
0.6729 0.7647 0.8581
VOP
AFSR
31
MB86437
■ TEST CIRCUIT
50 kΩ
50 kΩ
0.1 µF
BTPO
BTPI
BBO
STA
MICO
0.1 µF
VREF
SGC
–
MIC
+
SGI
XMIC
–
SGO
AMP5
SGC
+
A
Dout
DOUT
MICO
–
A/D
EV0
+
AMP2
8 kHz
2048 kHz
Din
SYNC
CLK
DIN
100 kΩ
←Ain1
10 kΩ
100 k
–
+
–
JMIC
+
AMP1
←Ain2
10 k
PLL
D/A
TAUD
SGC
EXSD
SGC
DSCK
SGC
EV1
SGC
SWI
1024 kHz
TCLK
SGC
MDI
TONE
+
EV4
EV3
EV5
+
–
SWO
SGC
+
RAUD
PTBO
TBI
50 kΩ
0.1 µ 50 kΩ
EV2
–
–
AMP4
EAR
0.1 µF
+
XEAR
+
TBO
32 Ω
0.1 µF
22 µF
–
+
32 Ω
JEAR
A
0.1 µF
DATA LATCH
P SAVE
–
TONE
10 µF
+
SRD SRC STB XPRST LO0 LO1 LO2 LO3
: Digital input
: Digital output
: Analog input
PS
: Analog output
: Input/output
Note: Insert a large bypass capacitor between VD and GND and between SGC and VS4.
32
600 Ω
: V DD
: GND
MB86437
■ ORDERING INFORMATION
Part number
MB86437PFV
Package
Remarks
48 pins, Plastic LQFP
(FPT-48P-M05)
33
MB86437
■ PACKAGE DIMENSION
48 pin Plastic LQFP
(FPT-48P-M05)
+0.20
1.50 −0.10
9.00±0.20(.354±.008)SQ
(MOUNTING HEIGHT)
+.008
.059 −.004
7.00±0.10(.276±.004)SQ
36
25
37
24
5.50
(.217)
REF
8.00
(.315)
NOM
INDEX
Details of "A" part
48
13
1
12
"A"
LEAD No.
0.50±0.08
(.0197±.0031)
+0.08
0.18 −0.03
+.003
.007 −.001
+0.05
0.127 −0.02
+.002
.005 −.001
0.10±0.10
(STAND OFF)
(.004±.004)
0.50±0.20
(.020±.008)
0.10(.004)
C
34
1995 FUJITSU LIMITED F48013S-2C-5
0
10˚
Dimensions in mm (inches)
MB86437
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9707
 FUJITSU LIMITED Printed in Japan
36