OKI MSM7584C

E2U0046-16-X2
¡ Semiconductor
MSM7584C
¡ Semiconductor
This version:MSM7584C
Jan. 1998
Previous version: Nov. 1996
p/4 Shift QPSK MODEM/ADPCM CODEC
GENERAL DESCRIPTION
The MSM7584C is a CMOS IC developed for use with digital cordless telephones. The device
provides a p/4 shift QPSK modem function and a CODEC function which performs transcoding
between the voice band analog signal and 32 kbps ADPCM data.
The MSM7584C is ideal for use in a handset of the PHS (Personal Handyphone System).
FEATURES
(p/4 Shift QPSK Modem)
• Built-in root Nyquist filter (a (rolloff rate) = 0.5) for the baseband limiter
• Differential I and Q analog outputs
• The DC offset and gain can be adjusted with respect to the differential I and Q analog outputs
• Completely digitized p/4 shift QPSK demodulator system
• Input IF signal frequency of 1.2 MHz or 10.8 MHz is available.
• Built-in A/D converter for RSSI detection
(ADPCM CODEC)
• ADPCM : ITU-T Recommendations G.721 (32 kbps)
• Transmit/receive full duplex capability
• PCM interface code format: selectable between m-law and A-law
• Built-in transmit/receive mute function and transmit/receive programmable gain setting
function
• Side tone path formation and level adjustment capabilities
• Built-in DTMF tone and other tones
• Built-in VOX function
• Built-in speech recording/playing interface
• Built-in 150 W driving OP AMP
• Built-in various analog switches
(Common)
• Single 3V power supply (VDD: 2.7 V to 3.6 V)
• Mode setting through serial interface
• Low power consumption
When the modem unit is operating :
When the ADPCM CODEC unit is operating :
When in the power down mode :
• Package:
80-pin plastic TQFP
(TQFP80-P-1212-0.50-K)
13 mA Typ. (VDD = 3.0 V)
7 mA Typ. (VDD = 3.0 V)
0.03 mA Typ. (VDD = 3.0 V)
(Product name : MSM7584CTS-K)
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¡ Semiconductor
MSM7584C
SL1
SL2
BLOCK DIAGRAM
IFIN
Phase detector
IFSEL
(From CR)
SL2
VDDM
DGM
AGM
S
E
L
DPLL
RPR
AFC/RCW
SLS
I+
+1
I–
–1
Q+
+1
LPF
–1
Root Nyquist
LPF
D/A
DC adjust
ATT
LPF
Q–
SL1
D
E
C
PDN0
PDN1
PDN2
RXD
RXC
RXSC
Judge
AFC
Delay detector
DC adjust
S/P
MAPPING
3.84M
To D/A
TXCSEL
(From CR)
D/A
ATT
S
E
L
Control
register
PLL
TXCI
384k
1/10
To MODEM
DIN
EXCK
DEN
DOUT
BSTO
TXD
TXW
8b
A/D
Conv.
To CODEC
TXCO
+
–
RSGAIN
RSSI
Offset adjust
SGRS
RESET
RO0 to RO1
2b
To internal SG
inside modem
SGM
SGCR
VREF
Receiver
Transmitter
R
SGCT
T
A/D
converter
ADPCM
CODER
ATT
TONE
generator
150 W driving AMP
RC
filter
D/A
converter
LPF
+
+
ATT
S
E
L
Expander
ADPCM
DECODER
From CR
VDD
SW3
SW4 SW5
IS
PCMSI
PCMSO
BCLK
SYNC
PCMRI
PCMRO
IR
VOXI
RXMUTE
MLV2
MLV1
MLV0
PDN3
VDDC
DGC
AGC
SW2
TOUT1
TOUT2
TOUT3
SW1
MCK
+1
IO7
+1
Power detect
IO4
VFRO
IO3
–1
IO1
IO2
AOUT+
P/S
&
S/P
ATT
–
+
Noise
generator
SAO
Compander
S
E
L
BPF
IO6
PWI
AOUT–
RC
filter
–
+
Voice
Detect
IO5
AIN–
AIN+
GSX
Serial
Register
Controller
DIO
WE
SAD
SAS
TAS
RWCK
CS1
CS2
VOXO
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¡ Semiconductor
MSM7584C
VDDM
Q–
Q+
I–
I+
RSGAIN
RSSI
SGRS
AGM
SGM
SGCR
AOUT+
AOUT–
PWI
VFRO
SAO
AGC
SGCT
AIN+
AIN–
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PIN CONFIGURATION (TOP VIEW)
PDN0
1
60
GSX
PDN1
2
59
IO1
PDN2
3
58
IO2
PDN3
4
57
IO3
SLS
5
56
IO4
AFC/RCW
6
55
VDDC
RPR
7
54
IO5
38
39
40
CS2
DIO
CS1
RWCK
41
DOUT
42
20
37
19
IR
DIN
PCMRI
36
TAS
DEN
43
35
18
EXCK
SAS
PCMRO
34
44
RESET
17
33
WE
DGM
MCK
45
32
16
DGC
SAD
IFIN
31
46
SYNC
15
30
RO1
TXCI
VOXO
47
29
14
VOXI
RO0
TXCO
28
48
MLV0
13
27
TOUT3
TXD
26
49
MLV1
12
MLV2
TOUT2
TXW
25
50
RXMUTE
11
24
TOUT1
BSTO
BCLK
51
23
10
PCMSI
IO7
RXSC
22
IO6
52
21
53
9
IS
8
PCMSO
RXC
RXD
80-Pin Plastic TQFP
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¡ Semiconductor
MSM7584C
PIN AND FUNCTIONAL DESCRIPTIONS
(ADPCM CODEC)
AIN+, AIN–, GSX
Transmit analog inputs and transmit level adjustment pin.
The AIN– input is connected to the inverting input of the internal transmit amplifier and AIN+
input is connected to the non-inverting input. The GSX pin is connected to the output pin of the
amplifier.
See Figure 1 for level adjustment.
VFRO, SAO
Receive analog output and sounder output.
VFRO is a receive filter output pin and SAO is a sounder output pin. These outputs can directly
drive the load of over 10 kW. When the system is in the power down mode, these outputs become
high impedance.
AOUT+, AOUT–, PWI
Input and outputs for internal operation amplifier.
See Figure 1 for connection. When the system is in the power down mode, these outputs become
high impedance. The AOUT– and AOUT+ outputs can directly drive the load of over 150 W.
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¡ Semiconductor
MSM7584C
AIN–
Vi
R1
C1
Differential analog input signal
C1
Transmit gain : (VGSX2/Vi)
= R2/R1
–
+
R2
to ENCODER
AIN+
R1
R2
Reference
voltage
generator
GSX
SGCT
SGCR
VFRO
+1
Receive side
output signal
Sounder output
signal gain
= R4/R3
SAO
from
DECODER
–1
SELECT
PWI
R3
R4
Sounder output signal
–
+
150 W driving amplifier
AOUT–
AOUT+
–1
Figure 1 Analog Interface
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¡ Semiconductor
MSM7584C
SGCT, SGCR
Outputs for CODEC analog signal ground.
The output voltage is approximately 1.4 V. Insert 10 mF and 0.1 mF bypass capacitors (ceramic
type) between these pins and the AG pin. When the device is in power down mode, the output
is 0 V.
SGCT is used for transmitting and SGCR is for receiving.
AGC
ADPCM CODEC analog ground (0 V).
DGC
ADPCM CODEC digital ground (0 V).
Since this pin is internally separated from AGC and AGM (modem ground pin), this pin must
be connected to these pins as close as possible on the circuit board.
VDDC
ADPCM CODEC 3 V power supply.
Connect this pin to the MODEM power Supply VDDM.
PDN3
ADPCM CODEC power down control input.
When this pin is set to "0" level, the device enters power down mode.
During normal operation mode, set this pin to "1" level.
The power down mode is controlled by CR0 - B5 of the control register ORed with the signal from
the PDN3 pin. Therefore, when using this pin, set CR0 - B5 to digital "0".
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¡ Semiconductor
MSM7584C
PCMSO
Transmit PCM data output.
This PCM output signal is output from MSB synchronously with the rising edge of BCLK and
XSYNC.
PCMSI
Transmit PCM data input.
This signal is converted to the ADPCM data. The PCM signal is shifted in on the falling edge of
BCLK. Normally, this pin is connected to PCMSO.
PCMRO
Receive PCM data output.
The PCM signal is the output signal after ADPCM decoder processing. This signal is serially
output from the MSB synchronously with the rising edge of BCLK and RSYNC.
PCMRI
Receive PCM data input.
The PCM input signal is shifted in on the rising edge of BCLK input from MSB. Normally, this
pin is connected to PCMRO.
IS
Transmit ADPCM signal output.
This signal is the output signal after ADPCM encoding, and is serially output from MSB
synchronously with the rising edge of BCLK and XSYNC. This pin is an open drain output which
requires a pull-up resistor and goes to a high impedence state during power-down mode.
IR
Receive ADPCM signal input.
Input data is shifted in serially from MSB on the rising edge of BCLK synchronously with
RSYNC.
BCLK
Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI) and the ADPCM data
(IS, IR) .
The frequency ranges from 64 kHz to 2048 kHz.
SYNC
8 kHz synchronous signal input for transmit/receive PCM and ADPCM data.
This signal should be synchronous with BCLK. SYNC is used for indicating MSB of the transmit
serial PCM and ADPCM data stream.
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¡ Semiconductor
MSM7584C
RXMUTE
Receive voice path mute control input. When this pin is at "0" level, the device enters normal
mode. When at "1" level, the voice level is muted to the value which has been set by MLV2, MLV1,
MLV0.
This pin is internally ORed like CR1-B3. Therefore, when using this pin, set CR1-B3 to digital "0".
MLV2, MLV1, MLV0
Receive voice path mute level setup signals. See the control register map for control method.
These signals are internally ORed with CR1-B2, B1, B0, respectively.
Therefore, when using this pin, set these register data to digital "0".
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¡ Semiconductor
MSM7584C
VOXO
Transmit VOX function signal output.
VOX function is used to recognize the presence or absence of the transmit voice signal by
detecting the signal energy. "1" and "0" levels on this pin correspond to the presence and the
absence, respectively. This result also appears at the register CR7 - B7. The signal energy detect
threshold is set by the control register data CR6 - B6, B5.
VOXI
Signal input for receive VOX function.
The "1" level on VOXI indicates the presence of voice signal, in which case the decoder block
processes normal receive signal and the voice signal appears at analog output pins. The "0" level
indicates the absence of voice signal, in which case the background noise generated in this device
is transferred to the analog output pins. The background noise amplitude is set by the control
register CR6. Because this signal is ORed with the register data CR6 - B3, the control register data
CR6 - B3 should be set to digital "0".
Input voice signal
GSX2 pin
VOXO pin
Voice
Silence
Voice
Silence detection time
(Hangover time) TVXOFF
Voice detection time
TVXON
(a) Transmission Side VOX Function Timing Diagram
VOXI pin
Voice
Silence
Regenerated voice signal
generation time
Internal background
noise generation time
Voice
Regenerated voice
VFRO pin
(b) Receive Side VOX Function Timing Diagram
Note: The VOXO and VOXI pin function are enabled when CR6 - B7 is set to "1".
Figure 2 VOX Function
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¡ Semiconductor
MSM7584C
(Voice Recording Serial Controller)
DIO
Input/output pin that outputs write data and to input read data.
Connect this pin to the DIN pin, DOUT pin of the serial registers and the DOUT pin of the serial
voice ROM. If neither a serial register nor a serial voice ROM is connected, pull this pin up with
an approx. 50 kW resistor.
WE
Output that selects the read mode or write mode.
Connect this pin to the WE pin of the serial registers.
SAD
Read/write start address output.
Connect this pin to the SAD pin of the serial registers and the SADX pin of the serial voice ROM.
SAS
Output of clocks for writing serial address.
Connect this pin to the SAS pin of the serial registers and the SASX and SASY pins of the serial
voice ROM.
TAS
Strobe signal output that sets the serial address which is entered from the SAD pin, to the address
counter inside the serial register/serial voice ROM.
Connect this pin to the TAS pins of the serial registers and serial voice ROM.
RWCK
Output of clocks for reading data from or writing data to the serial registers.
Connect this pin to the RWCK pin of the serial registers and the PDCK pin of the serial voice ROM.
CS1, CS2
Chip select pins.
Connect CS1 to the CS pin of the serial registers.
Connect CS2 to the CS pin of the serial voice ROM.
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¡ Semiconductor
MSM7584C
(Modem)
TXD
384 kbps transmit data input.
TXCI
Transmit clock input.
When the control register CR14 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should
be input to this pin. This clock pulse should be continuous because this device use APLL to
generate an internal clock pulse.
When CR14 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz
clock pulse is applied, a 384 kHz clock pulse, which is generated by dividing the TXCI by 10, is
output to the TXCO pin. The transmit data, synchronous to the 384 kHz clock pulse, should be
input to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse need
not be continuous. (Refer to Fig. 3)
TXCO
Transmit clock output.
When CR14 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring
purposes. When CR14 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing
the TXCI input by 10. (Refer to Fig. 3)
TXW
Transmit data window signal input.
The transmit timing signal for the burst data is input to this pin. If TXW is "1", the modulation
data is output. (Refer to Fig. 3)
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¡ Semiconductor
MSM7584C
(1) CR14 – B6 = "0"
TXD
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Dn-1 Dn
TXCI
(384kHz)
TXW
TXCO
(384kHz)
I, Q
,
Delay of 6.25 symbols
BSTO
(2) CR14 – B6 = "1"
TXD
TXCI
(3.84MHz)
TXW
TXCO
(384kHz)
I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Delay of 6.25 symbols
BSTO
Ramp rise-up
2 symbols
Ramp rise-up
2 symbols
Delay of 6.25 symbols
Ramp
Fall-down
2 symbols
Dn-1 Dn
Delay of 6.25 symbols
Ramp
Fall-down
2 symbols
Figure 3 Transmit Timing Diagram
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¡ Semiconductor
MSM7584C
BSTO
BSTO is the modulator side burst output position specification signal.
The burst time and position of the I and Q analog output including the lamp bits are output. (Refer
to Fig. 3)
I+, I–
Quadrature modulation signal I Component differential analog output.
Their output levels are 500 mVPP (maximum) with 1.6 Vdc as the center value. The output pin
load conditions are: R ≥ 10 kW, C ≤ 20 pF. The gain of these pins can be adjusted using the control
register CR15 - B7 to B4, and the offset voltage at the I– pin can be adjusted using CR16 - B7 to
B3.
Q+, Q–
Quadrature modulation signal Q component differential analog outputs.
Their output levels are 500 mVPP (maximum) with 1.6 Vdc as the center value. The output pin
load conditions are: R ≥ 10 kW, C ≤ 20 pF. The gain of these pins can be adjusted using the control
register CR15 - B7 to B4, and the offset voltage at the Q– pin can be adjusted by using CR17 - B7
to B3.
SGM
MODEM internal reference voltage output.
The output voltage value is approximately 2.0 V. Insert a bypass capacitor of approximately 0.1
mF between this pin and the AGM pin.
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¡ Semiconductor
MSM7584C
PDN0, PDN1, PDN2
Various power down controls.
PDN0 controls the standby mode/communication mode; PDN1 controls the modulator; PDN2
controls the demodulator. Refer to Table 1 for details.
Table 1 Description of Modem Power Down Control
PDN0 PDN2 PDN1
Standby
Mode
Operation State
Mode Name
0
0/1
0
Entire system is powered down. The control register is not reset.
Mode A
0
0/1
1
Modulator unit is powered off. (VREF and PLL also powered off.)
Mode B
1
0
0
Modulator unit is powered off. (VREF and PLL are powered on.)
Demodulator unit is powered on.
Communication
Mode
Mode C
I and Q outputs are in a high impedance state.
Only the demodulator clock regenerator unit is powered on.
1
0
1
Modulator unit is powered off. (VREF and PLL are powered on.)
Mode D
I and Q outputs are in a high impedance state.
Demodulator unit is powered on.
1
1
0
Modulator unit is powered on.
Mode E
Only the demodulator clock regenerator unit is powered on.
1
1
1
Modulator unit is powered on.
Mode F
Demodulator unit is powered on.
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¡ Semiconductor
MSM7584C
VDDM
+3 V power supply for the modem unit.
Connect this pin to the ADPCM CODEC power supply VDDC on the board.
AGM
Modem analog signal ground.
DGM
Modem digital signal ground.
Since this pin is internaly separated from AGM, AGC, and DGC, this pin must be connected to
theses pins on the board.
MCK
Master clock input. The clock frequency is 19.2 MHz.
The master clock must always be input to the ADPCM CODEC and MODEM except the device
being in power down mode because the both units share the master clock.
If the input level is less than 2 V, the master clock must be input after DC-component is cut by
an approx. 1000 pF capacitor. (See the application circuit example.)
IFIN
Modulated signal input for the demodulator unit.
The CR14 - B4 can select an IF frequency of 1.2 MHz or 10.8 MHz.
RXD, RXC, RXSC
Receive data, receive clock (384 kHz), receive symbol clock (192 kHz) outputs.
When the power is turned on, outputs in which a clock regeneration circuit selected by SLS
appear on these output pin.
RXD
RXC
RXSC
SLS
1 Symbol
The regenerated data and clock are
selected asynchronously by the SLS signal.
Figure 4 Timing Diagram of RXD, RXC, and RXSC
SLS
Receive side operation slot selection signal.
This device has two clock regeneration circuits and two AFC data memory registers. If SLS is at
"0" level, slot 1 is selected; if SLS is at "1" level, slot 2 is selected.
RPR
High-speed phase clock control signal input for the clock regeneration circuit.
If this pin is at "1" level, the clock regeneration circuit enters the high-speed phase clock mode.
When the phase difference is less than a defined value, the circuit shifts to the low-speed phase
clock mode automatically. If this pin is at "0" level, the circuit is always in the low-speed phase
clock mode.
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¡ Semiconductor
MSM7584C
AFC/RCW
AFC operation and clock regeneration range specification signal input.
As shown in Figure 5, AFC information is reset when AFC/RCW and RPR go to "1" level. The
AFC operation starts after a certain time elapses.
The average number of AFC operation times is small when RPR is at "1" level.
The average number of AFC operation times is large when RPR is at "0" level.
If AFC/RCW is at "0" level, DPLL will not adjust the phase.
(CASE1)
AFC/RCW
RPR
AFC information
is reset.
(CASE2)
Average number of AFC
operation times is large.
Averag number of
AFC operation
times is small.
AFC information
is maintained.
AFC/RCW
"0"
RPR
The clock generation circuit
starts with the previous
AFC information.
Average number of AFC
operation times is large.
AFC information
is maintained.
Figure 5 AFC Control Timing Diagram
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¡ Semiconductor
MSM7584C
(Common)
RESET
Device reset input.
The control registers CR0 to CR22 all are reset to the initial values by setting this pin to "0" level.
R0, R1
Output ports for the control register CR21.
The data written in CR21 - B0 and B1 are output on the R0 and R1 pins.
These pins become high impedance when the device is reset.
DEN, EXCK, DIN DOUT
, ,
Serial control ports for the microcontroller interface.
The device has 23 bytes of control registers. Data is written and read by the external CPU using
these ports. DEN is an enable signal input, EXCK is a data shift clock signal input, DIN is an
address/data input, and DOUT is a data output.
The input/output timing is shown in Fig. 6.
DEN
EXCK
DIN
W
A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
(a) Write Data Timing
DEN
EXCK
DIN
DOUT
R
A4 A3 A2 A1 A0
High Impedance
B7 B6 B5 B4 B3 B2 B1 B0
(b) Read Data Timing
Figure 6 MCU Interface I/O Timing
The control register map is shown in Table 2.
As shown in Fig. 6, data should be written or read in continuous pulses of the EXCK signal or in
16 bits.
IO1 to IO7
Input/output for internal analog switches.
See the control register map (CR22) and circuit configuration for connection information and
control method.
TOUT1, TOUT2, TOUT3
Sign bit outputs for the tone generator.
The outputs are controlled by the control register CR22. See the control register map and circuit
configuration for connection information and control method.
17/57
¡ Semiconductor
MSM7584C
Table 2 Control Register Map
Address
Register
name A4 A3 A2 A1 A0
Data Description
B7
B6
B5
B4
PDN
PDN
ALL
TX
TX ON/ RX ON/ ADPCM
TX
1
OFF
OFF
RST
MUTE
TX
TX
TX
TX
0 GAIN3 GAIN2 GAIN1 GAIN0
S_
S_
S_
T ON/
1 TONE2 TONE1 TONE0
OFF
DTMF/ TONE_
0
OT
SEND TONE5 TONE4
SEND/ ROM/ 4M8M/
1
—
REC
SR
1M
VOX
ON
ON
OFF
0 ON/OFF LVL1
LVL0
TIME
VOX
Silence Silence
1
—
OUT
L1
L0
B3
B2
B1
B0
PDN
RX
RX
MUTE
RX
GAIN3
Tone
G3
SA,VF_
OUT
SAO/
VFRO
SA,VF_
PDN
MLV2
MLV1
MLV0
RX
GAIN2
Tone
G2
RX
GAIN1
Tone
G1
RX
GAIN0
Tone
G0
TONE3
TONE2
TONE1
TONE0
—
—
CMD1
CMD0
VOX
IN
RX_N
SEL
N_
LV1
N_
LV0
—
—
BUSY
RPM
CR0
0 0
0 0 0
CR1
0 0
0 0
CR2
0 0
0 1
CR3
0 0
0 1
CR4
0 0
1 0
CR5
0 0
1 0
CR6
0 0
1 1
CR7
0 0
1 1
CR8
0 1
0 0 0
ST0
ST1
ST2
ST3
ST4
ST5
ST6
ST7
CR9
0 1
0 0 1
ST8
ST9
ST10
ST11
ST12
—
—
—
CR10 0 1
0 1 0
SPY0
SPY1
SPY2
SPY3
SPY4
SPY5
SPY6
SPY7
CR11 0 1
0 1 1
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
CR12 0 1
1 0 0
SP8
SP9
SP10
SP11
SP12
—
—
—
CR13 0 1
1 0 1
CH0
CH1
CH2
CH3
CH4
—
ADRD
ADWT
CR14 0 1
1 1 0
—
—
—
—
—
1 1 1
MOD
OFF
Ich
GAIN1
Ich
Offset2
Qch
Offset2
MODEM
TEST1
IFSEL
CR15 0 1
TXC
SEL
Ich
GAIN2
Ich
Offset3
Qch
Offset3
MODEM
TEST2
Qch
GAIN2
Qch
GAIN1
Qch
GAIN0
—
—
—
—
—
—
Local
INV0
—
—
ADO2
ADO1
ADO0
SEL
RS
RO0
A/m
—
CR18 1 0
Ich
GAIN3
Ich
0 0 0 Offset4
Qch
0 0 1 Offset4
MODEM
0 1 0 TEST3
CR19 1 0
0 1 1
ADO7
ADO6
ADO5
ADO4
ADO3
CR20 1 0
AD
1 0 0 Offset4
AD
Offset3
AD
Offset2
AD
Offset1
AD
Offset0
—
RS
PDN
CR21 1 0
1 0 1
—
—
—
—
—
—
RO1
CR22 1 0
1 1 0
SW1
CONT
SW2
CONT
SW3
CONT
SW4/5
CONT
AOUT
PDN
TOUT3
CONT
TOUT2
CONT
CR16 1 0
CR17 1 0
Ich
Qch
GAIN0 GAIN3
Ich
Ich
Offset1 Offset0
Qch
Qch
Offset1 Offset0
MODEM Local
TEST0
INV1
Register
function
ADPCM
control
VOX play
mode
control
MODEM
control
RSSI A/D
control
General I/O
TOUT1 Switches
CONT
control
18/57
¡ Semiconductor
MSM7584C
(RSSI-ADC)
RSSI, RSGAIN
RSSI input and level adjustment.
RSSI is connected to the inverting input pin of the internal amplifier. RSGAIN is connected to
the output pin of the amplifier.
Adjust the gain and DC so that the signal amplitude is between 0.7 V and 2.1 V on the RSGAIN
pin. See Fig. 7 for connection.
Gain: A = R2/R1 = 1.4/ (Vmax - Vmin)
if R1 + R2 ≥ 20 kW
DC adjustment value : Vadj = A/(1+A) ¥ ((Vmax + Vmin) /2– 1.4)
Set the register CR20 to the DC adjustment value nearest to Vadj.
See the control register map (CR20) for setup values.
SGRS
Internal reference voltage output for the RSSI - ADC.
The output voltage is 2.0 V. Insert an approx. 0.1 mF bypass capacitor between this pin and the
AGM pin.
RSGAIN
R2
RSSI signal
RSSI
R1
–
+
ADC
Gain = R2/R1
Reference
voltage
generator
SGRS
DC
ADJUST
CR20:B7 to B3
Control
register
CR19:B7 to B0
Figure 7 RSSI-ADC Interface
19/57
¡ Semiconductor
MSM7584C
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Symbol
Condition
Rating
Unit
VDD
—
–0.3 to +5
V
Analog Input Voltage
VAIN
—
–0.3 to VDD + 0.3
V
Digital Input Voltage
VDIN
—
–0.3 to VDD + 0.3
V
Operating Temperature
Top
—
–25 to +70
°C
Storage Temperature
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Conditon
Power Supply Voltage
VDD
—
Operating Temperature Range
Ta
Parameter
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Min.
Typ.
2.7
–25
0.45 ¥
Max.
Unit
—
3.6
V
—
+70
°C
—
VDD
V
High Level Input Voltage
VIH
Input pins fully digital
Low Level Input Voltage
VIL
Input pins fully digital
0
—
Digital Input Rise Time
tIr
Input pins fully digital
—
—
50
ns
tIf
Input pins fully digital
—
—
50
ns
RDL
IS (Pull-up resistor)
500
—
—
W
CDL
Input pins fully digital
—
—
100
pF
Bypass Capacitor for SG
CSG1
Between SGCT/R and AGC
10 + 0.1
—
—
mF
Bypass Capacitor for SG
CSG2
0.1
—
—
mF
Master Clock Frequency
FMCK MCK
—
19.2
—
MHz
Master Clock Duty Ratio
DMCK MCK
40
50
60
%
Digital Input Fall Time
Modem Unit
Digital Output Load
Between SGM, AGM and SGRS,
AGM
Modulator Side Input
FTXC1
TXCI (When CR14 - B6 = "0")
Frequency
Clock Duty Ratio
FTXC2
TXCI (When CR14 - B6 = "1")
DCKM IFCK, TXCI, EXCK
IF Input Duty Ratio
DCIF
Transmit Sync Pulse
Setting Time
CODEC Unit
VDD
IFIN
tXSM, tSXM TXCI´TXW
tDSM, tDHM TXCI´TXD
Fig.10
BCLK
Bit Clock Frequency
FBCK
Synchronous Signal Frequency
FSYNC XSYNC, RSYNC
Clock Duty Ratio
DCKC BCLK, EXCKC
0.16 ¥
VDD
V
—
384
—
kHz
—
3.84
—
MHz
40
50
60
%
45
50
55
%
—
—
200
ns
—
—
200
ns
64
—
2048
kHz
—
8.0
—
kHz
40
50
60
%
Transmit Sync Pulse Setting Time tXSC, tSXC BCLK´XSYNC
100
—
—
ns
Receive Sync Pulse Setting Time tRSC, tSRC BCLK´RSYNC
tWSC XSYNC, RSYNC
Synchronous Signal Width
100
—
—
ns
PCM, ADPCM Setup Time
PCM, ADPCM Hold Time
1 BCLK
—
125ms-1BCLK
ms
tDSC
—
100
—
—
ns
tDHC
—
100
—
—
ns
Fig.8
20/57
¡ Semiconductor
MSM7584C
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
IDD1
Mode A (When VDD = 3.0 V)
—
0.03
0.1
mA
Power Supply Current (Modem)
IDD2
Mode B (When VDD = 3.0 V)
—
4.5
10.0
mA
(When CODEC is in a
IDD3
Mode C (When VDD = 3.0 V)
—
4.5
10.0
mA
Power Down State)
IDD4
Mode D (When VDD = 3.0 V)
—
10.5
22.0
mA
IDD5
Mode E (When VDD = 3.0 V)
—
8.5
18.0
mA
IDD6
Mode F (When VDD = 3.0 V)
—
13.0
27.0
mA
IDD7
When operating*
—
7.0
15.0
mA
IDD8
(When no signal, and VDD = 3.0 V)
—
11.0
18.0
mA
—
0.03
0.1
mA
—
2.0
4.0
mA
—
—
2.0
mA
Power Supply Current (CODEC)
(When Modem is in a Power
Down State)
Power Supply Current
(RSSI-ADC)
Input Leakage Current
High Level Output Voltage
Low Level Output Voltage
*
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
IDD9
IDD10
When powered down
(When VDD = 3.0 V)
CR22–B3 = "1"
(When VDD = 3.0 V)
IIH
VI = VDD
IIL
VI = 0 V
—
—
0.5
mA
VOH1 IOH = 0.4 mA
0.5 ¥ VDD
—
VDD
V
VOH2 IOH = 1 mA
0.8 ¥ VDD
—
VDD
V
0
0.2
0.4
V
—
—
10
mA
—
5
—
pF
VOL
Output Leakage Current
IO
Input Capacitance
CIN
IOL = –1.2 mA (IS pin is pulled
up with 500 W resistor)
IS pin
—
IDD7 applies when CRC0 - B0 = "0" and CR22 - B3 = "0"; IDD8 applies when operating in other
conditions.
21/57
¡ Semiconductor
MSM7584C
Analog Interface Characteristics (RSSI - ADC)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input Resistance
RINAD RSSI
10
—
—
MW
Output Resistance Load
RLCAD RSGAIN
10
—
—
kW
Output Capacitance Load
CLAD RSGAIN
—
—
—
pF
Input Voltage Range
VINAD When a RSGAIN signal is output.
Offset Voltage Adjust Range
OVLAD
Offset Voltage Adjust Accuracy
OVSAD
A/D Conversion Resolution
RESAD One LSB step
—
When offset voltage is
adjusted per LSB step.
0.7
—
2.1
V
–400
—
375
mV
–12.5
—
12.5
mV
—
5.5
—
mV
Digital Interface Characteristics (RSSI - ADC)
Parameter
Output Delay Time
Symbol
tDAD
Condition
Cload = 50 pF
(VDD
Referrence
Fig.12
= 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Min.
Typ.
Max.
Unit
—
5
—
ms
22/57
¡ Semiconductor
MSM7584C
Analog Interface Characteristics (Modem)
Parameter
Symbol
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Condition
Min.
Typ.
Max.
Unit
Output Resistance Load
RLIQ
I+, I–, Q+, Q–
10
—
—
kW
Output Capacitance Load
CLIQ
I+, I–, Q+, Q–
—
—
20
pF
Output DC Voltage Level
VDCM I+, I–, Q+, Q– (TXW = 0)
1.55
1.6
1.65
V
—
360
—
mVPP
I+, I–, Q+, Q–
Output AC Voltage Level
VACM
Output DC Voltage Adjustment Level Range
DCVL
—
—
±45
—
mV
Output AC Voltage Adjustment Level Range
ACVL
—
—
±4
—
%
P600 600 kHz detuning
—
—
60
dB
P900 900 kHz detuning
—
—
65
dB
EVM
—
1.0
3.0
Out-of-band Spectrum
Modulation Accuracy
(For TXD = 0 continuous input)
—
%
rms
Demodulator Side IF Input Level
IFV
IFIN input level
0.5
—
VDD
VPP
IFIN Input Impedance
RIF
DC impedance
—
20
—
kW
SGM Output Voltage
VSGM
—
—
2.0
—
V
SGM Output Impedance
RSGM
—
—
1.5
—
kW
MCK Input Level
IX
—
0.7
—
2.0
VPP
MCK Input Impedance
RX
—
20
—
kW
DC impedance
Digital Interface Characteristics (Modem)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Symbol
Condition
Reference
Transmit Digital I/O Setting Time
tXDM1,2
Cload = 50 pF
tXDM3,4
Fig. 10
Receive Digital I/O Setting Time
tRDM1,2 Cload = 50 pF
Fig. 11
Min.
Typ.
Max.
Unit
0
—
200
ns
0
—
400
ns
0
—
200
ns
23/57
¡ Semiconductor
MSM7584C
Analog Interface Characteristics (CODEC)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Input Resistance
Output Resistance Load
Output Capacitance Load
Output Voltage Level (*1)
Symbol
SGCT, SGCR Output Voltage
Min.
Typ.
Max.
Unit
10
—
—
MW
AIN+, AIN–, PWI
RLC1
GSX
20
—
—
kW
RLC2
VFRO, SAO
10
—
—
kW
RLC3
AOUT
150
—
—
W
CLC1
GSX
—
—
100
pF
CLC2
VFRO, SAO
—
—
100
pF
CLC3
AOUT
—
—
100
pF
VOC1
GSX (RL = 20 kW)
—
—
1.3
VPP
—
—
1.3
VPP
VOC2
VOC3
Offset Voltage
Condition
RINC
VFRO, SAO
(RL = 10 kW)
AOUT (RL = 150 W)
—
—
1.3
VPP
VOFC1 VFRO, SAO
–100
—
100
mV
VOFC2 GSX, AOUT
–20
—
20
mV
VSGC
—
1.4
—
V
SGCT, SGCR
SGCT Output Impedance
RSGCT SGCT
—
40
80
kW
SGCR Output Impedance
RSGCR SGCR
—
4
8
kW
Analog Switch OFF Resistance
RSWof SW1 to SW5
50
—
—
MW
Analog Switch ON Resistance
RSWon SW1 to SW5
50
100
200
W
*1 –7.7 dBm (600 W) = 0 dBm0, +3.14 dBm0 = 1.30 VPP
24/57
¡ Semiconductor
MSM7584C
Digital Interface Characteristics (CODEC)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Min.
Typ.
Max.
Unit
0
—
200 (100)
ns
0
—
200 (100)
ns
0
—
200 (100)
ns
0
—
200 (100)
ns
tC1
50
—
—
ns
tC2
50
—
—
ns
tC3
50
—
—
ns
tC4
50
—
—
ns
tC5
100
—
—
ns
tC6
50
—
—
ns
Symbol
Digital Output Delay Time
tSDXC, tSDRC
tXDC1, tRDC1
PCM, ADPCM Interface
tXDC2, tRDC2
tXDC3, tRDC3
Serial Port Digital I/O
Timing Characteristics
tC7
Condition
Reference
Cload = 50 pF
pull-up resistor: 500 W
Fig. 8
Items in parenthesis
mean Cload = 10 pF, and
the pull-up resistor £ 2 kW
Cload = 50 pF
Fig. 9
50
—
—
ns
tC8
0
—
100
ns
tC9
50
—
—
ns
tC10
50
—
—
ns
tC11
0
—
50
ns
tC12
EXCK Clock Frequency
Fexck
EXCK
—
200
—
—
ns
—
—
10
MHz
25/57
¡ Semiconductor
MSM7584C
Serial Interface Characteristics
Parameter
Control Register Data Input
BUSY Bit
RPM Bit
(VDD
Referrence
= 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Min.
Typ.
Max.
Unit
tCRW Write
—
—
200
ns
tCRR
Reset
—
—
200
ns
tBSR
Rising
—
—
10
ms
tBSH
Active time
—
—
450
ms
Condition
Symbol
Fig.15
tRPR
Rising
—
—
10
ms
tRPF
Falling at Stop command
—
—
135
ms
26/57
¡ Semiconductor
MSM7584C
AC Characteristics (CODEC)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Symbol
Condition
Frequency (Hz)
Level dBm0
Min.
Typ.
Max.
Unit
LOSS T1
0 to 60
25
—
—
dB
LOSS T2
300 to 3 k
–0.15
—
0.20
dB
Transmit Frequency
LOSS T3
1020
Response
LOSS T4
3300
Receive Frequency
Response
Transmit Signal to
Distortion Ratio (*1)
Receive Signal to
Distortion Ratio (*1)
Transmit Gain
Tracking
Receive Gain
Tracking
0
Reference
–0.15
dB
—
0.80
dB
LOSS T5
3400
0
—
0.80
dB
LOSS T6
3968.75
13
—
—
dB
LOSS R1
0 to 3000
–0.15
—
0.20
dB
LOSS R2
1020
LOSS R3
3300
–0.15
—
0.80
dB
LOSS R4
3400
0
—
0.80
dB
LOSS R5
3968.75
13
—
—
dB
Reference
0
dB
SD T1
3
35
—
—
dB
SD T2
0
35
—
—
dB
1020
–30
35
—
—
dB
SD T4
–40
28
—
—
dB
SD T5
–45
23
—
—
dB
SD R1
3
35
—
—
dB
SD T3
0
35
—
—
dB
–30
35
—
—
dB
SD R4
–40
28
—
—
dB
SD R5
–45
23
—
—
dB
GT T1
3
–0.2
—
0.2
dB
SD R2
SD R3
1020
–10
GT T2
dB
Reference
–40
–0.2
—
0.2
dB
GT T4
–50
–0.5
—
0.5
dB
GT T5
–55
–1.2
—
1.2
dB
GT R1
3
–0.2
—
0.2
dB
GT R2
–10
GT T3
1020
–40
–0.2
—
0.2
dB
GT R4
–50
–0.5
—
0.5
dB
GT R5
–55
–1.2
—
1.2
dB
GT R3
1020
dB
Reference
*1 P-message filter used
27/57
¡ Semiconductor
MSM7584C
AC Characteristics (CODEC) (Continued)
Parameter
Idle Channel Noise
(*1)
Symbol
NIDLT
NIDLR
Absolute Level (*3)
AVT
AVR
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Condition
Frequency (Hz)
Level dBm0
Other
—
AIN = SG
—
(*2)
—
1020
0
Power Supply Noise
PSRRT Noise frequency:
Rejection Ratio
PSRRR
Noise level:
0 kHz to 50 kHz
50 mVPP
Min.
Typ.
—
—
Max.
Unit
–68
(–75.7)
dBm0p
–72
(dBmp)
—
—
—
GSX2
0.285
0.320
0.359
Vrms
VFRO
0.285
0.320
0.359
Vrms
30
—
—
dB
30
—
—
dB
—
(–79.7)
*1 P-message filter used
*2 PCMRI input: "11010101" (A-law), "11111111" (m-law)
*3 0.320 Vrms = 0 dBm0 = –7.7 dBm (600 W)
ADPCM characteristics are fully compliant with ITU-T Recommendation G.721.
AC Characteristics (DTMF and Other Tones)
Parameter
Frequency Deviation
Tone Reference
Output Level
(*1)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Condition
Symbol
Min.
Typ.
Max.
Unit
DFT1
DTMF tones
–7
—
7
Hz
DFT2
Other various tones
–7
—
7
Hz
DTMF (low group)
–18
–16
–14
dBm0
DTMF (high group), other
–16
–14
–12
dBm0
DTMF (low group)
–4
–2
0
dBm0
DTMF (high group), other
–2
0
2
dBm0
1
2
3
dB
VTL
VTH
VRL
VRH
DTMF Tone Level Relative Value RDTMF
Transmit side tone
Receive side tone
VTH/VTL, VRH/VRL
*1 Not including programmable gain set values
AC Characteristics (Gain Settings)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Transmit/Receive Gain
Setting Accuracy
Condition
Symbol
DG
For all gain set values
Min.
Typ.
Max.
Unit
–1
0
1
dB
AC Characteristics (VOX Function)
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Parameter
Transmit VOX
Detection Time
(Voice and Silence
Detection Time)
TVXON
SilenceÆvoice VOXO pin: See Fig. 2
TVXOF
VoiceÆsilence
Transmit VOX
Detection Level Accuracy
(Voice Detection Level)
Condition
Symbol
DVX
Voice/silence
differential: 10 dB
For detection level set values by
CR6 - B6, B5
Min.
Typ.
Max.
Unit
—
5
—
ms
140/300 160/320 180/340
–2.5
0
2.5
ms
dB
28/57
¡ Semiconductor
MSM7584C
TIMING DIAGRAM
(ADPCM CODEC)
Transmit Side PCM, ADPCM Timing
0
BCLK
1
tSXC
tXSC
SYNC
2
tWSC
tXDC1
3
4
5
6
7
8
tXDC2
10
tXDC3
LSB
MSB
PCMSO
9
tSDXC
BCLK
0
1
tSXC
tXSC
SYNC
2
tXDC1
IS
3
4
tXDC2
5
6
7
8
9
10
5
6
7
8
9
10
5
6
7
8
9
10
tXDC3
LSB
MSB
tSDXC
Receive Side PCM, ADPCM Timing
BCLK
0
tRSC
1
tSRC
2
3
tWSC
4
SYNC
tDHC
tDSC
IR
MSB
BCLK
0
tRSC
LSB
1
tSRC
2
3
4
SYNC
tRDC2
tRDC1
tRDC3
LSB
MSB
PCMRO
tSDXC
Figure 8 PCM, ADPCM Interface
Serial Port Timing for Microcontroller Interface
DEN
1
EXCK
tC1
DIN
tC3
2
3
4
A4
5
6
7
14
13
15
A3
A2
16
tC9
tC7
tC6
tC4
W/R
tC10
tC5
tC2
A1
A0
B7
B1
B0
tC8
DOUT
B7
B1
B0
Figure 9 Serial Control Port Interface
29/57
, ,
¡ Semiconductor
MSM7584C
TIMING DIAGRAM
(Modem)
Transmit Data Input Timing
TXCI [TXCO*]
(384 kHz)
TXW
TXD
1
2
3
N-2
N-1
N
tXSM
N+1
tXSM
tDSM tDHM
1
2
3
N-2
N-1
N
*TXCO in brackets [ ] is when CR14 - B6 = 1
Transmit Clock (TXCO) Output Timing (When CR14 - B6 = 1)
TXCI
(3.84 MHz)
TXCO
(384 kHz)
1
2
3
4
5
tXDM1
6
7
8
9
tXDM2
10
tXDM1
Transmit Burst Position (BSTO) Output Timing (When CR14 - B6 = 0)
TXCI
(384 kHz)
1
2
8
9
N
N+1
N+17
N+18
N+19
TXW
tXDM3
tXDM4
BSTO
Figure 10 Modem Transmit Side (Modulator Side) Digital I/O Timing
Receive Side Data I/O Timing
SLS
tRMS1
tRMS2
tRMS3
tRMS4
RCW
AFC
tRWM
RPR
RXC
tRDM1
tRDM2
RXD
Figure 11 Receive Side (Demodulator Side) Digital I/O Timing
30/57
¡ Semiconductor
MSM7584C
TIMING DIAGRAM
(RSSI - ADC)
RSSI - ADC Output Timing
RSSI input
(RSSIGAIN Pin)
DEN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EXCK
1
DIN
0
0
1
1
R address = 10011
MSB
DOUT
Internal AD
conversion output
latch signal
Notes:
1
LSB
AD conversion output data (8 bit)
AD conversion output
delay time
tDAD
1. AD conversion output data corresponds to the RSSI analog input value between the
rising edge of the 6th EXCK clock pulse and the start point of the AD conversion
output delay time (tDAD).
2. Normal AD conversion output data is output approximately 1ms after the power
down mode is cancelled.
Figure 12 RSSI - ADC Output Timing
31/57
¡ Semiconductor
MSM7584C
TIMING DIAGRAM
(Serial Register Interface)
Address Write/Read Timing
DEN
EXCK
DIN
(CR13)
X
X
(ADWT, ADRD)
(X, X)
CR13 – (B1, B0)
(0, 0)
tCRR
tCRW
BUSY
tBSR
Serial register
I/F
Address data transfer
tBSH
Recording/Playback Timing
DEN
EXCK
DIN
(CR5)
X
X
"1"
(PLAY/REC)
"1"
(STOP)
(X, X)
CR5 – (B1, B0)
(0, 0)
tCRR
tCRW
RPM
Serial register
I/F
tRPR
tRPF
Recording/playback data transfer
Figure 13 Serial Register Interface
32/57
¡ Semiconductor
MSM7584C
Mode State Transition Time in Modem
1 ms
Mode A
5 ms
Note: Values not indicated are
less than 1 ms.
Standby mode (PDN0 = 0)
Mode B
PDN2 = 0
PDN2 = 1
Communication mode (PDN0 = 1)
40 ms
Mode E
5 ms
Mode C
PDN1 = 1
PDN2 = 0
Mode D
PDN1 = 0
PDN2 = 0
5 ms
PDN1 = 0
PDN2 = 1
40 ms
Mode F
PDN1 = 1
PDN2 = 1
Figure 14 Transition Between Power-Down Mode and Power-ON Mode
33/57
¡ Semiconductor
MSM7584C
Timing Diagram for Demodulator Control in Modem (Example)
Demodulator unit
Modulator input data
PDN2
1st slot
R1
G
G
2nd slot
R2
3rd slot
R3
G
4th slot
R4
G
G
"0"
SLS
AFC/RCW
RXD
RXC
(1) Control ch/
synchronous burst
(SS + PR =64 bits)
240 bits
625ms
64 bits
RXD
G
G
G
G
G
G
G
G
R
R
R
R SS SS PR PR
PR UW
CR CR G
G
G
G
G
G
G
G
CR CR G
G
G
G
G
G
G
G
AFC/RCW
RPR
56 bits
(2) When synchronization is not yet established
AFC/RCW
RPR
In the case of a personal station, drive RPR
high in the initial state and wait for a control
signal to come from the central station.
Then, after a UW is detected, drive RPR low.
(3) Communication ch
(SS + PR = 8 bits)
RXD
G
8 bits
G
G
G
G
G
G
G
R
R
R
R SS SS PR PR
PR UW
AFC/RCW
RPR
"0"
When the strength of the received wave is large
Less than 30 bits
When the strength of the received wave is small
G : Guard bit
R : Ramp bit
SS : Start symbol bit
RR : Preamble bit
UM : Unique word bit
CR : CRC bit
Figure 15 Modem Unit Demodulator Timing Diagram Example
34/57
¡ Semiconductor
MSM7584C
FUNCTIONAL DESCRIPTION
Control Register Description Table
(ADPCM CODEC)
(1) CR0 (Basic Operation Mode Settings)
B7
A/m
CR0
SEL
Initial Value (*)
*
0
B6
—
0
B5
B4
B3
B2
PDN
PDN
PDN
SA, VF
ALL
TX
RX
_ OUT
0
0
0
0
B1
SAO/VFRO
0
B0
SA, VF
_ PDN
0
The initial value means a value which is set when the device is reset using the RESET signal.
B7: .............. PCM interface companding selection
0: m-law
1: A-law
B6: .............. Not used
B5: .............. Power down (entire unit) 0: Power ON 1: Power down
ORed with the inverting external power down signal PDN3. When using
this data, set PDN3 to "1".
B4: .............. Power down (transmit side only) 0: Power ON 1: Power down
B3: .............. Power down (receive side only)
0: Power ON 1: Power down
B2: .............. Output from VFRO and SAO at a time
0: Receive side output signals are output from a pin selected by B1.
1: Receive side output signals are output from VFRO and SAO at a time.
B1: .............. Receive side output switch control
0: Receive side output signals appear on the SAO (Sounder Amplifier
Output) pin.
1: These signals appear on the VFRO (Receiver Amplifier Output) pin.
B0: .............. Power down control for sounder output amplifier (SAO) and receiver
output amplifier (VFRO).
0: When SAO is selected by CR0 - B1, VFRO is powered down.
When VFRO is selected, SAO is powered down.
1: Both SAO and VFRO are powered ON.
35/57
¡ Semiconductor
MSM7584C
(2) CR1 (ADPCM Operation Mode Settings)
B7
CR1
Initial Value
B6
B5
B4
B3
TX
RX
ADPCM
TX
RX
ON/OFF
ON/OFF
RESET
MUTE
MUTE
0
0
0
0
0
B2
B1
B0
MLV2
MLV1
MLV0
0
0
0
B7: .............. Transmit side PCM signal ON/OFF.
0: ON
1: OFF
OFF: PCM idle pattern is transmitted.
B6: .............. Receive side PCM signal ON/OFF.
0: ON
1: OFF
OFF: PCM idle pattern is transmitted.
B5: .............. ADPCM reset (as specified by G. 721)
1: reset
B4: .............. Transmit side MUTE.
0: Transmit MUTE OFF.
1: Transmit MUTE ON.
Transmit output is in an idle state.
B3: .............. Receive side MUTE.
This bit is ORed with the external control pin
RXMUTE.
0: Receive side MUTE OFF.
1: Receive side MUTE ON. The receive side output signals are attenuated
by the values represented by a combination of bits B2, B1, and B0 of the
CR1. (For voice path only.)
B2, B1, B0: An attenuation value is selected at receive side MUTE (CR1 - B3 = "1")
(see Table 3). These bits are ORed with the external pins MLV2, MLV1, and
MLV0.
Table 3 MUTE Level Settings
B2
B1
B0
Attenuation value
0
0
0
0dB loss
0
0
1
– 6dB loss
0
1
0
–12dB loss
0
1
1
–18dB loss
1
0
0
–24dB loss
1
0
1
–30dB loss
1
1
0
–36dB loss
1
1
1
MUTE (idle state)
36/57
¡ Semiconductor
MSM7584C
(3) CR2 (PCMCODEC Operation Mode Settings and Transmit/Receive Gain Adjustment)
B7
CR2
Initial Value
B6
B5
B4
B3
B2
B1
B0
TX
TX
TX
TX
RX
RX
RX
RX
GAIN3
GAIN2
GAIN1
GAIN0
GAIN3
GAIN2
GAIN1
GAIN0
0
0
0
0
0
0
0
0
B7, B6, B5, B4: ....... Transmit side signal gain adjustment (see Table 4)
B3, B2, B1, B0: ....... Receive side signal gain adjustment (see Table 4)
Table 4 Receive/Transmit Gain Settings
Transmit/
receive gain
B7
B6
B5
B4
B3
B2
B1
B0
–16dB
1
0
0
0
1
0
0
0
–14dB
1
0
0
1
1
0
0
1
–12dB
1
0
1
0
1
0
1
0
–10dB
1
0
1
1
1
0
1
1
– 8dB
1
1
0
0
1
1
0
0
– 6dB
1
1
0
1
1
1
0
1
– 4dB
1
1
1
0
1
1
1
0
– 2dB
1
1
1
1
1
1
1
1
0dB
0
0
0
0
0
0
0
0
2dB
0
0
0
1
0
0
0
1
4dB
0
0
1
0
0
0
1
0
6dB
0
0
1
1
0
0
1
1
8dB
0
1
0
0
0
1
0
0
10dB
0
1
0
1
0
1
0
1
12dB
0
1
1
0
0
1
1
0
14dB
0
1
1
1
0
1
1
1
The above gain settings table shows the transmit/receive voice signal gain settings and the
transmit side gain settings for DTMF tones and other tones. Tone signal transmission is enabled
by CR4 - B6 (discussed later), and the gain setting is set to the levels shown below.
DTMF tones (low group): ................................. –16 dBm0
DTMF tones (high group) and other tones: ... –14 dBm0
For example, if the transmit gain set value is set to +8 dB (B7, B6, B5, B4) = (0, 1, 0, 0), then the
following tones appear at the PCMSO pin.
DTMF tones (low group): ................................. –8 dBm0
DTMF tones (high group) and other tones: ... –6 dBm0
–3 dBm0 (mixed tone)
However, the gain of the receive side tone and the gain of the side tones (path from transmit side
to receive side) are set by the CR3 register.
37/57
¡ Semiconductor
MSM7584C
(4) CR3 (Side Tone and Tone Generator Gain Adjustment)
B7
B6
B5
Side Tone Side Tone Side Tone
CR3
Initial Value
B4
B3
B2
B1
B0
TONE
TONE
TONE
TONE
TONE
GAIN2
GAIN1
GAIN0
ON/OFF
GAIN3
GAIN2
GAIN1
GAIN0
0
0
0
0
0
0
0
0
B7, B6, B5: ........ Side tone gain adjustment (refer to Table 5)
B4: ..................... Tone generator ON/OFF 0: OFF 1: ON
B3, B2, B1, B0: . Tone generator
Receive side gain adjustment (refer to Table 6)
Table 5 Side Tone Gain Settings
B7
B6
B5
Side Tone Gain
0
0
0
OFF
0
0
1
–15 dB
0
1
0
–13 dB
0
1
1
–11 dB
1
0
0
–9 dB
1
0
1
–7 dB
1
1
0
–5 dB
1
1
1
–3 dB
Table 6 Receive Side Tone Generator Gain Settings
B3
B2
B1
B0
Tone Generator Gain
B3
B2
B1
B0
Tone Generator Gain
0
0
0
0
–32 dB
1
0
0
0
–16 dB
0
0
0
1
–30 dB
1
0
0
1
–14 dB
0
0
1
0
–28 dB
1
0
1
0
–12 dB
0
0
1
1
–26 dB
1
0
1
1
–10 dB
0
1
0
0
–24 dB
1
1
0
0
–8 dB
0
1
0
1
–22 dB
1
1
0
1
–6 dB
0
1
1
0
–20 dB
1
1
1
0
–4 dB
0
1
1
1
–18 dB
1
1
1
1
–2 dB
The receive side tone generator gain settings shown in Table 6 are set with the following levels
as a reference.
DTMF tones (low group): ................................. –2 dBm0
DTMF tones (high group) and other tones: ... 0 dBm0
For example, if the tone generator gain set value is set to –6 dB (B3, B2, B1, B0)=(1, 1, 0, 1), then
tones at the following levels appear at the SAO+/SAO– or VFRO pin.
DTMF tones (low group): ................................. –8 dBm0
DTMF tones (high group) and other tones: ... –6 dBm0
–3 dBm0 (mixed tone)
38/57
¡ Semiconductor
MSM7584C
(5) CR4 (Tone Generator Operation Mode and Frequency Settings)
B7
CR4
B6
DTMF/
TONE
OTHERS SEL
SEND
0
0
Initial Value
B5
B4
B3
B2
B1
B0
TONE5
TONE4
TONE3
TONE2
TONE1
TONE0
0
0
0
0
0
0
B7: ........................... Selection of DTMF signal and other tones
(S tone, F tone, R tone, etc.) 0: Other tones 1: DTMF signal
B6: ........................... Transmission side tone transmit
0: Voice signal transmit 1: Tone transmit
B5, B4, B3, B2, B1, B0: Tone frequency setting (refer to Table 7)
Table 7 Tone Generator Frequency Settings
(a) When B7 = 1 (DTMF Tones)
B5
B4
B3
B2
B1
B0
Description
B5
B4
B3
B2
B1
B0
Description
*
*
0
0
0
0
697 Hz + 1209 Hz
*
*
0
0
0
0
852 Hz + 1209 Hz
*
*
0
0
0
1
697 Hz + 1336 Hz
*
*
0
0
0
1
852 Hz + 1336 Hz
*
*
0
0
1
0
697 Hz + 1477 Hz
*
*
0
0
1
0
852 Hz + 1477 Hz
*
*
0
0
1
1
697 Hz + 1633 Hz
*
*
0
0
1
1
852 Hz + 1633 Hz
*
*
0
1
0
0
770 Hz + 1209 Hz
*
*
0
1
0
0
941 Hz + 1209 Hz
*
*
0
1
0
1
770 Hz + 1336 Hz
*
*
0
1
0
1
941 Hz + 1336 Hz
*
*
0
1
1
0
770 Hz + 1477 Hz
*
*
0
1
1
0
941 Hz + 1477 Hz
*
*
0
1
1
1
770 Hz + 1633 Hz
*
*
0
1
1
1
941 Hz + 1633 Hz
39/57
¡ Semiconductor
MSM7584C
(b) When B7 = 0 (Other than DTMF Tones)
B5 B4 B3 B2 B1 B0
Description
0
0
0
0
0
0 400/500 Hz
0
0
0
0
0
1 800/1 Hz
0
0
0
0
1
0 400/500 Hz
0
0
0
0
1
1 400/1 Hz
0
0
0
1
0
0 667/800 Hz
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
B5 B4 B3 B2 B1 B0
Description
8 Hz Wamble
1
0
0
0
0
0 1100 Hz
Single tone
8 Hz Wamble
1
0
0
0
0
1 1142 Hz
Single tone
16 Hz Wamble
1
0
0
0
1
0 1200 Hz
Single tone
16 Hz Wamble
1
0
0
0
1
1 1210 Hz
Single tone
16 Hz Wamble
1
0
0
1
0
0 1250 Hz
Single tone
1 800/1 Hz
16 Hz Wamble
1
0
0
1
0
1 1300 Hz
Single tone
0 1 k/1.33 kHz
16 Hz Wamble
1
0
0
1
1
0 1333 Hz
Single tone
1
1 2.7 k/1 kHz
16 Hz Wamble
1
0
0
1
1
1 1360 Hz
Single tone
0
0 2 k/2.1 kHz
16 Hz Wamble
1
0
1
0
0
0 1410 Hz
Single tone
0
0
1 2 k/2.7 kHz
8 Hz Wamble
1
0
1
0
0
1 1455 Hz
Single tone
0
1
0 2.6 k/2.7 kHz 16 Hz Wamble
1
0
1
0
1
0 1477 Hz
Single tone
1
0
1
1 3.2 k/3.31 kHz 16 Hz Wamble
1
0
1
0
1
1 1500 Hz
Single tone
0
1
1
0
0 400 kHz
16 Hz Wamble
1
0
1
1
0
0 3310 Hz
Single tone
0
1
1
0
1 2 kHz
16 Hz Wamble
1
0
1
1
0
1 1600 Hz
Single tone
0
0
1
1
1
0 2.7 kHz
16 Hz Wamble
1
0
1
1
1
0 1635 Hz
Single tone
0
0
1
1
1
1 400 kHz
10 Hz Wamble
1
0
1
1
1
1 1710 Hz
Single tone
0
1
0
0
0
0 350 + 440 kHz
Mixed tone
1
1
0
0
0
0 1800 Hz
Single tone
0
1
0
0
0
1 400 + 480 kHz
Mixed tone
1
1
0
0
0
1 1900 Hz
Single tone
0
1
0
0
1
0 480 + 620 kHz
Mixed tone
1
1
0
0
1
0 2000 Hz
Single tone
0
1
0
0
1
1 350 kHz
Single tone
1
1
0
0
1
1 2100 Hz
Single tone
0
1
0
1
0
0 400 kHz
Single tone
1
1
0
1
0
0 2200 Hz
Single tone
0
1
0
1
0
1 440 kHz
Single tone
1
1
0
1
0
1 2285 Hz
Single tone
0
1
0
1
1
0 480 kHz
Single tone
1
1
0
1
1
0 2400 Hz
Single tone
0
1
0
1
1
1 500 kHz
Single tone
1
1
0
1
1
1 2500 Hz
Single tone
0
1
1
0
0
0 533 kHz
Single tone
1
1
1
0
0
0 2600 Hz
Single tone
0
1
1
0
0
1 571 kHz
Single tone
1
1
1
0
0
1 2670 Hz
Single tone
0
1
1
0
1
0 620 kHz
Single tone
1
1
1
0
1
0 2700 Hz
Single tone
0
1
1
0
1
1 667 kHz
Single tone
1
1
1
0
1
1 2820 Hz
Single tone
0
1
1
1
0
0 727 kHz
Single tone
1
1
1
1
0
0 2910 Hz
Single tone
0
1
1
1
0
1 800 kHz
Single tone
1
1
1
1
0
1 3000 Hz
Single tone
0
1
1
1
1
0 888 kHz
Single tone
1
1
1
1
1
0 3110 Hz
Single tone
0
1
1
1
1
1 1000 kHz
Single tone
1
1
1
1
1
1 3200 Hz
Single tone
40/57
¡ Semiconductor
MSM7584C
(6) CR5 (Control of Serial Register I/F)
CR5
Initial Value
B7
B6
B5
SEND/
ROM/
4M8M/
REC
SR
1M
0
0
0
B4
B3
B2
B1
B0
—
—
—
CMD1
CMD0
0
0
0
0
0
B7: .............. Register I/F connection.
0: Connection with ADPCM receiver
1: Connection with ADPCM transmitter
B6: .............. Switching between voice ROM and serial register.
0: Serial register
1: Voice ROM
B5: .............. Capacitance of serial register to be connected.
0: 1 Mbit (MSM6389)
1: 4 Mbit (MSM6684), 8 Mbit (MSM6685)
B1, B0: .......Serial register I/F command (CMD1, CMD0) =
(0. 0): NOP
(0. 1): PLAY
(1. 0): REC (RECORD)
(1. 1): STOP
Note:
CMD1 and CMD0 are reset to "0" after the instruction is executed.
The PLAY and REC instructions must not be executed when BUSY (CR5 - B1) and RPM
(CR5 - B0) are set to "1".
41/57
¡ Semiconductor
MSM7584C
(7) CR6 (VOX Function Control)
B7
CR6
Initial Value
B6
B5
B4
B3
B2
B1
B0
VOX
ON
ON
OFF
VOX
ON/OFF
LVL1
LVL0
TIME
IN
LEVEL SEL
RX NOISE RX NOISE RX NOISE
LVL1
LVL0
0
0
0
0
0
0
0
0
B7: .............. VOX function ON/OFF
0: OFF
1: ON
B6, B5: .......Transmit side voice/silence detector level settings
(0,0): –20 dBm0
(0,1): –25 dBm0
(1,0): –30 dBm0
(1,1): –35 dBm0
B4: .............. Hangover time (refer to Fig. 2) settings 0: 160 ms
1: 320 ms
B3: .............. Receive side VOX input signal
0: Internal background noise transmit
1: Voice receive signal transmit
When using this data, set the VOXI pin to "0".
B2: .............. Receive side background noise level setting
0: Internal automatic setting
1: Externa setting (by B1, B0)
Internal automatic setting Æ Sets to the voice signal level when B3
(VOXI) changes from "1" to "0".
B1, B0: .......External setting background noise level
(0,0): No noise
(0,1): –45 dBm0
(1,0): –35 dBm0
(1,1): –25 dBm0
(8) CR7 (Detect Register: Read-only)
B7
VOX
CR7
Initial Value
B6
B5
Silent Level Silent Level
OUT
1
0
0
0
0
B4
B3
B2
B1
B0
—
—
—
BUSY
RPM
0
0
0
0
0
B7: ........................... Transmit side voice/silence detection
0: Silence 1: Voice
B6, B5: .................... Transmit side silence level (indicator)
(0,0):Below –60 dBm0
(0,1): –50 to –60 dBm0
(1,0): –40 to –50 dBm0
(1,1): Above –40 dBm0
Note:
These outputs are enabled when the VOX function is turned ON by CR6 - B7.
B4 - B2: ................... Not used
B1: ........................... Serial register I/F monitoring.
This bit monitors the Read and Write of addresses at the serial
register I/F.
0: Stop
1: Reading or Writing
B0: ........................... Monitors serial register recording and playback.
0: Stop
1: Recording or Playing back
42/57
¡ Semiconductor
MSM7584C
(9) CR8 (Start X-address 0 to 7)
CR8
Initial Value
B7
B6
B5
B4
B3
B2
B1
B0
ST0
ST1
ST2
ST3
ST4
ST5
ST6
ST7
0
0
0
0
0
0
0
0
CR9 (Start X-address 8 to 12)
CR9
Initial Value
B7
B6
B5
B4
B3
B2
B1
B0
ST8
ST9
ST10
ST11
ST12
—
—
—
0
0
0
0
0
0
0
0
CR8 (B7 to B0), CR9 (B7 to B3) : Recording/playback start X-address storage register
(10) CR10 (Start Y-address 0 to 7)
CR10
Initial Value
B7
B6
B5
B4
B3
B2
B1
B0
SPY0
SPY1
SPY2
SPY3
SPY4
SPY5
SPY6
SPY7
0
0
0
0
0
0
0
0
CR10 (B7 to B0) : Recording/playback stop Y-address storage register
(11) CR11 (Stop X-address 0 to 7)
CR11
Initial Value
B7
B6
B5
B4
B3
B2
B1
B0
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
0
0
0
0
0
0
0
0
CR12 (Stop X-address 8 to 12)
CR12
Initial Value
B7
B6
B5
B4
B3
B2
B1
B0
SP8
SP9
SP10
SP11
SP12
—
—
—
0
0
0
0
0
0
0
0
CR11 (B7 to B0), CR12 (B7 to B3) : Recording/playback stop X-address storage register
43/57
¡ Semiconductor
MSM7584C
(12) CR13 (Channel Selection)
CR13
Initial Value
B7
B6
B5
B4
B3
B2
B1
B0
CH0
CH1
CH2
CH3
CH4
—
ADRD
ADWT
0
0
0
0
0
0
0
0
B7 - B3: ................... Channel selection (all 32 channels are selected by HEX code)
B2: ........................... Not used
B1: ........................... Address Read instruction
0: NOP
1: When "1" is written in this bit, the start/stop addresses
corresponding to the channels specified by B7 - B3 are transferred
from the channel index area of the serial register to CR8 - CR12.
These bits are reset to "0"s after the addresses are transferred.
B0: ........................... Address write instruction
0: NOP
1: When "1" is written in this bit, the start/stop address
corresponding to the channel specified by B7 - B3 is transfered from
CR8 - 12 to the channel index area of the serial register.
These bits are reset to "0"s after the addresses are transferred.
Note:
When BUSY (CR7 - B1) and RPM (CR7 - B0) are set to "1", writing to ADRD and ADWT
is not allowed.
44/57
¡ Semiconductor
MSM7584C
(Modem)
(13) CR14 (Basic Operation Mode Setting)
B7
CR14
—
Initial Value
0
B6
B5
TXC
MOD
SEL
OFF
0
0
B4
B3
B2
B1
B0
IFSEL
—
—
TEST1
TEST0
0
0
0
0
0
B7, B3, B2: ........ Not used
B6: ..................... Transmission timing clock selection
0: TXCI input: 384 kHz TXCO output: APLL 384 kHz output
Transmit data TXD is input synchronously with the rising edge of
TXCI. APLL is ON.
1: TXCI input: 3.84 MHz
TXCO output: 384 kHz (TXCI
divided by 10)
Transmit data TXD is input synchronously with the rising edge of
TXCO. APLL is OFF.
B5: ..................... Modulation OFF/ON control
0: Modulation ON
1: Modulation OFF (fixed phase)
B4: ..................... Receive side input IF frequency selection
0: 1.2 MHz
1: 10.8 MHz
B1, B0: .............. Device test control bits
These bits should be set to "0" for normal use.
45/57
¡ Semiconductor
MSM7584C
(14) CR15 (I and Q Gain Adjustment)
B7
CR15
Initial Value
B6
B5
B4
B3
B2
B1
B0
lch
lch
lch
lch
Qch
Qch
Qch
RX Qch
GAIN3
GAIN2
GAIN1
GAIN0
GAIN3
GAIN2
GAIN1
GAIN0
0
0
0
0
0
0
0
0
B7 - B4: ......I+ and I– output gain setting: 3 mV steps (refer to Table 8)
B3 - B0: ......Q+ and Q– output gain setting: 3 mV steps (refer to Table 8)
Table 8 I and Q Channel Amplitude Value
CR1 - B7
B6
B5
B4
CR1 - B3
B2
B1
B0
0
1
1
1
Amplitude Value : 1.042 (Reference Value)
0
1
1
0
1.036
0
1
0
1
1.030
0
1
0
0
1.024
0
0
1
1
1.018
0
0
1
0
1.012
0
0
0
1
1.006
0
0
0
0
1.000 (Reference Value)
0
1
1
1
0.994
0
1
1
0
0.988
0
1
0
1
0.982
0
1
0
0
0.976
0
0
1
1
0.970
0
0
1
0
0.964
0
0
0
1
0.958
0
0
0
0
0.952
Description
46/57
¡ Semiconductor
MSM7584C
(15) CR16 (I– Output Offset Voltage Adjustment)
CR16
B7
B6
B5
B4
B3
lch
lch
lch
lch
lch
Offset4
Offset3
Offset2
Offset1
Offset0
0
0
0
0
0
Initial Value
B2
B1
B0
—
—
—
0
0
0
B2
B1
B0
—
—
—
0
0
0
B7 - B3: ......I– output pin offset voltage adjustment (refer to Table 9)
B2 - B0: ......Not used
(16) CR17 (Q– Output Offset Voltage Adjustment)
CR17
B7
B6
B5
B4
B3
Qch
Qch
Qch
Qch
Qch
Offset4
Offset3
Offset2
Offset1
Offset0
0
0
0
0
0
Initial Value
B7 - B3: ......Q– output pin offset voltage adjustment (refer to Table 9)
B2 - B0: ......Not used
Table 9 Ich and Qch Offset Adjustment Values
CR11 - B7 B6 B5 B4 B3
Offset Voltage
CR11 - B7 B6 B5 B4 B3
Offset Voltage
CR12 - B7 B6 B5 B4 B3
(mV)
CR12 - B7 B6 B5 B4 B3
(mV)
0
1
1
1
1
+45
1
1
1
1
1
–3
0
1
1
1
0
+42
1
1
1
1
0
–6
0
1
1
0
1
+39
1
1
1
0
1
–9
0
1
1
0
0
+36
1
1
1
0
0
–12
0
1
0
1
1
+33
1
1
0
1
1
–15
0
1
0
1
0
+30
1
1
0
1
0
–18
0
1
0
0
1
+27
1
1
0
0
1
–21
0
1
0
0
0
+24
1
1
0
0
0
–24
0
0
1
1
1
+21
1
0
1
1
1
–27
0
0
1
1
0
+18
1
0
1
1
0
–30
0
0
1
0
1
+15
1
0
1
0
1
–33
0
0
1
0
0
+12
1
0
1
0
0
–36
0
0
0
1
1
+9
1
0
0
1
1
–39
0
0
0
1
0
+6
1
0
0
1
0
–42
0
0
0
0
1
+3
1
0
0
0
1
–45
0
0
0
0
0
0
1
0
0
0
0
–48
47/57
¡ Semiconductor
MSM7584C
(17) CR18
B7
B6
B5
B4
CR18
—
—
—
—
Initial Value
0
0
0
0
B3
B2
LOCAL
LOCAL
INV1
INV0
0
0
B1
B0
—
—
0
0
B7 - B4: ......Not used
B3, B2: .......Local inversion mode setting bits
(These bits are used when the demodulator side IF input is phase inverted
in the system configuration)
(0, 0): Normal mode
(1, 1): Local inversion mode
B1, B0: .......Not used
(18) CR19
CR19
Initial Value
B7
B6
B5
B4
B3
B2
B1
B0
ADO7
ADO6
ADO5
ADO4
ADO3
ADO2
ADO1
ADO0
0
0
0
0
0
0
0
0
B7 - B0: ......8bit output data from the RSSI-AD converter is written.
The output results are listed in Table 10.
Table 10
BBBBBBB
76543210
RSGAIN pin
voltage (V)
11111111
2.1000
11111110
2.0945
to
to
10000001
1.4055
10000000
1.4000
01111111
1.3945
to
to
00000001
0.7055
00000000
0.7000
48/57
¡ Semiconductor
MSM7584C
(19) CR20 (SRRI-ADC Offset Voltage Adjustment)
B7
CR20
Initial Value
B6
B5
B4
B3
AD
AD
AD
AD
AD
Offset4
Offset3
Offset2
Offset1
Offset0
0
0
0
0
0
B2
B1
RS
—
PDN
0
0
B0
—
0
B7 - B3: ......RSGAIN pin DC adjustment value (Table 11)
Table 11
CR20
B7 B6 B5 B4 B3
Adjustment
Value
CR20
Adjustment
Value
(mV)
B7 B6 B5 B4 B3
(mV)
0
1
1
1
1
375
1
1
1
1
1
–25
0
1
1
1
0
350
1
1
1
1
0
–50
0
1
1
0
1
325
1
1
1
0
1
–75
0
1
1
0
0
300
1
1
1
0
0
–100
0
1
0
1
1
275
1
1
0
1
1
–125
0
1
0
1
0
250
1
1
0
1
0
–150
0
1
0
0
1
225
1
1
0
0
1
–175
0
1
0
0
0
200
1
1
0
0
0
–200
0
0
1
1
1
175
1
0
1
1
1
–225
0
0
1
1
0
150
1
0
1
1
0
–250
0
0
1
0
1
125
1
0
1
0
1
–275
0
0
1
0
0
100
1
0
1
0
0
–300
0
0
0
1
1
75
1
0
0
1
1
–325
0
0
0
1
0
50
1
0
0
1
0
–350
0
0
0
0
1
25
1
0
0
0
1
–375
0
0
0
0
0
0
1
0
0
0
0
–400
B1: .............. RSSI - ADC power down control
0: Power down
1: Power ON
B2, B0: .......Not used
49/57
¡ Semiconductor
MSM7584C
(20) CR21 (General I/O)
B7
B6
B5
B4
B3
B2
B1
B0
CR21
—
—
—
—
—
—
RO1
RO0
Initial Value
0
0
0
0
0
0
0
0
B7 - B2: ......Not used
B1 - B0: ......Data written in B1 and B0 is output to the RO1 and RO0 pins.
(21) CR22 (Control of Switches)
CR22
Initial Value
B7
B6
B5
B4
B3
B2
B1
B0
SW1
SW2
SW3
SW4/5
AOUT
AOUT3
AOUT2
AOUT1
CONT
CONT
CONT
CONT
PDN
CONT
CONT
CONT
0
0
0
0
0
0
0
0
B7, B6: .................... SW1, SW2 control
0: Open
1: Closed
B5: ........................... SW3 control
0: Open
1: Closed
B4: ........................... SW4/5 control
0: SW4 open, SW5 closed
1: SW4 closed, SW5 open
B3: ........................... Sounder amplifier power down control
0: Power ON
1: Power down
B2, B1, B0: .............. TOUT3 - 1 control
0: TOUT3 - 1 disabled
1: TOUT3 - 1 enabled
Note:
Set the unused bits of CR0 - CR22 to "0".
50/57
¡ Semiconductor
MSM7584C
DATA CONFIGURATION IN THE EXTERNAL SERIAL REGISTER
X Address Space
The address space of the external serial register is accessed based on (word direction indicated
by the X address) ¥ (1 Kb depth in Y direction). The maximum X address in word direction
depends on the total memory capacity of serial registers connected. Since the leading 32 words
(32 Kb) of the serial register are used as the channel index area, X address 020h onward can be
used as the voice data area.
CR5-B5
0
1
1
Total Memory Capacity
(device name)
1 Mb
(MSM6389)
4 Mb
(MSM6684)
8 Mb
(MSM6685)
Number of words
1K words
4K words
8K words
X address*
000h to 3FFh
0000h to 0FFFh
0000h to 1FFFh
* 0000h to 001Fh are used as the channel index area.
,
Y Address Space
For 1 Kb ADPCM data in Y direction, 4 bits ¥ 256 samples = 1024 bits are stored in the 1 Kb
memory area. One Y address is allocated to one sample (4 bits) of ADPCM data and addressing
is made with 00h to FFh.
X address (1 K words of 000h to 3FFh : 1 word = 1 Kb)
000h
Channel index area (32 words ¥ 1 Kb + 32 Kb)
1Mb serial register
01Fh
020h
3FFh
ADPCM (voice) data area
1 Kb in Y direction
1 word = 1 Kb
Y address
00h
01h
FEh
FFh
4 bit
4 bit
4 bit
4 bit
Figure 16 Address Space of 1 Mb Serial Register
51/57
¡ Semiconductor
MSM7584C
Channel Index Area of the Serial Register
One channel (1 Kb) of the channel index area consists of the 40 bits of address data.
(1) Stop Y address
The Y address is represented by 8 bits and addressing is made with 00h to FFh.
(2) Start X address, stop X address
The X address is represented by 16 bits (valid 13 bits). If, for example, the serial register is
1Mb, the 1K-word X address space is addressed with 000h to 3FFh.
Address
data
Blank data
40-bit
16-bit
8-bit
16-bit
Start
X address
Stop
Y address
Stop
X address
Start X address (ST0 to ST12)
ST0
ST1
Stop Y address (SPY0 to SPY7)
SPY0 SPY1
Stop X address (ST0 to SP12)
SP0
SP1
ST11 ST12
—
—
—
—
—
SPY6 SPY7
SP11 SP12
—
Figure 17 Channel Index Area of Serial Register
52/57
¡ Semiconductor
MSM7584C
METHODS OF RECORDING AND PLAYBACK
Recording Method (See the flow chart in Figure 18)
Recording
(1) • Set up the connection between the serial register/
voice ROM and ADPCM transmit-receive
system. (See Figure 20) (CR5 - B7)
N
BUSY = 0?
RPM = 0?
• Specify the serial register/voice ROM. (CR5 B6)
Y
• Set the external capacity. (CR5 - B5)
Basic setting
• Set the NOP command. (CR5 - B1 = "0", B0 = "0")
(2) • Set the start/stop address. (CR8 to CR12)
(3) • Set the channel. (CR13 - B7 to B3)
ST, SP
• Set the ADWT (address write) instruction. (CR13
address setting
- B1 = "0", B0 = "1")
(4) • The start/stop address of the channel set by the
Channel setting
(ADWT)
ADWT instruction is stored in the channel index
area. When status register BUSY (CR7 - B1)
changes from "1" to "0", storage is complete.
N
BUSY = 0?
(5) • Start recording by setting the REC (recording)
command (CR5 - B1 = "1", B0 = "0").
Y
(6) • Check the recording start with the status register
REC
RPM bit (CR7 - B0 = "1").
(7) • To interrupt during recording, set the STOP
(stop) command (CR5 - B1 = "1", B0 = "1").
N
RPM = 1?
In this case, to store the address counter contents
in the channel index area as a new stop address,
Y
the following settings are required:
• Set the channel.
• Set the ADWT instruction.
STOP
• When the BUSY bit changes from "1"
to "0", settings are complete.
N
(8) • When the address counter reaches the
RPM = 0?
stop address, recording is complete.
Check completion of recording with
Y
RPM bit = "0".
Channel setting
(1) CR5
(2) CR8 to 12
(3) CR13
(4) CR7
(5) CR5
Recording start
(6) CR7
Recording start
check
(7) CR5
Recording stop
CR13
CR7
(ADWT)
N
BUSY = 0?
Y
N
RPM = 0?
Y
(8) CR7
Recording
completion
check
END
Figure 18 Flow Chart of Recording
53/57
¡ Semiconductor
MSM7584C
Playback Method (See the flow chart in Figure 19)
(1) • Set up the connection between
the serial register/voice ROM
and ADPCM transmit-receive
system. (See Figure 20) (CR5 B7)
• Specify the serial register/voice
ROM. (CR5 - B6)
• Set the external capacity. (CR5 B5)
• Set the NOP command. (CR5 B1 = "0", B0 = "0")
(2) • Set the channel. (CR13 - B7 to
B3)
• Set the ADRD (address read)
instruction. (CR13 - B1 = "1", B0
= "0")
(3) • The start/stop address of the
channel set by the ADRD
instruction is fetched from the
channel index area.
When status register BUSY (CR7
- B1) changes from "1" to "0",
fetching is complete.
(4) • Start playback by setting the
PLAY (playback) command
(CR5 - B1 = "0", B0 = "1").
(5) • Check the playback start with
the status register RPM bit (CR7
- B0 = "1").
(6) • To stop playback set the STOP
command (CR5 - B1 = "1", B0 =
"1").
(7) • When the address counter
reaches the stop address,
playback is complete.
Check completion of playback
with RPM bit = "0".
Playback
N
BUSY = 0?
RPM = 0?
Y
N
Basic setting
(1) CR5
Channel setting
(ADRD)
(2) CR13
BUSY = 0?
(3) CR7
Y
N
PLAY
(4) CR5
Playback start
RPM = 1?
(5) CR7
Playback start
check
Y
STOP
(6)
CR5
Playback stop
N
RPM = 1?
Y
(7) CR7
Playback completion
check
END
Figure 19 Flow Chart of Playback
54/57
¡ Semiconductor
MSM7584C
SIGNAL FLOW IN RECORDING/PLAYBACK
When the serial register is connected to each ADPCM transmitter and receiver, the flow of
recording/playback signal is as follows:
Transmit-side recording
(CR5 – B7 = "1" + REC)
ADPCM
CODER
A-IN
Transmit-side playback
(CR5 – B7 = "1" + PLAY)
IS(ADPCM-OUT)
A-IN
ADPCM
CODER
IS(ADPCM-OUT)
Serial register
Serial register
Receive-side recording
(CR5 – B7 = "0" + REC)
Receive-side playback
(CR5 – B7 = "0" + PLAY)
A-OUT
ADPCM
DE-CODER
Serial register
IR (ADPCM-IN)
A-OUT
ADPCM
DE-CODER
IR (ADPCM-IN)
Serial register
Figure 20 Signal Flow in Transmit/Receive Side Recording/Playback
55/57
C1
R1
R1
C1 = 1 mF, C2 = 10 + 0.1 mF
C3 = 0.1 mF, C4 = 1000 pF
R1 = 27 kW, R2 = 510 W
1 mF
+
10 mF
–
MSM7584CTS-K
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DGM, DGC,
AGM, AGC
VDD
C3
C2
C3
CS1
CS2
DOUT
DIN
DEN
EXCK
RESET
MCK
DGC
SYNC
VOXO
VOXI
MLV0
MLV1
MLV2
RXMUTE
BCLK
PCMSI
PCMSO
IS
IR
PCMRI
PCMRO
DGM
IFIN
TXCI
TXCO
TXD
TXW
BSTO
RXSC
RXD
RXC
RPR
AFC/RCW
SLS
PDN3
PDN2
PDN1
PDN0
VDDM, VDDC
Modulator I component output
To quadrature modulator
Modulator Q component output
R1
R1
AIN–
AIN+
SGCT
AGC
SAO
VFRO
PWI
AOUT–
AOUT+
SGCR
SGM
AGM
SGRS
RSSI
RSGAIN
I+
I–
Q+
Q–
VDDM
DIO
RWCK
TAS
SAS
SAD
WE
RO0
RO1
TOUT3
TOUT2
TOUT1
IO7
IO6
IO5
VDDC
IO4
IO3
IO2
IO1
GSX
RSSI input
Speaker input
Receive side
voice analog input
R1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Transmit side voice analog input
C2
Ringer output
R1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Transmit Side ADPCM Output
R2
Voice Mute Control Signal
Bit Clock Input
Master Clock Input
8 kHz Sync Signal Input
Receive Side VOX Input
Transmit Side VOX output
C4
Control Register
Control Signal
Reset
VDD
CS
SADY
TEST
TEST
SADX
SASX
TAS
RDCK
SASY
DOUT
1 Mbit Serial Voice ROM
MSM6595-XXX
• A 1 Mbit serial register and a 1 Mbit serial voice ROM are used.
AU/D
RS/A
RFSH
AM
TEST
CS
DOUT
WE
SAD
SAS
TAS
RWCK
DIN
1 Mbit Serial Register
MSM6389
¡ Semiconductor
MSM7584C
APPLICATION CIRCUIT
Receive side ADPCM input
C4
Demodulator IF input
Modulator input clock
Modulator input data
Modulator data window
Modulator burst position output
Receive symbol clock output
Receive data output
Receive clock output
Demodulator control signal
Power down control signal
56/57
¡ Semiconductor
MSM7584C
PACKAGE DIMENSIONS
(Unit : mm)
TQFP80-P-1212-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.40 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
57/57