9 GHz DIVIDE-BY-4 DYNAMIC PRESCALER FEATURES INPUT POWER vs. INPUT FREQUENCY WIDE OPERATING FREQUENCY RANGE: fIN = 3.5 to 9.0 GHz (TA = 25°C) • • DIVISION RATIO OF 4 VDD = 3.8V VSS1 = 0V VSS2 = - 2.2 V (VGG1,2 OPEN) GUARANTEED OPERATING TEMPERATURE RANGE: -25°C to +75°C DESCRIPTION Input Power, PIN (dBm) • +10 ELECTRICAL CHARACTERISTICS1 0 TA = -25˚C TA = +25˚C TA = +75˚C 0 1 2 3 4 5 7 8 Supply Current = IDD - ISS2 UNITS MIN TYP MAX mA 40 80 130 ISS1 Sink Sink Current2 mA 21 53 fIN(U) Upper Limit of Input Frequency, PIN = +9 to +10 dBm GHz 8.6 9.0 fIN(L) Lower Limit of Input Frequency, PIN = +9 to +10 dBm GHz PIN Input Power, fIN = 3.7 to 8.6 GHz fIN = 5.0 to 7.4 GHz Output Power, fIN = 8.6 GHz, PIN = +10 dBm fIN = 3.7 GHz, PIN = +10 dBm dBm dBm dBm dBm Thermal Resistance, Channel to Case °C/W RTH 10 UPG503B BF08 ISS2 POUT 9 (TA = 25°C, VDD = 3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) PARAMETERS AND CONDITIONS Current2 ISS1 6 Input Frequency, f (GHz) PART NUMBER PACKAGE OUTLINE SYMBOLS TA = -25˚C to +75˚C Recommended Operating Region -10 The UPG503B is a GaAs divide-by-4 prescaler that is capable of operating up to 9 GHz. It is designed to be used in the frequency synthesizers of microwave communication systems and measurement equipment. The UPG503B is a dynamic divider. It employs buffered FET logic (BFL). The UPG503B is available in a hermetic 8-lead ceramic flat package. IDD UPG503B mA 27 3.5 9.0 3.0 0 0 93 3.7 10.0 10.0 3 3 10 Note: 1.Device may exhibit low frequency spur typically below 150 Hz and -45 dBm. 2. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins. California Eastern Laboratories UPG503B ELECTRICAL CHARACTERISTICS TA = 25°C to +75°C, VDD = 3.8 V, VSS1 = 0 V, VSS2 = -2.2 V) PART NUMBER PACKAGE OUTLINE SYMBOLS UPG503B BF08 PARAMETERS AND CONDITIONS UNITS MIN TYP IDD Supply Current mA 80 ISS1 Sink Current1 ISS1 = IDD - ISS2 mA 27 ISS2 Sink Current1 mA 53 fIN(U) Upper Limit of Input Frequency, PIN = +9 to +10 dBm GHz fIN(L) Lower Limit of Input Frequency, PIN = +9 to +10 dBm GHz PIN Input Power, fIN = 4.0 to 8.0 GHz fIN = 5.0 to 7.0 GHz Output Power fIN = 8.0 GHz, PIN = +10 dBm fIN = 4.0 GHz, PIN = +10 dBm dBm dBm dBm dBm POUT MAX 8.0 4.0 9.0 4.0 -1.0 -1.0 10.0 10.0 2.0 2.0 Note: 1. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins. ABSOLUTE MAXIMUM RATINGS1 POWER DERATING CURVE (TA = 25°C) SYMBOLS UNITS RATINGS VDD-VSS1 Supply Voltage PARAMETERS V 5.0 VSS2-VSS1 Supply Voltage V -5.0 PIN Input Power dBm 13 PT Total Power Dissipation2 W 1.5 Storage Temperature °C -65 to +175 Case Temperature °C -65 to +125 TSTG TC Notes: 1. Operation in excess of any one of these conditions may result in permanent damage. 2. TC ≤ 125°C Total Power Dissipation, PT (W) 2.5 2.0 1.5 1.0 TCASE MAX = 125°C 0.5 0 0 100 110 50 150 200 250 Case Temperature, TC (°C) TYPICAL PERFORMANCE CURVES (TA = 25°) SSB PHASE NOISE VS. OFFSET FROM CARRIER fIN = 6.82 GHz, TA = 25°C OUTPUT POWER vs. INPUT FREQUENCY -60 -80 Output Power, P OUT (dBm) SSB Phase Noise (dBc/Hz) -70 -90 -100 -110 -120 -130 -140 -150 +10 VDD = 3.8V VSS1=0V VSS2=-2.2V (VGG1,2 OPEN) TA = -25°C TA = +25°C TA = +75°C 0 -10 -160 10 100 1K 10K 100K Offset from Carrier (Hz) 1M 0 1 2 3 4 5 6 7 8 Input Frequency, fIN (GHz) 9 10 POWER SUPPLY CONFIGURATIONS (VGG1 and VGG2 are normally open) CONFIGURATION 1 2 Bias Supply C Zo = 50 Ω IN 5 IN VDD 4 10 µF C See Note 1 6 VGG1 VDD (3.8 V) NC 3 OPEN OPEN VSS1 (0 V) GND 7 VGG2 VSS1 2 8 VSS2 OUT 1 OPEN VSS2 (-2.2 V) 10 µF OUT Zo = 50 Ω C C VDD = 3.8 V VSS1 = 0 V (GND) VSS2 = –2.2 V C: 1000 - 5000 pF Chip Capacitor CONFIGURATION 2 Single Positive Bias Supply Zo = 50 Ω IN C 5 IN VDD 4 10 µF C See Note 1 6 VGG1 NC 3 * 7 VGG2 VSS1 2 C OPEN 2.2 V 8 VSS2 GND (0 V) VSS2 10 µF OPEN OPEN VDD (+6 V) OUT OUT 1 Zo = 50 Ω C VDD = +6.0 V VSS2 = 0 V (GND) C: 1000 - 5000 pF Chip Capacitor * VSS1 should be connected to GND through a 2.2 V Zener Diode (RD2.2FB or IN3394). CONFIGURATION 3 Single Negative Bias Supply Zo = 50 Ω C IN 5 IN VDD 4 See Note 1 6 VGG1 OPEN 7 VGG2 C 8 VSS2 10 µF VDD = 0 V (GND) VSS2 = –6 V C: 1000 - 5000 pF Chip Capacitor C -6 V* VSS1 2 OPEN VSS2 (-6 V) 10 µF NC 3 OPEN 2.2 V OUT OUT 1 C Zo = 50 Ω * For VSS1, the bias voltage of -6.0 should be applied through a 2.2 V Zener Diode (RD2.2FB or IN3394). Notes: 1. Because of the high internal gain and gain compression of the UPG503B, the device is prone to self-oscillation in the absence of an RF input signal. This self-oscillation can be suppressed by either of the following means: • Add a shunt resistor to the RF input line. Typically a resistor value between 50 and 1000 ohms will suppress the selfoscillation (see the test circuit schematic). • Apply a negative voltage through a 1000 ohm resistor to the normally open VGG1 connection. Typically voltages between 0 and -9 volts will suppress the self-oscillation. Both of these approaches will reduce the input sensitivity of the device (by as much as 3 dB for a 50 ohm shunt resistor), but otherwise have no effect on the reliability or electrical characteristics of the device. UPG503B OUTLINE DIMENSIONS (Units in mm) UPG503B PACKAGE OUTLINE BF08 7.0±0.5 1.27 1.27 1.27 ±0.1 ±0.1 ±0.1 8 7 6 1.7 MAX 5 10.4±0.5 2.6 4.4±0.2 1 2 3 4 +0.05 0.2 -0.02 0.4 5.0±0.2 LEAD CONNECTIONS: 1. 2. 3. 4. OUTPUT VSS1 NC* VDD 5. 6. 7. 8. INPUT VGG1 VGG2 VSS2 * No Connection EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: http://WWW.CEL.COM PRINTED IN USA ON RECYCLED PAPER -4/97 DATA SUBJECT TO CHANGE WITHOUT NOTICE