VFC101 ® Synchronized VOLTAGE-TO-FREQUENCY CONVERTER FEATURES DESCRIPTION ● FULL-SCALE FREQUENCY SET BY SYSTEM CLOCK The VFC101 voltage-to-frequency converter uses the proven charge-balance technique with internal digital logic to control the critical reference integration period. Reference timing is derived from an external clock signal which accurately sets the full-scale frequency. This technique eliminates the errors and drift from external timing components which are required with other VFCs. ● MULTIPLE INPUT RANGES: 5V, 8V, 10V Full Scale ● ACCURATE 5V REFERENCE VOLTAGE ● LOW NONLINEARITY: 0.02% max at 100kHz FS ● LOW GAIN DRIFT: 40ppm/°C APPLICATIONS ● INTEGRATING A/D CONVERTER ● MULTICHANNEL DATA ACQUISITION ● FREQUENCY-TO-VOLTAGE CONVERSION ● VOLTAGE ISOLATION Internal resistors provide accurate full-scale input ranges of 5V, 8V or 10V inputs without external resistors or trimming. An accurate 5V reference voltage output is useful for bridge or sensor excitation. With simple pin interconnections, it can provide halfscale offset to allow bipolar input voltages. The open-collector frequency output interfaces easily to CMOS or TTL circuitry. Output one-shot circuitry may be used to optimize the output pulse width for optical couplers or transformers. The VFC101 is packaged in a surface-mount 20-pin PLCC (plastic leaded chip carrier) package. +VCC 8 4 5 17 2 13 14 7 10kΩ 10kΩ 9 16kΩ 4kΩ 10 Integrator Comparator Clocked Logic Output One-Shot 15 1mA 5V Reference I1 6 –VCC 16 18 20 12 11 –VCC International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1988 Burr-Brown Corporation PDS-779B Printed in U.S.A. October, 1993 SPECIFICATIONS ELECTRICAL At TA = +25°C and ±15VDC supplies unless otherwise noted. VFC101JN PARAMETER CONDITIONS TRANSFER FUNCTION Voltage-to-Frequency Mode Gain Error(1) Linearity Error Gain Drift(2) Referred to Internal VREF Offset Referred to Input Offset Drift Power Supply Rejection Response Time fOUT = fCLOCK (VIN/2VFS) FSR(2) = 100kHz FSR = 100kHz, Over Temperature FSR = 500kHz, COS = 60pF FSR = 1MHz, COS = 60pF FSR = 100kHz Full Supply Range To Step Input Change Frequency-to-Voltage Mode Gain Accuracy(1) Linearity Error MIN ZLOAD = 5kΩ/10,000pF MAX 100 80 –7.5 –0.2 % of FSR % of FSR % of FSR % of FSR ppm of FSR/°C ppm of FSR/°C mV µV/°C %/V * * * ±0.02 % % ±30 ±50 ±100 * * * % ppm°C ±150 ±5 ±50 100 120 105 ±1000 ±25 ±100 200 +0.1 +12 * * * * * ±25 50 * * * * 5 4 1.4 0.8 –VCC + 3 0.5 OPEN COLLECTOR OUTPUT (Referenced to Digital Common) VOL IOUT = 10mA IOL IOH (off leakage) VOUT = 30V Delay Time, Positive Clock Edge to Output Pulse Fall Time Output Capacitance UNITS ±0.5 ±0.025 –VCC + 4V < VIN < +VCC CLOCK INPUT (Referenced to Digital Common) Frequency (maximum operating) Threshold Voltage Over Temperature Voltage Range Input Current Rise Time TYP ±0.3 ±0.01 14 COMPARATOR INPUTS Input Bias Current (IS) OUTPUT ONE-SHOT Pulse Width Out MIN ±0.5 * * ±0.025 * ±0.02 ±0.05 * * ±0.1 * * ±80 ±30 ±40 ±25 * ±15 ±3 * ±2 ±100 ±6.5 ±25 0.02 0.015 One Period of New Output Frequency Plus One Clock Period Input Resistors Resistance Temperature Coefficient (TC)(2) ZLOAD = 5kΩ/10,000pF VFC101KN MAX ±0.3 ±0.01 ±0.02 ±0.05 ±50 10 ±1 ±12 VOUT = 2VFS (fIN/fCLOCK) FSR = 100kHz FSR = 100kHz INTEGRATOR OP AMP VOS(1) VOS Drift IB IOS AOL CMRR CM Range VOUT Range Bandwidth TYP 0.01 * ±15 ±50 100 * * * µA * * * * MHz V V V µA µs * * * V mA µA * * 2 +VCC 5 2 * * * 0.4 15 10 * 300 100 5 µV µV/°C nA nA dB dB V V MHz * * * ns ns pF Nominal PWOUT = (5ns/pF) x COS – 90ns; COS = 300pF 1 1.4 2 * * * µs No Load 4.9 5 ±60 5.1 ±105 4.95 * ±40 5.05 ±55 0.5 0.015 2 * * * V ppm/°C mA %/V Ω * * * * * * V V V V V mA mA REFERENCE VOLTAGE Accuracy Drift(2) Current Output (sourcing) Power Supply Rejection Output Impedance POWER SUPPLY Rated Voltage Operating Voltage Range Total Supply Digital Common Quiescent Current: +ICC –ICC 10 * ±15 +VCC –VCC +VCC – (–VCC) +7.5 –7.5 15 –VCC + 2 Over Temperature 10.6 9.6 ® VFC101 2 * +28.5 –28.5 36 +VCC – 4 15 15 * * * * * * SPECIFICATIONS (CONT) ELECTRICAL At TA = +25°C and ±15VDC supplies unless otherwise noted. VFC101JN PARAMETER CONDITIONS TEMPERATURE RANGE Specification Storage θJA θJC MIN TYP 0 –65 VFC101KN MAX MIN +70 +150 * * TYP 90 35 MAX UNITS * * °C °C °C/W °C/W * * * Specification same as JN grade. NOTES: (1) Offset and gain error can be trimmed to zero. (2) Specified by the box method: (max – min) ÷ (Avg x ∆T). PIN CONFIGURATION PIN ASSIGNMENTS Top View PIN # 3 2 1 20 19 18 4 17 5 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20-Pin PLCC Package 16 7 15 8 14 9 10 11 12 13 Grade Designation ABSOLUTE MAXIMUM RATINGS Power Supply Voltage (+VCC to –VCC) ................................................. 36V +VCC to Analog Common ..................................................................... 28V –VCC to Analog Common ...................................................................... 28V Integrator Out Short-Circuit to Ground ........................................ Indefinite Integrator Differential Input ................................................................ ±10V Integrator Common-Mode Input .................................... –VCC +5V to +2V VIN (pins 7, 8, 9, 10) .......................................................................... ±VCC Clock Input ......................................................................................... ±VCC VREF Out Short-Circuit to Ground ................................................. Indefinite COS (Pin 12) ................................................................................ 0 to +VCC fOUT (referred to digital common) ........................................... –0.5V to 36V Digital Common ................................................................................. ±VCC Storage Temperature Range .......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C DESCRIPTION NC +VCC Power Supply NC VOUT Integrator Amp Output CINT, Integrator Inverting Input +VIN, Integrator Noninverting Input VIN, 5V FS VIN, 10V FS VIN, 8V FS VIN, 10V FS –VCC Power Supply COS, Output One-Shot Capacitor fCLOCK Input fOUT Frequency Output Digital Ground Analog Ground – Comparator Input + Comparator Input NC VREF +5V Reference Output PACKAGE INFORMATION(1) MODEL VFC101JN VFC101KN PACKAGE PACKAGE DRAWING NUMBER 20-Pin PLCC 20-Pin PLCC 181 181 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL VFC101JN VFC101KN PACKAGE TEMPERATURE RANGE 20-Pin PLCC 20-Pin PLCC 0°C to +70°C 0°C to +70°C The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 VFC101 TYPICAL PERFORMANCE CURVES At +25°C, ±VCC = 15VDC, and in circuit of Figure 1, unless otherwise specified. QUIESCENT CURRENT vs TEMPERATURE REFERENCE VOLTAGE vs REFERENCE LOAD CURRENT 5.01 5 15 +I CC VREF (V) Supply Current (mA) 20 10 –I CC 5 Short Circuit Current Limit 4.99 4.98 4.97 0 –75 4.96 –50 –25 0 25 50 75 100 125 0 5 10 Ambient Temperature (°C) NONLINEARITY AND GAIN ERROR vs FULL-SCALE FREQUENCY 3 0.02 2 1 Nonlinearity (%) 0.01 Gain Error (%) Nonlinearity (%) Nonlinearity 30 fFS = 100kHz 0.005 0 Gain Error 0 –0.005 0 0 1M 2 4 6 VIN (V) fFS – Full Scale Frequency (Hz) ® VFC101 25 0.015 0.01 500k 20 NONLINEARITY vs VIN 0.03 0 15 Output Current (mA) 4 8 10 THEORY OF OPERATION other VFC circuits. One period (from rising edge to rising edge) of the clock input determines the integrator reset period. The VFC101 voltage-to-frequency converter provides digital output pulses with an average frequency proportional to the analog input voltage. The output is an active low pulse of constant duration, with a repetition rate determined by the input voltage. Falling edges of the output pulses are synchronized with rising edges of the clock input. When the negative-going integration of the input signal crosses the comparator threshold, integration of the input signal will continue until the reset period can start (awaiting the necessary transitions of the clock). Output pulses are thus made to align with rising edges of the external clock. This causes the instantaneous output frequency to be a subharmonic of the clock frequency. The average frequency, however, will be an accurate analog of the input voltage. Operation is similar to a conventional charge-balance VFC. An input operational amplifier (Figure 1) is configured as an integrator so that a positive input voltage causes an input current to flow in CINT. This forces the integrator output to ramp negatively. When the output of the integrator crosses the reference voltage (5V), the comparator trips, activating the clocked logic circuit. Once activated, the clocked logic awaits a falling edge of the clock input, followed by a rising edge. On the rising edge, switch SW1 is closed for one complete clock cycle, causing the reset current, I1, to switch to the integrator input. Since I1 is larger than the input current, IIN, the output of the integrator ramps positively during the one clock cycle reset period. The clocked logic circuitry also generates a VFC output pulse during the reset period. A full-scale input causes a nominal output frequency equal to one-half the clock frequency. The transfer function is fOUT = (VIN/2VFS) fCLOCK. Input voltages greater than VFS cause the output frequency to limit at half the clock frequency. Negative inputs cause all output pulses to cease. The full-scale input voltage, VFS, is determined by the input pin used—see Figure 1. One of the useful functions made possible by the VFC101’s multiple input resistors is shown in Figure 2. By connecting one 10V input to the 5V VREF output, the other 10V input pin functions as a bipolar input. A –5V to +5V input range causes a zero to fCLOCK/2 output frequency range. Accurate ratio matching and temperature tracking of the input resistors provides improved stability of the half-scale offset. Unlike conventional VFC circuits, the VFC101 accurately derives its reset period from an external clock frequency. This eliminates the critical timing capacitor required by INPUT FULL-SCALE VOLTAGE Pin Number VRS 8 10V 10 10V 9 8V 7 5V (1) 7 2.5V NOTE: (1) Pin 8 connected to pin 5. +VCC fCLOCK TTL/CMOS C INT +VL 0.1µF 0.1µF 0 to 10V 8 5 4 17 2 13 14 +VCC 0 to 5V 7 0 to 8V 9 10kΩ 10kΩ Integrator Comparator Clocked Logic fOUT 0 to fCLOCK/2 Output One-Shot 15 16kΩ SW1 4kΩ VIN 10 1mA 5V Reference I1 6 –VCC Digital Ground –VCC 16 18 20 Analog Ground 12 11 0.1µF +VCC –VCC Clock Integrator 5V fO FIGURE 1. Basic Voltage-to-Frequency Operations. ® 5 VFC101 +VCC C INT 8 fCLOCK TTL/CMOS 5 4 17 +VL 0.1µF 2 13 14 +VCC 10kΩ 10kΩ VIN Comparator Integrator Clocked Logic 7 –5V to +5V 0.1µF fOUT 0 to fCLOCK/2 Output One-Shot 15 16kΩ 9 4kΩ 1mA 10 5V Reference I1 6 –VCC Digital Ground –VCC 16 18 20 Analog Ground 12 11 0.1µF +VCC –VCC FIGURE 2. Offset for Bipolar Input Voltages. INSTALLATION AND OPERATING INSTRUCTIONS VFC operation. It may be desirable to deviate from the suggested value. Smaller integrator voltages, for instance, allow more “headroom” for averaging noisy input signals. The VFC is a fully integrating input converter, able to reject large levels of interfering noise. This ability is limited only by the output voltage swing range of the integrator amplifier. By setting a small integrator voltage swing using a large CINT value, larger levels of noise can be integrated without integrator output saturation and loss of accuracy. The integrator capacitor CINT (see Figure 1) affects the magnitude of the integrator voltage waveform. Its absolute accuracy is not critical since it does not affect the transfer function. Figure 3 facilitates choosing an appropriate standard value to assure that the integrator waveform voltage is within acceptable limits. Good dielectric absorption properties are required to achieve best linearity. Mylar™, polycarbonate, mica, polystyrene, Teflon™ and glass types are appropriate choices. Choice will depend on the particular value and size. Ceramic capacitors vary considerably from type to type and some produce significant nonlinearities. Polarized capacitors should not be used. The maximum integrator voltage swing requirement is nearly symmetrical about the comparator threshold voltage (see Figure 5.) One-third greater swing is required above the threshold than below it. Maximum demand on positive integrator swing occurs at low scale, while the negative swing is greatest just below full scale. Deviation from the nominal recommended +1V to –0.75V integrator voltage (as controlled by the integrator capacitor value) is permissible and will have a negligible effect on 10µ Integrator Swing(1) +100mV –75mV 1µ C INT (F) CLOCK INPUT The clock input is TTL- and CMOS-compatible. Its input threshold is approximately 1.4V (two diode voltage drops) referenced to digital ground (pin 15). The clock “high” input may be standard TLL or may be as high as +VCC. The clock input has a high input impedance, so no special drivers are required. Rise time in the transition region from 0.5V to 2V must be less than 2µs for proper operation. 0.1µ +1V –0.75V 0.01µ OUTPUT The frequency output is an open collector current-sink transistor. Output pulses are active-low during the reset integration period (see “Shortened Output Pulses”.) +2.5V –1.9V 1000p 100p 100 1k 10k 100k 1M Interface to a logic circuit normally uses a pull-up resistor to the logic power supply. Selection of the pull-up resistor should be made such that no more than 15mA flows in the output transistor. The actual choice of the pull-up resistor may depend on the full-scale frequency and the stray capaci- 10M Full-Scale Frequency (Hz) NOTE: (1)This is the maximum swing of the integrator output voltage referred to the comparator noninverting input voltage. FIGURE 3. Integrator Capacitor Selection Graph. Mylar™, Teflon™ E. I. du Pont de Nemours & Co. ® VFC101 6 tance on the output line. The rising edge of an output pulse is determined by the RC time constant of the pull-up resistor and the stray capacitance. causing the output pulse to last one clock period. The minimum practical pulse width of the one-shot circuit is approximately 100ns. Using COS to generate shorter output pulses does not affect the output frequency or the gain equation. The synchronized nature of the VFC101 makes viewing its output on an oscilloscope somewhat tricky. Since all output pulses align with the clock, it is best to trigger and view the clock on one of the input channels and the output can then be viewed on another oscilloscope channel. Depending on the VFC input voltage, the output waveform may appear as if the oscilloscope is not properly triggered. The output might best be visualized by imagining a constant output frequency which is locked to a submultiple of the clock frequency with occasional extra pulses or missing pulses to create the necessary average frequency. It is these extra or missing pulses that make the output waveform appear as if the oscilloscope is not properly triggered. This behavior amounts to a frequency or phase jitter in the output, making frequency detection with most phase-locked loop circuitry impractical. For the same reason, fast period measurement (ratiometric counting) will not provide a stable reading. The output frequency must be measured (averaged) for N counts of fCLOCK to achieve a stable N counts of resolution. REFERENCE VOLTAGE Low gain drift is achieved with a precision internal 5V reference. This reference is brought to an external pin and can be used for a variety of purposes. It is used to offset the noninverting comparator input in voltage-to-frequency mode (although a precise voltage is not required for this function). It is very useful in many other applications such as offsetting the input to accept bipolar input signals. It can source up to 10mA and sink 100µA. Heavy loading of the reference will change the gain of the VFC. A 10mA load interacting with a 0.5Ω typical output impedance will change the VFC gain equation and reference voltage by 0.1%. LINEARITY PERFORMANCE The linearity of the VFC100 is specified as the worst-case deviation from a straight line defined by low scale and high scale end point measurements. This worst-case deviation is expressed as a percentage of the 10V full-scale input. All units are tested. SHORTENED OUTPUT PULSES With pin 12 connected to +VCC, the negative output pulse duration is equal to one period of the clock input. Shorter output pulses may be useful in driving optical couplers or transformers for voltage isolation or noise rejection. This can be accomplished by connecting capacitor COS as shown in Figure 4. Output pulses cannot be made to exceed one clock period in duration. Thus, a COS value which would create an output pulse which is longer than one period of the clock will have the same effect as disabling the one-shot, Linearity performance and gain error change with full-scale operating frequency as shown in the typical performance curves. Integrator voltage swing (determined by CINT) has a minor effect on linearity. A small integrator voltage swing typically leads to best linearity performance. The best linearity performance at high full-scale frequencies (above 500kHz) is obtained by using short output pulses +VCC 1µF 14 f OUT Output One-Shot 15 12 Digital Common One-Shot Capacitor Value, C OS 2 0.1µF 0.01µF 1000pF tO 100pF 11 10pF 100ns COS 0.1µF 1µs 10µs 100µs 1ms 10ms Nominal Output Pulse Width, t O +VCC –VCC Clock tO f OUT Output Pulse Width With Pin 12 Connected to +VCC. FIGURE 4. Circuit and Timing Diagram for Shortened Output Pulses. ® 7 VFC101 with a one-shot capacitor of 60pF. As with any highfrequency circuit, careful attention to good power supply bypassing techniques (see “Power Supplies and Grounding”) is also required. tually be connected together at a common point in the circuitry, separate circuit connections to this common point can reduce the error voltages created by varying currents flowing through the ground return impedance. The +5V VREF pin is referenced to analog ground. TEMPERATURE DRIFT Conventional VFC circuits are affected significantly by external component temperature drift. Drift of the external input resistor and timing capacitor required with these devices may easily exceed the specified drift of the VFC itself. The power supplies should be well bypassed using capacitors with low impedance at high frequency. A value of 0.1µF is adequate for most circuit layouts. The VFC101 is specified for a nominal supply voltage of ±15V. Supply voltages ranging from ±7.5V to ±18V may be used. Either supply can be up to 28V as long as the total of both does not exceed 36V. Steps must be taken, however, to assure that the integrator output does not exceed its linear range. Although the integrator output is capable of 12V output swing with 15V power supplies, with 7.5V supplies, output swing will be limited to approximately 4.5V. In this case, the comparator input cannot be offset by directly connecting to the 5V reference output pin. The comparator input must be connected to a lower voltage point (approximately 2V.) This allows the integrator output to operate around a lower voltage point, assuring linear operation. This threshold voltage does not affect the accuracy or drift of the VFC as long as it is not noisy. It should not be made too small, however, or the negative output limitation of the integrator (–0.2V) may cause saturation. Also, a large integrator capacitor may be used to limit the required integrator waveform swing to approximately 100mV (see Figure 3.) When used with its internal input resistor, the gain drift of the complete VFC101 circuit is totally determined by the performance of the VFC101. Gain drift is specified at a fullscale output frequency of 100kHz. Gain drift remains excellent at higher operating frequency, typically remaining within specifications at fFS = 1MHz. Drift of the external clock frequency directly affects the output frequency, but by using a common clock for the VFC and counting circuitry, this drift can be cancelled. POWER SUPPLIES AND GROUNDING Separate analog and digital grounds are provided on the VFC101 and it is important to separate these grounds to attain greatest accuracy. Logic sink current flowing in the fOUT pin is returned to the digital ground. If this “noisy” current were allowed to flow in analog ground, errors could be created. Although analog and digital grounds may even- +8V Clock 100kHz C INT +VL 0.1µF VIN 0 to 10V 0.1µF +VCC RIN Clocked Logic fOUT 0 to 50kHz Output One-Shot 5V Reference –VCC –VCC 0.1µF 2.2kΩ (2.25V) 0.05µF VTH 1.8kΩ +8V –8V Integrator Voltage Waveform (Pin 4) VTH + 100mV VTH 2.25V Low Scale (VIN ≈ 120mV) Slow Oscilloscope Sweep High Scale (VIN ≈ 8.3V) Fast Oscilloscope Sweep VTH – 75mV FIGURE 5. Circuit Diagram and Integrator Voltage Waveform for Low Power Supply Voltage Operation. ® VFC101 8 The circuit in Figure 5 operates from the minimum power supplies, avoiding saturation of the integrator amplifier and loss of accuracy. CINT is chosen for a +100mV to –75mV integrator voltage swing (referred to the noninverting comparator input). The offset voltage applied to the comparator’s noninverting input is derived from a resistive voltage divider from VREF. The proper timing of the input frequency waveform is shown in Figure 7. The input pulse should go low for one clock cycle, centered around a falling edge of the clock. The minimum acceptable input pulse width must fall no later than 200ns before a negative clock edge and rise no sooner than 200ns after the falling clock edge. An input pulse which remains low for more than one falling edge of the clock will produce incorrect output voltages. Positive (active high) input pulses can be accepted by reversing the connections to pins 14 and 15. The relationship of the allowable operating voltage ranges on important pins is shown in Figure 6. Note that the integrator amplifier output cannot swing more than 0.2V below ground. Although this is not “normal” for an operational amplifier, a special design of this type optimizes highfrequency performance. It is this characteristic which requires offsetting the noninverting comparator input in voltage-to-frequency mode. The integrator amplifier output is designed to drive up to 10,000pF and 5kΩ loads in frequency-to-voltage mode. This allows driving long lines in a large system. Ripple voltage in the voltage output is unavoidable and is inversely proportional to the value of the integrator capacitor. Figure 8 shows the output ripple and settling time as a function of the CINT value. FREQUENCY-TO-VOLTAGE MODE The VFC100 can also function as a frequency-to-voltage converter by supplying an input frequency to the comparator input as shown in Figure 7. The input resistor, RIN, is connected as a feedback resistor. The voltage at the integrator amp output is proportional to the ratio of the input frequency to the clock frequency. The transfer function is: The ripple frequency is equal to the input frequency. Its magnitude can be reduced by using a large integrator capacitor value, but with the tradeoff of slow settling time in response to an input frequency change. The settling time constant is equal to RIN x CINT. A better compromise between output ripple and settling time can be achieved by using a moderately low integrator capacitor value and adding a lowpass filter on the analog output. The cutoff frequency of the filter should be made below the lowest expected input frequency to the frequency-to-voltage converter. VOUT = (fOUT/fCLOCK) 20V. This transfer function is complementary to the voltage-tofrequency mode transfer function, making voltage-to-frequency-to-voltage conversions simple and accurate. NOTE: Several useful applications circuits may be found in the VFC100 product data sheet. These require only minor adaptation to the different pinout and input resistor configurations of the VFC101. Direct coupling of the input frequency to the comparator is easily accomplished by driving both comparators with complementary frequency input signals. Alternatively, one of the comparator inputs can be biased at half the logic voltage (using VREF and a voltage divider) and the other input driven directly. +VCC –VCC + 4V to +VCC > 3V –VCC + 3V to +VCC 8 5 4 17 2 13 7 7.5V to 28.5V RIN Clocked Logic > 4V 14 +VCC –0.5V to 30V Output One-Shot 15 9 > –0.2V 15V to 36V 10 6 < 0.1V > –7.5V 5V Reference –VCC 16 18 20 –VCC 12 > 2V 11 (5V) > 7.5V 7.5V to 28.5V –VCC –VCC + 4V to +VCC – 2 +VCC or C OS FIGURE 6. Relationships of Allowable Voltages. ® 9 VFC101 fIN Clock In VOUT C INT 8 +15VDC 5 17 4 2 13 14 +VCC Output One-Shot Clocked Logic 7 No Connection Required 15 9 10 6 5V Reference –VCC 16 18 –VCC 20 12 11 +15VDC –15VDC Frequency-to-Voltage Mode Timing Clock f IN (Preferred) 5V 200ns 200ns f IN (Limits) 5V 200ns Minimum Input Pulse Maximum Input Pulse FIGURE 7. Circuit and Timing Diagram of a Frequency-to-Voltage Converter. 100 f FS = 100kHz f FS 10kHz 100 Settling Time 1 10 f FS 1MHz 0.1 1 0.01 0.001 100pF 0.1 Settling Time to 0.1% (ms) Ripple Voltage (Vp-p) 10 1000 0.01 1000pF 0.01µF 0.1µF 1µF 10µF C INT FIGURE 8. Frequency-to-Voltage Mode Output Ripple and Settling Time vs Integrator Capacitance. ® VFC101 10 200ns