DAC1218/DAC1219 12-Bit Binary Multiplying D/A Converter General Description The DAC1218 and the DAC1219 are 12-bit binary, 4-quadrant multiplying D to A converters. The linearity, differential non-linearity and monotonicity specifications for these converters are all guaranteed over temperature. In addition, these parameters are specified with standard zero and fullscale adjustment procedures as opposed to the impractical best fit straight line guarantee. This level of precision is achieved though the use of an advanced silicon-chromium (SiCr) R-2R resistor ladder network. This type of thin-film resistor eliminates the parasitic diode problems associated with diffused resistors and allows the applied reference voltage to range from b25V to 25V, independent of the logic supply voltage. CMOS current switches and drive circuitry are used to achieve low power consumption (20 mW typical) and minimize output leakage current errors (10 nA maximum). Unique digital input circuitry maintains TTL compatible input threshold voltages over the full operating supply voltage range. The DAC1218 and DAC1219 are direct replacements for the AD7541 series, AD7521 series, and AD7531 series with a significant improvement in the linearity specification. In applications where direct interface of the D to A converter to a microprocessor bus is desirable, the DAC1208 and DAC1230 series eliminate the need for additional interface logic. Features Y Y Y Y Linearity specified with zero and full-scale adjust only Logic inputs which meet TTL voltage level specs (1.4V logic threshold) Works with g 10V referenceÐfull 4-quadrant multiplication All parts guaranteed 12-bit monotonic Key Specifications Y Y Y Y Y Y Current Settling Time Resolution Linearity (Guaranteed over temperature) Gain Tempco Low Power Dissipation Single Power Supply Typical Application 1 ms 12 Bits 12 Bits (DAC1218) 11 Bits (DAC1219) 1.5 ppm/§ C 20 mW 5 VDC to 15 VDC Connection Diagram Dual-In-Line Package TL/H/5691 – 1 VOUT e b VREF # A1 A2 A3 A12 a a a ... 2 4 8 4096 J TL/H/5691 – 15 where: AN e 1 if digital input is high Top View AN e 0 if digital input is low Ordering Information Temperature Range Non Linearity 0.012% 0.024% 0§ C to a 70§ C b 40§ C to a 85§ C DAC1218LCJ-1 DAC1218LCJ J18A Cerdip DAC1219LCJ J18A Cerdip Package Outline BI-FETTM is a trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/H/5691 RRD-B30M115/Printed in U. S. A. DAC1218/DAC1219 12-Bit Binary Multiplying D/A Converter December 1994 Absolute Maximum Ratings (Notes 1 and 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Temperature Range DAC1218LCJ, DAC1219LCJ DAC1218LCJ-1 Supply Voltage (VCC) 17 VDC Voltage at Any Digital Input VCC to GND g 25V Voltage at VREF Input b 65§ C to a 150§ C Storage Temperature Range Package Dissipation at TA e 25§ C (Note 3) 500 mW b 100 mV to VCC DC Voltage Applied to IOUT1 or IOUT2 (Note 4) Lead Temp. (Soldering, 10 seconds) 300§ C ESD Susceptibility (Note 11) 800V Range of VCC Voltage at Any Digital Input TMIN s TA s TMAX b 40§ C s TA s a 85§ C 0§ C s TA s 70§ C 5 VDC to 16 VDC VCC to GND Electrical Characteristics VREF e 10.000 VDC, VCC e 11.4 VDC to 15.75 VDC unless otherwise noted. Boldface limits apply from TMIN to TMAX (see Note 9); all other limits TA e TJ e 25§ C. Parameter Conditions Notes Resolution Linearity Error (End Point Linearity) Differential Non-Linearity Zero and Full-Scale Adjusted DAC1218 DAC1219 4, 5, 9 Zero and Full-Scale Adjusted DAC1218 DAC1219 4, 5, 9 Monotonicity Gain Error (Min) Gain Error (Max) Using Internal RFb, VREF e g 10V, g 1V Gain Error Tempco Typ (Note 10) Tested Limit (Note 11) Design Limit (Note 12) Units 12 12 12 Bits g 0.018 g 0.024 g 0.018 g 0.024 % of FSR % of FSR g 0.018 g 0.024 g 0.018 g 0.024 % of FSR % of FSR 12 4 12 12 5 b 0.1 0.0 5 b 0.1 b 0.2 5 g 1.3 % of FSR g 6.0 Power Supply Rejection All Digital Inputs High 5 g 3.0 g 30 Reference Input Resistance (Min) 9 15 10 10 (Max) 9 15 20 20 Output Feedthrough Error VREF e 120 Vp-p, f e 100 kHz All Data Inputs Low 6 3.0 Output Capacitance All Data Inputs IOUT1 High IOUT2 All Data Inputs IOUT1 Low IOUT2 Supply Current Drain Output Leakage Current IOUT1 IOUT2 9 Bits % of FSR ppm of FS/§ C ppm of FSR/V kX kX mVp-p 200 70 70 200 pF pF pF pF 2.0 2.5 mA 10 10 10 10 nA nA 7, 9 All Data Inputs Low All Data Inputs High Digital Input Threshold Low Threshold High Threshold 9 0.8 2.2 0.8 2.2 VDC VDC Digital Input Currents Digital Inputs k0.8V Digital Inputs l2.2V 9 b 200 b 200 10 10 mADC mADC ts Current Settling Time RL e 100X, Output Settled to 0.01%, All Digital Inputs Switched Simultaneously 1 2 ms Electrical Characteristics Notes Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify the power dissipation) removes concern for heat sinking. Note 4: Both IOUT1 and IOUT2 must go to ground or the virtual ground of an operational amplifier. The linearity error is degraded by approximately VOS d VREF. For example, if VREF e 10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will introduce an additional 0.01% linearity error. Note 5: The unit FSR stands for full-scale range. Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular VREF value to indicate the true performance of the part. The Linearity Error specification of the DAC1218 is 0.012% of FSR. This guarantees that after performing a zero and full-scale adjustment, the plot of the 4096 analog voltage outputs will each be within 0.012% c VREF of a straight line which passes through zero and fullscale. The unit ppm of FSR (parts per million of full-scale range) and ppm of FS (parts per million of full-scale) are used for convenience to define specs of very small percentage values, typical of higher accuracy converters. 1 ppm of FSR e VREF/106 is the conversion factor to provide an actual output voltage quantity. For example, the gain error tempco spec of g 6 ppm of FS/§ C represents a worst-case full-scale gain error change with temperature from b 40§ C to a 85§ C of g (6)(VREF/106)(125§ C) or g 0.75 (10b3) VREF which is g 0.075% of VREF. Note 6: To achieve this low feedthrough in the D package, the user must ground the metal lid. If the lid is left floating the feedthrough is typically 6 mV. Note 7: A 10 nA leakage current with RFb e 20k and VREF e 10V corresponds to a zero error of (10 c 10b9c 20 c 103) c 100% 10V or 0.002% of FS. Note 8: Human body model, 100 pF discharged through 1.5 kX resistor. Note 9: Tested limit for b 1 suffix parts applies only at 25§ C. Note 10: Typicals are at 25§ C and represent the most likely parametric norm. Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 12: Design limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels. Typical Performance Characteristics Digital Input Threshold vs VCC Digital Input Threshold vs Temperature Gain and Linearity Error Variation vs Temperature Gain and Linearity Error Variation vs Supply Voltage TL/H/5691 – 2 3 Definition of Package Pinouts DAC transfer characteristic. It is measured after adjusting for zero and full scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted. National’s linearity test (a) and the best straight line test (b) used by other suppliers are illustrated below. The best straight line (b) requires a special zero and FS adjustment for each part, which is almost impossible for the user to determine. The end point test uses a standard zero FS adjustment procedure and is a much more stringent test for DAC linearity. Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output. Settling Time: Full-scale current settling time requires zero to full-scale or full-scale to zero output change. Settling time is the time required from a code transition until the DAC output reaches within g 1/2 LSB of the final output value. Full-scale Error: Full-scale error is a measure of the output error between an ideal DAC and the actual device output. Ideally, for the DAC1218 full-scale is VREFb1 LSB. For VREF e 10V and unipolar operation, VFULLSCALE e 10.0000V b 2.44 mV e 9.9976V. Full-scale error is adjustable to zero. Differential Non-Linearity: The difference between any two consecutive codes in the transfer curve from the theoretical 1 LSB is differential non-linearity. Monotonic: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 12-bit DAC which is monotonic to 12 bits simply means that input increasing digital input codes will produce an increasing analog output. (A1 – A12): Digital Inputs. A12 is the least significant digital input (LSB) and A1 is the most significant digital input (MSB). IOUT1: DAC Current Output 1. IOUT1 is a maximum for a digital input of all 1s, and is zero for a digital input of all 0s. IOUT2: DAC Current Output 2. IOUT2 is a constant minus IOUT1, or IOUT1 a IOUT2 e constant (for a fixed reference voltage). RFb: Feedback Resistor. The feedback resistor is provided on the IC chip for use as the shunt feedback resistor for the external op amp which is used to provide an output voltage for the DAC. This on-chip resistor should always be used (not an external resistor) since it matches the resistors in the on-chip R-2R ladder and tracks these resistors over temperature. VREF: Reference Voltage Input. This input connects to an external precision voltage source to the internal R-2R ladder. VREF can be selected over the range of 10V to b10V. This is also the analog voltage input for a 4-quadrant multiplying DAC application. VCC: Digital Supply Voltage. This is the power supply pin for the part. VCC can be from 5 VDC to 15 VDC. Operation is optimum for 15 VDC. GND: Ground. This is the ground for the circuit. Definition of Terms Resolution: Resolution is defined as the reciprocal of the number of discrete steps in the DAC output. It is directly related to the number of switches or bits within the DAC. For example, the DAC1218 has 212 or 4096 steps and therefore has 12-bit resolution. Linearity Error: Linearity error in the maximum deviation from a straight line passing through the endpoints of the a) End point test after zero and FS adjust b) Shifting FS adjust to pass best straight line test TL/H/5691 – 3 4 Application Hints The DAC1218 and DAC1219 are pin-for-pin compatible with the DAC1220 series but feature 12 and 11-bit linearity specifications. To preserve this degree of accuracy, care must be taken in the selection and adjustments of the output amplifier and reference voltage. Careful PC board layout is important, with emphasis made on compactness of components to prevent inadvertent noise pickup and utilization of single point grounding and supply distribution. 2.0 CREATING A UNIPOLAR OUTPUT VOLTAGE (A DIGITAL ATTENUATOR) To generate an output voltage and keep the potential at the current output terminals at 0V, an op amp current to voltage converter is used. As shown in Figure 2 , the current from IOUT1 flows through the feedback resistor, forcing a proportional voltage at the amplifier output. The voltage at IOUT1 is held at a virtual ground potential. The feedback resistor is provided on the chip and should always be used as it matches and tracks the R value of the R-2R ladder. The output voltage is the opposite polarity of the applied reference voltage. 1.0 BASIC CIRCUIT DESCRIPTION Figure 1 illustrates the R-2R current switching ladder network used in the DAC1218 and DAC1219. As a function of the logic state of each digital input, the binarily weighted current in each leg of the ladder is switched to either IOUT1 or IOUT2. The voltage potential at IOUT1 and IOUT2 must be at zero volts to keep the current in each leg the same, independent of the switch state. The switches operate with a small voltage drop across them and can therefore conduct currents of either polarity. This permits the reference to be positive or negative, thereby allowing 4-quadrant multiplication by the digital input word. The reference can be a stable DC source or a bipolar AC signal within the range of g 10V, for specified accuracy, with an absolute maximum range of g 25V. The reference can also exceed the applied VCC of the DAC. The maximum output current from either IOUT1 or IOUT2 is equal to VREF(max) 4095 , R 4096 where R is the reference input resistance (typically 15 kX). A high level on any digital input steers current to IOUT1 and a low level steers current to IOUT2. # 2.1 Amplifier Considerations To maintain linearity of the output voltage with changing digital input codes the input offset voltage of the amplifier must be nulled. The resistance from IOUT1 to ground (RIOUT1) varies non-linearly with the applied digital code from a minimum of R with all ones applied to the input to near % with an all zeros code. Any offset voltage between the amplifier inputs appears at the output with a gain of RF . RIOUT1 Since RIOUT1 varies with the input code, any offset will degrade output linearity. (See Note 4 of Electrical Characteristics.) If the desired amplifier does not have offset balancing pins available (it could be part of a dual or quad package) the nulling circuit of Figure 3 can be used. The voltage at the non-inverting input will be set to b VOS initially to force the inverting input to 0V. The common technique of summing current into the amplifier summing junction cannot be used as it directly introduces a zero code output current error. 1a J TL/H/5691 – 4 Note: Switches shown in digital high state. FIGURE 1. The R-2R Current Switching Ladder Network 5 Application Hints (Continued) VOUT e b VREF #2 A1 a A2 A3 A12 a a... 4 8 4096 where: AN e 1 if digital input is high J TL/H/5691 – 5 AN e 0 if digital input is low FIGURE 2. Unipolar Output Voltage TL/H/5691 – 6 FIGURE 3. Zeroing an Amplifier Which Does Not Have Balancing Provisions The selected amplifier should have as low an input bias current as possible since input bias current contributes to the current flowing through the feedback resistor. BI-FETTM op amps such as the LF356 or LF351 or bipolar op amps with super b input transistors like the LM11 or LM308A produce negligible errors. 2.3 Output Settling Time The output voltage settling time for this circuit in response to a change of the digital input code (a full-scale change is the worst case) is a combination of the DAC’s output current settling characteristics and the settling characteristics of the output amplifier. The amplifier settling is further degraded by a feedback pole formed by the feedback resistance and the DAC output capacitance (which varies with the digital code). First order compensation for this pole is achieved by adding a feedback zero with capacitor CC shown in Figure 2 . In many applications output response time and settling is just as important as accuracy. It can be difficult to find a single op amp that combines excellent DC characteristics (low VOS, VOS drift and bias current) with fast response and settling time. BI-FET op amps offer a reasonable compromise of high speed and good DC characteristics. The circuit of Figure 4 illustrates a composite amplifier connection that combines the speed of a BI-FET LF351 with the excellent DC input characteristics of the LM11. If output settling time is not so critical, the LM11 can be used alone. 2.2 Zero and Full-Scale Adjustments The fundamental purpose is to make the output voltages as near 0 VDC as possible. This is accomplished in the circuit of Figure 2 by shorting out the amplifier feedback resistance, and adjusting the VOS nulling potentiometer of the op amp until the output reads zero volts. This is done, of course, with an applied digital input of all zeros if IOUT1 is driving the op amp (all ones for IOUT2). The feedback short is then removed and the converter is zero adjusted. A unique characteristic of these DACs is that any full-scale or gain error is always negative. This means that for a fullscale input code the output voltage, if not inherently correct, will always be less than what it should be. This ensures that adding an appropriate resistance in series with the internal feedback resistor, RFb, will always correct for any gain error. The 50X potentiometer in Figure 2 is all that is needed to adjust the worst case DAC gain error. Conversion accuracy is only as good as the applied reference voltage, so providing a source that is stable over time and temperature is important. Figure 5 is a settling time test circuit for the complete voltage output DAC circuit. The circuit allows the settling time of the DAC amplifier to be measured to a resolution of 1 mV out of a zero to g 10V full-scale output change on an oscilloscope. Figure 6 summarizes the measured settling times for several output amplifiers and feedback compensation capacitors. 6 Application Hints (Continued) TL/H/5691 – 7 FIGURE 4. Composite Output Amplifier Connection Diodes are 1N4148 TL/H/5691 – 8 FIGURE 5. DAC Settling Time Test Circuit Amplifier CC Settling Time to 0.01% LM11 LF351 LF351 Composite LM11-LF351 LF356 20 pF 15 pF 30 pF 30 ms 8 ms 5 ms 20 pF 8 ms 15 pF 6 ms FIGURE 6. Some Measured Settling Times 7 Application Hints (Continued) where D is the decimal equivalent of the true binary input word. This configuration inherently accepts a code (halfscale or D e 2048) to provide 0V out without requiring an external (/2 LSB offset as needed by other bipolar multiplying DAC circuits. Only the offset voltage of amplifier A1 need be nulled to preserve linearity. The gain setting resistors around A2 must match and track each other. A thin film, 4-resistor network available from Beckman Instruments, Inc. (part no. 694-3R10K-D) is ideally suited for this application. Two of the four resistors can be paralleled to form R and the other two can be used separately as the resistors labeled 2R. Operation is summarized in the table below: 3.0 OBTAINING A BIPOLAR OUTPUT VOLTAGE FROM A FIXED REFERENCE The addition of a second op amp to the circuit of Figure 2 can generate a bipolar output voltage from a fixed reference voltage (Figure 7 ). This, in effect gives sign significance to the MSB of the digital input word to allow two quadrant multiplication of the reference voltage. The polarity of the reference voltage can also be reversed to realize full 4-quadrant multiplication. The output responds in accordance to the following expression: VO e VREF MSB 1 1 1 0 0 0 1 1 0 1 1 0 # J D b 2048 , 0 s D s 4095 2048 . . Applied Digital Input . . . 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 Where 1 LSB e 1 0 0 1 0 0 1 0 0 1 0 0 . . . 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 LSB 1 0 0 1 0 0 1 0 0 1 0 0 Decimal Equivalent a VREF VOUT b VREF 4095 3072 2048 2047 1024 0 VREFb1 LSB VREF/2 0 b 1 LSB b VREF/2 b VREF b VREF a 1 LSB b VREF /2 l l l 0 a 1 LSB a l VREF l /2 a l VREF l lVREFl 2048 *0.1% matching TL/H/5691 – 9 FIGURE 7. Obtaining a Bipolar Output from a Fixed Reference 8 Application Hints (Continued) 4.0 MISCELLANEOUS APPLICATION HINTS The devices are CMOS products and reasonable care should be exercised in handling them to prevent catastrophic failures due to electrostatic discharge. During power-up supply voltage sequencing, the negative supply of the output amplifier may appear first. This will typically cause the output of the op amp to bias near the negative supply potential. No harm is done to the DAC, however, as the on-chip 15 kX feedback resistor sufficiently limits the current flow from IOUT1 when this lead is clamped to one diode drop below ground. As a general rule, any unused digital inputs should be tied high or low as required by the application. As a troubleshooting aid, if any digital input is left floating, the DAC will interpret that input as a logical 1 level. 3.1 Zero and Full-Scale Adjustments The three adjustments needed for this circuit are shown in Figure 7 . The first step is to set all of the digital inputs LOW (to force IOUT1 to 0) and then trim ‘‘zero adjust’’ for zero volts at the inverting input (pin 2) of OA1. Next, with a code of all zeros still applied, adjust ‘‘- full-scale adjust’’, the reference voltage, for VOUT e g l(ideal VREF)l. The sign of the output voltage will be opposite that of the applied reference. Finally, set all of the digital inputs HIGH and adjust ‘‘ a fullscale adjust’’ for VOUT e VREF (511/512). The sign of the output at this time will be the same as that of the reference voltage. This a full-scale adjustment scheme takes into account the effects of the VOS of amplifier A2 (as long as this offset is less than 0.1% of VREF) and any gain errors due to external resistor mismatch. Additional Application Ideas For the circuits shown, D represents the decimal equivalent of the binary digital input code. D ranges from 0 (for an all zeros input code) to 4095 (for an all ones input code) and for any code can be determined from: D e 2048(A1) a 1024(A2) a 512(A2) a . . . 2(A11) a 1(A12) where AN e 1 if that input is high AN e 0 if that input is low DAC Controlled Amplifier TL/H/5691 – 10 9 Additional Application Ideas (Continued) Offsetting the Zero Code Output Voltage VZero Shift e 2VREFR2 R1 a R2 TL/H/5691 – 11 High Current Controller IO e 1 Amp (D) 4096 TL/H/5691 – 12 10 Additional Application Ideas (Continued) DAC Controlled Function Generator # C1 controls maximum frequency # k 0.5% sine wave THD over range # Range 30 kHz maximum # LinearityÐDAC limit #fe D 4096 (4/3 RFb C) TL/H/5691 – 13 Digitally Programmable Pulse-Width Generator PW j C(7.5V) (4096) (RFb) D l VREF TL/H/5691 – 14 11 DAC1218/DAC1219 12-Bit Binary Multiplying D/A Converter Physical Dimensions inches (millimeters) Order Number DAC1218LCJ-1, DAC1218LCJ or DAC1219LCJ NS Package Number J18A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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