APEX Signal, A Division of NAI, Inc. VME-64SD1 SIXTEEN (16) SYNCHRO/RESOLVER-to-DIGITAL TWO-SPEED or SINGLE-SPEED or COMBINATION ( PROGRAMMABLE) ON-BOARD PROGRAMMABLE REFERENCE SUPPLY TO COMMERCIAL OR MILITARY SPECIFICATIONS • • • • • • • • • • • • • • • • • • • • • • 16-bit resolution (optional 24 bits combined) ±1 arc-minute accuracy Continuous background BIT testing with Reference and Signal loss detection Self-calibrating. Does not require removal for calibration 50 Hz to 10 kHz operation Tracking rate to 150 RPS 16, 12, 8, 4 and 2-channel versions available Programmable 2-speed ratios: 2 to 255 Power-On Self-Test (POST) Accurate Digital Velocity outputs Optional programmable encoder (A & B) plus index outputs Optional equivalent Hall Effect (A, B, C) commutation outputs Optional on-board programmable reference supply Watchdog timer and soft reset Angle change alert Transformer isolated Synthetic reference compensates for ±60° phase shift Optional conduction cooling with wedgelocks I/O via front panel, P2 or both Latch feature No adjustments or trimming required Part number, S/N, Date Code and Revision in permanent memory DESCRIPTION: This high density intelligent DSP-based card incorporates up to sixteen (16) single-speed or eight (8) two-speed transformer isolated Synchro/Resolver-to-Digital tracking converters with extensive diagnostics, digital velocity outputs, angle change alert, and optional programmable reference supply. Any combination of two-speed and single-speed channels can be field programmed to any ratio between 2 and 255. Each channel also produces differential (A & B) incremental encoder outputs (with programmable resolution) and a zero degree marker pulse. Alternatively, commutation outputs are available for 4, 6, or 8 pole brushless DC motors that eliminate the need for Hall Effect sensors on the motor, thus eliminating processor time and reducing bus traffic. For 2-speed usage, ambiguity circuits maintain monotonic outputs by compensating for misalignment between the Coarse and Fine Synchros. However, the processor will set a flag when it senses that the maximum allowable misalignment of 90°/gear ratio is exceeded. This card, even when large accelerations are encountered, never looses tracking, because it incorporates the unique capability to automatically shift to higher bandwidths. The shifting is smooth and continuous with no glitches. Tracking rates are only limited to bandwidth restrictions, up to 150 RPS, at 16-bit resolution. The LATCH feature permits the user to read all channels at the same time. Reading will unlatch that channel. The angle alert monitors each channel for the programmed angle difference and sets an interrupt as soon as that threshold is reached. Thus, no polling of the angle registers is required until an angle has reached the specified difference. The use of Type II servo loop processing techniques enables tracking, at full accuracy, up to the specified rate. A step input will not cause any hang-up condition. Intermediate transparent latches, on all angle and velocity outputs, assure that valid data is always available without interrupts or waiting time. Our synthetic reference compensates for ±60° phase shifts, thus eliminating the need for individual compensation networks. Each channel can be specified for a different voltage or frequency. A watchdog timer is provided to monitor the processor. Part number, S/N, Date Code and Revision are stored in permanent memory. This board can operate over a "C" or "M" operating temperature range (see part number). The "C" version (0°C to +70°C) uses standard high quality commercial semiconductors. The "M" version (-55°C to +85°C), used for severe environmental conditions, uses high quality extended temperature semiconductors. Conduction cooling, using a thermal plane and wedge locks, can be specified in the part number. Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 2-05-01 Code:OVGU1 S 64 SD1 A001 REV A 1.4 Page 1 of 9 This board incorporates major diagnostics that offer substantial improvements to system reliability, because the user is alerted to channel malfunction. This approach reduces bus traffic, because the Status Registers need not be constantly polled. Three different tests, one on-line and two off-line, can be selected: The (D2) Test initiates automatic background BIT testing. Each channel is checked every 5° to a testing accuracy of 0.05° and each Signal and Reference is always monitored. Any failure triggers an Interrupt (if enabled) and the results are available in Status Registers. The testing is totally transparent to the user, requires no external programming, has no effect on the standard operation of the card, and can be enabled or disabled via the bus. The (D3) Test initiates a BIT test that disconnects all channels from the outside world and connects them across an internal stimulus that generates and tests 72 different angles to a test accuracy of 0.05°. Results can be read from registers and external reference is not required. Any failure triggers an Interrupt (if enabled). The testing requires no external programming, and can be initiated or stopped via the bus. The (D0) Test is used to check the card and the VME interface. All channels are disconnected from the outside world, allowing the user to write any number of input angles to the card and then to read the data from the interface. External reference is not required. Power-On Self-Test (POST): When enabled and saved, POST will initiate the D3 Test upon power-on. SPECIFICATIONS: Resolution: 16 bits (up to 24 bits optional for two-speed configuration) Accuracy: ±1 arc-minute for single speed inputs ±1 arc-minute divided by the gear ratio for two-speed inputs VME Data transfer: Data transfers within 200 ns. Tracking Rate: 18.5 RPS max. at 60 Hz; 150 RPS max. above 400 Hz. Referred to Fine input in a twospeed configuration Bandwidth: Normal is 10 Hz at 60 Hz; 40 Hz at 400 Hz, and 100 Hz above 1 kHz. Can be readily customized Input format: Synchro or Resolver, (see part number) Gear ratio: Each channel pair is programmable from 2 to 255 Input voltage: Resolver: 2-28 VL-L Autoranging, 90 VL-L ; Synchro: 11.8 VL-L , 90 VL-L Resolver and Synchro are Transformer isolated Input Impedance: 40 kΩ min. up to 28 VL-L , 100 kΩ min. at 90 VL-L Reference: 2-28 Vrms, Autoranging or 115 Vrms. Transformer isolated. Reference Zin 100 kΩ min. Frequency: 50 Hz to 10 kHz (see part number) Encoder outputs: Either 12,13,14,15, or 16-bit resolution, (field programmable) and Index marker. 12-bit resolution is equivalent to 1,024 cycles (4,096 transitions) etc. Differential outputs. The encoder resolution is fixed and does not change with speed. (Optional, see P/N). Commutation outputs: Equivalent to the A, B, C outputs from Hall Effect Sensors for 4, 6 or 8 pole motors Angle change alert: Each channel can be set to a different angle differential. When that differential is exceeded, an interrupt (if enabled) is triggered. Default: “Ch. Disabled”. MSB=180°; Min. differential is 0.05°. Max differential that can be programmed is 179.9 degrees. Phase shift: The synthetic reference circuit automatically compensates for phase shifts between the transducer excitation and output up to ±60°. Velocity, Digital: 16-bit resolution; Linearity: 0.1%. Scalable to 0.1°/sec resolution. Wrap around Self Test: The three different powerful test methods are detailed in the Description section and further described in the Programming Instructions. Interrupts: One Interrupt capability is implemented. One of seven priority lines can be specified. Power: + 5 VDC: 0.350 A for 16 channels; ±12 VDC: 0.08 A without Reference; .600 A with 5 VA out. Temperature, operating: "C" 0°C to +70°C; "M" -55°C to +85°C (see part number) Storage temperature: -55°C to +105°C. Conformal coating: Both sides of the board can be conformal coated (see part number). Burn-in: All “M” boards are burned in for 24 hours and cycled from -55°C to +85°C. Size: 6U (9.2") height, 4HP (0.8") width. 233.4 mm x 20.3 mm x 160 mm deep Weight: 22 oz. Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 2-05-01 Code:OVGU1 S 64 SD1 A001 REV A 1.4 Page 2 of 9 REFERENCE: Voltage: Frequency: Regulation: Output power: Optional. (see part number). 2.0-28 Vrms programmable (resolution 0.1 Vrms) or 115 Vrms fixed. Accuracy ±2%. 360 Hz to 10 kHz ±1% with 1 Hz resolution. 10% max. No load to full load. 5 VA max. at 40° min. inductive. PROGRAMMING INSTRUCTIONS: This card offers many options. Any option that is not required may be ignored. For ease of use, all channels are referred to as 1 to 16. For two-speed applications, we generally refer to Coarse and Fine inputs. Therefore, channel 1 becomes 1 Coarse, channel 2 becomes 1 Fine, channel 3 becomes 2 Coarse, etc. I/O CONFIGURATION: The VMEbus interface will respond to A32:D16, A24:D16 and A16:D16 DTB cycles. A32 mode: Unit responds to address modifiers 0A, 0D, 0E and 09. Base address can be set anywhere in the 4 Gigabyte address space on 256 byte boundaries (Standard), or 512 byte boundaries, when offset addresses above 100 are enabled. A24 mode: Responds to address modifiers 3A, 3D, 3E and 39. Base address can be set anywhere in the 16 Megabyte address space on 256 byte boundaries (Standard), or 512 byte boundaries, when offset addresses above 100 are enabled A16 mode: Responds to address modifiers 2A, 2D, 2E and 29. Base address can be set anywhere in the 64 K byte address space on 256 byte boundaries (Standard), or 512 byte boundaries, when offset addresses above 100 are enabled. Note: Address switch A8 must be set to "ON" (logic 0) for 512 byte boundaries. Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 2-05-01 Code:OVGU1 S 64 SD1 A001 REV A 1.4 Page 3 of 9 ADDRESS = BASE + OFFSET 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 Ch.1 read Ch.2 (Hi) read Ch.3 read Ch.4 (Hi) read Ch.5 read Ch.6 (Hi) read Test read/write Status, Sig. read Ch.7 read Ch.8 (Hi) read Latch write Ch.9 read Ch.10 (Hi) read Status, Ref read Vel.1 read Vel.2 read Vel.3 read Vel.4 read Vel.5 read Vel.6 read Vel.7 read Vel.8 read Vel.9 read Vel.10 read Vel.11 read Vel.12 read Test ∠ write Ch.11 read Ch.12 (Hi) read Freq. read/write Eo read/write Part # read Serial # read Date code read 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 7A 7C 7E 80 82 84 86 Rev level read Status, Test, read Active channels, read/write Save read/write Test (D2) verify read/write Interrupt priority read/write Interrupt vector 1 read/write Interrupt vector 2 read/write Ratio Ch 2/ Ch 1 read/write Ratio Ch 4/ Ch 3 read/write Ratio Ch 6/ Ch 5 read/write Ratio Ch 8/ Ch 7 read/write Ratio Ch 10/ Ch 9 read/write Ratio Ch 12/ Ch 11 read/write Ratio Ch 14/ Ch 13 read/write Ratio Ch 16/ Ch 15 read/write Ch.13 read Ch.14 (Hi) read Ch.15 read Ch.16 (Hi) read Vel.13 read Vel.14 read Vel.15 read Vel.16 read Angle ∆ Ch.1 read/write Angle ∆ Ch.2 read/write Angle ∆ Ch.3 read/write Angle ∆ Ch.4 read/write Angle ∆ Ch.5 read/write Angle ∆ Ch.6 read/write Angle ∆ Ch.7 read/write Angle ∆ Ch.8 read/write Angle ∆ Ch.9 read/write Angle ∆ Ch.10 read/write 88 8A 8C 8E 90 92 94 96 98 9A 9C 9E A0 A2 A4 A6 A8 AA AC AE B0 B2 B4 B6 B8 BA BC BE C0 C2 C4 C6 C8 CA Angle ∆ Ch.11 Angle ∆ Ch.12 Angle ∆ Ch.13 Angle ∆ Ch.14 Angle ∆ Ch.15 Angle ∆ Ch.16 Angle ∆ initiate Angle change alert (A & B) res. Ch.1 (A & B) res. Ch.2 (A & B) res. Ch.3 (A & B) res. Ch.4 (A & B) res. Ch.5 (A & B) res. Ch.6 (A & B) res. Ch.7 (A & B) res. Ch.8 (A & B) res. Ch.9 (A & B) res. Ch.10 (A & B) res. Ch.11 (A & B) res. Ch.12 (A & B) res. Ch.13 (A & B) res. Ch.14 (A & B) res. Ch.15 (A & B) res. Ch.16 (A&B) or A,B,C, Ch.1 (A&B) or A,B,C, Ch.2 (A&B) or A,B,C, Ch.3 (A&B) or A,B,C, Ch.4 (A&B) or A,B,C, Ch.5 (A&B) or A,B,C, Ch.6 (A&B) or A,B,C, Ch.7 (A&B) or A,B,C, Ch.8 (A&B) or A,B,C, Ch.9 (A&B) or A,B,C, Ch.10 read/write read/write read/write read/write read/write read/write read/write read read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write CC CE D0 D2 D4 D6 D8 DA DC DE E0 E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE 102 104 106 108 10A 10C 10E 110 (A&B) or A,B,C, Ch.11 (A&B) or A,B,C, Ch.12 (A&B) or A,B,C, Ch.13 (A&B) or A,B,C, Ch.14 (A&B) or A,B,C, Ch.15 (A&B) or A,B,C, Ch.16 Velocity, scale Ch.1 Velocity, scale Ch.2 Velocity, scale Ch.3 Velocity, scale Ch.4 Velocity, scale Ch.5 Velocity, scale Ch.6 Velocity, scale Ch.7 Velocity, scale Ch.8 Velocity, scale Ch.9 Velocity, scale Ch.10 Velocity, scale Ch.11 Velocity, scale Ch.12 Velocity, scale Ch.13 Velocity, scale Ch.14 Velocity, scale Ch.15 Velocity, scale Ch.16 (POST) test enable Two speed lock loss Watchdog timer Soft reset Ch.2 (Lo) ! Ch.4 (Lo) ! Ch.6 (Lo) ! Ch.8 (Lo) ! Ch.10 (Lo) ! Ch.12 (Lo) ! Ch.14 (Lo) ! Ch.16 (Lo) ! read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read read/write write read read read read read read read read ! Optional registers for 2-speed, extended resolution. (see Part Number) D15 D14 180 90 Data°° (Hi) .00274 .00137 Data°° (Lo) Test Enable X X Status, Test Ch.1 Ch.2 Status, Reference Ch.1 Ch.2 Status, Signal Ch.1 Ch.2 Angle change alert Ch.1 Ch.2 Active channels Ch.1 Ch.2 Two-speed lock X Ch1/2 (A & B) resolution X X D13 45 .00068 X Ch.3 Ch.3 Ch.3 Ch.3 Ch.3 X X D12 22.5 .00034 X Ch.4 Ch.4 Ch.4 Ch.4 Ch.4 Ch3/4 X D11 D10 D9 D8 D7 D6 11.25 5.625 2.813 1.406 .703 .352 .00017 .00008 .00004 .00002 X X X X X X X X Ch.5 Ch.6 Ch.7 Ch.8 Ch.9 Ch.10 Ch.5 Ch.6 Ch.7 Ch.8 Ch.9 Ch.10 Ch.5 Ch.6 Ch.7 Ch.8 Ch.9 Ch.10 Ch.5 Ch.6 Ch.7 Ch.8 Ch.9 Ch.10 Ch.5 Ch.6 Ch.7 Ch.8 Ch.9 Ch.10 X Ch5/6 X Ch7/8 X 9/10 X X X X X X Commutation outputs D5 .176 X X Ch.11 Ch.11 Ch.11 Ch.11 Ch.11 X X D4 .088 X X Ch.12 Ch.12 Ch.12 Ch.12 Ch.12 11/12 X 4 6 8 Encoder outputs Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 2-05-01 Code:OVGU1 D3 .044 X D3 Ch.13 Ch.13 Ch.13 Ch.13 Ch.13 X X 16 bit 15 bit 14 bit 13 bit 12 bit D2 .022 X D2 Ch.14 Ch.14 Ch.14 Ch.14 Ch.14 13/14 D2 0 0 0 0 1 D1 D0 .011 .0055 X X X D1 Ch.15 Ch.16 Ch.15 Ch.16 Ch.15 Ch.16 Ch.15 Ch.16 Ch.15 Ch.16 X 15/16 D1 D0 0 0 0 1 1 0 1 1 0 0 S 64 SD1 A001 REV A 1.4 Page 4 of 9 At Power-ON or System Reset, all parameters are restored to last saved setup and, if POST is enabled, a D3 Test is initiated. Enter Active Channels: Set the bit corresponding to each channel to be monitored during BIT testing in the Active Channel Register at 48h. “1”=active; “0”=not used. Omitting this step will produce false alarms, because unused channels will set faults. Save Setup: The current setup can be saved by writing 5555h to the Save Register at 4Ah. This location will automatically clear to 0000h when the save is completed (within 5 seconds). When save is elected, all parameters are saved. However, any parameter can be changed at will. Saving is optional. If not saved, reenter parameters at each power up. To restore factory shipped parameters, write AAAAh to the Save Register at 4Ah, followed by System Reset. Note: After a SAVE or RESTORE, poll 4Ah and do not perform any other operation until word is at "0". Read: For single-speed applications (Ratio=1), read individual channels: 1, 2, 3, 4 etc. For two-speed applications, read only channels (2, 4, 6, 8, etc.) for the combined output. For resolution up to 24-bit, read Hi word, then Lo word. Hi word, when read, latches Lo word. 24 bit resolution, along with carrier frequency etc., will determine how many of the 16 channels are available…consult factory for specifics. Latch: All channels may be latched by writing “1” to D1 of Latch Register at 14h. Reading channel will disengage latch for that channel. Ratio: Enter the desired ratio, as a binary number, in the Ratio Register corresponding to the pair of channels to be used for a two-speed channel. Example: Single speed = 1; 36:1 = 100100. Two-Speed Lock-Loss: When two Synchros are geared to each other, either electrically or mechanically, in order to achieve higher accuracy, the misalignment of the Coarse and Fine Synchros must not exceed 90°/gear ratio or the digital angle output may not be valid. Should this problem occur, with a given channel pair, the corresponding bit in the Two-Speed Lock-Loss Register at FAh will be set to “0”. Velocity Scale Factor: To scale the Max Velocity word for 150 RPS set Velocity Scale Factor = 4095 in HEX (max velocity word of 7FFFh being max. CW rotation, and 8000h being max. CCW rotation. Scaling effects only the Velocity output word and not the dynamic performance. Ex: To get max. velocity word @ 150 rps: 4095(150/150) = 4095 (0FFFh) This is also the Factory setting. To get max. velocity word @ 50 rps. 4095(150/50) = 12,285 (2FFDh) To get max. velocity word @ 9.375rps. 4095(150/9.375) = 65,520 (FFF0h) This is also the lowest setting Velocity Output: Read Velocity Registers of each channel as a 2’s complement word, with 7FFFh being maximum CW rotation, and 8000h being maximum CCW rotation. When max. velocity is set to 150 RPS, an actual speed of 10 RPS CW would be read as 0888h. When max. velocity is set to 150 RPS, an actual speed of 10 RPS CCW would be read as F778h. When max. velocity is set to 50 RPS, an actual speed of 10 RPS CW would be read as 1999h. When max. velocity is set to 50 RPS, an actual speed of 10 RPS CCW would be read as E667h. To convert a velocity word (for example E667h) into RPS: If maximum velocity, set to 50 RPS, then RPS = 50 x E667h / 32,768 = 50 x -6,553 / 32,768 = -10 RPS Power-On Self-Test (POST): Will initiate the D3 Test upon power-on, if POST is enabled and saved. Enable by writing "1" to POST Register at F8h. Disable by writing "0" at F8h and then save setup. D2 Test Enable: Writing “1” to D2 of Test Register at 0Ch initiates automatic background BIT testing that checks each channel every 5° to a test accuracy of 0.05° and monitors each Signal and Reference. An Interrupt (if enabled) will be set to indicate an accuracy problem or Signal or Reference loss and the results are available in Status Registers (Signal or Reference loss within 2 sec, accuracy within 45 sec). A “0” deactivates this test. The testing is totally transparent to the user, requires no external programming, has no effect on the standard operation of this card and can be enabled or disabled. Card will (every 30 seconds) write 55h at address 4Ch when D2 is enabled. User can periodically clear to 0000h and then read 4Ch again, after 30 seconds, to verify that background BIT testing is activated. Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 2-05-01 Code:OVGU1 S 64 SD1 A001 REV A 1.4 Page 5 of 9 D3 Test Enable: Writing “1” to D3 of Test Register at 0Ch, initiates a BIT test that disconnects all channels from the outside world and connects them across an internal stimulus that generates and tests 72 different angles to a test accuracy of 0.05°. External reference is not required. Test cycle is completed within 45 seconds and results can be read from the Status Registers. D3 changes from “1” to “0” when test is complete. A failure will trigger an Interrupt (if enabled). The testing requires no external programming, and can be initiated by writing "1" at D3 or terminated by writing "0" at D3. D0 Test Enable: Checks card and VME interface. Writing “1” to D0 of Test Register at 0Ch disconnects all channels from the outside world, enabling user to write any number of angles to the card at 34h. Data is then read from the VME interface (after writing, allow 400 ms before reading). Test accuracy to be <.05°. Disable by setting D0 to “0”. Upon writing “1”, the default test angle of D0 is 30°. External reference is not required. (ex. 330°=1110101010101011). Status, Test: Check the corresponding bit of the Test Status Register at 46h, for status of BIT testing for each active channel. A ”1” means Accuracy OK; “0” means failed. (test cycle takes 45 seconds for accuracy error). Status, Ref: Check the corresponding bit of the Ref Status Register at 1Ah, for status of the reference input for each active channel. A ”1” =Ref. ON, “0” = Ref. Loss. (Reference loss is detected after 2 seconds). Status, Sig: Check the corresponding bit of the Sig Status Register at 0Eh, for status of the input signals for each active channel. A "1" = Signal ON, “0” = Signal loss. (Signal loss is detected after 2 seconds). Interrupt: Enter requirements into 4Eh as an 8-bit binary number. 0= no interrupt; 1-7 indicates priority levels. Any error will latch Status Register and trigger an Interrupt. When Interrupt is acknowledged, additional errors will set another Interrupt. Reading will unlatch registers. Now, let us consider what happens when a status bit changes before registers are read. For example, if a reference loss was detected and latched into registers and subsequent scans find that the reference was reconnected, then this status change will be held in background until registers are read. Within 250ms registers will be updated with the background data. Allow 250 ms to scan all channels. Interrupt Vector 1: Write 8-bit word (0-255). Used for failure reports. Interrupt Vector 2: Write 8-bit word (0-255). Used for angle change alert reports. Angle Change Alert: Write a 16-bit word to each channel, to represent the minimum differential required. MSB=180°; minimum differential is 0.05°. Setting to zero disables the Angle Change Alert for a given channel. Initiate monitoring by writing “1” to Angle Change Initiate Register at 94h. When that differential is exceeded, on any monitored channel, an interrupt is generated. Read Angle Change Alert Flag Register at 96h for status of each channel ("0" = no change, "1" = change) Soft Reset: (Level sensitive): Writing a “1” to FEh initiates and holds software in reset state. Then, writing “0” initiates reboot (takes 400 ms). Status Registers cleared; Watchdog Timer functional; Failure bit at "0"; Saved parameters remain saved; Angle outputs held at last update; Interrupts disabled. Watchdog Timer: This feature monitors the Watchdog Timer Register (FCh). When it detects that a code has been received, that code will be inverted within 100 µSec. The inverted code stays in the register until replaced by a new code. User, after 100 µSec, should look for the inverted code to confirm that the processor is operating. Optional Reference Supply: For frequency, write a 16-bit word (Ex: 400 Hz = 1 1001 0000) to address 3A. For voltage, write a word (Ex: 26.1 Vrms =1 0000 0101) with LSB=0.1 Vrms, to address 3C. It is recommended that user program the required frequency before setting the output voltage. Optional (A&B) Encoder Resolution: Enter required resolution, for each channel, per above table. Can be changed on the fly. Also set corresponding [(A&B) or A, B, C] register to “0”. Encoder/Commutation outputs are optional, see part ordering information. Default is 12-bit encoder mode. Optional Commutation Outputs (A,B,C): Set channels that should produce commutation outputs to “1” in the appropriate [(A&B) or A, B, C] register. Then, set the required motor poles (per above table) in the equivalent (A&B) resolution registers. Encoder/Commutation outputs are optional, see part ordering information. Serial Number: At 40h, is read as a 16-bit binary word. Date Code: Read as a decimal number at 42h. The four digits represent YYWW (Year,Year,Week.Week) Rev: At 44h. 15 14 13 Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 12 11 10 9 8 7 6 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 5 4 3 2 2-05-01 Code:OVGU1 1 0 S 64 SD1 A001 REV A 1.4 Page 6 of 9 Example 0 0 0 0 DSP Rev 1.1 1 1 0 0 0 0 FPGA Rev 3 1 1 0 0 PC Rev 0 1 1 Front panel Connectors: J1: DC37P; Mate: DC37S (not supplied) 37 36 19 18 35 17 34 33 16 S1 S3 S2 S4 RHi RLo S1 S3 S2 Ch. 1 Ch. 1 Ch. 1 Ch. 1 Ch. 1 Ch. 1 Ch. 2 Ch. 2 Ch. 2 15 32 14 31 30 13 12 29 11 S4 RHi RLo S1 S3 S2 S4 RHi RLo Ch. 2 Ch. 2 Ch. 2 Ch. 3 Ch. 3 Ch. 3 Ch. 3 Ch. 3 Ch. 3 28 27 10 9 26 8 25 24 7 S1 S3 S2 S4 RHi RLo S1 S3 S2 J2: DC37P; Mate: DC37S (not supplied) Ch. 4 6 S4 Ch. 5 Ch. 4 23 RHi Ch. 5 Ch. 4 5 RLo Ch. 5 Ch. 4 22 S1 Ch. 6 Ch. 4 21 S3 Ch. 6 Ch. 4 4 S2 Ch. 6 Ch. 5 3 S4 Ch. 6 Ch. 5 20 RHi Ch. 6 Ch. 5 2 RLo Ch. 6 1 Chassis 37 36 19 18 35 17 34 33 16 S1 S3 S2 S4 RHi RLo S1 S3 S2 Ch. 7 Ch. 7 Ch. 7 Ch. 7 Ch. 7 Ch. 7 Ch. 8 Ch. 8 Ch. 8 15 32 14 31 30 13 12 29 11 S4 RHi RLo S1 S3 S2 S4 RHi RLo Ch. 8 Ch. 8 Ch. 8 Ch. 9 Ch. 9 Ch. 9 Ch. 9 Ch. 9 Ch. 9 28 27 10 9 26 8 25 24 7 S1 S3 S2 S4 RHi RLo S1 S3 S2 Ch.10 6 S4 Ch.11 Ch.10 23 RHi Ch.11 Ch.10 5 RLo Ch.11 Ch.10 22 S1 Ch.12 Ch.10 21 S3 Ch.12 Ch.10 4 S2 Ch.12 Ch.11 3 S4 Ch.12 Ch.11 20 RHi Ch.12 Ch.11 2 RLo Ch.12 1 Chassis J3: DB25P; Mate: DB25S Pin Pin Pin 1 S1 Ch.13 14 S4 Ch.13 4 S1 Ch.14 2 S3 Ch.13 15 RHi Ch.13 5 S3 Ch.14 3 S2 Ch.13 16 RLo Ch.13 6 S2 Ch.14 Pin Pin Pin Pin Pin Pin 17 S4 Ch.14 7 S1 Ch.15 20 S4 Ch.15 10 S1 Ch.16 23 S4 Ch.16 13 Chassis 18 RHi Ch.14 8 S3 Ch.15 21 RHi Ch.15 11 S3 Ch.16 24 RHi Ch.16 19 RLo Ch.14 9 S2 Ch.15 22 RLoCh.15 12 S2 Ch.16 25 RLo Ch.16 P2 Connector: Uses a 5 row 160 pin connector Pin 18c 22c 20c 24c 29c 27c 10c 14c 12c 16c 30c 28c 25c 32c 26c 31c 28a Designation S1 Ch. 1 S3 Ch. 1 S2 Ch. 1 S4 Ch. 1 RHi Ch. 1 RLo Ch. 1 S1 Ch. 2 S3 Ch. 2 S2 Ch. 2 S4 Ch. 2 RHi Ch. 2 RLo Ch. 2 S1 Ch. 3 S3 Ch. 3 S2 Ch. 3 S4 Ch. 3 RHi Ch. 3 Pin Designation 30a RLo Ch. 3 18a S1 Ch. 4 22a S3 Ch. 4 20a S2 Ch. 4 24a S4 Ch. 4 27a RHi Ch. 4 29a RLo Ch. 4 10a S1 Ch. 5 14a S3 Ch. 5 12a S2 Ch. 5 16a S4 Ch. 5 21c RHi Ch. 5 23c RLo Ch. 5 25a S1 Ch. 6 32a S3 Ch. 6 26a S2 Ch. 6 31a S4 Ch. 6 Pin 21a 23a 11a 15a 13a 17a 8a 9a 11c 15c 13c 17c 6a 7a 1c 2c 3c S4 pins are used only with Resolvers. Designation Pin Designation RHi Ch. 6 4c S4 Ch. 9 RLo Ch. 6 1a RHi Ch. 9 S1 Ch. 7 2a RLo Ch. 9 S3 Ch. 7 5c S1 Ch. 10 S2 Ch. 7 6c S3 Ch. 10 S4 Ch. 7 7c S2 Ch. 10 RHi Ch. 7 8c S4 Ch. 10 RLo Ch. 7 3a RHi Ch. 10 S1 Ch. 8 4a RLo Ch. 10 S3 Ch. 8 3d S1 Ch. 11 S2 Ch. 8 4d S3 Ch. 11 S4 Ch. 8 5d S2 Ch. 11 RHi Ch. 8 6d S4 Ch. 11 RLo Ch. 8 7d RHi Ch. 11 S1 Ch. 9 8d RLo Ch. 11 S3 Ch. 9 9d S1 Ch. 12 S2 Ch. 9 10d S3 Ch. 12 Pin 11d 12d 13d 14d 15d 16d 17d 18d 19d 20d 21d 22d 23d 24d 25d 26d 27d Designation S2 Ch. 12 S4 Ch. 12 RHi Ch. 12 RLo Ch. 12 S1 Ch. 13 S3 Ch. 13 S2 Ch. 13 S4 Ch. 13 RHi Ch. 13 RLo Ch. 13 S1 Ch. 14 S3 Ch. 14 S2 Ch. 14 S4 Ch. 14 RHi Ch. 14 RLo Ch. 14 S1 Ch. 15 Pin 28d 29d 30d 5z 7z 9z 11z 13z 15z 17z 19z 19a 19c Designation S3 Ch. 15 S2 Ch. 15 S4 Ch. 15 RHi Ch. 15 RLo Ch. 15 S1 Ch. 16 S3 Ch. 16 S2 Ch. 16 S4 Ch. 16 RHi Ch. 16 RLo Ch. 16 Int. Ref. Output Hi Int. Ref. Output Lo Do not connect to any undesignated pins. NOTE: P2 is always active P0 Connector: Only supplied when (A & B) outputs are specified 1e 1d 1a 1b 1c 2c 2b 2a 2d 2e 3e 3d 3a 3b 3c 4c Ch.1 A Hi Ch.1 A Lo Ch.1 B Hi Ch.1 B Lo Ch.1 Index Hi Ch.1 Index Lo Ch.2 A Hi Ch.2 A Lo Ch.2 B Hi Ch.2 B Lo Ch.2 Index Hi Ch.2 Index Lo Ch.3 A Hi Ch.3 A Lo Ch.3 B Hi Ch.3 B Lo 4b 4a 4d 4e 5e 5d 5a 5b 5c 6c 6b 6a 6d 6e 7e 7d Ch.3 Index Hi Ch.3 Index Lo Ch.4 A Hi Ch.4 A Lo Ch.4 B Hi Ch.4 B Lo Ch.4 Index Hi Ch.4 Index Lo Ch.5 A Hi Ch 5 A Lo Ch.5 B Hi Ch.5 B Lo Ch.5 Index Hi Ch.5 Index Lo Ch.6 A Hi Ch.6 A Lo 7a 7b 7c 8c 8b 8a 8d 8e 9e 9d 9a 9b 9c 10c 10b 10a Ch.6 B Hi Ch.6 B Lo Ch.6 Index Hi Ch.6 Index Lo Ch.7 A Hi Ch.7 A Lo Ch.7 B Hi Ch.7 B Lo Ch.7 Index Hi Ch.7 Index Lo Ch.8 A Hi Ch.8 A Lo Ch.8 B Hi Ch.8 B Lo Ch.8 Index Hi Ch.8 Index Lo 10d 10e 11e 11d 11a 11b 11c 12c 12b 12a 12d 12e 13e 13d 13a 13b Ch.9 A Hi Ch.9 A Lo Ch.9 B Hi Ch.9 B Lo Ch.9 Index Hi Ch.9 Index Lo Ch.10 A Hi Ch.10 A Lo Ch.10 B Hi Ch.10 B Lo Ch.10 Index Hi Ch.10 Index Lo Ch.11 A Hi Ch.11 A Lo Ch.11 B Hi Ch.11 B Lo 13c 14c 14b 14a 14d 14e 15e 15d 15a 15b 15c 16c 16b 16a 16d 16e Ch.11 Index Hi Ch.11 Index Lo Ch.12 A Hi Ch.12 A Lo Ch.12 B Hi Ch.12 B Lo Ch.12 Index Hi Ch.12 Index Lo Ch.13 A Hi Ch.13 A Lo Ch.13 B Hi Ch.13 B Lo Ch.13 Index Hi Ch.13 Index Lo Ch.14 A Hi Ch.14 A Lo 17e 17d 17a 17b 17c 18c 18b 18a 18d 18e 19e 19d 19a 19b P2-1z P2-3z Ch.14 B Hi Ch.14 B Lo Ch.14 Index Hi Ch.14 Index Lo Ch.15 A Hi Ch.15 A Lo Ch.15 B Hi Ch.15 B Lo Ch.15 Index Hi Ch.15 Index Lo Ch.16 A Hi Ch.16 A Lo Ch.16 B Hi Ch.16 B Lo Ch.16 Index Hi Ch.16 Index Lo NOTE: For commutation (A,B,C) outputs: A Hi becomes A, B Hi becomes B, and Index Hi becomes C. Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 2-05-01 Code:OVGU1 S 64 SD1 A001 REV A 1.4 Page 7 of 9 The board contains two green LED's (D8 & D9) that are for factory use only. Both will be ON during normal operation. Miniature test connector, JP2 is used to download programming data and JP3 is a ground. Do not interface to these two connectors unless factory instructed to be used for field modification. Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 2-05-01 Code:OVGU1 S 64 SD1 A001 REV A 1.4 Page 8 of 9 Resolver: 2-28 VL-L Autoranging, 90 VL-L Synchro: 11.8 VL-L , 90 VL-L Code Table Code Input (VL-L) Ref (Vrms) 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 50 11.8 90 90 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 90 11.8 2-26 3 26 26 115 115 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 2-26 115 115 26 2-26 6 26 51 52 53 Frequency (Hz) Notes 400 400 50/400 400 800 1000 1200 1600 2000 2500 3000 4000 5000 6500 7000 10000 400 400 400 6000 2950 400 This code is available for card with a maximum of 12 channels This code is available for card with a maximum of 12 channels This code is available for card with a maximum of 12 channels This code is available for card with a maximum of 12 channels This code is available for card with a maximum of 6 channels Channel 1 to Channel 4 Channel 5 to Channel 8 This code is available for card with a maximum of 12 channels 2 chan r/d w/special software for ref loss detection Special synchro L/L Contact factory for other combinations. IMPORTANT: Tracking rate and bandwidth can easily be customized to meet your specific requirements. Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 2-05-01 Code:OVGU1 S 64 SD1 A001 REV A 1.4 Page 9 of 9 PART NUMBER DESIGNATION 64SD1- XX X X X X - XX CODE (See Code Table) TOTAL NUMBER OF CHANNELS(*) 02 – 2 S/D Channels 04 – 4 S/D Channels 08 – 8 S/D Channels 12 – 12 S/D Channels 16 – 16 S/D Channels ENVIRONMENTAL C = 0°C to +70°C M = -55°C to +85°C H = M With Removable Conformal Coating J = M With Permanent Conformal Coating K = C With Removable Conformal Coating OPTIONS With On-Board Reference: 1 = One Common Reference Input Tied to On-Board Reference Supply 2 = Individual Reference Inputs 3 = One Common Reference Input Tied to On-Board Reference Supply; Programmable Encoder (A & B) and Index/Commutation 4 = Individual Reference Inputs; Programmable Encoder (A & B) and Index/Commutation Without On-Board Reference: 5 = One Common Reference Input 6 = Individual Reference Inputs 7 = One Common Reference Input; Programmable Encoder (A & B) and Index/Commutation 8 = Individual Reference Inputs; Programmable Encoder (A & B) and Index/Commutation FORMAT S = Synchro R = Resolver M = Mixed (See Code Table) (*) Number of 24 bit channels is dependant upon carrier frequency etc…consult factory for specifics Custom Design: 9 = Custom Design (See Separate Spec) MECHANICAL F = Front Panel I/O and P2 I/O P = P2 I/O only W = P With Wedgelocks V = VME64 Front Panel I/O Apex Signal, A Division of NAI, Inc. 170 Wilbur Place, Bohemia, NY, 11716,USA 631.567.1100/631.567.1823(fax) www.naii.com / e-mail:[email protected] 2-05-01 Code:OVGU1 S 64 SD1 A001 REV A 1.4 Page 10 of 9