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KT133 - VT8363
VIA VT8363
KT133 AMD ATHLON™ NORTH BRIDGE
Single-Chip North Bridge
for Socket-A (Socket-462) Based Athlon CPUs
with 200 MHz Front Side Bus
for Desktop PC Systems
with AGP 4x and PCI
plus Advanced Memory Controller
supporting PC133 / PC100 SDRAM and VCM
• High Performance and High Integration Athlon AGP 4x / PC133 Chipset with Advanced System
Power Management
− KT133 Chipset: VT8363 system controller and VT82C686A PCI to ISA bridge
− Single chip Athlon system controller with 64-bit Socket-A Athlon CPU, 64-bit system memory, 32-bit PCI and 32bit AGP interfaces
− PCI-to-ISA bridge chip includes UltraDMA-33/66 EIDE, 4 USB Ports, Integrated Super-I/O, AC97 / MC97 link (for
−
−
Audio and Modem support), Hardware Monitoring, Power Management, and Keyboard / PS2-Mouse Interfaces plus
RTC / CMOS on chip
Supports separately powered 3.3V (5V tolerant) interface to system memory, AGP, and PCI bus
Modular power management and clock control for advanced system power management
• High Performance Athlon CPU Interface
− Supports Socket-A (Socket-462) AMD Athlon processors
− HSTL-like 1.5V high-speed transceiver logic signal levels
− Support independent address, data, and snoop interfaces
− 100 MHz DDR (Double Data Rate) transfer on Athlon CPU address and data buses
− Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions
− Four-entry command queue to accommodate maximum CPU throughput
− Four-entry probe queue to stores probes from the system to the processor
− Twenty four-entry processor system data and control queue to store system data control commands in two separate
read and write buffers for data movement in and out of processor interface
− Supports WC (Write Combining) cycles
− Sleep mode support
− System management interrupt, memory remap and STPCLK mechanism
Preliminary Revision 1.0, May 12, 2000
-1-
Features
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KT133 - VT8363
• Full Featured Accelerated Graphics Port (AGP) Controller
− Synchronous and pseudo-synchronous with the host CPU bus with optimal skew control
−
−
−
−
−
−
−
−
−
−
−
PCI
AGP
CPU
Mode
33 MHz 66 MHz 100 MHz DDR 3x synchronous
AGP v2.0 compliant
Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)
Supports 66 MHz 1x, 2x and 4x modes for AD and SBA signaling
Pipelined split-transaction long-burst transfers up to 1GB/sec
Thirty-two level read request queue
Four level posted-write request queue
Thirty-two level (quadwords) read data FIFO (256 bytes)
Sixteen level (quadwords) write data FIFO (128 bytes)
Intelligent request reordering for maximum AGP bus utilization
Supports Flush/Fence commands
Graphics Address Relocation Table (GART)
− One level TLB structure
− Sixteen entry fully associative page table
− LRU replacement scheme
− Windows 95 OSR-2 VXD and integrated Windows 98 / Windows 2000 miniport driver support
• Concurrent PCI Bus Controller
− PCI buses are synchronous / pseudo-synchronous to host CPU bus
− 33 MHz operation on the primary PCI bus
− 66 MHz PCI operation on the AGP bus
− PCI-to-PCI bridge configuration on the 66MHz PCI bus
− Supports up to five PCI masters
− Peer concurrency
− Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
− Zero wait state PCI master and slave burst transfer rate
− PCI to system memory data streaming up to 132Mbyte/sec
− Two lines (32 double-words) of CPU to PCI posted write buffers
− Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
− Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
− Thirty-two levels (double-words) of post write buffers from PCI masters to DRAM
−
−
−
−
−
−
−
(two cache lines / 16 double-words for PCI bus, two cache lines / 16 double-words for Athlon processor interface)
Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
Delay transaction from PCI master accessing DRAM
Read caching for PCI master reading DRAM
Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
Symmetric arbitration between Host/PCI bus for optimized system performance
Complete steerable PCI interrupts
PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
Preliminary Revision 1.0, May 12, 2000
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Features
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KT133 - VT8363
• Advanced High-Performance DRAM Controller
− Supports PC133 and PC100 SDRAM and Virtual Channel Memory (VCM) SDRAM up to 3 DIMMs
− Concurrent CPU, AGP, and PCI access
− Different DRAM types may be used in mixed combinations
− Different DRAM timing for each bank
− Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems
− Mixed 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs
− Support up to 1.5 GB memory space (256Mb DRAM technology)
− Flexible row and column addresses
− 64-bit data width and 3.3V DRAM interface
− Programmable I/O drive capability for MA, command, and MD signals
− Two-bank interleaving for 16Mbit SDRAM support
− Two-bank and four bank interleaving for 64Mbit SDRAM support
− Supports maximum 16-bank interleave (i.e., 16 pages open simultaneously); banks are allocated based on LRU
− Independent SDRAM control for each bank
− Seamless DRAM command scheduling for maximum DRAM bus utilization
−
−
−
−
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−
−
(e.g., precharge other banks while accessing the current bank)
Four cache lines (32 quadwords) of CPU to DRAM write buffers
Four cache lines (32 quadwords) of CPU to DRAM read prefetch buffers
Read around write capability for non-stalled CPU read
Burst read and write operation
BIOS shadow at 16KB increment
Decoupled and burst DRAM refresh with staggered RAS timing
CAS before RAS or self refresh
• Advanced System Power Management Support
− Dynamic power down of SDRAM (CKE)
− PCI and AGP bus clock run and clock generator control
− VTT suspend power plane preserves memory data
− Suspend-to-DRAM and Self-Refresh operation
− SDRAM self-refresh power down
− 8 bytes of BIOS scratch registers
− Low-leakage I/O pads
• Built-in NAND-tree pin scan test capability
• 3.3V, 0.35um, high speed / low power CMOS process
• 35 x 35 mm, 552 pin BGA Package
Preliminary Revision 1.0, May 12, 2000
-3-
Features
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KT133 - VT8363
OVERVIEW
PROCRDY
CONNECT
CFWDRST
The KT133 / VT8363 and VT82C686A chipset is a high performance, cost-effective and energy efficient system controller for
the implementation of AGP / PCI / ISA desktop personal computer systems based on 64-bit Socket-A (AMD Athlon) processors.
3D
Graphics
Controller
Athlon
Host CPU
Address
Out
GCLK
AGP Bus
GCKRUN#
PCKRUN#
PCLK
PCI Bus
BIOS ROM
ATA 33 / 66
USB Ports 0-3
AC97 Audio Codec
AC97
Link
MC97 Modem Codec
ISA Bus
RTC
Crystal
Data
SYSCLK, SYSCLK#
INTR, NMI, SMI#, STPCLK#,
IGNNE#, FERR#, A20M#,
PWROK, INIT#, RESET#
In
CKE
KT133
VT8363
North Bridge
552 BGA
Memory Bus
SDRAM
MCLK
HCLK
PCLK
Clock
Buffer
SUSCLK,
SUSST1#
Super
South
VT82C686A
South Bridge
352 BGA
CPUSTP#
PCISTP#
Clock
Generator
SMBus
Power Plane & Peripheral Control
GPIO and ACPI Events
Hardware Monitoring Inputs
Keyboard / PS2 Mouse
Serial Ports 1 and 2
Parallel Port
Floppy Drive Interface
MIDI / Game Ports
Figure 1. KT133 System Block Diagram Using the VT82C686A South Bridge
The KT133 chip set consists of the VT8363 system controller (552 pin BGA) and the VT82C686A PCI to ISA bridge (352 pin
BGA). The system controller provides superior performance between the CPU, DRAM, AGP bus, and PCI bus with pipelined,
burst, and concurrent operation.
The VT8363 supports eight banks of DRAMs up to 1.5 GB. The DRAM controller supports standard Synchronous DRAM
(SDRAM) and Virtual Channel SDRAM (VC SDRAM), in a flexible mix / match manner. The Synchronous DRAM interface
allows zero wait state bursting between the DRAM and the data buffers at 66/100/133 MHz. The six banks of DRAM can be
composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs.
The VT8363 system controller also supports full AGP v2.0 capability for maximum bus utilization including 1x, 2x and 4x mode
transfers, SBA (SideBand Addressing), Flush/Fence commands, and pipelined grants. An eight level request queue plus a four
level post-write request queue with thirty-two and sixteen quadwords of read and write data FIFO's respectively are included for
deep pipelined and split AGP transactions. A single-level GART TLB with 16 full associative entries and flexible CPU / AGP /
PCI remapping control is also provided for operation under protected mode operating environments. Both Windows-95 VXD and
Windows-98 / Windows 2000 miniport drivers are supported for interoperability with major AGP-based 3D and DVD-capable
multimedia accelerators.
The VT8363 supports two 32-bit 3.3 / 5V system buses (one AGP and one PCI) that are synchronous / pseudo-synchronous to the
CPU bus. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five levels
(doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation, fortyeight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent
PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line, Memory-
Preliminary Revision 1.0, May 12, 2000
-4-
Overview
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KT133 - VT8363
Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are supported
such as snoop ahead, snoop filtering, L1/L2 write-back forward to PCI master, and L1/L2 write-back merged with PCI post write
buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also
implemented for further improvement of overall system performance.
The 352-pin Ball Grid Array VT82C686A PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA
transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.1 compliant). The VT82C686A also includes an
integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 256 byte CMOS
RAM, integrated master mode enhanced IDE controller with full scatter / gather capability and extension to UltraDMA-33/66 for
33/66 MB/sec transfer rate, integrated USB interface with root hub and four function ports with built-in physical layer transceivers,
Distributed DMA support, and OnNow / ACPI compliant advanced configuration and power management interface. The
VT82C686A also includes an AC97 / MC97 link for interface to external audio and modem codecs, and all “Super-I/O” functions
(serial ports, parallel port, and floppy drive interface and game port).
For sophisticated power management, KT133 provides independent clock stop control for the CPU / SDRAM, PCI, and AGP
buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for the
SDRAM control signals for Suspend-to-DRAM operation. The VT82C686A also includes a complete hardware monitoring
subsystem for monitoring and control of internal and external (motherboard and system) conditions including voltages,
temperatures, fan speeds, switch open/close states, etc. Coupled with the VT82C686A south bridge chip, a complete power
conscious PC main board can be implemented with no external TTLs.
The KT133 chipset is ideal for high performance, high quality, high energy efficient and high integration desktop AGP / PCI / ISA
computer systems.
Preliminary Revision 1.0, May 12, 2000
-5-
Overview
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KT133 - VT8363
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ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Ambient operating temperature
0
55
oC
Case operating temperature
0
110
oC
Storage temperature
-55
125
oC
Input voltage
-0.5
5.5
Volts
Output voltage (VCC = 3.1 - 3.6V)
-0.5
VCC + 0.5
Volts
Note: Stress above the conditions listed may cause permanent damage to the
device. Functional operation of this device should be restricted to the
conditions described under operating conditions.
DC Characteristics
TA-0-55oC, VCC=5V+/-5%, GND=0V
Symbol
Parameter
Min
Max
Unit
VIL
Input low voltage
-0.50
0.8
V
Condition
VIH
Input high voltage
2.0
VCC+0.5
V
VOL
Output low voltage
-
0.45
V
IOL=4.0mA
VOH
Output high voltage
2.4
-
V
IOH=-1.0mA
IIL
Input leakage current
-
+/-10
uA
0<VIN<VCC
IOZ
Tristate leakage current
-
+/-20
uA
0.45<VOUT<VCC
ICC
Power supply current
-
mA
AC Timing Specifications
AC timing specifications provided are based on external zero-pf capacitance load. Min/max cases are based on the following table:
Table 8. AC Timing Min / Max Conditions
Parameter
Min
Max
Unit
3.3V Power (VCC, VCCI, VTT, AVCC, HVCC)
3.135
3.465
Volts
5V Reference (5VREF)
4.75
5.25
0
70
Volts
oC
Temperature
Drive strength for each output pin is programmable. See Rx6D for details.
Preliminary Revision 1.0, May 12, 2000
-46-
Electrical Specifications
'HOLYHULQJ 9DOXH
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7HFKQRORJLHV ,QF
MECHANICAL SPECIFICATIONS
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Figure 5. Mechanical Specifications - 552-Pin Ball Grid Array Package
Preliminary Revision 1.0, May 12, 2000
-47-
Mechanical Specifications