W24512A 64K × 8 HIGH SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W24512A is a high speed, low power CMOS static RAM organized as 65536 × 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology. FEATURES • • High speed access time: 15/20/25/35 nS (max.) • All inputs and outputs directly TTL compatible Low power consumption: • Three-state outputs − Active: 500 mW (typ.) • Available packages: 32-pin 300 mil SOJ, skinny DIP, 450 mil SOP, and standard type one TSOP • Single +5V power supply • Fully static operation PIN CONFIGURATIONS BLOCK DIAGRAM V DD A11 A9 A8 A13 WE CS2 A15 V DD NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC 1 32 V DD NC 2 31 A15 A14 3 30 CS2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A1 0 A1 11 22 CS1 A0 12 21 I/O8 I/O1 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 VSS 16 17 I/O4 32-pin TSOP V SS A0 . . DECODER CORE C O RE ARRAY A15 CS2 CS1 OE WE CONTROL DATA I/O I/O1 . . I/O8 PIN DESCRIPTION 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SYMBOL A0−A15 I/O1−I/O8 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 V SS I/O3 I/O2 I/O1 A0 A1 A2 A3 -1- CS1, CS2 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs WE OE VDD VSS NC Write Enable Input Output Enable Input Power Supply Ground No Connection Publication Release Date: March 1999 Revision A7 W24512A TRUTH TABLE CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L MODE VDD CURRENT I/O1−I/O8 High Z High Z High Z Data Out Data In Not Selected Not Selected Output Disable Read Write ISB, ISB1 ISB, ISB1 IDD IDD IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature RATING -0.5 to +7.0 -0.5 to VDD +0.5 1.0 -65 to +150 UNIT V V W 0 to +70 °C Operating Temperature °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C) PARAMETER Input Low Voltage Input High Voltage Input Leakage Current SYM. VIL VIH ILI TEST CONDITIONS VIN = VSS to VDD MIN. -0.5 +2.2 -10 TYP. - MAX. +0.8 VDD +0.5 +10 UNIT V V µA Output Leakage Current ILO VI/O = VSS to VDD -10 - +10 µA Output Low Voltage Output High Voltage Operating Power VOL VOH IDD CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL IOL = +8.0 mA IOH = -4.0 mA 15 CS1 = VIL, CS2 = VIH 2.4 - - 0.4 200 V V mA - - 160 160 140 30 mA - - 10 mA Supply Current Standby Power Supply Current I/O = 0 mA, Cycle = min. Duty = 100% 20 25 35 ISB CS1 = VIH or CS2 = VIL Cycle = min., Duty = 100% ISB1 CS1 ≥ VDD -0.2V or CS2 ≤ 0.2V Note: Typical characteristics are at VDD = 5V, TA = 25° C. -2- W24512A CAPACITANCE (VDD = 5V, TA = 25° C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 8 pF Input/Output Capacitance CI/O VOUT = 0V 10 pF Note: These parameters are sampled but not 100% tested. THERMAL RESISTANCE PARAMETER SYM. CONDITIONS MAX. UNIT Junction to Case Thermal Resistance θJC A. F. R. = 1m/sec, TA = 25° C 20 °C/W Junction to Ambient Thermal Resistance θJA A. F. R. = 1m/sec, TA = 25° C 60 °C/W Note: These parameters are only applied to "TSOP" and "SOJ" package types. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA AC Test Loads and Waveform R1 480 ohm R1 480 ohm 5V 5V OUTPUT 5 pF OUTPUT 30 pF Including Jig and Scope Including Jig and Scope R2 255 ohm R2 255 ohm (For TCLZ1, TCLZ2, TOLZ, TCHZ1,TCHZ2, TOHZ, TWHZ, TOW ) 3.0V 90% 10% 0V 90% 10% 5 nS 5 nS -3- Publication Release Date: March 1999 Revision A7 W24512A AC Characteristics, continued (VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C) Read Cycle PARAMETER SYM. W24512A-15 W24512A-25 W24512A-25 W24512A-35 UNIT MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Read Cycle Time TRC 15 - 20 - 25 - 35 - nS Address Access Time TAA - 15 - 20 - 25 - 35 nS CS1 TACS1 - 15 - 20 - 25 - 35 nS CS2 TACS2 - 15 - 20 - 25 - 35 nS TAOE - 7 - 10 - 12 - 17 nS CS1 TCLZ1* 3 - 3 - 3 - 3 - nS CS2 TCLZ2* 3 - 3 - 3 - 3 - nS TOLZ* 0 - 0 - 0 - 0 - nS Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in CS1 TCHZ1* - 7 - 10 - 12 - 17 nS High Z CS2 TCHZ2* - 7 - 10 - 12 - 17 nS Output Disable to Output in High Z TOHZ* - 7 - 1 - 12 - 17 nS Output Hold from Address Change TOH 3 - 3 - 3 - 3 - nS * These parameters are sampled but not 100% tested. Write Cycle PARAMETER SYM. W24512A-15 W24512A-25 W24512A-25 W24512A-35 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT Write Cycle Time TWC 15 - 20 - 25 - 35 - nS Chip Selection to End of Write CS1 TCW1 13 - 17 - 18 - 20 - nS CS2 TCW2 13 - 17 - 18 - 20 - nS Address Valid to End of Write TAW 13 - 17 - 18 - 20 - nS Address Setup Time TAS 0 - 0 - 0 - 0 - nS Write Pulse Width TWP 10 - 12 - 15 - 18 - nS Write Recovery Time CS1, WE TWR1 0 - 0 - 0 - 0 - nS CS2 TWR2 0 - 0 - 0 - 0 - nS Data Valid to End of Write TDW 9 - 10 - 12 - 15 - nS Data Hold from End of Write TDH 0 - 0 - 0 - 0 - nS Write to Output in High Z TWHZ* - 8 - 10 - 12 - 15 nS Output Disable to Output in High Z TOHZ* - 8 - 10 - 12 - 15 nS Output Active from End of Write TOW 0 - 0 - 0 - 0 - nS * These parameters are sampled but not 100% tested. -4- W24512A TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TOH TAA TOH D OUT Read Cycle 2 (Chip Select Controlled) CS1 TACS1 TCHZ1 TACS2 CS2 TCHZ2 TCLZ1 D OUT TCLZ2 Read Cycle 3 (Output Enable Controlled) TRC Address TAA OE TAOE TOH TOLZ CS1 TACS1 TCLZ1 CS2 TCHZ1 T ACS2 TCLZ2 TCHZ2 TOHZ D OUT -5- Publication Release Date: March 1999 Revision A7 W24512A Timing Waveforms, continued Write Cycle 1 (OE Clock) T WC Address TWR1 OE TCW1 CS1 CS2 TCW2 TAW WE TWR2 TWP TAS TOHZ (1, 4) D OUT TDW TDH D IN Write Cycle 2 (OE = VIL Fixed) TWC Address TCW1 TWR1 CS1 TCW2 CS2 TAW WE TWR2 T WP TAS TOH TWHZ (1, 4) TOW (2) (3) D OUT TDW TDH D IN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24512A ORDERING INFORMATION PART NO. ACCESS TIME (nS) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (mA) PACKAGE W24512AK-15 15 200 10 300 mil skinny DIP W24512AK-20 20 160 10 300 mil skinny DIP W24512AK-25 25 160 10 300 mil skinny DIP W24512AK-35 35 140 10 300 mil skinny DIP W24512AJ-15 15 200 10 300 mil SOJ W24512AJ-20 20 160 10 300 mil SOJ W24512AJ-25 25 160 10 300 mil SOJ W24512AJ-35 35 140 10 300 mil SOJ W24512AS-15 15 200 10 450 mil SOP W24512AS-20 20 160 10 450 mil SOP W24512AS-25 25 160 10 450 mil SOP W24512AS-35 35 140 10 450 mil SOP W24512AT-15 15 200 10 standard type one TSOP W24512AT-20 20 160 10 standard type one TSOP W24512AT-25 25 160 10 standard type one TSOP W24512AT-35 35 140 10 standard type one TSOP Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -7- Publication Release Date: March 1999 Revision A7 W24512A PACKAGE DIMENSIONS 32-pin SOJ Symbol 17 32 E 1 He 16 Dimension in Inches Dimension in mm Max. Min. Nom. __ __ 0.140 __ __ 0.095 0.100 0.105 B 0.026 0.028 b c 0.016 0.008 D E e e1 Min. Nom. A __ __ A1 A2 0.020 3.556 __ 2.413 2.540 2.667 0.032 0.660 0.711 0.813 0.018 0.022 0.406 0.457 0.010 0.014 0.203 0.254 0.356 0.815 0.825 0.835 20.701 20.955 21.209 0.295 0.300 0.305 7.493 7.620 7.747 0.044 0.050 0.056 1.118 1.270 1.422 0.247 0.267 0.287 6.274 6.782 7.290 He 0.325 0.080 __ 0.345 __ 8.255 L 0.335 __ 8.509 __ __ 0.045 __ 0.004 S Y θ __ __ 0 2.032 __ __ __ 10 __ __ 0° D A2 c A L e1 B S e A1 b θ Y Seating Plane 32-pin SO Wide Body Symbol A A1 A2 b c D E e HE L LE S y θ 17 32 e1 E E H L Detail F 1 b 16 Dimension in Inches Min. Nom. Max. Dimension in mm Min. Nom. 0.004 0.10 0.101 0.106 0.014 0.016 0.006 Max. 3.00 0.118 0.111 2.57 2.69 0.020 0.36 0.41 0.008 0.012 0.15 0.20 2.82 0.31 0.805 0.817 20.45 20.75 11.43 0.51 0.440 0.445 0.450 11.18 11.30 0.044 0.050 0.056 1.12 1.27 1.42 0.546 0.556 0.556 13.87 14.12 14.38 0.023 0.031 0.039 0.58 0.79 0.99 0.047 0.055 0.063 1.19 1.40 1.60 0.036 0.91 0.004 0 10 0.10 0 10 Notes: e1 D c 2 A A S Seating Plane y e 1 LE A See Detail F -8- Max. __ 0.508 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch . and are determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. 0.559 8.763 __ 1.143 0.102 10° W24512A Package Dimensions, continued 32-pin TSOP HD Dimension in Inches Dimension in mm Symbol D A c A1 M e E 0.10(0.004) b A2 A1 __ __ 0.047 Min. Nom. __ __ 0.006 0.05 Max. 1.20 __ 0.15 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.005 0.006 0.007 0.12 0.15 0.17 D 0.720 0.724 0.728 18.30 18.40 18.50 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.780 0.787 0.795 19.80 20.00 20.20 __ L L __ Max. A2 0.020 0.016 __ L1 θ Nom. 0.002 e A Min. 0.020 0.031 Y 0.000 θ 1 __ 3 __ __ 0.024 0.40 __ __ 0.004 0.00 5 1 __ 0.50 0.50 0.60 __ 0.80 __ 0.10 3 5 Y L1 Note: Controlling dimension: Millimeter 32-pin P-DIP Skinny (300 mil) Symbol A A1 A2 B B1 c D E E1 e1 L D 32 17 E1 1 16 Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 5.08 0.200 0.015 0.38 0.145 0.150 0.155 3.68 3.81 3.94 0.016 0.018 0.022 0.41 0.46 0.56 0.058 0.060 0.064 1.47 1.52 1.63 0.008 0.010 0.014 0.20 0.25 0.36 40.64 41.15 1.60 1.62 0.295 0.315 0.335 7.49 8.00 8.50 0.286 0.290 0.294 7.26 7.36 7.46 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 11.43 11.94 a 0 eA S 0.430 15 0.450 0.470 0.065 0° 10.92 15° 1.65 Notes: E S c Base Plane A1 A A2 L Mounting Plane B1 e1 a B -9- eA 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. Publication Release Date: March 1999 Revision A7 W24512A VERSION HISTORY VERSION DATE PAGE A7 Mar. 1999 - DESCRIPTION Arrange access time for 15/20/25/35 nS Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 10 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668