W29EE512 64K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29EE512 is a 512K bit, 5-volt only CMOS flash memory organized as 64K × 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29EE512 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES • Single 5-volt program and erase operations • Low power consumption − Active current: 50 mA (max.) • Fast page-write operations − Standby current: 100 µA (max.) − 128 bytes per page − Page program cycle: 10 mS (max.) − Effective byte-program cycle time: 39 µS − Optional software-protected data write • Automatic program timing with internal VPP generation • End of program detection − Toggle bit • Fast chip-erase operation: 50 mS • Read access time: 70/90/120 nS • Typical page program/erase cycles: 1K/10K • Ten-year data retention • Software and hardware data protection − Data polling • Latched address and data • TTL compatible I/O • JEDEC standard byte-wide pinouts • Available packages: 32-pin PLCC, TSOP and VSOP -1- Publication Release Date: February 18, 2002 Revision A7 W29EE512 PIN CONFIGURATIONS A 1 2 A 1 5 V N N C C C C 4 3 2 1 BLOCK DIAGRAM VDD VSS # W N E C 5 29 A14 A6 6 28 A13 27 A8 26 A9 A5 7 A4 8 #CE #OE 32 31 30 A7 32-pin PLCC A3 9 25 A11 A2 10 24 #OE A1 11 23 A10 A0 12 22 # CE DQ0 13 21 DQ7 A0 . D G Q N 2 D D Q 3 D Q 4 D Q 5 OUTPUT BUFFER #WE 14 15 16 17 18 19 20 D Q 1 DQ0 CONTROL D Q 6 DECODER . CORE ARRAY A15 #OE A11 A9 A8 A13 A14 NC 1 2 31 A10 3 30 #CE 4 5 29 #WE 7 VCC NC NC A15 A12 A7 A6 A5 A4 8 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 32 28 27 6 26 25 32-pin TSOP 9 10 24 23 11 12 22 21 20 13 14 19 15 18 17 16 PIN DESCRIPTION SYMBOL A11 A9 A8 A13 A14 NC 32 2 31 A10 3 30 # CE 4 29 5 28 6 27 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 #WE 7 VCC NC NC A15 A12 A7 A6 A5 A4 8 9 10 11 12 13 14 15 16 32-pin VSOP 26 25 24 23 22 2 1 20 1 9 1 8 17 A0 − A15 #OE 1 DQ0 − DQ7 Address Inputs Data Inputs/Outputs #CE Chip Enable #OE Output Enable #WE Write Enable VCC Power Supply GND Ground NC -2- PIN NAME No Connection . . DQ7 W29EE512 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29EE512 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details. Page Write Mode The W29EE512 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FFh" during programming of the page. The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE, whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200 µS, after the initial byte-load cycle, the W29EE512 will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer A7 to A15 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29EE512 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte program command cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is required. -3- Publication Release Date: February 18, 2002 Revision A7 W29EE512 Hardware Data Protection The integrity of the data stored in the W29EE512 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VCC Power Up/Down Detection: The programming and read operation are inhibited when VCC is less than 2.8V. (3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. Data Polling (DQ7)-Write Status Detection The W29EE512 includes a data polling feature to indicate the end of a programming cycle. When the W29EE512 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data. Toggle Bit (DQ6)-Write Status Detection In addition to data polling, the W29EE512 provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 5-Volt-only Software Chip Erase The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the device code (C8h). The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE high, and raising A9 to 12 volts. -4- W29EE512 TABLE OF OPERATING MODES Operating Mode Selection (Operating Range = 0 to 70° C (Ambient Temperature), VCC = 5V ±10%, VSS = 0V, VHH = 12V) MODE PINS #CE #OE #WE Read VIL VIL VIH AIN Dout Write VIL VIH VIL AIN Din Standby VIH X X X High Z X VIL X X High Z/DOUT X X VIH X High Z/DOUT X VIH X X High Z 5-Volt Software Chip Erase VIL VIH VIL AIN DIN Product ID VIL VIL VIH A0 = VIL; A1 − A15 = VIL; A9 = VHH Manufacturer Code DA (Hex) VIL VIL VIH A0 = VIH; A1 − A15 = VIL; A9 = VHH Device Code C8 (Hex) Write Inhibit Output Disable ADDRESS -5- DQ. Publication Release Date: February 18, 2002 Revision A7 W29EE512 Command Codes for Software Data Protection BYTE SEQUENCE TO ENABLE PROTECTION TO DISABLE PROTECTION ADDRESS DATA ADDRESS DATA 0 Write 5555H AAH 5555H AAH 1 Write 2AAAH 55H 2AAAH 55H 2 Write 5555H A0H 5555H 80H 3 Write - - 5555H AAH 4 Write - - 2AAAH 55H 5 Write - - 5555H 20H Software Data Protection Acquisition Flow Software Data Protection Enable Flow Load data AA to address 5555 (Optional page-load operation) Software Data Protection Disable Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data A0 to address 5555 Load data 80 to address 5555 Sequentially load up to 128 bytes of page data Pause 10 mS Exit Load data AA to address 5555 Load data 55 to address 2AAA Load data 20 to address 5555 Pause 10 mS Exit Notes for software program code: Data Format: DQ7 − DQ0 (Hex) Address Format: A14 − A0 (Hex) -6- W29EE512 Command Codes for Software Chip Erase BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Software Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 50 mS Exit Notes for software chip erase: Data Format: DQ7 − DQ0 (Hex) Address Format: A14 − A0 (Hex) -7- Publication Release Date: February 18, 2002 Revision A7 W29EE512 Command Codes for Product Identification BYTE SEQUENCE ALTERNATE SOFTWARE (5) PRODUCT IDENTIFICATION ENTRY ADDRESS DATA SOFTWARE PRODUCT IDENTIFICATION ENTRY ADDRESS SOFTWARE PRODUCT IDENTIFICATION EXIT DATA ADDRESS 0 Write 5555H AAH 5555H AAH 5555H DATA 1 Write 2AAAH 55H 2AAAH 55H 2AAAH 55H 2 Write 5555H 90H 5555H 80H 5555H F0H AAH 3 Write - - 5555H AAH - - 4 Write - - 2AAAH 55H - - 5 Write - - 5555H 60H - Pause 10 µS Pause 10 µS - Pause 10 µS Software Product Identification Acquisition Flow Product Identification Entry (1) Product Identification Mode (2,3) Product Identification Exit (1) Load data AA to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Read address = 0 data = DA Load data FO to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Read address = 1 data = C8 Pause 10 µS (4) Load data 60 to address 5555 Normal Mode Pause 10 µS Notes for software product identification: (1) Data format: DQ7 − DQ0 (Hex); address format: A14 − A0 (Hex). (2) A1 − A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns to standard operation mode. (5) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used. -8- W29EE512 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential except A9 -0.5 to VCC +1.0 V Transient Voltage (¡ Õ 20 nS) on Any Pin to Ground Potential -1.0 to VCC +1.0 V -0.5 to 12.5 V Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature Voltage on A9 and #OE Pin to Ground Potential Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VCC = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C) PARAMETER Power Supply Current SYM. ICC TEST CONDITIONS #CE = #OE = VIL, #WE = VIH, all I/Os open LIMITS UNIT MIN. TYP. MAX. - - 50 mA - 2 3 mA - 20 100 µA Address inputs = VIL/VIH, at f = 5 MHz Standby Vcc Current (TTL Input) ISB1 Standby Vcc Current (CMOS Input) ISB2 #CE = VIH, all I/Os open Other inputs = VIL/VIH #CE = VCC -0.3V, all I/Os open Other inputs = VCC -0.3V/GND Input Leakage Current ILI VIN = GND to VCC - - 10 µA Output Leakage Current ILO VIN = GND to VCC - - 10 µA Input Low Voltage VIL - - - 0.8 V Input High Voltage VIH - 2.0 - - V Output Low Voltage VOL - - 0.45 V Output High Voltage VOH1 IOH = -0.4 mA 2.4 - - V Output High Voltage CMOS VOH2 IOH = -100 µA; VCC = 4.5V 4.2 - - V IOL = 2.1 mA -9- Publication Release Date: February 18, 2002 Revision A7 W29EE512 Power-up Timing PARAMETER Power-up to Read Operation SYMBOL TPU.READ Power-up to Write Operation TPU.WRITE TYPICAL 100 5 UNIT µS mS CAPACITANCE (VCC = 5.0V, TA = 25° C, f = 1 MHz) PARAMETER I/O Pin Capacitance Input Capacitance SYMBOL CI/O CIN CONDITIONS VI/O = 0V VIN = 0V MAX. 12 6 AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time CONDITIONS 0V to 3V < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 100 pF/30 pF Input/Output Timing Level Output Load AC Test Load and Waveform +5V 1.8 Kohm D OUT 100 pF (For 90 nS/120 nS) 30 pF (For 70 nS) 1.3 Kohm Output Input 3V 1.5V 1.5V 0V Test Point Test Point - 10 - UNIT pF pF W29EE512 Read Cycle Timing Parameters (VCC = 5.0V ±10%, VCC = 5.0 ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. W29EE512-70 W29EE512-90 W29EE512-12 MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 70 - 90 - 120 - nS Chip Enable Access Time TCE - 70 - 90 - 120 nS Address Access Time TAA - 70 - 90 - 120 nS Output Enable Access Time TOE - 35 - 40 - 50 nS #CE High to High-Z Output TCHZ - 25 - 25 - 30 nS #OE High to High-Z Output TOHZ - 25 - 25 - 30 nS Output Hold from Address Change TOH 0 - 0 - 0 - nS Byte/Page-write Cycle Timing Parameters SYMBOL MIN. TYP. MAX. UNIT Write Cycle (Erase and Program) TWC - - 10 mS Address Setup Time TAS 0 - - nS Address Hold Time TAH 50 - - nS #WE and #CE Setup Time TCS 0 - - nS #WE and #CE Hold Time TCH 0 - - nS #OE High Setup Time TOES 0 - - nS #OE High Hold Time TOEH 0 - - nS #CE Pulse Width TCP 90 - - nS #WE Pulse Width TWP 90 - - nS #WE High Width TWPH 100 - - nS Data Setup Time TDS 35 - - nS Data Hold Time TDH 0 - - nS Byte Load Cycle Time TBLC - - 200 µS PARAMETER Notes: All AC timing signals observe the following guidelines for determining setup and hold times: (1) High level signal's reference level is VIH. (2) Low level signal's reference level is VIL. - 11 - Publication Release Date: February 18, 2002 Revision A7 W29EE512 #DATA Polling Characteristics (1) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Data Hold Time TDH 10 - - nS #OE Hold Time TOEH 10 - - nS #OE to Output Delay (2) TOE - - - nS Write Recovery Time TWR 0 - - nS MIN. TYP. MAX. UNIT Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. Toggle Bit Characteristics (1) PARAMETER SYMBOL Data Hold Time TDH 10 - - nS #OE Hold Time TOEH 10 - - nS #OE to Output Delay (2) TOE - - - nS #OE High Pulse TOEHP 150 - - nS Write Recovery Time TWR 0 - - nS Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. - 12 - W29EE512 TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A15-0 TCE #CE TO #OE E TOH VIH Z #WE TO TCH H DQ7-0 High-Z Z High-Z Data Valid Data Valid TAA #WE Controlled Write Cycle Timing Diagram T WC TAS TAH Address A15-0 #CE TCS TCH TOES T OEH #OE #WE TWPH TWP TDS DQ7-0 Data Valid TDH Internal write starts - 13 - Publication Release Date: February 18, 2002 Revision A7 W29EE512 Timing Waveforms, continued #CE Controlled Write Cycle Timing Diagram TAS TWC TAH Address A15-0 TCPH TCP #CE TOES TOEH #OE #WE TDS High Z DQ7-0 Data Valid TDH Internal write starts Page Write Cycle Timing Diagram TWC Address A15-0 DQ7-0 #CE #OE TWP TWPH TBLC #WE Byte 0 Byte 1 Byte 2 Byte N-1 Byte N Internal write starts - 14 - W29EE512 Timing Waveforms, continued #DATA Polling Timing Diagram Address A15-0 #WE #CE TOEH #OE TDH TWR HIGH-Z TOE DQ7 Toggle Bit Timing Diagram #WE #CE #OE TOEH TDH TOE HIGH-Z TWR DQ6 - 15 - Publication Release Date: February 18, 2002 Revision A7 W29EE512 Timing Waveforms, continued Page Write Timing Diagram Software Data Protection Mode Address A15-0 5555 DQ7-0 AA TWC Byte/page load cycle starts Three-byte sequence for software data protection mode 5555 2AAA 55 A0 #CE #OE TBLC TWP #WE TWPH Word 0 SW2 SW1 SW0 Word N-1 Word N (last word) Internal write starts Reset Software Data Protection Timing Diagram TWC Six-byte sequence for resetting software data protection mode Address A15-0 DQ7-0 5555 2AAA 55 AA 5555 5555 80 AA 2AAA 5555 55 20 SW4 SW5 #CE #OE TWP TBLC #WE TWPH SW0 SW1 SW2 SW3 Internal programming starts - 16 - W29EE512 Timing Waveforms, continued 5-Volt-only Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A15-0 DQ7-0 5555 AA 2AAA 5555 55 80 5555 AA TWC 2AAA 5555 55 10 SW4 SW5 #CE #OE TWP TBLC #WE TWPH SW0 SW1 SW2 SW3 Internal programming starts - 17 - Publication Release Date: February 18, 2002 Revision A7 W29EE512 ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VCC CURRENT MAX. (µA) PACKAGE CYCLE W29EE512P-70 70 50 100 32-pin PLCC 1K W29EE512P-90 90 50 100 32-pin PLCC 1K W29EE512P-12 120 50 100 32-pin PLCC 1K W29EE512T-70 70 50 100 Type one TSOP 1K W29EE512T-90 90 50 100 Type one TSOP 1K W29EE512T-12 120 50 100 Type one TSOP 1K W29EE512Q-70 70 50 100 Type one VSOP 1K W29EE512Q-90 90 50 100 Type one VSOP 1K W29EE512P-70B 70 50 100 32-pin PLCC 10K W29EE512P-90B 90 50 100 32-pin PLCC 10K W29EE512P-12B 120 50 100 32-pin PLCC 10K W29EE512T-70B 70 50 100 Type one TSOP 10K W29EE512T-90B 90 50 100 Type one TSOP 10K W29EE512T-12B 120 50 100 Type one TSOP 10K W29EE512Q-70B 70 50 100 Type one VSOP 10K W29EE512Q-90B 90 50 100 Type one VSOP 10K Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 18 - W29EE512 HOW TO READ THE TOP MARKING Example: The top marking of 32L-PLCC W29EE512P-70B W29EE512P-70B 2138977A-A12 149OBRA st 1 line: winbond logo nd 2 line: the part number: W29EE512P-70B rd 3 line: the lot number th 4 line: the tracking code: 149 O B RA 149: Packages made in ’01, week 49 O: Assembly house ID: A means ASE, O means OSE, ... etc. B: IC revision; A means version A, B means version B, ... etc. RA: Process code - 19 - Publication Release Date: February 18, 2002 Revision A7 W29EE512 PACKAGE DIMENSIONS 32-pin PLCC HE E 4 1 32 30 Symbol 5 A A1 A2 b1 b c D E e GD GE HD HE L y 29 GD D HD 21 13 14 c 20 Dimension In mm Dimension In Inches Min. Nom. Max. Min. Nom. Max. 0.140 0.020 0.105 3.56 0.50 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 11.35 11.43 11.51 0.447 0.450 0.453 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.510 0.530 12.45 12.95 13.46 0.390 0.410 0.430 9.91 10.41 10.92 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.490 0.495 12.32 12.45 12.57 0.090 0.095 1.91 2.29 2.41 0.075 0.004 θ 0° 10° 0.10 0° 10° Notes: L A2 θ Seating Plane e 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on fina visual inspection sepc. A A1 b b1 y GE 32-pin TSOP HD Dimension In mm Dimension In Inches Symbol D A c A1 M e E 0.10(0.004) b __ 0.002 __ 0.047 1.20 0.006 0.05 0.041 0.95 1.00 1.05 0.009 0.17 0.20 0.23 0.12 0.15 0.039 c 0.005 0.006 0.007 0.15 0.17 D 0.720 0.724 0.728 18.30 18.40 18.50 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.780 0.787 0.795 19.80 20.00 20.20 __ __ 0.024 0.40 __ __ __ 0.016 __ Y 0.000 A1 1 0.020 0.020 0.031 __ 3 0.004 0.00 5 1 Note: Controlling dimension: Millimeters - 20 - __ Max. 0.008 θ L1 Nom. __ 0.037 A2 Y __ Min. 0.007 L L __ Max. b L1 θ Nom. A2 e A Min. 0.50 0.50 0.80 __ 3 __ 0.60 __ 0.10 5 W29EE512 Package Dimensions, continued 32-pin VSOP HD Dimension In Inches Dimension In mm Symbol D A A A1 M e E Min. Nom. __ __ A1 0.002 Max. Min. Nom. __ __ 0.047 __ 0.006 0.05 0.15 __ Max. 1.20 0.15 b 0.006 0.008 0.010 0.20 0.25 D 0.484 0.488 0.492 12.30 12.40 12.50 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.543 0.551 0.559 13.80 14.00 14.20 __ __ 0.10(0.004) b e __ L 0.020 Y 0.004 θ 0 0.020 0.024 __ __ 0.028 0.50 0.008 0.10 5 0 0.50 0.60 __ __ __ 0.70 0.20 5 Note: Controlling dimension: Millimeters θ Y L - 21 - Publication Release Date: February 18, 2002 Revision A7 W29EE512 VERSION HISTORY VERSION DATE PAGE A5 Mar. 1998 6 Add. pause 10 mS 7 Add. pause 50 mS 8 Correct the time from 10 mS to 10 µS A6 Oct. 1999 1, 2, 18, 19 Eliminate 600 mil DIP, 450 mil SOP packages 1, 2, 18, 20 Add 32-pin VSOP package 3, 11 A7 Feb. 18, 2002 DESCRIPTION Change Byte Load Cycle Time from 150 µS to 200 µS 4 Modify VCC Power Up/Down Detection in Hardware Data Protection 21 Add HOW TO READ THE TOP MARKING Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 22 -