WINBOND W681513

W681513
5V SINGLE-CHANNEL VOICEBAND CODEC FOR USB
APPLICATIONS
Preliminary Data Sheet
-1-
Publication Release Date: October 1, 2003
Revision A3
W681513
1. GENERAL DESCRIPTION
The W681513 is a single channel PCM CODEC with pin-selectable µ-Law or A-Law companding
dedicated to the USB accessory market by supporting a derivative 2MHz clock. The device is
compliant with the ITU G.712 specification. It operates off of a single +5V power supply and is
available in 20-pin SOP package option. Functions performed include digitization and reconstruction
of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are
compliant with ITU G.712 specification. W681513 performance is specified over the industrial
temperature range of –40°C to +85°C.
The W681513 includes an on-chip precision voltage reference and an additional power amplifier,
capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is
fully differential, reducing noise and improving the power supply rejection ratio. The data transfer
protocol supports both long-frame and short-frame synchronous communications for PCM
applications, and IDL and GCI communications for ISDN applications. W681513 accepts 2MHz
master clock rate, and an on-chip pre-scaler automatically determines the division ratio for the
required internal clock.
ApplIcations
2. FEATURES
•
Single +5V power supply
•
Typical power dissipation of 30 mW,
power-down mode of 0.5 µW
•
Fully-differential analog circuit design
•
On-chip precision reference of 1.575 V for
a 0 dBm TLP at 600 Ω
•
Push-pull power amplifiers with external
gain adjustment with 300 Ω load capability
•
Master clock rate supports 2.000MHz
clock for USB applications
•
Pin-selectable
µ-Law
and
A-Law
companding (compliant with ITU G.711)
•
CODEC A/D and D/A filtering compliant
with ITU G.712
•
Industrial temperature range (–40°C to
+85°C)
•
Package: 20-pin SOP (SOG)
•
-2-
Soft phones running on a PC (VoInternet):
o
USB Phones
o
USB to PSTN Gateway
•
USB Microphones
•
USB Headset for PC and Game Consules
W681513
3. BLOCK DIAGRAM
Re
Int
PC
cei
erf
M
ve
ace
Receive
PCM
Interface
BCLKR
FSR
PCMR
G.712 CODEC
G.711 µ/A -Law
Tra Int
ns PC erf
mitM ace
Transmit
PCM
Interface
BCLKT
FST
PCMT
PAO+
PAOPAI
RO+
RO
AO
AI+
AI-
µ/A-Law
512 kHz
256 kHz
Voltage reference
V AG
8 kHz
PUI
Power Conditioning
VDD
2000 kHz,
Pre -Scaler
scaler
VSS
MCLK
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Publication Release Date: October 1, 2003
Revision A3
W681513
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION ............................................................................................................................. 7
7. FUNCTIONAL DESCRIPTION............................................................................................................ 8
7.1. Transmit Path............................................................................................................................. 8
7.2. Receive Path.............................................................................................................................. 9
7.3. Power Management................................................................................................................. 10
7.3.1. Analog and Digital Supply .............................................................................................. 10
7.3.2. Analog Ground Reference Voltage Output .................................................................... 10
7.4. PCM Interface .......................................................................................................................... 10
7.4.1. Long Frame Sync ........................................................................................................... 10
7.4.2. Short Frame Sync .......................................................................................................... 11
7.4.3. GCI Interface .................................................................................................................. 11
7.4.4. IDL Interface................................................................................................................... 12
7.4.5. System Timing................................................................................................................ 12
8. TIMING DIAGRAMS.......................................................................................................................... 13
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20
9.1. Absolute Maximum Ratings ..................................................................................................... 20
9.2. Operating Conditions ............................................................................................................... 20
10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21
10.1. General Parameters .............................................................................................................. 21
10.2. Analog Signal Level and Gain Parameters............................................................................ 22
10.3. Analog Distortion and Noise Parameters .............................................................................. 23
10.4. Analog Input and Output Amplifier Parameters ..................................................................... 24
10.5. Digital I/O ............................................................................................................................... 26
10.5.1. µ-Law Encode Decode Characteristics........................................................................ 26
10.5.2. A-Law Encode Decode Characteristics ....................................................................... 27
10.5.3. PCM Codes for Zero and Full Scale ............................................................................ 28
10.5.4. PCM Codes for 0dBm0 Output .................................................................................... 28
11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 29
12. PACKAGE SPECIFICATION .......................................................................................................... 31
12.1. 20L SOP – 300mil.................................................................................................................. 31
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W681513
13. ORDERING INFORMATION........................................................................................................... 32
14. VERSION HISTORY ....................................................................................................................... 33
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Publication Release Date: October 1, 2003
Revision A3
W681513
5. PIN CONFIGURATION
RO+
RO+
PAI
PAOPAO+
VDD
FSR
PCMR
BCLKR
PUI
1
20
2
19
3
18
4
17
5
6
7
SINGLE
CHANNEL
CODEC
16
15
14
8
13
9
12
10
11
SOP
-6-
VAG
AI+
AIAO
/A
µ/A-Law
VSS
FST
PCMT
BCLKT
MCLK
W681513
6. PIN DESCRIPTION
Pin
Name
Pin
No.
Functionality
RO+
1
Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to
1.575 volt peak referenced to the analog ground level.
RO+
2
Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to
1.575 volt peak referenced to the analog ground level.
PAI
3
This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.
PAO-
4
Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced
to the VAG voltage level.
PAO+
5
Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak
referenced to the VAG voltage level.
VDD
6
Power supply. This pin should be decoupled to VSS with a 0.1µF ceramic capacitor.
FSR
7
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
PCMR
8
PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR
9
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI
10
Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,
the part is powered down.
MCLK
11
System master clock input supporting 2000 kHz only.
BCLKT
12
PCM transmit bit clock input pin.
PCMT
13
PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
FST
14
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
VSS
15
This is the supply ground. This pin should be connected to 0V.
µ/A-Law
16
Compander mode select pin. µ-Law companding is selected when this pin is tied to VDD. A-Law
companding is selected when this pin is tied to VSS.
AO
17
Analog output of the first gain stage in the transmit path.
AI-
18
Inverting input of the first gain stage in the transmit path.
AI+
19
Non-inverting input of the first gain stage in the transmit path.
VAG
20
Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal
processing. This pin should be decoupled to VSS with a 0.01µF to 0.1 µF capacitor. This pin
becomes high impedance when the chip is powered down.
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Publication Release Date: October 1, 2003
Revision A3
W681513
7. FUNCTIONAL DESCRIPTION
W681513 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC
complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a
complete µ-Law and A-Law compander. The µ-Law and A-Law companders are designed to comply
with the specifications of the ITU-T G.711 recommendation.
The block diagram in section 3 shows the main components of the W681513. The chip consists of a
PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.
The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample
rate with the external frame sync frequency. The power conditioning block provides the internal
power supply for the digital and the analog section, while the voltage reference block provides a
precision analog ground voltage for the analog signal processing. The main CODEC block diagram
is shown in section 3.
VA
VAG
G
+
Receive Path
-
PAO+
+
PAO PAI
8
µ/Aµ/ACont
Control
ol
+
D/A
Converter
w
fC= 3400Hz
H
Smoot
Smoothing
n Filter
1
RO +
Smoothing
Smoot
nFilter
2
Transmit Path
AO
8
A/D
Converter
µ/A µ/A- Control
Cont
++
ffCC == 200Hz
200
High
H Pass
High
Filt
Filter
Pas
fC== 3400Hz
AntH-Aliasi
Aliasing
Ant
i Filter
n
AI+
AI -
Ant-Aliasi
Ant-Aliasing
Filter
Figure 7.1 The W681513 Signal Path
7.1. Transmit Path
The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain
setting (see application examples in section 11). The device has an input operational amplifier whose
output is the input to the encoder section. If the input amplifier is not required for operation it can be
powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or
the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The
input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. The AO pin is selected
as an input when AI+ is tied to VDD and the AI- pin is selected as an input when AI+ is tied to VSS (see
Table 7.1).
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W681513
AI+
Input Amplifier
Input
VDD
Powered Down
AO
1.2 to VDD-1.2
Powered Up
AI+, AI-
VSS
Powered Down
AI-
Table 7.1 Input Amplifier Modes of operation
When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the
analog ground voltage VAG.
The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched
capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of
input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is
filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the
recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is
digitized. The signal is converted into a compressed 8-bit digital representation with either µ-Law or ALaw format. The µ-Law or A-Law format is pin-selectable through the µ/A-Law pin. The compression
format can be selected according to Table 7.2.
µ/A-Law Pin
Format
VSS
A-Law
VDD
µ-Law
Table 7.2. Pin-selectable Compression Format
The digital 8-bit µ-Law or A-Law samples are fed to the PCM interface for serial transmission at the
sample rate supplied by the external frame sync FST.
7.2. Receive Path
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed
through the pin-selectable µ-Law or A-Law expander and converted to analog samples. The mode of
expansion is selected by the µ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.
A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is
buffered to provide the receive output signal RO+. The RO+ output can be externally connected to the
PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By
using external resistors (see section 11 for examples), various gain settings of this output amplifier
can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting
PAI to VDD.
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Publication Release Date: October 1, 2003
Revision A3
W681513
7.3. POWER MANAGEMENT
7.3.1. Analog and Digital Supply
The power supply for the analog and digital parts of the W681513 must be 5V +/- 10%. This supply
voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 µF
ceramic capacitor.
7.3.2. Analog Ground Reference Voltage Outpt
The analog ground reference voltage is available for external reference at the VAG pin. This voltage
needs to be decoupled to VSS through a 0.01 µF ceramic capacitor.
7.4. PCM INTERFACE
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received
through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of
operation of the interface are shown in Table 7.3.
BCLKR
FSR
Interface Mode
2.000 MHz
8 kHz
Long or Short Frame Sync
VSS
VSS
ISDN GCI with active channel B1
VSS
VDD
ISDN GCI with active channel B2
VDD
VSS
ISDN IDL with active channel B1
VDD
ISDN IDL with active channel B2
VDD
Table 7.3 PCM Interface mode selections
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the
BCLKR or BCLKT pin to a 2.000 MHz clock and connecting the FSR or FST pin to the 8 kHz frame
sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on
the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is
held high for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame
Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125
µsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will
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W681513
become low impedance when the Frame Sync signal FST is high or when the 8 bit data word is being
transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync signal
FST becomes low while the data is transmitted or when half of the LSB is transmitted. The internal
decision logic will determine whether the next frame sync is a long or a short frame sync, based on the
previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two
frame sync cycles after every power down state. More detailed timing information can be found in the
interface timing section.
7.4.2. Short Frame Sync
The W681513 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is high
for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the
bit-clock, the W681513 starts clocking out the data on the PCMT pin, which will also change from high
to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway
the LSB. The Short Frame Sync operation of the W681513 is based on an 8-bit data word. When
receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge
that coincides with the Frame Sync signal. The internal decision logic will determine whether the next
frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus
collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down
state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface
consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data
clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted
consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is
transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
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Publication Release Date: October 1, 2003
Revision A3
W681513
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface
consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the
first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK
cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after
the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK
after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the
IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when
not used for data transmission and also in the time slot of the unused channel. For more timing
information, see the timing section.
7.4.5. System Timing
The system can work at 2000 kHz master clock rate only. The system clock is supplied through the
master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is
used to generate a fixed 256 kHz and 8 kHz sample clock for the internal CODEC. The pre-scaler
measures the master clock frequency versus the Frame Sync frequency and sets the division ratio
accordingly. If the Frame Sync is low for the entire frame sync period while the MCLK and BCLK pin
clock signals are still present, the W681513 will enter the low power standby mode. Another way to
power down is to set the PUI pin to low. When the system needs to be powered up again, the PUI pin
needs to be set to high and the Frame Sync pulse needs to be present. It will take two Frame Sync
cycles before the pin PCMT will become low impedance.
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W681513
8. TIMING DIAGRAMS
T FTR H M
T FTR SM
TM CK L
TM CK H
T R ISE
T FA LL
M C LK
TM CK
T FS
T FSL
FST
T FTR H
B C LK T
0
T FTR S
1
T FTFH
2
3
T FD TD
TBCK H
4
5
6
7
T B D TD
PC M T
D7
D6
8
T H ID
D5
D4
D3
D2
TBCK L
0
1
TBCK
T H ID
D1 D0
M SB
LSB
T FS
T FSL
FSR
T FR R H
B C LK R
0
T FR R S
1
T FR FH
2
3
TBCK H
4
5
6
7
8
TBCK L
0
1
TBCK
PC M R
D7
M SB
TD RS
D6
D5
D4
D3
D2
D1 D0
LSB
TD RH
Figure 8.1 Long Frame Sync PCM Timing
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Publication Release Date: October 1, 2003
Revision A3
W681513
SYMBOL
DESCRIPTION
1/TFS
FST, FSR Frequency
1
MIN
TYP
MAX
UNIT
---
8
---
kHz
TFSL
FST / FSR Minimum Low Width
TBCK
sec
1/TBCK
BCLKT, BCLKR Frequency
2000
---
2000
kHz
TBCKH
BCLKT, BCLKR High Pulse Width
50
---
---
ns
TBCKL
BCLKT, BCLKR Low Pulse Width
50
---
---
ns
TFTRH
BCLKT 0 Falling Edge to FST Rising
Edge Hold Time
20
---
---
ns
TFTRS
FST Rising Edge to BCLKT 1 Falling
edge Setup Time
80
---
---
ns
TFTFH
BCLKT 2 Falling Edge to FST Falling
Edge Hold Time
50
---
---
ns
TFDTD
FST Rising Edge to Valid PCMT Delay
Time
---
---
60
ns
TBDTD
BCLKT Rising Edge to Valid PCMT
Delay Time
---
---
60
ns
THID
Delay Time from the Later of FST
Falling Edge, or
10
---
60
ns
BCLKT 8 Falling Edge to PCMT Output
High Impedance
TFRRH
BCLKR 0 Falling Edge to FSR Rising
Edge Hold Time
20
---
---
ns
TFRRS
FSR Rising Edge to BCLKR 1 Falling
edge Setup Time
80
---
---
ns
TFRFH
BCLKR 2 Falling Edge to FSR Falling
Edge Hold Time
50
---
---
ns
TDRS
Valid PCMR to BCLKR Falling Edge
Setup Time
0
---
---
ns
TDRH
PCMR Hold Time from BCLKR Falling
Edge
50
---
---
ns
Table 8.1 Long Frame Sync PCM Timing Parameters
1
TFSL must be at least ≥ TBCK
- 14 -
W681513
T FTR H M
T FTR SM
TM CK L
TM CK H
T R ISE
T FA LL
M C LK
TM CK
T FS
T FTFH
T FTFS
FST
T FTR S
T FTR H
B C LK T
-1
0
TBCK H
1
2
3
T B D TD
PC M T
D7
4
5
6
7
0
8
T B D TD
D6
D5
D3
D2
1
TBCK
T H ID
D4
TBCK L
D1 D0
M SB
LSB
T FS
T FR FH
T FR FS
FSR
T FR R S
T FR R H
B C LK R
-1
0
TBCK H
1
2
3
4
5
6
7
TBCK L
0
8
1
TBCK
PC M R
D7
M SB
TD RS
D6
D5
D4
D3
D2
D1 D0
LSB
TD RH
Figure 8.2 Short Frame Sync PCM Timing
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Publication Release Date: October 1, 2003
Revision A3
W681513
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
1/TFS
FST, FSR Frequency
---
8
---
kHz
1/TBCK
BCLKT, BCLKR Frequency
2000
---
2000
kHz
TBCKH
BCLKT, BCLKR High Pulse Width
50
---
---
ns
TBCKL
BCLKT, BCLKR Low Pulse Width
50
---
---
ns
TFTRH
BCLKT –1 Falling Edge to FST Rising Edge Hold
Time
20
---
---
ns
TFTRS
FST Rising Edge to BCLKT 0 Falling edge Setup
Time
80
---
---
ns
TFTFH
BCLKT 0 Falling Edge to FST Falling Edge Hold Time
50
---
---
ns
TFTFS
FST Falling Edge to BCLKT 1 Falling Edge Setup
Time
50
---
---
ns
TBDTD
BCLKT Rising Edge to Valid PCMT Delay Time
10
---
60
ns
THID
Delay Time from BCLKT 8 Falling Edge to PCMT
Output High Impedance
10
---
60
ns
TFRRH
BCLKR –1 Falling Edge to FSR Rising Edge Hold
Time
20
---
---
ns
TFRRS
FSR Rising Edge to BCLKR 0 Falling edge Setup
Time
80
---
---
ns
TFRFH
BCLKR 0 Falling Edge to FSR Falling Edge Hold Time
50
---
---
ns
TFRFS
FSR Falling Edge to BCLKR 1 Falling Edge Setup
Time
50
---
---
ns
TDRS
Valid PCMR to BCLKR Falling Edge Setup Time
0
---
---
ns
TDRH
PCMR Hold Time from BCLKR Falling Edge
50
---
---
ns
Table 8.2 Short Frame Sync PCM Timing Parameters
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W681513
T FS
FST
T FSFH
T FSR S
T FSR H
B C LK T
-1
0
1
TBCK H
2
3
4
5
T B D TD
PC M T
6
8
LSB
TD RS
9
T H ID
T B D TD
D7 D6 D5 D4 D3 D2 D1 D0
M SB
PC M R
7
10
11 12
LSB
15 16
17
18
TBCK
T H ID
T B D TD
D7 D6 D5 D4 D3 D2
D1 D0
LSB
M SB
TD RS
D7 D6 D5 D4 D3 D2 D1 D0
14
T B D TD
TD RH
M SB
13
TBCK L
TD RH
D7 D6 D5 D4 D3 D2
M SB
BCH = 0
B 1 C hannel
D1 D0
LSB
BCH = 1
B 2 C hannel
Figure 8.3 IDL PCM Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
1/TFS
FST Frequency
---
8
---
kHz
1/TBCK
BCLKT Frequency
2000
---
2000
kHz
TBCKH
BCLKT High Pulse Width
50
---
---
ns
TBCKL
BCLKT Low Pulse Width
50
---
---
ns
TFSRH
BCLKT –1 Falling Edge to FST Rising Edge
Hold Time
20
---
---
ns
TFSRS
FST Rising Edge to BCLKT 0 Falling edge
Setup Time
60
---
---
ns
TFSFH
BCLKT 0 Falling Edge to FST Falling Edge
Hold Time
20
---
---
ns
TBDTD
BCLKT Rising Edge to Valid PCMT Delay
Time
10
---
60
ns
THID
Delay Time from the BCLKT 8 Falling Edge
(B1 channel) or BCLKT 18 Falling Edge (B2
Channel) to PCMT Output High Impedance
10
---
50
ns
TDRS
Valid PCMR to BCLKT Falling Edge Setup
Time
20
---
---
ns
TDRH
PCMR Hold Time from BCLKT Falling Edge
75
---
---
ns
Table 8.3 IDL PCM Timing Parameters
- 17 -
Publication Release Date: October 1, 2003
Revision A3
W681513
T FS
FST
T FSFH
T FSR S
T FSR H
TBCK H
TBCK L
B C LK T
0
1 2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
T FD TD
PC M T
T B D TD
T B D TD
D7 D6 D5 D4 D3 D2 D1 D0
TD RS
D7 D6 D5 D4 D3 D2
D1 D0
LSB
TD RS
TD RH
TD RH
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
M SB
T H ID
T B D TD T B C K
LSB M SB
M SB
PC M R
T H ID
D1 D0
LSB M SB
BCH = 0
B 1 C hannel
LSB
BCH = 1
B 2 C hannel
Figure 8.4 GCI PCM Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
1/TFST
FST Frequency
---
8
---
kHz
1/TBCK
BCLKT Frequency
2000
---
2000
kHz
TBCKH
BCLKT High Pulse Width
50
---
---
ns
TBCKL
BCLKT Low Pulse Width
50
---
---
ns
TFSRH
BCLKT 0 Falling Edge to FST Rising Edge Hold Time
20
---
---
ns
TFSRS
FST Rising Edge to BCLKT 1 Falling edge Setup Time
60
---
---
ns
TFSFH
BCLKT 1 Falling Edge to FST Falling Edge Hold Time
20
---
---
ns
TFDTD
FST Rising Edge to Valid PCMT Delay Time
---
---
60
ns
TBDTD
BCLKT Rising Edge to Valid PCMT Delay Time
---
---
60
ns
THID
Delay Time from the BCLKT 16 Falling Edge (B1
channel) or BCLKT 32 Falling Edge (B2 Channel) to
PCMT Output High Impedance
10
---
50
ns
TDRS
Valid PCMR to BCLKT Rising Edge Setup Time
20
---
---
ns
TDRH
PCMR Hold Time from BCLKT Rising Edge
---
---
60
ns
Table 8.4 GCI PCM Timing Parameters
- 18 -
W681513
SYMBOL
DESCRIPTION
1/TMCK
Master Clock Frequency
TMCKH
TMCK
/
MCLK Duty
Operation
TYP
MIN
Cycle
--for
256
kHz
High
2000
45%
MAX
UNIT
---
kHz
55%
TMCKH
Minimum Pulse Width
MCLK(512 kHz or Higher)
for
50
---
---
ns
TMCKL
Minimum Pulse Width Low for MCLK
(512 kHz or Higher)
50
---
---
ns
TFTRHM
MCLK falling Edge to FST Rising Edge
Hold Time
50
---
---
ns
TFTRSM
FST Rising Edge to MCLK Falling edge
Setup Time
50
---
---
ns
TRISE
Rise Time for All Digital Signals
---
---
50
ns
TFALL
Fall Time for
---
---
50
ns
All Digital Signals
Table 8.5 General PCM Timing Parameters
- 19 -
Publication Release Date: October 1, 2003
Revision A3
W681513
9. ABSOLUTE MAXIMUM RATINGS
9.1. ABSOLUTE MAXIMUM RATINGS
Condition
Value
Junction temperature
1500C
Storage temperature range
-650C to +1500C
Voltage Applied to any pin
(VSS - 0.3V) to (VDD + 0.3V)
Voltage applied to any pin (Input current limited to +/-20 mA)
(VSS – 1.0V) to (VDD + 1.0V)
Lead temperature (soldering
3000C
– 10 seconds)
VDD - VSS
-0.5V to +6V
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
9.2. OPERATING CONDITIONS
Condition
Value
Industrial operating temperature
-400C to +850C
Supply voltage (VDD)
+4.5V to +5.5V
Ground voltage (VSS)
0V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device.
- 20 -
W681513
10. ELECTRICAL CHARACTERISTICS
10.1. GENERAL PARAMETERS
Conditions
Min (2)
Typ (1)
Max (2)
Units
0.6
V
Symbol
Parameters
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
PCMT Output Low Voltage
IOL = 3 mA
VOH
PCMT Output High Voltage
IOL = -3 mA
IDD
VDD Current (Operating) - ADC + DAC
No Load
6
8
ISB
VDD Current (Standby)
FST & FSR =Vss ;
PUI=VDD
10
100
Ipd
VDD Current (Power Down)
PUI= Vss
0.1
10
µA
IIL
Input Leakage Current
VSS<VIN<VDD
+/-10
µA
IOL
PCMT Output Leakage Current
VSS<PCMT<VDD
+/-10
µA
10
pF
15
pF
2.4
V
0.4
VDD –
0.4
V
V
mA
µA
High Z State
CIN
Digital Input Capacitance
COUT
PCMT Output Capacitance
PCMT High Z
1. Typical values: TA = 25°C , VDD = 5.0 V
2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
- 21 -
Publication Release Date: October 1, 2003
Revision A3
W681513
10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;
PARAMETER
SYM.
CONDITION
TYP.
TRANSMIT
(A/D)
MIN.
RECEIVE
(D/A)
MAX.
MIN.
MAX.
UNIT
Absolute
Level
LABS
0 dBm0 = 0dBm @ 600Ω
1.096
---
---
---
---
VPK
Max. Transmit
Level
TXMAX
3.17 dBm0 for µ-Law
1.579
---
---
---
---
VPK
3.14 dBm0 for A-Law
1.573
---
---
---
---
VPK
Absolute Gain
(0 dBm0 @
1020 Hz;
TA=+25°C)
GABS
0 dBm0 @ 1020 Hz;
TA=+25°C
0
-0.25
+0.25
-0.25
+0.25
dB
Absolute Gain
variation with
Temperature
GABST
TA=0°C to TA=+70°C
0
-0.03
+0.03
-0.03
+0.03
dB
-0.05
+0.05
-0.05
+0.05
Frequency
Response,
GRTV
TA=-40°C to TA=+85°C
Relative to
0dBm0 @
1020 Hz
Gain Variation
vs. Level Tone
(1020 Hz
relative to –10
dBm0)
GLT
15 Hz
---
---
-40
-0.5
0
50 Hz
---
---
-30
-0.5
0
60 Hz
---
---
-26
-0.5
0
200 Hz
---
-1.0
-0.4
-0.5
0
300 to 3000 Hz
---
-0.20
+0.15
-0.20
+0.15
3300 Hz
---
-0.35
+0.15
-0.35
+0.15
3400 Hz
---
-0.8
0
-0.8
0
3600 Hz
---
---
0
---
0
4000 Hz
---
---
-14
---
-14
4600 Hz to 100 kHz
---
---
-32
---
-30
+3 to –40 dBm0
---
-0.3
+0.3
-0.2
+0.2
-40 to –50 dBm0
---
-0.6
+0.6
-0.4
+0.4
-50 to –55 dBm0
---
-1.6
+1.6
-1.6
+1.6
- 22 -
dB
dB
W681513
10.3. ANALOG DISTORTION AND NOISE PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;
PARAMETER
Total Distortion vs.
Level Tone (1020 Hz,
µ-Law, C-Message
Weighted)
Total Distortion vs.
Level Tone (1020 Hz,
A-Law, Psophometric
Weighted)
SYM.
DLTµ
CONDITION
MIN.
TYP.
MAX.
36
---
---
36
---
-40 dBm0
29
-45 dBm0
+3 dBm0
RECEIVE (D/A)
TYP.
MAX.
34
---
---
---
36
---
---
---
---
30
---
---
25
---
---
25
---
---
36
---
---
34
---
---
36
---
---
36
---
---
-40 dBm0
29
---
---
30
---
---
-45 dBm0
25
---
---
25
---
---
4600 Hz to 7600 Hz
---
---
---
---
---
-30
7600 Hz to 8400 Hz
---
---
---
---
---
-40
8400 Hz to 100000 Hz
---
---
---
---
---
-30
+3 dBm0
0 dBm0 to -30 dBm0
DLTA
TRANSMIT (A/D)
0 dBm0 to -30 dBm0
MIN.
UNIT
dBC
dBp
dB
Spurious Out-Of-Band
at RO+ (300 Hz to
3400 Hz @ 0dBm0)
DSPO
Spurious In-Band (700
Hz to 1100 Hz @
0dBm0)
DSPI
300 to 3000 Hz
---
---
-47
---
---
-47
dB
Intermodulation
Distortion (300 Hz to
3400 Hz –4 to –21
dBm0
DIM
Two tones
---
---
-41
---
---
-41
dB
Crosstalk (1020 Hz @
0dBm0)
DXT
---
---
-75
---
---
-75
dBm0
Absolute Group Delay
τABS
1200Hz
---
---
360
---
---
240
µsec
Group Delay
Distortion (relative to
group delay @ 1200
Hz)
τD
500 Hz
---
---
750
---
---
750
µsec
600 Hz
---
---
380
---
---
370
1000 Hz
---
---
130
---
---
120
2600 Hz
---
---
130
---
---
120
2800 Hz
---
---
750
---
---
750
µ-Law; C-message
---
---
5
---
---
13
dBrnc
A-Law; Psophometric
---
---
-69
---
---
-79
dBm0p
Idle Channel Noise
NIDL
- 23 -
Publication Release Date: October 1, 2003
Revision A3
W681513
10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;
PARAMETER
SYM.
CONDITION
MIN.
TYP.
MAX.
UNIT.
AI Input Offset Voltage
VOFF,AI
AI+, AI-
---
---
±25
mV
AI Input Current
IIN,AI
AI+, AI-
---
±0.1
±1.0
µA
AI Input Resistance
RIN,AI
AI+, AI- to VAG
10
---
---
MΩ
AI Input Capacitance
CIN,AI
AI+, AI-
---
---
10
pF
AI Common Mode Input Voltage
Range
VCM,AI
AI+, AI-
1.2
---
VDD-1.2
V
AI Common Mode Rejection
Ratio
CMRRTI
AI+, AI-
---
60
---
dB
AI Amp Gain Bandwidth Product
GBWTI
AO, RLD≥10kΩ
---
2150
---
kHz
AI Amp DC Open Loop Gain
GTI
AO, RLD≥10kΩ
---
95
---
dB
AI Amp Equivalent Input Noise
NTI
C-Message Weighted
---
-24
---
dBrnC
AO Output Voltage Range
VTG
RLD=10kΩ to VAG
0.5
---
VDD-0.5
V
RLD=2kΩ to VAG
1.0
---
VDD-1.0
Load Resistance
RLDTGRO
AO, RO to VAG
2
---
---
kΩ
Load Capacitance
CLDTGRO
AO, RO
---
---
100
pF
AO & RO Output Current
IOUT1
0.5 ≤AO,RO+≤ VDD-0.5
±1.0
---
---
mA
RO+ Output Resistance
RRO+
RO+, 0 to 3400 Hz
---
1
---
Ω
RO+ Output Offset Voltage
VOFF,RO+
RO+ to VAG
---
---
±25
mV
Analog Ground Voltage
VAG
Relative to VSS
2.429
2.5
2.573
V
VAG Output Resistance
RVAG
Within ±25mV change
---
2.5
12.5
Ω
Power Supply Rejection Ratio (0
to 100 kHz to VDD, C-message)
PSRR
Transmit
40
80
---
dBC
Receive
40
75
---
PAI Input Offset Voltage
VOFF,PAI
PAI
---
---
±20
mV
PAI Input Current
IIN,PAI
PAI
---
±0.05
±1.0
µA
PAI Input Resistance
RIN,PAI
PAI to VAG
10
---
---
MΩ
PAI Amp Gain Bandwidth
Product
GBWPI
PAO- no load
---
1000
---
kHz
Output Offset Voltage
VOFF,PO
PAO+ to PAO-
---
---
±50
mV
Load Resistance
RLDPO
PAO+, PAOdifferentially
300
---
---
Ω
Load Capacitance
CLDPO
PAO+, PAOdifferentially
---
---
1000
pF
- 24 -
W681513
PARAMETER
SYM.
CONDITION
MIN.
TYP.
MAX.
UNIT.
PO Output Current
IOUTPO
0.5 ≤AO,RO+≤ VDD-0.5
±10.0
---
---
mA
PO Output Resistance
RPO
PAO+ to PAO-
---
1
---
Ω
PO Differential Gain
GPO
RLD=300Ω, +3dBm0, 1
kHz, PAO+ to PAO-
-0.2
0
+0.2
dB
PO Differential Signal to
Distortion C-Message weighted
DPO
ZLD=300Ω
45
60
---
dBC
ZLD=100nF + 100Ω
---
40
---
ZLD=100nF + 20Ω
---
40
---
PSRRP
0 to 4 kHz
40
55
---
O
4 to 25 kHz
---
40
---
PO Power Supply Rejection
Ratio (0 to 25 kHz to VDD,
Differential out)
- 25 -
dB
Publication Release Date: October 1, 2003
Revision A3
W681513
10.5. DIGITAL I/O
10.5.1. µ-Law Encode Decode Characteristics
Normalized
Encode
Decision
Levels
8159
7903
Normalized
Digital Code
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
Step
Step
Step
1
0
0
0
0
0
0
0
4063
1
0
0
0
1
1
1
1
2015
1
0
0
1
1
1
1
1
991
1
0
1
0
1
1
1
1
479
1
0
1
1
1
1
1
1
223
1
1
0
0
1
1
1
1
95
1
1
0
1
1
1
1
1
31
1
1
1
0
1
1
1
1
1
0
33
:
:
3
99
:
:
35
231
:
:
103
495
:
:
239
1023
:
:
511
2079
:
:
1055
4191
:
:
2143
8031
:
:
4319
Decode
Levels
1
1
1
1
1
1
1
0
2
1
1
1
1
1
1
1
1
0
Notes:
Sign bit = 0 for negative values, sign bit = 1 for positive values
- 26 -
W681513
10.5.2. A-Law Encode Decode Characteristics
Normalized
Encode
Decision
Levels
4096
3968
Digital Code
Normalized
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
Step
Step
Step
1
0
1
0
1
0
1
0
2048
1
0
1
0
0
1
0
1
1024
1
0
1
1
0
1
0
1
512
1
0
0
0
0
1
0
1
256
1
0
0
1
0
1
0
1
128
1
1
1
0
0
1
0
1
64
1
1
1
0
0
1
0
1
0
66
:
:
2
132
:
:
68
264
:
:
136
528
:
:
272
1056
:
:
544
2112
:
:
1088
4032
:
:
2048
Decode
Levels
1
1
0
1
0
1
0
1
1
Notes:
1. Sign bit = 0 for negative values, sign bit = 1 for positive values
2. Digital code includes inversion of all even number bits
- 27 -
Publication Release Date: October 1, 2003
Revision A3
W681513
10.5.3. PCM Codes for Zero and Full Scale
µ-Law
Level
A-Law
Sign bit
Chord bits
Step bits
Sign bit
Chord bits
Step bits
(D7)
(D6,D5,D4)
(D3,D2,D1,D0)
(D7)
(D6,D5,D4)
(D3,D2,D1,D0)
+ Full Scale
1
000
0000
1
010
1010
+ Zero
1
111
1111
1
101
0101
- Zero
0
111
1111
0
101
0101
- Full Scale
0
000
0000
0
010
1010
10.5.4. PCM Codes for 0dBm0 Output
µ-Law
Sample
A-Law
Sign bit
Chord bits
Step bits
Sign bit
Chord bits
Step bits
(D7)
(D6,D5,D4)
(D3,D2,D1,D0)
(D7)
(D6,D5,D4)
(D3,D2,D1,D0)
1
0
001
1110
0
011
0100
2
0
000
1011
0
010
0001
3
0
000
1011
0
010
0001
4
0
001
1110
0
011
0100
5
1
001
1110
1
011
0100
6
1
000
1011
1
010
0001
7
1
000
1011
1
010
0001
8
1
001
1110
1
011
0100
- 28 -
W681513
11. TYPICAL APPLICATION CIRCUITS
LS1
VCC
R10 1K
SPEAKER
R1
1.5K
C4
4.7uF
1.0uF
C6 330pF
R3 1K
R5 91K
R9
select
C3
MICROPHONE
R2
1.5K
C1
0.1uF
C2
U1
17
18
19
R4 1K
R6
91K
C7 330pF
1.0uF
R7 20K
R8 3K
20
1
2
3
4
5
C5
0.01uF
6
VDD
AO
FST
BCLKT
PCMT
AIAI+
MCLK
VAG
RO+
PCMR
BCLKR
FSR
RO+
14
12
13
11
FRAME SYNC 8KHz INPUT
PCM OUTPUT
2.000 MHz MASTER CLOCK IN
8
9
7
PCM INPUT
PAI
PAOPAO+
VSS
u/A
PUI
16
10
PCM MODE CONTROL
POWER CONTROL
W681513 15
Figure 11.1 A USB VoIP Phone application
SUGGESTED COMPONENT VALUES BY APPLICATION
SCHEMATIC
COMPONENT #
TELEPHONE
HANDSET
VoIP PHONE SET
R3,4
1K
1K
R5,6
27K
91K
C6,7
1200 pF
330 pF
R9
SELECT
SELECT
R7
20K
20K
R8
3K
3K
In the handset application the gain from the handset microphone is set to 27 for the input amplifier.
This is because the acoustical chamber in the telephone type handset lets the electret microphone
provide an output of ~28 mVRMS. The chamber typically has a gain of 3 over a bare microphone (or
one placed with only a small opening to the outside world.) Because of the high sensitivity of the
- 29 -
Publication Release Date: October 1, 2003
Revision A3
W681513
earphone (150 Ώ impedance) in a typical handset, the output gain from the Power Amp is set to ~0.16
for a satisfactory listening level.
In the VoIP telephone, or small wireless phones, the plastic case is typically too small to provide a
reasonable acoustic chamber. Thus the output from the microphone is less than in the previous
example. This results in having to set the input gain of the CODEC to ~75 to 90 and in a comparable
signal level to the receive telephone handset but, because of the increased gain, the Signal-to-Noise
Ratio (SNR) has decreased and the signal sounds noisier. On the receive side, the gain is set as in
the previous example. When the Power Amp gain is as low as 0.16 a 32 ohm load speaker can be
driven.
Resistor R9 sets the sidetone level (the signal fed back to the earpiece from the microphone so the
telephone sounds “live”) to the level desired by the designer.
Capacitors C6 and C7 are introduced for external compensation to keep the input amplifier stable at
such high gain figures and prevent oscillation. These capacitors are not needed when the gain is
close to unity or less than unity.
- 30 -
W681513
12. PACKAGE SPECIFICATION
12.2. 20L SOP (SOG)-300MIL
SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS
1
2
c
E HE
L
1
1
D
0.2
O
A
Y
SEATING PLANE
e
GAUGE
A
b
SYMBOL
DIMENSION (MM)
DIMENSION (INCH)
MIN.
MAX.
MIN.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
b
0.33
0.51
0.013
0.020
c
0.23
0.32
0.009
0.013
E
7.40
7.60
0.291
0.299
D
12.60
13.00
0.496
0.512
e
1.27 BSC
0.050 BSC
HE
10.00
10.65
0.394
0.419
Y
-
0.10
-
0.004
L
0.40
1.27
0.016
0.050
0
0º
8º
0º
8º
- 31 -
Publication Release Date: October 1, 2003
Revision A3
W681513
13. ORDERING INFORMATION
Winbond Part Number Description
W681513_
Package Type:
Product Family
W681511 Product
S
=
20-Lead Plastic Small Outline Package (SOG/SOP)
When ordering W681513 series devices, please refer to the following part numbers.
Part Number
W681513S
- 32 -
W681513
14. VERSION HISTORY
VERSION
DATE
A3
October 1,
2003
PAGE
DESCRIPTION
First published version
The information contained in this datasheet may be subject to change without
notice. It is the responsibility of the customer to check the Winbond USA website
(www.winbond-usa.com) periodically for the latest version of this document, and
any Errata Sheets that may be generated between datasheet revisions.
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
http://www.winbond-usa.com/
27F, 299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62356998
Taipei Office
Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District,
Taipei, 114, Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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Publication Release Date: October 1, 2003
Revision A3