Winbond Integrated Media Reader W83L519D W83L519D PRELIMINARY W83L519D Datasheet Revision History Pages Dates Version Version Main Contents on Web 1 n.a. 2002/Feb. 0.5 All versions before 0.5 are only for internal reference. n.a. 2 3 4 5 6 7 8 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 1 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY CONTENT 1 GENERAL DESCRIPTION...............................................................................................................3 2 FUNCTIONS .....................................................................................................................................4 2.1 2.2 2.3 2.4 2.5 GENERAL ........................................................................................................................................4 SMART CARD INTERFACE .................................................................................................................4 MEMORY STICK INTERFACE ..............................................................................................................4 SD MEMORY CARD INTERFACE ........................................................................................................4 PACKAGE ........................................................................................................................................4 3 PIN CONFIGURATION ....................................................................................................................5 4 PIN DESCRIPTION ..........................................................................................................................6 4.1 4.2 4.3 4.4 5 BUS INTERFACE ...............................................................................................................................6 SMART CARD INTERFACE PINS .........................................................................................................7 MEMORY STICK INTERFACE/SD MEMORY INTERFACE PINS ................................................................8 CRYSTAL AND POWER PINS .............................................................................................................9 CONFIGURATION REGISTER ......................................................................................................10 5.1 PLUG AND PLAY CONFIGURATION ...................................................................................................10 5.2 COMPATIBLE PNP..........................................................................................................................10 5.2.1 Extended Function Register ................................................................................................10 5.2.2 Extended Functions Enable Register (EFER) .....................................................................11 5.2.3 Extended Function Index Register (EFIR), Extended Function Data Register (EFDR) ......11 5.3 CONFIGURATION SEQUENCE ..........................................................................................................11 5.3.1 Software programming example..........................................................................................12 5.4 GLOBAL REGISTERS ......................................................................................................................12 5.5 LOGICAL DEVICE 0 (SMART CARD INTERFACE)................................................................................14 5.6 LOGICAL DEVICE 1 (MEMORY STICK INTERFACE) ............................................................................15 5.7 LOGICAL DEVICE 2 (GPIO) ............................................................................................................15 5.8 LOGICAL DEVICE 3 (SD MEMORY INTERFACE) ................................................................................17 6 ORDERING INSTRUCTION...........................................................................................................18 7 HOW TO READ THE TOP MARKING...........................................................................................18 8 PACKAGE DRAWING AND DIMENSIONS ..................................................................................19 9 THE W83L519D SCHEMATIC .......................................................................................................20 The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 2 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 1 GENERAL DESCRIPTION W83L519D is Winbond's innovative solution to a new class of storage devices for IA Noetebook, Desktop PC and PC system-related products. It incorporates a security Application: Smart Card Interface and two most promising compact storage interfaces: Memory Stick interface, and Secure Digital Memory Card interface in IT era. To cater boundless IT implementation possibilities, W83L519D can be configured to interface with host through ISA bus. Base on the ISA interface, one Smart Card Interface port and an optional Memory Stick/SD memory Interface ports are provided. The kind of versatility allows user to design very costeffective products in a very flexible way. The whole chip of W83L519D operates at voltage level of 3.3 V except Smart Card Interface port's I/O pins and ISA bus interface that are at 5 V to be compatible with mainstream Smart Card implementations. Advanced power management feature further optimizes power consumption whether in operation or in power down mode. W83L519D comes as a 48-pin LQFP streamline package. Combining with powerful functions, effective power management, and versatile configurability, this integrated media reader offers a perfect approach for design of storage device of IT products. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation. Information check: http://www.memorystick.org/ The trademarks and intellectual property rights of Secure Digital belong to SD Group. Information check: http://www.sdcard.org/ The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 3 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 2 2.1 FUNCTIONS General Support ISA bus Programmable configuration settings 48 MHz crystal inputs 2.2 Smart Card Interface ISO-7816 compliant PC/SC T=0, T=1 compliant 16-byte transmitter FIFO and 16-byte receiver FIFO FIFO threshold interrupt to optimize system performance Programmable transmission clock frequency Versatile baud rate configuration UART-like register file structure 2.3 Memory Stick Interface Memory Stick Standard Format Specifications ver. 1.3 compliant Support interrupt polling transmission Support FIFO threshold interrupt to optimize system performance Automatic clock halt to prevent underrun/overrun 16 MHz interface clock 2.4 SD Memory Card Interface SD Memory Card Specifications: Part 1 PHYSICAL LAYER SPECIFICATION Version 1.0 Compliant Support interrupt polling transmission Support FIFO threshold interrupt to leverage system performance 24 MHz interface clock 2.5 Package 48-pin LQFP The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 4 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY TC DACK# DRQ MSLED/SDLED/SD_WP MSPWR#/SDPWR# VSS MSCLK/SDCLK MS1/SD1 MS2/SD2 MS3/SD3 MS4/SD4 35 34 33 32 31 29 28 27 26 25 30 AEN 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 RESET# PME# VSS D7 D6 D5 D4 D3 D2 W83L519D IOR# IOW# A9 A8 A7 VDD3V A6 A5 A4 A3 A2 A1 A0 IRQB 36 PIN CONFIGURATION IRQA 3 The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 5 24 23 22 21 20 19 18 17 16 15 14 13 MS5/SD5 XIN XOUT SCRST# SCIO SCCLK SCPSNT SCPWR# SCLED VDD D0 D1 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 4 PIN DESCRIPTION Note: INtp3 - 3.3V TTL level input pin INts - 5V TTL level Schmitt-trigger input pin INtsp3 - 3.3V TTL level Schmitt-trigger input pin I/O12t - 5V TTL level bi-directional pin with 12 mA drive-sink capability I/O24t - 5V TTL level bi-directional pin with 24 mA drive-sink capability I/O24tp3 - 3.3V TTL level bi-directional pin with 24 mA drive-sink capability O2 - 5V output pin with 2 mA drive-sink capability O12 - 5V output pin with 12 mA drive-sink capability O24p3 - 3.3V output pin with 24 mA drive-sink capability OD12 - Open-drain output pin with 12 mA sink capability 4.1 Bus Interface SYMBOL RESET# IOW# PIN 4 I/O INtsp3 FUNCTION Active-low system reset signal. 3 INtsp3 ISA configuration: Active-low signal to enable ISA I/O write accesses. IOR# 2 INtsp3 ISA configuration: Active-low signal to enable ISA I/O read accesses. IRQA 1 O24p3 ISA configuration: Interrupt output of Smart Card interface port. IRQB 48 O24p3 ISA configuration: Interrupt output of Memory Stick/SD Memory Card interface port. A0 47 INtp3 ISA configuration: Address bit 0. A1 46 INtp3 ISA configuration: Address bit 1. A2 45 INtp3 ISA configuration: Address bit 2. A3 44 INtp3 ISA configuration: Address bit 3. A4 43 INtp3 ISA configuration: Address bit 4. A5 42 INtp3 ISA configuration: Address bit 5. A6 41 INtp3 ISA configuration: Address bit 6. A7 39 INtp3 ISA configuration: Address bit 7. A8 38 INtp3 ISA configuration: Address bit 8. A9 37 INtp3 ISA configuration: Address bit 9. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 6 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 4.1 Bus Interface (continued.) SYMBOL AEN PIN 36 I/O INtp3 FUNCTION ISA configuration: Active-low I/O address enable signal. It is pulled high in DMA accesses. TC 35 INtp3 ISA configuration: This pin signals termination of DMA accesses. DACK# 34 INtp3 ISA configuration: DMA acknowledge. This active-low signal validates DMA accesses. DRQ 33 O24p3 ISA configuration: DMA request signal. D7 7 I/O12t ISA configuration: System data bit 7. D6 8 I/O12t ISA configuration: System data bit 6. D5 9 I/O12t ISA configuration: System data bit 5. D4 10 I/O12t ISA configuration: System data bit 4. D3 11 I/O12t ISA configuration: System data bit 3. D2 12 I/O12t ISA configuration: System data bit 2. D1 13 I/O24t ISA configuration: System data bit 1. D0 14 I/O24t ISA configuration: System data bit 0. PME# 5 OD12 Active-low PME event. 4.2 Smart Card Interface Pins SYMBOL SCLED PIN 16 I/O O24 FUNCTION This pin outputs an oscillating clock signal of various frequencies depending on traffic of primary Smart Card interface. SCPWR# 17 O24 Primary Smart Card interface power control signal. SCPSNT 18 INts Primary Smart Card interface card present detection Schmitttrigger input. SCCLK 19 O2 SCIO 20 I/O12t SCRST# 21 O12 Primary Smart Card interface clock output. Primary Smart Card interface data I/O channel. Primary Smart Card interface reset output. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 7 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 4.3 Memory Stick Interface/SD Memory Interface Pins SYMBOL MSLED PIN 32 I/O O24p3 FUNCTION MS/SD select = 0, MS function - This pin outputs an oscillating clock signal of various frequencies depending on traffic of primary Memory Stick interface; SDLED O24p3 MS/SD select = 1, SD function - This pin outputs an oscillating clock signal of various frequencies depending on traffic of primary SD memory card interface. SD_WP MSPWR# INts 31 O24p3 MS/SD select = 1, SD function – Write protect input signal. MS/SD select = 0, MS function - This pin is power control signal for primary Memory Stick interface; SDPWR# O24p3 MS/SD select = 1, SD function - This pin is power control signal for primary SD memory card interface. MSCLK 29 O24p3 MS/SD select = 0, MS function - This pin is SCLK for primary Memory Stick interface; SDCLK O24p3 MS/SD select = 1, SD function - This pin is CLK for primary SD memory card interface. MS1 28 O24p3 MS/SD select = 0, MS function - This pin is MS1 for primary Memory Stick interface; SD1 I/O24tp3 MS/SD select = 1, SD function - This pin is SD1 for primary SD memory card interface. MS2 27 I/O24tp3 MS/SD select = 0, MS function - This pin is MS2 for primary Memory Stick interface; SD2 I/O24tp3 MS/SD select = 1, SD function - This pin is SD2 for primary SD memory card interface. MS3 26 --- MS/SD select = 0, MS function - This pin is MS3 for primary Memory Stick interface; SD3 I/O24tp3 MS/SD select = 1, SD function - This pin is SD3 for primary SD memory card interface. MS4 25 INtsp3 MS/SD select = 0, MS function - This pin is MS4 for primary Memory Stick interface; SD4 I/O24tp3 MS/SD select = 1, SD function - This pin is SD4 for primary SD memory card interface. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 8 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 4.3 Memory Stick Interface/SD Memory Interface Pins (Continued.) SYMBOL MS5 PIN 24 I/O --- FUNCTION MS/SD select = 0, MS function - This pin is MS5 for primary Memory Stick interface; SD5 I/O24tp3 MS/SD select = 1, SD function - This pin is SD5 for primary SD memory card interface. 4.4 Crystal and Power Pins SYMBOL XOUT, XIN PIN 22, 23 FUNCTION Connected to a 48 MHz crystal and function as the working clock for all the media reader interfaces. VDD3V 40 +3.3V power supply for host interface, MSI/SDI interfaces, and internal core. VDD 15 VSS 6, 30 +5V power supply for Smart Card interface I/O pins. Ground. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 9 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 5 CONFIGURATION REGISTER 5.1 Plug and Play Configuration W83L519D implement compatible PNP protocol to access configuration registers for setting up different types of configurations. There are three Logical Devices (Logical Device 0 to Logical Device 2) in W83L518D/W83L519D which correspond to three major functions: Smart Card Interface (logical device 0), Memory Stick Interface/SD memory Interface (logical device 1), GPIO (logical device 2). Each Logical Device has its own configuration registers (CR30 and above). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7 first. 07h logical device select global registers 30h logical device control 3Fh 40h One set per logical device logical device configuration FEh 5.2 Compatible PnP 5.2.1 Extended Function Register W83L518D/W83L519D provide two methods to enter Extended Function mode (compatible PnP) and access configuration registers dependent on value of HEFRAS (bit 6 of CR26) as follows: HEFRAS address and value 0 write 83h to I/O address 2Eh twice 1 write 83h to I/O address 4Eh twice In Compatible PnP, a specific value (83h) must be written twice to the Extended Function Enable Register (EFER at I/O address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Function Index Register (EFIR, I/O address at 2Eh or 4Eh which is the same as EFER) to identify which configuration register is to be accessed. User can then access the addressed configuration register through the Extended Function Data Register (EFDR, I/O address at 2Fh or 4Fh). The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 10 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY After programming of the configuration register is completed, another specific value (AAh) should be written to EFER to leave Extended Function mode to prevent inadvertent accesses to those configuration registers. User may write a "1" to bit 5 of CR26 (LOCKREG) to prevent configuration registers from accidental accesses. 5.2.2 Extended Functions Enable Register (EFER) After a power-on reset, W83L518D/W83L519D enters the default operation mode. A specific value must be programmed into the Extended Function Enable Register (EFER) so that configuration registers can be accessed. On a PC/AT system, its I/O address is 2Eh or 4Eh (as described in previous section). 5.2.3 Extended Function Index Register (EFIR), Extended Function Data Register (EFDR) After entering Extended Function mode, Extended Function Index Register (EFIR) must be written with an index value (02h, 07h-FEh) to specify which configuration register is to be accessed through Extended Function Data Register (EFDR). EFIR is a write-only register at I/O address 2Eh or 4Eh (as described in section 6.2.1) on a PC/AT system and EFDR is a read/write register at I/O address 2Fh or 4Fh. 5.3 Configuration Sequence To program configuration registers, specific configuration sequence must be followed: (1) Write 83h to EFER twice to enter Extended Function mode. (2) Select logical device select register by writing 07h to EFIR. (3) Select logical device by writing a value to EFDR. (4) Select control/configuration register by writing its index to EFIR. (5) Access selected control/configuration register through EFDR. (6) Repeat step 4 ~ 5 as needed. (7) Leave Extended Function mode by writing AAh to EFER. Step 2 and step 3 are not necessary for accessing global register (index 00h to 2Fh). The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 11 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 5.3.1 Software programming example The following example is written in Intel 8086 assembly language. EFER and EFIR are assumed to be at 2Eh, and EFDR is at 2Fh. Use 4Eh/4Fh instead of 2Eh/2Fh if HEFRAS (bit 6 of CR26) is set. ;----------------------------------------------------------------------------------; Enter Extended Function mode, interruptible double-write | ;----------------------------------------------------------------------------------MOV DX, 2Eh MOV AL, 83h OUT DX, AL OUT DX, AL ;----------------------------------------------------------------------------; Configure logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX, 2Eh MOV AL, 07h OUT DX, AL ; point to Logical Device Number Reg. MOV DX, 2Fh MOV AL, 01h OUT DX, AL ; select logical device 1 ; MOV DX, 2Eh MOV AL, F0H OUT DX, AL ; select CRF0 MOV DX, 2Fh MOV AL, 3Ch OUT DX, AL ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;-----------------------------------------MOV DX, 2Eh MOV AL, AAh OUT DX, AL 5.4 Global Registers CR02 (Default 00h, write only) Bit [7:1]: Reserved. Bit 0: SWRST =0 Normal operation. =1 Software reset. CR07 (Default 00h) Bit [7:0]: Logical Device Number. CR20 (read only) Bit [7:0]: Device ID number (higher byte). = 71h The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 12 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY CR21 (read only) Bit [7:0]: Device ID number (lower byte) = 2Xh CR22 (Default 80h) Bit 7: SCPWD =0 Power down Smart Card interface. =1 No Power down. Bit 6: MSPWD =0 Power down Memory Stick interface. =1 No Power down. Bit 5: SDPWD =0 Power down SD memory card interface. =1 No Power down. Bit [4:0]: Reserved. CR23 (Default 00h) Bit 7: PME_EN. Power management event enable bit. =0 PME_L function is disabled. =1 Enable to issue a low pulse on PME_L when a power management event occurs. Bit 6: MSPME_EN. Memory Stick interface power management event enable bit. =0 =1 Memory Stick interface power management event is disabled. Enable Memory Stick interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit 5: SDPME_EN. SD memory card interface power management event enable bit. =0 =1 SD memory card interface power management event is disabled. Enable SD memory card interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit 4: SCPME_EN. Smart Card interface power management event enable bit. =0 =1 Smart Card interface power management event is disabled. Enable Smart Card interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit [3:0]: Reserved. CR24 (Default 00h) Bit 7: Reserved. Bit 6: MSPME_STS. Memory Stick interface power management event status bit. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 13 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY =0 =1 No Memory Stick interface power management event occurs. Memory Stick interface power management event occurs. Bit 5: SDPME_STS. SD memory card interface power management event status bit. =0 =1 No SD memory card interface power management event occurs. SD memory card interface power management event occurs. Bit 4: SCPME_STS. Smart Card interface power management event status bit. =0 =1 No Smart Card interface power management event occurs. No Smart Card interface power management event occurs. Bit [3:0]: Reserved. CR26 (Default 00h) Bit 7: Reserved Bit 6: HEFRAS, Extended Function Register Address Select. =0 Extended Function Registers are at 2Eh/2Fh. =1 Extended Function Registers are at 4Eh/4Fh. Bit 5: LOCKREG =0 Enable accesses of Configuration Registers. =1 Disable accesses of Configuration Registers. Bit [4:0]: Reserved 5.5 Logical Device 0 (Smart Card Interface) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. =0 Logical device is inactive. =1 Activates the logical device. CR60, CR61 (Default 0x00, 0x00) These two registers select Smart Card base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Smart Card interface. CRF0 (Default 0x00) Bit [7:1]: Reserved. Bit 0: SCPSNT_POL (Smart Card PreSeNT POLarity). SCPSNT polarity bit. =0 SCPSNT is active high. =1 SCPSNT is active low. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 14 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 5.6 Logical Device 1 (Memory Stick Interface) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. = 0: Logical device is inactive. = 1: Activates the logical device. CR60, CR61 (Default 0x00, 0x00) These two registers select MSI base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for MSI. CR74 (Default 0x04) Bit [7:4]: Reserved. Bit [3:0]: These bits select DRQ resource for MSI. 5.7 Logical Device 2 (GPIO) CR30 (Default 00h) Bit [7:3]: Reserved. Bit 2: Individual disable/enable bit for GPIO2. =0 GPIO2 is disabled if bit 0 is also "0". =1 GPIO2 is enabled. Bit 1: Individual disable/enable bit for GPIO1. =0 GPIO1 is disabled if bit 0 is also "0". =1 GPIO1 is enabled. Bit 0: Logical device disable/enable bit. =0 GPIO1 and GPIO2 are disabled/enabled dependent on bit 1 and 2 respectively. =1 Activates GPIO1 and GPIO2. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 15 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY CR60, CR61 (Both default 00h) Base address configuration registers: programmable at addresses from 0100h to 0FF8h on 4-byte boundary. Base address + 0 and base address + 1 are for GPIO1 as direction register and data register respectively while base address + 2 and base address + 3 are for GPIO2 as direction register and data register respectively. CRF0 (GP10 ~ GP17 direction register. Default FFh) When set to "1", respective GPIO port is programmed as an input port. When set to a "0", respective GPIO port is programmed as an output port. CRF1 (GP10 ~ GP17 data register. Default 00h) If a port is programmed to be an output port, its respective bit can be read/written and output to respective pin. If a port is programmed to be an input port, its respective bit reflects what is on respective pin. CRF2 (GP10 ~ GP17 inversion register. Default 00h) When set to "1", respective incoming/outgoing port value is inverted. When set to "0", respective incoming/outgoing port value is the same as in data register. CRF3 (GP20 ~ GP27 direction register. Default FFh) When set to "1", respective GPIO port is programmed as an input port. When set to a "0", respective GPIO port is programmed as an output port. CRF4 (GP20 ~ GP27 data register. Default 00h) If a port is programmed to be an output port, its respective bit can be read/written and output to respective pin. If a port is programmed to be an input port, its respective bit reflects what is on respective pin. CRF5 (GP20 ~ GP27 inversion register. Default 00h) When set to "1", respective incoming/outgoing port value is inverted. When set to "0", respective incoming/outgoing port value is the same as in data register. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 16 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 5.8 Logical Device 3 (SD Memory Interface) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. =0 Logical device is inactive. =1 Activates the logical device. CR60, CR61 (Default 0x00, 0x00) These two registers select SD Card interface base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for SD interface. CR74 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select DRQ resource for SD interface. CRF0 (Default 0x01) Bit [7:6]: Reserved. Bit 5: Set the output value of the DATA3 pin when bit4 is setted 1. =0 The DATA3 pin will output low. =1 The DATA3 pin will output high. Bit 4: Set the DATA3 (MS1 or MSB1) pin to output pin. =0 Set the DATA3 pin to bi-direction pin. =1 Set the DATA3 pin to output pin. Bit 3: Reserved. Bit 2: Select the pole of the GP11 card-detect pin. =0 When detecting the low signal indicate the card is inserted and high signal indicate the card is extracted. =1 When detecting the high signal incicate the card is inserted and low signal indicate the card is extracted. Bit 1: Select GP11 pin to detect card. =0 Don’t use the GP11 pin to detect card. =1 Use the GP11 (SCBPWR_L) pin to detect card. Bit 0: Select DATA3 pin to detect card. =0 Don’t use the DATA3 (MS1 or MSB1) to detect card. =1 Use the DATA3 (MS1 or MSB1) pin to detect card. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 17 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 6 ORDERING INSTRUCTION PART NO. PACKAGE W83L519D 7 REMARKS 48-pin LQFP HOW TO READ THE TOP MARKING SMART@IO W83L519D 114GBSB 1st line: Winbond logo and the SMART@IO Trademark 2nd line: The chip part number. 3rd line: Tracking code 114 G BSB 114: packages made in '01, week 14 G: assembly house ID; O means OSE, G means GR, … BSB: IC revision The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 18 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY 8 PACKAGE DRAWING AND DIMENSIONS Package- 48-pin LQFP H 36 25 37 24 48 13 H 12 1 θ Controlling dimension : Millimeters Symbol A A1 A2 b c D E e HD HE L L1 Y 0 Dimension in inch Dimension in mm Min Nom Max Min Nom Max 0.002 0.004 0.006 0.05 0.053 0.055 0.057 1.35 0.006 0.008 0.010 0.004 0.006 0.008 0.272 0.276 0.272 0.276 0.014 0.15 1.45 0.15 0.20 0.25 0.10 0.15 0.20 0.280 6.90 7.00 7.10 0.280 6.90 7.00 7.10 0.020 0.026 0.35 0.50 0.65 0.350 0.354 0.358 8.90 9.00 9.10 0.350 0.354 0.358 8.90 9.00 9.10 0.018 0.024 0.030 0.45 0.60 0.75 1.00 0.039 0.004 0 7 0.10 0 The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 0.10 1.40 19 7 Publication Release Date: Feb. 2002 Revision 0.50 W83L519D PRELIMINARY THE W83L519D SCHEMATIC LED SCLED 3.3U 1 2 3 4 SCRST# SCCLK LED SCPSNT R11 1 1 2 5VCC C5 C6 C7 C8 S1 S2 SCIO DRQ DACK# TC AEN 10 4 5 A9 A8 A7 6 3VCC 2 4 6 8 MOSFET P Q3 RP1 IRQB IRQA IOR# IOW# R12 4.7K 8P4R-4.7K A6 A5 A4 A3 A2 A1 A0 37 38 39 40 41 42 43 44 45 46 47 48 A9 A8 A7 VDD3V A6 A5 A4 A3 A2 A1 A0 IRQB W83519D 5VCC 24 23 22 21 20 19 18 17 16 15 14 13 MSA/SD5 XIN XOUT SCRST# SCIO SCCLK SCPSNT SCPWRCTL# SCLED VDD D0 D1 XIN XOUT SCRST# SCIO SCCLK SCPSNT SCPWCTL# SCLED D0 D1 D2 D3 D4 D5 D6 D7 SD_3VCC J2 + C2 10 MS4/SD4 MS3/SD3 3.3U LED SD_3VCC R14 D4 MSCLK/SDCLK MS2/SD2 MS1/SD1 MS5/SD5 330 LED SD read/write LED MSLED/SDLED R15 R17 10K 8 7 6 5 4 3 2 1 Q4 NPN R16 9 Wr_Pt_Vss 11 SD4 SD3 Vss2 SDCLK Vdd Vss1 SD2 SD1 D[7:0] U1 3VCC RESET# PME# SD5 SD_SOCKET 1M 1K Wr_Pt Memory Stick Socket S2 Circuit. 2 MS_3VCC U2 48MHZ 1 3 7 3VCC OUT D3 8 2 IRQA IOR# IOW# RESET# PME# VSS1 D7 D6 D5 D4 D3 D2 1 3 5 7 2 SD_3VCC 1 3VCC C1 C2 C3 C4 A[9..0] 3VCC R13 330 R10 20K 5 6 7 8 SC_SOCKET Circuit. MSPWCTL#/SDPWCTL# Q2 NPN 3 The SW is used to select sence level of card present SD Socket 9 S1 4.7K 2 2 J1 GND 4.7K 1 MSLED/SDLED MSPWCTL#/SDPWCTL# MSCLK/SDCLK MS1/SD1 MS2/SD2 MS3/SD3 MS4/SD4 MS5/SD5 SC_VCC 36 35 34 33 32 31 30 29 28 27 26 25 + C1 R9 1K 14 R7 SCA_VCC AEN TC DACK# DRQ MSLED/SDLED MSPWCTL#/SDPWCTL# VSS2 MSCLK/SDCLK MS1/SD1 MS2/SD2 MS3/SD3 MS4/SD4 2 330 1 2 3 4 5 6 7 8 9 10 11 12 330 D2 R6 1 1 SC_VCC SC read/write LED D1 SC_VCC 2 SC_VCC R8 5VCC MOSFET P Q1 SCPWCTL# VCC SC Socket (1) Circuit. 1 9 Q5 1 2 3.3U D5 MS_3VCC R21 J3 330 C7 LED MSLED/SDLED 1 2 2 X1 R20 48MHz 1M C4 4.7U C5 10P C6 10P Title Q6 NPN MS read/write LED Size B Date: Publication Release Date: Feb. 2002 Revision 0.50 The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners L1 2.2UH inbond MS_SOCKET 0.1U 1 1 The LC resonance circuit is used to filter base frequency of 3rd overtone crystal. 1 2 3 4 5 6 7 8 9 10 MS1/SD1 D6 R22 1K XOUT 4.7K MS2/SD2 MS3/SD3 MS4/SD4 MS5/SD5 MSCLK/SDCLK LED XIN R18 + C3 21 MOSFET P MS_3VCC R19 330 2 MSPWCTL#/SDPWCTL# 20 WINBOND ELECTRONICS CORP. Document Number W83L519D schematic circuit Monday, February 18, 2002 Rev 0.2 Sheet 2 of 2 W83L519D PRELIMINARY The W83L519D Schematic Winbond Recommended Reader Board <<Connector Side>> Extension Connectors 3VCC SD1 R_J1 MS2 MS3 MS4 MS5 MSCLK MSPWR# MSLED MS2 MS3 MS4 MS5 MSCLK MSPWR# MSLED (R_JP2) PIN 10 PIN 1 (R_JP1) PIN 10 MS4 10 2 1 2 3 4 5 6 7 8 9 10 PIN 1 MS1 R4 1M PIN 6 PIN 1 1 JP2 2 3VCC MS1 : 2x5 ; 2.54 mm(pitch) 2 3VCC R3 1M MS1 R_JP1,2: 1x10 ; 2.0 mm(pitch) R2 1M SD4 1 SD2 SD3 SD4 SD5 SDCLK SDPWR# SDLED SD2 SD3 SD4 SD5 SDCLK SDPWR# SDLED R1 R 1 SD1 SD1 2 1 2 3 4 5 6 7 8 9 10 1 JP1 1 3VCC SCAPSNT 2 5 (R_J1) R5 1M 5VCC 1 2 3 4 5 2 JP3 SCAPWR# SCAC4 SCAIO SCACLK SCAPWR# SCAC4 SCAIO SCACLK 6 7 8 9 10 SCARST# SCALED SCAC8 SCAPSNT SCARST# SCALED SCAC8 SCAPSNT HEADER 5X2 Note 1:These IRQ signals (IRQA,IRQB) can tie to IRQX(IRQ3,4,...) of ISA bus or compatible ones. Note 2:These DMA signals (DRQ,DACK#) can tie to which pair (DRQ1,DACK1#,...) of ISA bus or compatible ones.(except 16 bits DMA transaction) Note 3:The RESET# should be connected Note 4:There is either design. with a low asserted signal.(active low) function of SD and MS can be used and depeneded on the Note 5:If any of SC or MS/SD function isn't intened to use, signal SCPSNT should be tied to a pull-down resitor and MS4/SD4 to a pull-high one. (recommended: 4.7K Ohm ) Note 6:The trade marks and intellectual property rights of Memory Stick belong to SONY Corporation. Information check: http://www.memorystick.org inbond Title Size B Date: Publication Release Date: Feb. 2002 Revision 0.50 The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 21 WINBOND ELECTRONICS CORP. Document Number W83L519D schematic circuit Monday, February 18, 2002 Rev 0.2 Sheet 2 of 2 W83L519D PRELIMINARY Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners 22 Publication Release Date: Feb. 2002 Revision 0.50