WEDC WF4M32

WF4M32-XXX5
White Electronic Designs
4MX32 5V FLASH MODULE, SMD 5962-97612 (pending)
PRELIMINARY*
FEATURES
n Organized as 4Mx32
n
Access Times of 100, 120, 150ns
n
Packaging:
n User configurable as 8Mx16 or 16Mx8 in HIP and
G4T packages.
n Commercial, Industrial, and Military Temperature Ranges
• 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
n 5 Volt Read and Write. 5V ± 10% Supply.
n Low Power CMOS
• 68 lead, 40mm Low Profile CQFP ( Package
502 ), 3.5mm (0.140") height.
n Data Polling and Toggle Bit feature for detection of
program or erase cycle completion.
• 68 lead, Hermetic CQFP (G2T), 22.4mm
(0.880") square (Package 509) 4.57mm
(0.180") height. Designed to fit JEDEC 68
lead 0.990CQFJ footprint (Fig. 3)
n
n Supports reading or programming data to a sector
not being erased.
n RESET pin resets internal state machine to the read
mode.
Sector Architecture
• 32 equal size sectors of 64KBytes per each
2Mx8 chip
n Built-in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation, Separate Power
and Ground Planes to improve noise immunity
• Any combination of sectors can be erased. Also
supports full chip erase.
n
*This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Minimum 100,000 Write/Erase Cycles Minimum
Note:
For programming information refer to Flash Programming 16M5 Application Note.
FIG. 1
PIN CONFIGURATION FOR WF4M32-XH2X5
PIN DESCRIPTION
TOP VIEW
1
12
I/O8
23
I/O15
RESET
CS2
I/O9
34
I/O14
45
VCC
I/O24
I/O 0-31
Data Inputs/Outputs
A 0-21
Address Inputs
WE
Write Enables
I/O31
CS4
I/O25
56
I/O30
CS1-4
Chip Selects
OE
Output Enable
I/O10
GND
I/O13
I/O26
NC
I/O29
VCC
Power Supply
A14
I/O11
I/O12
A7
I/O27
I/O28
GND
Ground
RESET
Reset
A16
A10
OE
A12
A4
A1
A11
A9
A17
A21
A5
A2
A0
A15
WE
A13
A6
A3
BLOCK DIAGRAM
CS 1
CS3
CS 2
CS 4
A21
A18
VCC
I/O7
A8
A20
I/O23
I/O0
CS1
I/O6
I/O16
CS3
I/O22
I/O1
A19
I/O5
I/O17
GND
I/O21
I/O2
I/O3
I/O4
I/O18
I/O19
I/O20
OE
WE
A0-20
RESET
11
22
33
44
55
2M x 8
2M x 8
2M x 8
66
I/O0-7
August 2002 Rev. 4
1
2Mx 8
2M x 8
2M x 8
2M x 8
2M x 8
I/O8-15
I/O16-23
I/O24-31
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M32-XXX5
White Electronic Designs
PIN CONFIGURATION F OR WF4M32-XG4TX5
TOP VIEW
P IN D ESCRIPTION
I/O 0-31 Data Inputs/Outputs
NC
A0
A1
A2
A3
A4
A5
CS1
GND
CS3
WE
A6
A7
A8
A9
A10
VCC
FIG. 2
A0-21
Address Inputs
WE
Write Enable
CS1-4
Chip Selects
OE
Output Enable
VCC
Power Supply
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
RESET
Reset
GND
Ground
NC
Not Connected
BLOCK DIAGRAM
CS 1
OE
WE
BUFFER
RESET
2M x 8
A21
RESET
NC
VCC
A11
A12
A13
A14
A15
A16
CS2
OE
CS4
A17
A18
A19
A20
2M x 8
2M x 8
2M x 8
2M x 8
I/O0-7
I/O8-15
I/O16-23
P IN CONFIGURATION FOR WF4M32-XG2TX5
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
The White 68 lead G2T CQFP
fills the same fit and function
as the JEDEC 68 lead CQFJ or
68 PLCC. But the G2T has the
TCE and lead inspection
advantage of the CQFP form.
Address Inputs
WE
Write Enables
CS1-2
Banks Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
RESET
Reset
BLOCK DIAGRAM
8
2M x 8
2M x 8
2M x 8
2M x 8
8
2M x 8
2M x 8
2M x 8
A19
A20
OE
CS2
A17
NC
NC
NC
A18
A16
CS1
A15
A14
A13
A12
A11
A 0-20
CS 1
RESET
WE
OE
A0-20
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
VCC
I/O24-31
I/O 0-31 Data Inputs/Outputs
RESET
A0
A1
A2
A3
A4
A5
NC
GND
NC
WE
A6
A7
A8
A9
A10
VCC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
2M x 8
P IN D ESCRIPTION
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
2M x 8
2M x 8
TOP VIEW
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS 4
A0-20
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
FIG. 3
CS3
CS 2
A21
8
2M x 8
8
CS 2
I/O0-7
I/O8-15
I/O16-23
I/O24-31
Note: CS1& CS2 are used as bank select
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2
WF4M32-XXX5
White Electronic Designs
A BSOLUTE MAXIMUM RATINGS
Parameter
CAPACITANCE (PF)
(TA = +25°C, VIN = OV, F = 1.0MH Z )
Symbol
Ratings
Unit
VT
-2.0 to +7.0
V
Parameter
W
OE capacitance
COE
75
75
Voltage on Any Pin Relative to VSS
Power Dissipation
Symbol HIP (H2) CQFP (G2T) CQFP( G4T)
20
PT
8
Storage Temperature
Tstg
-65 to +125
°C
WE capacitance
CWE
75
75
20
Short Circuit Output Current
IOS
100
mA
CS capacitance
CCS
20
50
20
100,000 min
cycles
Data I/O capacitance
CI/O
30
30
30
Address input capacitance
CAD
75
75
20
Endurance - Write/Erase Cycles
(Mil Temp)
Data Retention (Mil Temp)
20
years
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V CC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.0
-
V CC + 0.5
V
Input Low Voltage
V IL
-0.5
-
+0.8
V
Operating Temperature (Mil.)
TA
-55
-
+125
°C
Operating Temperature (Ind.)
TA
-40
-
+85
°C
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Conditions
I LI
VCC = 5.5, VIN = GND to VCC
Min
HIP
Max
Min
G2T
Max
10
G4T
Min
Max
10
10
Unit
µA
I LOx32
VCC = 5.5, VIN = GND to VCC
10
10
10
µA
VCC Active Current for Read (1)
I CC1
CS = VIL, OE = VIH, f = 5MHz
320
215
345
mA
VCC Active Current for Program
or Erase (2)
I CC2
CS = VIL, OE = VIH
420
295
445
mA
VCC Standby Current
I CC3
VCC = 5.5, CS = VIH, f = 5MHz, RESET = VIH
Output Low Voltage
VOL
IOL = 12.0 mA, VCC = 4.5
Output High Voltage
VOH
IOH = -2.5 mA, VCC = 4.5
Low VCC Lock-Out Voltage
VLKO
20
2.0
95
mA
0.45
0.45
0.45
V
0.85 x
Vcc
3.2
0.85 x
Vcc
4.2
3.2
0.85 x
Vcc
4.2
3.2
V
4.2
V
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The
frequency component typically is less than 2mA/MHz, with OE at VIH.
2. Icc active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions V IL = 0.3V, V IH = V CC - 0.3V
HIP = 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
G2T = 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880")
square. Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (Fig. 3) (Package 509)
G4T = 68 lead, 40mm Low Profile CQFP, 3.5mm (0.140")
(Package 502 )
3
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WF4M32-XXX5
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AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter
Symbol
-100
Min
-120
Max
Min
-150
Max
Min
Unit
Max
Write Cycle Time
tAVAV
tWC
100
120
150
ns
Chip Select Setup Time
tELWL
tCS
0
0
0
ns
Write Enable Pulse Width
tWLWH
tWP
45
50
50
ns
Address Setup Time
tAVWL
tAS
0
0
0
ns
Data Setup Time
tDVWH
tDS
45
50
50
ns
Data Hold Time
tWHDX
tDH
0
0
0
ns
Address Hold Time
t WLAX
tAH
45
50
50
ns
Write Enable Pulse Width High
tWHWL
tWPH
20
20
20
ns
Duration of Byte Programming Operation (1)
tWHWH1
300
300
300
µs
Sector Erase (2)
tWHWH2
15
15
15
sec
Read Recovery Time before Write
t GHWL
V CC Setup Time
t VCS
0
0
0
50
50
50
Chip Programming Time
44
Chip Erase Time (3)
µs
44
256
Output Enable Hold Time (4)
µs
256
44
sec
256
sec
tOEH
10
10
10
ns
tRP
500
500
500
ns
RESET Pulse Width
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
AC CHARACTERISTICS FOR G2T PACKAGE – READ-ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter
Symbol
-100
Min
-120
Max
100
Min
-150
Max
120
Min
Unit
Max
Read Cycle Time
t AVAV
t RC
Address Access Time
t AVQV
tACC
100
120
150
150
ns
Chip Select Access Time
t ELQV
t CE
100
120
150
ns
Output Enable to Output Valid
t GLQV
tOE
40
50
55
ns
ns
Chip Select High to Output High Z (1)
t EHQZ
t DF
20
30
35
ns
Output Enable High to Output High Z (1)
t GHQZ
t DF
20
30
35
ns
Output Hold from Addresses, CS or OE Change,
whichever is First
t AXQX
tOH
RST Low to Read Mode (1)
0
20
t Ready
1. Guaranteed by design, not tested.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
0
4
0
20
ns
20
µs
WF4M32-XXX5
White Electronic Designs
AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
-100
Min
-120
Max
Min
-150
Max
Min
Unit
Max
Write Cycle Time
tAVAV
tWC
100
120
150
ns
Write Enable Setup Time
tWLEL
tWS
0
0
0
ns
Chip Select Pulse Width
tELEH
tCP
45
50
50
ns
Address Setup Time
tAVEL
tAS
0
0
0
ns
Data Setup Time
tDVEH
tDS
45
50
50
ns
Data Hold Time
tEHDX
tDH
0
0
0
ns
Address Hold Time
tELAX
tAH
45
50
50
ns
Chip Select Pulse Width High
tEHEL
tCPH
20
20
20
Duration of Byte Programming Operation (1)
t WHWH1
Sector Erase Time (2)
t WHWH2
Read Recovery Time
tGHEL
300
15
0
15
0
Chip Programming Time
44
Chip Erase Time (3)
Output Enable Hold Time (4)
300
10
256
10
µs
15
sec
44
sec
256
sec
0
44
256
tOEH
ns
300
10
µs
ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
5
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WF4M32-XXX5
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AC CHARACTERISTICS FOR G4T A ND H2 PACKAGES – WRITE/ERASE/P ROGRAM OPERATIONS - WE CONTROLLED
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter
Symbol
-100
Min
-120
Max
Min
-150
Max
Min
Unit
Max
Write Cycle Time
tAVAV
tWC
100
120
150
ns
Chip Select Setup Time
t ELWL
tCS
0
0
0
ns
Write Enable Pulse Width
tWLWH
tWP
45
50
50
ns
Address Setup Time
t AVWL
tAS
0
0
0
ns
Data Setup Time
tDVWH
tDS
45
50
50
ns
Data Hold Time
tWHDX
tDH
15
15
15
ns
Address Hold Time (1)
t WLAX
tAH
45
50
50
ns
Write Enable Pulse Width High (2)
tWHWL
tWPH
20
20
20
Duration of Byte Programming Operation (3)
t WHWH1
Sector Erase (4)
t WHWH2
Read Recovery Time before Write
t GHWL
V CC Setup Time
t VCS
300
ns
300
15
15
0
0
0
50
50
50
300
µs
15
sec
µs
µs
Chip Programming Time
44
44
44
sec
Chip Erase Time (5)
256
256
256
sec
Output Enable Hold Time (6)
tOEH
10
10
10
ns
tRP
500
500
500
ns
RESET Pulse Width
NOTES:
1. A21 must be held constant until WE or CS go high, whichever occurs first.
2. Guaranteed by design, but not tested.
3. Typical value for tWHWH1 is 7µs.
4. Typical value for tWHWH2 is 1sec.
5. Typical value for Chip Erase Time is 32sec.
6. For Toggle and Data Polling.
AC CHARACTERISTICS FOR G4T AND H2 PACKAGES – READ-ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C TO +125°C)
Parameter
Symbol
-100
Min
-120
Max
100
Min
-150
Max
120
Min
Unit
Max
Read Cycle Time
tAVAV
tRC
150
ns
Address Access Time
tAVQV
tACC
100
120
150
Chip Select Access Time
tELQV
tCE
100
120
150
ns
Output Enable to Output Valid
tGLQV
tOE
50
50
55
ns
ns
Chip Select High to Output High Z
tEHQZ
tDF
40
45
45
ns
Output Enable High to Output High Z
tGHQZ
tDF
40
45
45
ns
Output Hold from Addresses, CS or OE Change,
whichever is First
tAXQX
tOH
RST Low to Read Mode
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
0
tReady
0
20
6
0
20
ns
20
µs
WF4M32-XXX5
White Electronic Designs
AC CHARACTERISTICS FOR G4T A ND H2 P ACKAGES – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 5.0V, GND = 0V, TA = -55°C TO +125°C)
Parameter
Symbol
-100
Min
-120
Max
Min
-150
Max
Min
Unit
Max
Write Cycle Time
tAVAV
tWC
100
120
150
ns
Write Enable Setup Time
t WLEL
tWS
0
0
0
ns
Chip Select Pulse Width
tELEH
tCP
45
50
50
ns
Address Setup Time
tAVEL
tAS
0
0
0
ns
Data Setup Time
tDVEH
tDS
45
50
50
ns
Data Hold Time
tEHDX
tDH
15
15
15
ns
Address Hold Time (1)
t ELAX
tAH
45
50
50
ns
Chip Select Pulse Width High
tEHEL
tCPH
20
20
20
Duration of Byte Programming Operation (2)
tWHWH1
Sector Erase Time (3)
tWHWH2
Read Recovery Time
tGHEL
300
15
0
15
0
Chip Programming Time
44
Chip Erase Time (4)
tOEH
10
300
µs
15
sec
44
sec
256
sec
0
µs
44
256
Output Enable Hold Time (5)
ns
300
256
10
10
ns
NOTES:
1. A21 must be held constant until WE or CS go high, whichever occurs first.
2. Typical value for tWHWH1 is 7µs.
3. Typical value for tWHWH2 is 1sec.
4. Typical value for Chip Erase Time is 32sec.
5. For Toggle and Data Polling.
AC TEST CONDITIONS
FIG. 4 AC TEST CIRCUIT
Parameter
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
1.5
V
Input and Output Reference Level
Output Timing Reference Level
1.5
V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75W.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
FIG. 5 RESET T IMING DIAGRAM
RESET
tRP
tReady
7
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FIG. 6 AC WAVEFORMS F OR READ OPERATIONS
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
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WF4M32-XXX5
White Electronic Designs
WF4M32-XXX5
FIG. 7 WRITE/ERASE/PROGRAM OPERATION, WE C ONTROLLED
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D 7 is the output of the complement of the data written to each chip.
4. D OUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
9
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FIG. 8 AC W AVEFORMS C HIP/SECTOR E RASE OPERATIONS
NOTE:
1. SA is the sector address for Sector Erase.
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11
D0-D6
Data
WE
OE
CS
D7
t CH
tOEH
tCE
t OE
tWHWH 1 or 2
D7
D0-D6 = Invalid
D7 =
Valid Data
D0-D7
Valid Data
t OH
t DF
High Z
FIG. 9 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED A LGORITHM OPERATIONS
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FIG. 10 A LTERNATE CS C ONTROLLED PROGRAMMING O PERATION TIMINGS
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D 7 is the output of the complement of the data written to each chip.
4. D OUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
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WF4M32-XXX5
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WF4M32-XXX5
PACKAGE 402: 66 PIN , PGA TYPE , CERAMIC HEX-IN-LINE PACKAGE, H IP (H2)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
P ACKAGE 502: 68 L EAD, CERAMIC QUAD F LAT PACK , LOW PROFILE CQFP (G4T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETIC ALLY IN INCHES
13
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White Electronic Designs
P ACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
The White 68 lead G2T CQFP
fills the same fit and function
as the JEDEC 68 lead CQFJ or
68 PLCC. But the G2T has the
TCE and lead inspection
advantage of the CQFP form.
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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WF4M32-XXX5
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ORDERING INFORMATION
W F 4M32 - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
V PP PROGRAMMING VOLTAGE
5=5V
DEVICE GRADE:
M =Military Screened
I =Industrial
C =Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
PACKAGE TYPE:
H 2 =Ceramic Hex In line Package, HIP (Package 402)
G4T = 40mm Low Profile CQFP (Package 502)
G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)
ACCESS TIME (ns)
ORGANIZATION, 4M x 32
User configurable as 8M x 16 or 16M x 8 in HIP and G4T packages
FLASH
WHITE ELECTRONIC DESIGNS CORP.
DEVICE
TYPE
SECTOR SIZE S P E E D
PACKAGE
SMD NO.
4M x 32 5V Flash Module
64KByte
150ns
66 pin HIP (H2)
5962-97612 01HXX*
4M x 32 5V Flash Module
64KByte
120ns
66 pin HIP (H2)
5962-97612 02HXX*
4M x 32 5V Flash Module
64KByte
100ns
66 pin HIP (H2)
5962-97612 03HXX*
4M x 32 5V Flash Module
64KByte
150ns
68 lead CQFP Low Profile (G4T)
5962-97612 01HXX*
4M x 32 5V Flash Module
64KByte
120ns
68 lead CQFP Low Profile (G4T)
5962-97612 02HXX*
4M x 32 5V Flash Module
64KByte
100ns
68 lead CQFP Low Profile (G4T)
5962-97612 03HXX*
4M x 32 5V Flash Module
64KByte
150ns
68 lead CQFP Low Profile (G2T)
5962-97612 01HXX*
4M x 32 5V Flash Module
64KByte
120ns
68 lead CQFP Low Profile (G2T)
5962-97612 02HXX*
4M x 32 5V Flash Module
64KByte
100ns
68 lead CQFP Low Profile (G2T)
5962-97612 03HXX*
*Pending
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com