WEDC WV3HG128M72AER403D6SG

White Electronic Designs
WV3HG128M72AER-D6
ADVANCED*
1GB – 128Mx72 DDR2 SDRAM REGISTERED, w/PLL
FEATURES
DESCRIPTION
240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
Utilizes 800, 667, 533 and 400 MT/s DDR2 SDRAM
components
The WV3HG128M72AER is a 128Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory module
consists of eighteen 128Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
VCC = VCCQ = 1.8V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Product is lead-free
RoHS compliant
Package option
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• 240 Pin DIMM
• PCB – 29.97mm (1.18") Max
OPERATING FREQUENCIES
PC2-3200
PC2-4300
PC2-5300*
PC2-6400*
Clock Speed
200MHz
266MHz
333MHz
400MHz
CL-tRCD-tRP
3-3-3
4-4-4
5-5-5
6-6-6
* Consult factory for availability
March 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG128M72AER-D6
ADVANCED
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
RESET#
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3#
DQS3
VSS
DQ26
DQ27
VSS
CB0
CB1
VSS
DQS8#
DQS8
VSS
CB2
CB3
VSS
VCCQ
CKE0
VCC
NC
NC
VCCQ
A11
A7
VCC
A5
March 2005
Rev. 0
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
A4
VCCQ
A2
VCC
VSS
VSS
VCC
NC
VCC
A10/AP
BA0
VCCQ
WE#
CAS#
VCCQ
NC
NC
VCCQ
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5#
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
SA2
NC
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7#
DQS7
VSS
DQ58
DQ59
VSS
SDA
SCL
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
VSS
DQ4
DQ5
VSS
DM0/DQS9
NC/DQS9#
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1/DQS10
NC/DQS10#
VSS
NC
NC
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2/DQS11
NC/DQS11#
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3/DQS12
NC/DQS12#
VSS
DQ30
DQ31
VSS
CB4
CB5
VSS
DM8/DQS17
NC/DQS17#
VSS
CB6
CB7
VSS
VCCQ
NC
VCC
NC
NC
VCCQ
A12
A9
VCC
A8
A6
PIN NAMES
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
VCCQ
A3
A1
VCC
CK0
CK0#
VCC
A0
VCC
BA1
VCCQ
RAS#
S0#
VCCQ
ODT0
A13
VCC
VSS
DQ36
DQ37
VSS
DM4/DQS13
NC/DQS13#
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5/DQS14
NC/DQS14#
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
NC
NC
VSS
DM6/DQS15
NC/DQS15#
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7/DQS16
NC/DQS16#
VSS
DQ62
DQ63
VSS
VCCSPD
SA0
SA1
Pin Name
CK0,CK0#
CKE0
CB0-CB7
RAS#
CAS#
WE#
S0#
A0-A13
BA0,BA1
ODT0
SCL
SDA
SA0-SA2
DQ0-DQ63
DQS0-DQS17
DQS0#-DQS17#
VCC
VCCQ
VSS
VREF
VCCSPD
NC
RESET#
Function
Clock Inputs, positive line
Clock Enables
Check Bits
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
SDRAM Bank Address
On-die termination control
Serial Presence Detect(SPD) Clock Input
SPD Data Input/Output
SPD address
Data Input/Output
Data strobes
Data strobes complement
Core and I/O Power (1.8V)
I/O Power (1.8V)
Ground
Input/Output Reference
SPD Power
Spare pins, No connect
Register Reset Input
* These pins are not used in this module
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG128M72AER-D6
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
VSS
RS0#
DQS0
DQS0#
DM0/DQS9
NC/DQS9#
CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ8
DQ9
DQ10
DQ11
DM
I/O 0
I/O 1
I/O 2
I/O 3
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQS1
DQS1#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM1/DQS10
NC/DQS10#
DQS2
DQS2#
DM2/DQS11
NC/DQS11#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3#
DM3/DQS12
NC/DQS12#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS4
DQS4#
DM4/DQS13
NC/DQS13#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS5#
DM5/DQS14
NC/DQS14#
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS6#
Serial PD
DM6/DQS15
NC/DQS15#
DQ48
DQ49
DQ50
DQ51
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
SCL
DQ52
DQ53
DQ54
DQ55
DQS7
DQS7#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
SDA
WP A0
A1
A2
SA0 SA1 SA2
DM7/DQS16
NC/DQS16#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS8
DQS8#
VCCSPD
DM8/DQS17
NC/DQS17#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
S0#
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
CS# DQS DQS#
CB4
CB5
CB6
CB7
1:2
R
E
G
I
S
T
E
R
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
CK0
RS0# : DDR2 SDRAMs
RBA0 - RBA1 : DDR2 SDRAMs
CK0#
RA0 - RA13 : DDR2 SDRAMs
RRAS# : DDR2 SDRAMs
RESET#
RCAS# : DDR2 SDRAMs
P
L
L
OE
Serial PD
VCC/VCCQ
DDR2 SDRAMs
VREF
DDR2 SDRAMs
VSS
DDR2 SDRAMs
PCK0-PCK6, PCK8, PCK9 CK : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9# CK# : DDR2 SDRAMs
PCK7 CK : Register
PCK7# CK# : Register
RWE# : DDR2 SDRAMs
RCKE0 : DDR2 SDRAMs
RODT0 : DDR2 SDRAMs
RST#
PCK7
PCK7#
NOTE: All resistor values are 22 ohms unless otherwise specified.
March 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG128M72AER-D6
ADVANCED
RECOMMENDED DC OPERATING CONDITIONS
All Voltages Referenced to VSS
Rating
Parameter
Symbol
Min.
Type
Max.
Units
VCC
1.7
1.8
1.9
V
Supply Voltage for DLL
VCCL
1.7
1.8
1.9
V
4
Supply Voltage for Output
VCCQ
1.7
1.8
1.9
V
4
Input Reference Voltage
VREF
0.49*VCCQ
0.50*VCCQ
0.51*VCCQ
V
1, 2
Termination Voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
Supply Voltage
Notes
There is no specific device VCC supply voltage requirement for SSTL-1.8 compliance. However under all conditions VCCQ must be less than or equal to VCC.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VCCQ of the transmitting
device and VREF is expected to track variations in VCCQ.
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VCC, VCCQ and VCCDL tied together.
ABSOLUTE MAXIMUM RATINGS
SSTL_1.8V
Symbol
Parameter
Rating
Units
Notes
VCC
Voltage on VCC pin relative to VSS
- 1.0 V - 2.3 V
V
5
VCCQ
Voltage on VCCQ pin relative to VSS
- 0.5 V - 2.3 V
V
5
VCCL
Voltage on VCCL pin relative to VSS
- 0.5 V - 2.3 V
V
5
VIN, VOUT
Voltage on any pin relative to VSS
- 0.5 V - 2.3 V
V
5
-55 to +100
C
5, 6
TSTG
Storage Temperature
5. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
6. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = VCCQ = 1.8V
Parameter
Symbol
Max
Units
Input Capacitance: CK, CK#
CCK
11
pF
Input Capacitance: CKE, CS#
CI1
12
pF
Input Capacitance: Addr. RAS#, CAS#, WE#
CI2
12
pF
Input/Output Capacitance: DQ, DQS, DM, DQS#
CIO
10
pF
March 2005
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG128M72AER-D6
ADVANCED
DDR2 IDD SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD6W
IDD6R
IDD5B
IDD6
IDD7
March 2005
Rev. 0
Proposed Conditions
534
403
Units
Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2,420
2,250
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);
CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is
same as IDD6W
2,640
2,400
mA
730
670
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE;
Data bus inputs are FLOATING
1,110
1,110
mA
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
1,090
1,060
mA
Fast PDN Exit MRS(12) = 0mA
1,190
1,130
mA
Slow PDN Exit MRS(12) = 1mA
600
570
mA
Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,840
1,730
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
3,550
2,810
mA
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD6W
3,230
2,730
mA
Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
3,610
3,430
mA
740
680
mA
5,540
5,210
mA
Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data pattern is same as IDD6R; Refer to the following page for
detailed timing conditions
5
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White Electronic Designs
WV3HG128M72AER-D6
ADVANCED
AC TIMING PARAMETERS
0°C ≤ TA ≤ +70°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
534
PARAMETER
Data Strobe
Data
Clock
Clock cycle time
CL = 4
CL = 3
CK high-level width
CK low-level width
Half clock period
DQ output access time from CK/CK#
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
A DQ and DM input pulse width (for each input)
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go nonvalid, per access
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold time
DQS…DQ skew, DQS to last DQ valid, per group,
per access
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
Write command to first DQS latching transition
403
SYMBOL
tCK (4)
tCK (3)
MIN
3,750
5,000
MAX
8,000
8,000
MIN
5,000
5,000
MAX
8,000
8,000
UNIT
ps
ps
tCH
0.45
0.55
0.45
0.55
tCK
tCL
tHP
tAC
tHZ
tLZ
tDS
tDH
tDIPW
tQHS
tQH
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
0.45
MIN (tCH, tCL)
-500
0.55
0.45
MIN (tCH, tCL)
-600
0.55
tCK
ps
ps
ps
ps
ps
ps
tCK
ps
ps
tCK
tCK
ps
tCK
tCK
tAC MIN
100
225
0.35
tAC MIN
150
275
0.35
400
tHP - tQHS
0.35
0.35
-450
0.2
0.2
tDQSQ
tRPRE
tRPST
tWPRE
tWPST
tDQSS
+500
tAC MAX
tAC MAX
+450
450
tHP - tQHS
0.35
0.35
-500
0.2
0.2
300
0.9
0.4
0.35
0.4
WL - 0.25
1.1
0.6
0.6
WL + 0.25
+600
tAC MAX
tAC MAX
0.9
0.4
0.35
0.4
WL - 0.25
+500
350
ps
1.1
0.6
tCK
tCK
tCK
tCK
tCK
0.6
WL + 0.25
Continued on next page
March 2005
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG128M72AER-D6
ADVANCED
AC TIMING PARAMETERS (cont'd)
0°C ≤ TA ≤ +70°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Power-Down
ODT
Self
Refresh
Refresh
Command and Address
AC CHARACTERISTICS
PARAMETER
Address and control input pulse width for each input
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
6 Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
LOAD MODE command cycle time
OCD Drive mode delay
CKE low to CK,CK# uncertainty
REFRESH to REFRESH command interval
534
MIN
0.6
250
375
2
55
7.5
15
40
7.5
15
tWR + tRP
7.5
15
2
0
tIS + tCK + tIH
70,000
tRFC
105
70,000
Average periodic refresh interval
tREFI
Exit self refresh to non-READ command
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSNR
tXSRD
tIS
tAOND
tRFC (MIN) + 10
200
250
2
ODT turn-on
tAON
tAC (MIN)
ODT turn-off delay
tAOFD
2.5
ODT turn-off
tAOF
tAC (MIN)
ODT turn-on (power-down mode)
tAONPD
tAC (MIN) +
2000
ODT turn-off (power-down mode)
tAOFPD
tAC (MIN) +
2000
ODT to power-down entry latency
ODT power-down exit latency
Exit active power-down to READ command, MR[bit12=0]
Exit active power-down to READ command, MR[bit12=1]
A Exit precharge power-down to any non-READ command.
Exit precharge power-down to READ command.
CKE minimum high/low time
tANPD
tAXPD
tXARD
tXARDS
tXP
tXPRD
tCKE
3
8
2
6 - AL
2
6 - AL
3
March 2005
Rev. 0
403
SYMBOL
tIPW
tIS
tIH
tCCD
tRC
tRRD
tRCD
tRAS
tRTP
tWR
tDAL
tWTR
tRP
tMRD
tOIT
tDELAY
MAX
12
MIN
0.6
350
475
2
55
7.5
15
40
7.5
15
tWR + tRP
10
15
2
0
tIS + tCK + tIH
70,000
105
70,000
ns
7.8
µs
7.8
7
2
tAC (MAX) +
1000
2.5
tAC (MAX) +
600
2 x tCK +
tAC (MAX) +
1000
2.5 x tCK +
tAC (MAX) +
1000
tRFC (MIN) + 10
200
350
2
tAC (MIN)
2.5
tAC (MIN)
tAC (MIN) +
2000
tAC (MIN) +
2000
3
8
2
6 - AL
2
6 - AL
3
MAX
12
2
tAC (MAX) +
1000
2.5
tAC (MAX) +
600
2 x tCK +
tAC (MAX) +
1000
2.5 x tCK +
tAC (MAX) +
1000
UNIT
tCK
ps
ps
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
ns
tCK
ps
tCK
ps
tCK
ps
ps
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG128M72AER-D6
ADVANCED
ORDERING INFORMATION FOR D6
Part Number
Speed
CAS Latency
tRCD
tRP
Height*
WV3HG128M72AER534D6
266MHz/533Mb/s
4
4
4
29.97mm (1.18")
WV3HG128M72AER403D6
200MHz/400Mb/s
3
3
3
29.97mm (1.18")
NOTES:
• RoHS products. (“G” = RoHS Compliant)
• Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options.
(M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D6
Front View
133.35 (5.25)
3.00
(0.118)
Register
4.00
(0.157)
29.97
(1.18)
PLL
4.00
(0.157)
0.80 ± 0.002
(0.031 ± 0.002)
4.00 (0.157)
1.50 ± 0.10
(0.059 ± 0.004)
1.00 (0.039)
2.50 ± 0.20
(0.098 ± 0.007)
1.27 ± 0.10
0.05 ± .004
5.00
(0.196)
1.7
(0.066)
MAX
Back View
55.00 (2.165)
Register
63.00 (2.48)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
March 2005
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG128M72AER-D6
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 128M 72 A E R xxx D6 x G
WEDC
MEMORY
DDR 2
GOLD
DEPTH
BUS WIDTH
x4
1.8V
REGISTERED
SPEED (MHz)
PACKAGE 240 PIN
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
G = ROHS COMPLIANT
March 2005
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3HG128M72AER-D6
ADVANCED
Document Title
1GB – 128Mx72 DDR2 SDRAM REGISTERED, w/PLL
Revision History
Rev #
History
Release Date
Status
Rev 0
Created
March 2005
Advanced
March 2005
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com