WEDC W3EG64128S335JD3

W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED*
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
Double-data-rate architecture
Clock speeds of 100MHz, 133MHz, 166MHz and
200MHz
DDR200, DDR266, DDR333 and DDR400
The W3EG64128S is a 2x64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
component. The module consists of sixteen 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply:
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and 166 MHz)
• VCC = VCCQ = +2.6V ±0.1V (200 MHz)
JEDEC standard 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") MAX
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
May 2005
Rev. 5
DDR400 @ CL=3
200MHz
3-3-3
DDR333 @ CL=2.5
166MHz
2.5-3-3
DDR266 @ CL=2
133MHz
2-2-2
1
DDR266 @ CL=2
133MHz
2-3-3
DDR266 @ CL=2.5
133MHz
2.5-3-3
DDR200 @ CL=2
100MHz
2-2-2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
May 2005
Rev. 5
SYMBOL
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VCC
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VCCQ
CK1
CK1#
VSS
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VCC
DQ26
DQ27
A2
VSS
A1
NC
NC
VCC
PIN
47
48
49
50
51
52
53
54
55
56
57
56
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
SYMBOL
NC
A0
NC
VSS
NC
BA1
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
VCC
NC
DQ48
DQ49
VSS
CK2#
CK2
VCCQ
DQS6
DQ50
DQ51
VSS
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
PIN
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
SYMBOL
VSS
DQ4
DQ5
VCCQ
DQM0
DQ6
DQ7
VSS
NC
NC
NC
VCCQ
DQ12
DQ13
DQM1
VCC
DQ14
DQ15
CKE1
VCCQ
NC
DQ20
A12
VSS
DQ21
A11
DQM2
VCC
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VCCQ
DQM3
A3
DQ30
VSS
DQ31
NC
NC
VCCQ
CK0
CK0#
PIN NAMES
PIN
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
A0-A12
BA0-BA1
DQ0-DQ63
DQS0-DQS7
CK0, CK1, CK2
CK0#. CK1#, CK2#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
DQM0-DQM7
VCC
VCCQ
VSS
VREF
VCCSPD
SDA
SCL
SA0-SA2
VCCID
NC
SYMBOL
VSS
NC
A10
NC
VCCQ
NC
VSS
DQ36
DQ37
VCC
DQM4
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
CS1#
DQM5
VSS
DQ46
DQ47
NC
VCCQ
DQ52
DQ53
NC
VCC
DQM6
DQ54
DQ55
VCCQ
NC
DQ60
DQ61
VSS
DQM7
DQ62
DQ63
VCCQ
SA0
SA1
SA2
VCCSPD
2
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Data Strobe Input/Output
Clock Input
Clock Input
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data-in Mask
Power Supply
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
Serial clock
Address in EEPROM
VCC Indentification Flag
No Connect
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS4
DQM4
DQS0
DQM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS2
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQS6
DQM2
DQM6
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS3
DQM7
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DQM5
DQM1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS#
DQS5
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RAS#
RAS#: DDR SDRAMs
CAS#
CAS#: DDR SDRAMs
BA0-BA1
WE#
A0-A12
DQS
SERIAL PD
BA0-BA1: DDR SDRAMs
SCL
WP
WE#: DDR SDRAMs
A0-A12: DDR SDRAMs
CKE0
CKE0: DDR SDRAMs
CKE1
CKE1: DDR SDRAMs
VCCSPD
CLOCK INPUT
CK0, CK0#
4 SDRAMS
CK1, CK1#
6 SDRAMS
CK2, CK2#
6 SDRAMS
SDA
A0
A1
A2
SA0
SA1
SA2
SPD
VCCQ
DDR SDRAMs
VCC
DDR SDRAMs
VREF
DDR SDRAMs
VSS
DDR SDRAMs
NOTE: All resistor values are 22 ohms unless otherwise specified
May 2005
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 to 3.6
V
Voltage on VCC supply relative to VSS
VCC, VCCQ
-1.0 to 3.6
V
TSTG
-55 to +150
°C
Power Dissipation
PD
16
W
Short Circuit Current
IOS
50
mA
Storage Temperature
Note:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V
Parameter
Symbol
Min
Max
Unit
Supply Voltage
VCC
2.3
2.7
V
Supply Voltage
VCCQ
2.3
2.7
V
Reference Voltage
VREF
1.15
1.35
V
Termination Voltage
VTT
1.15
1.35
V
Input High Voltage
VIH
VREF + 0.15
VCCQ + 0.3
V
Input Low Voltage
VIL
-0.3
VREF -0.15
V
Output High Voltage
VOH
VTT + 0.76
—
V
Output Low Voltage
VOL
—
VTT-0.76
V
CAPACITANCE
TA = 25°C. f = 1MHz, VCC = 2.5V, VREF = 1.4V ± 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
CIN1
50
pF
Input Capacitance (RAS#,CAS#,WE#)
CIN2
50
pF
Input Capacitance (CKE0, CKE1)
CIN3
26
pF
Input Capacitance (CK0#,CK0)
CIN4
50
pF
Input Capacitance (CS0#, CS1#)
CIN5
26
pF
Input Capacitance (DQM0-DQM8)
CIN6
13
pF
Input Capacitance (BA0-BA1)
CIN7
50
pF
Data input/output capacitance (DQ0-DQ63)(DQS)
COUT
13
pF
May 2005
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
DDR400@
CL=3
Max
DDR333@
CL=2.5
Max
DDR266@
CL=2
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
DDR200@
CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge; tRC=tRC (MIN);
tCK=tCK (MIN); DQ,DM and DQS inputs changing
once per clock cycle; Address and control inputs
changing once every two cycles.
2200
1840
1840
1840
1840
1840
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst = 2;
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per clock cycle.
2520
2080
2080
2080
2080
2080
mA
Precharge PowerDown Standby Current
IDD2P
All device banks idle; Power-down mode; tCK=tCK
(MIN); CKE=(low)
80
80
80
80
80
80
rnA
Idle Standby Current
IDD2F
CS# = High; All device banks idle; tCK=tCK (MIN); CKE
= high; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS and
DM.
880
720
720
720
720
720
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down mode; tCK
(MIN); CKE=(low)
720
560
560
560
560
560
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank; ActivePrecharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle.
960
800
800
800
800
800
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
2640
2120
2120
2120
2120
2120
mA
Operating Current
IDD4W Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
2680
2360
2080
2080
2080
2080
rnA
3720
3120
3120
3120
3120
3120
mA
96
80
80
80
80
80
mA
4800
4040
4000
4000
4000
4000
mA
Auto Refresh Current
IDD5
tRC = tRC (MIN)
Self Refresh Current
IDD6
CKE £ 0.2V
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address
and control inputs change only during Active Read or
Write commands.
May 2005
Rev. 5
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1.
Typical Case : VCC=2.5V, T=25°C
1.
Typical Case : VCC=2.5V, T=25°C
2.
Worst Case : VCC=2.7V, T=10°C
2.
Worst Case : VCC=2.7V, T=10°C
3.
Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3.
Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4.
Timing Patterns :
4.
Timing Patterns :
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR400 (200MHz, CL=3) : tCK=5ns, BL=4,
tRCD=15*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
repeat the same timing with random address
changing; 100% of data changing at every
burst
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
•
DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
•
DDR400 (200MHz, CL=3) : tCK=5ns,
BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
R (0-3) = Read Bank 0-3
May 2005
Rev. 5
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 299: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
403
Parameter
335
262/263/265
202
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units
Access window of DQs from CK, CK#
tAC
-0.70
+0.70
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
Notes
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
16
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
16
CL=3
tCK (3)
5
7.5
6
13
7.5
13
7.5
13
ns
22
CL=2.5
tCK (2.5)
6
13
6
13
7.5
13
7.5
13
ns
22
CL=2
tCK (2)
7.5
13
7.5
13
7.5
13
10
13
tDH
0.45
0.45
DQ and DM input setup time relative to DQS
tDS
0.45
0.45
0.5
DQ and DM input pulse width (for each input)
tDIPW
1.75
1.75
1.75
Access window of DQS from CK, CK#
tDQSCK
-0.60
+0.60
-0.75
DQS input high pulse width
tDQSH
0.35
0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
0.35
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group,
per access
tDQSQ
Write command to first DQS latching transition
tDQSS
0.72
DQS falling edge to CK rising - setup time
tDSS
0.2
DQS falling edge from CK rising - hold time
tDSH
0.2
0.2
Half clock period
tHP
tCH, tCL
tCH, tCL
Data-out high-impedance window from CK, CK#
tHZ
ns
8,19
Data-out low-impedance window from CK, CK#
tLZ
-0.70
-0.70
-0.75
-0.75
ns
8,20
Clock cycle time
DQ and DM input hold time relative to DQS
+0.60
0.5
-0.60
0.40
1.28
0.45
0.75
1.25
0.2
+0.75
22
14,17
0.5
ns
14,17
1.75
ns
17
-0.75
0.5
0.75
1.25
0.2
+0.70
ns
ns
0.5
0.75
+0.75
ns
0.5
ns
1.25
tCK
0.2
tCK
0.2
0.2
tCK
tCH, tCL
tCH, tCL
ns
+0.70
+0.75
+0.75
13,14
18
Address and control input hold time (fast slew rate)
tIHf
0.60
0.75
0.90
0.90
ns
6
Address and control input set-up time (fast slew rate)
tISf
0.60
0.75
0.90
0.90
ns
6
Address and control input hold time (slow slew rate)
tIHs
0.60
0.80
1
1
ns
6
Address and control input setup time (slow slew rate)
tISs
0.60
0.80
1
1
ns
6
Address and control input pulse width (for each input)
tIPW
2.2
2.2
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
10
12
15
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH
tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
ns
Data hold skew factor
tQHS
ACTIVE to PRECHARGE command
tRAS
40
ACTIVE to READ with Auto precharge command
tRAP
15
15
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
55
60
60
65
ns
AUTO REFRESH command period
tRFC
70
72
75
75
ns
May 2005
Rev. 5
0.55
70,000
7
0.55
42
70,000
0.75
40
120,000
45
0.75
ns
120,000
ns
13,14
15
21
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 299: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
Parameter
ACTIVE to READ or WRITE delay
PRECHARGE command period
403
Symbol
Min
tRCD
15
335
Max
Min
262/263/265
Max
15
Min
Max
15
15
202
Min
Max
20
15
Units
Notes
ns
tRP
15
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
20
1.1
tCK
ns
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
10
12
15
15
ns
DQS write preamble
tWPRE
0.25
0.25
0.25
0.25
tCK
DQS write preamble setup time
tWPRES
0
0
0
0
ns
10,11
DQS write postamble
tCK
9
tWPST
0.4
Write recovery time
tWR
15
0.6
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
ns
Internal WRITE to READ command delay
tWTR
2
1
1
1
tCK
Data valid output window
NA
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns
13
70.3
μs
12
7.8
μs
12
REFRESH to REFRESH command interval
tREFC
Average periodic refresh interval
tREFI
Terminating voltage delay to VCC
tVTD
Exit SELF REFRESH to non-READ command
tXSNR
70
75
75
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
200
200
200
tCK
May 2005
Rev. 5
70.3
70.3
7.8
0
7.8
0
8
70.3
7.8
0
0
ns
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG64128S-D3
-JD3
ADVANCED
Notes
1.
All voltages referenced to VSS
2.
Tests for AC timing, IDD, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specifications and device operations are guaranteed for
the full voltage range specified.
3.
Outputs are measured with equivalent load:
11.
It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on tDQSS.
12.
The refresh period is 64ms. This equates to an average refresh
rate of 7.8125µs. However, an AUTO REFRESH command must
be asserted at least once every or 70.3µs; burst refreshing or
posting by the DRAM controller greater than eight refresh cycles is
not allowed.
13.
The valid data window is derived by achieving other specifications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid
window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
VTT
Output
(VOUT)
4.
5.
6.
50Ω
Reference
Point
30pF
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
The AC and DC input level specifications are defined in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
For slew rates less than 1V/ns and greater than or equal to 0.5V/
ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS
has an additional 50ps per each 100mV/ns reduction in slew rate
from the 500mV/ns. tIH has 0ps added, that is, it remains constant.
If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403
and 335, slew rates must be greater than or equal to 0.5V/ns.
14.
Referenced to each output group: x8 = DQS with DQ0-DQ7.
15.
READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfied prior to the internal precharge
command being issued.
16.
JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17.
DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to tDS and tDH for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
18.
tHP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.
7.
Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is
recognized as LOW.
19.
tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX)
condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX)
condition.
8.
tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
20.
For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
21.
CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tRFC has been satisfied.
22.
Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
9.
10.
The intent of the “Don’t Care” state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above VIHDC (MIN) then it must not transition
LOW (below VIHDC) prior to tDQSH (MIN).
This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
May 2005
Rev. 5
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR JD3
Part Number
Speed
CAS Latency
tRCD
tRP
Height*
W3EG64128S403JD3
200MHz/266Mb/s
3
3
3
30.48 (1.20)
W3EG64128S335JD3
166MHz/333Mb/s
2.5
3
3
30.48 (1.20)
W3EG64128S262JD3
133MHz/266Mb/s
2
2
2
30.48 (1.20")
W3EG64128S263JD3
133MHz/266Mb/s
2
3
3
30.48 (1.20)
W3EG64128S265JD3
133MHz/266Mb/s
2.5
3
3
30.48 (1.20")
W3EG64128S202JD3
100MHz/200Mb/s
2
2
2
30.48 (1.20")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
3.81
(0.150 MAX)
3.99
(0.157 (2x))
30.48
(1.20)
MAX
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
64.77
(2.550)
6.35
(0.250)
49.53
(1.950)
1.27
(0.050 TYP.)
1.78
(0.070)
3.99
(0.157)
(MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2005
Rev. 5
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency
tRCD
tRP
Height*
W3EG64128S403D3
200MHz/266Mb/s
3
3
3
30.48 (1.20)
W3EG64128S335D3
166MHz/333Mb/s
2.5
3
3
30.48 (1.20)
W3EG64128S262D3
133MHz/266Mb/s
2
2
2
30.48 (1.20")
W3EG64128S263D3
133MHz/266Mb/s
2
3
3
30.48 (1.20)
W3EG64128S265D3
133MHz/266Mb/s
2.5
3
3
30.48 (1.20")
W3EG64128S202D3
100MHz/200Mb/s
2
2
2
30.48 (1.20")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
3.81
(0.150 MAX)
3.99
(0.157 (2x))
30.48
(1.20)
MAX
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
64.77
(2.550)
6.35
(0.250)
49.53
(1.950)
1.27
(0.050 TYP.)
1.78
(0.070)
3.99
(0.157)
(MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2005
Rev. 5
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG64128S-D3
-JD3
White Electronic Designs
ADVANCED
Document Title
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date
Status
Rev 0
Created Datasheet
9-18-02
Advanced
Rev 1
1.1 Removed "ED" from part marking
4-04
Primary
Rev 2
2.1 Added Clock speed 133 & 200MHz
9-04
Advanced
Rev 3
3.1 Added AC specs
11-1-04
Advanced
5-05
Advanced
5-05
Advanced
3.2 Changed to Advanced until DDR400 is tested
Rev 4
4.1 Added lead-free and RoHS notes
4.2 Added source control notes
4.3 Added industrial temperature option
Rev 5
5.1 Added JEDEC standard PCB
5.2 D3 option "NOT RECOMMENDED FOR NEW DESIGNS"
May 2005
Rev. 5
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com