New Feature
Low Power + Quad 256-tap +
2-Wire bus + Up/Down interface
Dual Interface
Quad Digitally-Controlled (XDCPTM) Potentiometer
X9252
FEATURES
DESCRIPTION
• Quad solid state potentiometer
• 256 wiper tap points–0.4% resolution
• 2-wire serial interface for Write, Read, and
transfer operations of the potentiometer
• Up/down interface for individual potentiometers
• Wiper resistance: 40Ω typical
• Non-volatile storage of wiper positions
• Power On Recall. Loads saved wiper position on
Power-Up.
• Standby current < 20µA Max
• Maximum wiper current: 3mA
• VCC: 2.7V to 5.5V operation
• 2.8kΩ,10kΩ, 50kΩ, 100kΩ version of total pot
resistance
• Endurance: 100, 000 data changes per bit per
register
• 100 yr. data retention
• 24-Lead TSSOP
The X9252 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are implemented using 255 resistive elements in a series array.
Between each pair of elements are tap points connected to wiper terminals through switches. The position of each wiper on the array is controlled by the user
through the Up/Down (U/D) or 2-wire bus interface.
The wiper of each potentiometer has an associated
volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers (DRs) that can be directly written to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. At power-up, the device recalls
the contents of the default data registers DR00, DR10,
DR20, DR30, to the corresponding WCR.
Each DCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide
variety of applications including the programming of
bias voltages, the implementation of ladder networks,
and three resistor programmable networks.
FUNCTIONAL DIAGRAM
RH1
RH0
VCC
RH3
RH2
A2
A1
2-Wire
Interface
WCR0
DR00
DR01
DR02
DR03
A0
SDA
SCL
DS0
Up-Down
Interface
POWER UP,
INTERFACE
CONTROL
AND
STATUS
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
DS1
CS
U/D
VSS
REV 1.4.1 7/29/03
WP
RW0
RL0
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RW1
RL1
RW2
RL2
RW3
RL3
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X9252
PIN CONFIGURATION
TSSOP
DS0
1
24
DS1
A0
2
23
SCL
RW3
3
22
RL2
RH3
4
21
RH2
RL3
5
20
RW2
U/D
6
19
CS
VCC
7
8
18
VSS
RL0
17
RW1
RH0
9
16
RH1
RW0
10
RL1
A2
11
WP
12
15
14
13
X9252
A1
SDA
ORDERING INFO
Ordering Number
RTOTAL
Package
Operating Temperature Range
X9252YV24-2.7
2.8kΩ
24-lead TSSOP
0°C to 70°C
X9252YV24I-2.7
2.8kΩ
24-lead TSSOP
-40°C to +85°C
X9252WV24-2.7
10kΩ
24-lead TSSOP
0°C to 70°C
X9252WV24I-2.7
10kΩ
24-lead TSSOP
-40°C to +85°C
X9252UV24-2.7
50kΩ
24-lead TSSOP
0°C to 70°C
X9252UV24I-2.7
50kΩ
24-lead TSSOP
-40°C to +85°C
X9252TV24-2.7
100kΩ
24-lead TSSOP
0°C to 70°C
X9252TV24I-2.7
100kΩ
24-lead TSSOP
-40°C to +85°C
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X9252
PIN ASSIGNMENTS
TSSOP pin
Symbol
Brief Description
1
DS0
2
A0
3
RW3
Wiper terminal of DCP3.
4
RH3
High terminal of DCP3.
5
RL3
Low terminal of DCP3.
6
U/D
Increment/Decrement for Up/Down interface.
7
VCC
System Supply Voltage
8
RL0
Low terminal of DCP0.
9
RH0
High terminal of DCP0.
10
RW0
Wiper terminal of DCP0.
11
A2
Device Address for 2-wire bus.
12
WP
Hardware Write Protect
13
SDA
Serial Data Input/Output for 2-wire bus.
14
A1
DCP select for Up/Down interface.
Device Address for 2-wire bus.
Device Address for 2-wire bus.
15
RL1
Low terminal of DCP1.
16
RH1
High terminal of DCP1.
17
RW1
Wiper terminal DCP1.
18
VSS
System ground
19
CS
20
RW2
Wiper terminal of DCP2.
21
RH2
High terminal of DCP2.
22
RL2
Low terminal of DCP2.
23
SCL
Serial Clock for 2-wire bus.
24
DS1
DCP select for Up/Down interface.
REV 1.4.1 7/29/03
Chip select for Up/Down interface.
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X9252
ABSOLUTE MAXIMUM RATINGS
COMMENT
Junction Temperature under bias ......–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage at any digital interface pin
with respect to VSS.................................. –1V to +7V
VCC ............................................................ –1V to +7V
Voltage at any DCP pin with
respect to VSS ..........................................-1V to VCC
Lead temperature (soldering, 10 seconds).........300°C
IW (10 seconds) ................................................. ±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Max.
Device
Supply Voltage (VCC)(4) Limits
0°C
+70°C
X9252
2.7V to 5.5V
–40°C
+85°C
Temp
Min.
Commercial
Industrial
ANALOG CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
Parameter
Min.
End to end resistance
End to end resistance tolerance
Typ.(4)
-20
DCP to DCP resistance
matching
IW(5)
Wiper current
RW
Wiper resistance
0.75
-3.0
50
Unit
kΩ
2.8, 10,
50, 100
Power rating
RTOTAL
Matching
Max.
+20
%
50
mW
2.0
%
+3.0
mA
150
Ω
Test Conditions
Y, W, U, T versions respectively
25°C, each DCP
See test circuit
Wiper current =
VCC
RTOTAL
VTERM
Voltage on any DCP pin
Vss
(5)
Noise
Resolution
(1)
Vcc
V
-120
dBV
0.4
%
Absolute linearity
–1
+1
MI(3)
Relative linearity(2)
–0.3
+0.3
MI(3)
Ratiometric Temperature(5)
Coefficient
CH/CL/CW
Potentiometer Capacitance(5)
IOL
Leakage on DCP pins
REV 1.4.1 7/29/03
ppm/°C V(RH0)=V(RH1)=V(RH2)=V(RH3)=VCC
V(RL0)=V(RL1)=V(RL2)=V(RL3)=VSS
±300
Temperature coefficient of
resistance(5)
–20
Ref: 1kHz
+20 ppm/°C
10/10/25
0.1
10
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pF
See equivalent circuit
µA
Voltage at pin from VSS to VCC
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X9252
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Symbol
Units
Test Conditions
ICC1
VCC supply current
(Volatile write/read)
3
mA
ICC2
VCC supply current
(active)
VCC supply current
(nonvolatile write)
3
mA
5
mA
ISB
VCC current (standby)
20
µA
IL
Leakage current, bus
interface pins
Input HIGH voltage
Input LOW voltage
SDA pin output LOW
voltage
-10
10
µA
fSCL = 400kHz;SDA = Open; (for 2-Wire,
Active, Read and Volatile Write States
only)
fSCL = 200kHz; (for U/D interface,
increment, decrement)
fSCL = 400kHz; SDA = Open;
(for 2-Wire, Active, Nonvolatile Write State
only)
VCC = +5.5V; VIN = VSS or VCC; SDA =
VCC; (for 2-Wire, Standby State only)
Voltage at pin from VSS to VCC
VCC x 0.7
–1
VCC + 1
VCC x 0.3
0.4
V
V
V
IOL = 3mA
ICC3
VIH
VIL
VOL
Parameter
Limits
Max.
Min.
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum endurance
Data retention
100,000
100
Data changes per bit
Years
CAPACITANCE
Symbol
(5)
CIN/OUT
CIN(5)
Test
Max.
Units
Test Conditions
Input / Output capacitance (SDA)
Input capacitance (SCL, WP, DS0, DS1, CS, U/D,
A2, A1 and A0)
8
6
pF
pF
VOUT = 0V
VIN = 0V
POWER-UP TIMING
Symbol
tD(5)(9)
Parameter
Max.
Units
Power Up Delay from VCC power up (VCC
above 2.7V) to wiper position recall completed, and communication interfaces ready
for operation.
2
ms
A.C. TEST CONDITIONS
Input Pulse Levels
Input rise and fall times
Input and output timing threshold level
External load at pin SDA
REV 1.4.1 7/29/03
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
2.3kΩ to VCC and 100 pF to VSS
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X9252
2-WIRE INTERFACE TIMING(S)
Symbol
Parameter
Min.
Max.
Units
400
kHz
fSCL
Clock Frequency
tHIGH
Clock High Time
600
ns
tLOW
Clock Low Time
1300
ns
tSU:STA
Start Condition Setup Time
600
ns
tHD:STA
Start Condition Hold Time
600
ns
tSU:STO
Stop Condition Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
100
ns
tHD:DAT
SDA Data Input Hold Time
30
ns
tR(5)
SCL and SDA Rise Time
300
ns
SCL and SDA Fall Time
300
ns
tAA
SCL Low to SDA Data Output Valid Time
0.9
µs
tDH
SDA Data Output Hold Time
(5)
tF
(5)
(5)
0
Pulse Width Suppression Time at SCL and SDA inputs
tIN
(5)
50
Bus Free Time (Prior to Any Transmission)
tBUF
(5)
ns
ns
1200
ns
tSU:WPA
A0, A1, A2 and WP Setup Time
600
ns
tHD:WPA(5)
A0, A1, A2 and WP Hold Time
600
ns
SDA vs. SCL Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
SDA
(Input Timing)
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA
(Output Timing)
WP, A0, A1, and A2 Pin Timing
STOP
START
SCL
Clk 1
SDA IN
tSU:WP
tHD:WP
WP, A0, A1, or A2
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X9252
INCREMENT/DECREMENT TIMING
Limits
Symbol
Parameter
tCI
Typ.(4)
Min.
Units
Max.
CS to SCL Setup
600
ns
(5)
SCL HIGH to U/D, DS0 or DS1 change
600
ns
(5)
tDI
U/D, DS0 or DS1 to SCL setup
600
ns
tIL
SCL LOW period
2.5
µs
tIH
SCL HIGH period
2.5
µs
tIC
SCL inactive to CS inactive (Nonvolatile Store
Setup Time)
1
µs
CS deselect time (STORE)
10
ms
CS deselect time (NO STORE)
1
µs
tID
tCPHS
(5)
tCPHNS
(5)
SCL to RW change
tIW
100
SCL cycle time
tCYC
(5)
tR, tF
500
µs
5
µs
SCL input rise and fall time
500
µs
Increment/Decrement Timing
CS
tCYC
tCI
tIL
tIC
tIH
tCPHNS
tCPHS
90% 90%
10%
SCL
tID
tDI
tF
tR
U/D
DS0, DS1
tIW
RW
REV 1.4.1 7/29/03
MI
(3)
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X9252
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
tWC(8)(5)
Parameter
Non-volatile write cycle time
Typ.
Max.
Units
5
10
ms
XDCP TIMING
Symbol
Parameter
Min.
Max.
Units
(5)
SCL rising edge to wiper code changed, wiper response time after
instruction issued (all load instructions)
5
20
µs
tWRL
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))–V(RW(n)(expected))]/MI
V(RW(n)(expected)) = n(V(RH)-V(RL))/255 + V(RL), with n from 0 to 255.
(2) Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))–(V(RW(n)) + MI)]/MI , with n from 0 to 254
(3) 1 Ml = Minimum Increment = [V(RH)–V(RL)]/255.
(4) Typical values are for TA = 25°C and nominal supply voltage.
(5) This parameter is not 100% tested.
(6) Ratiometric temperature coefficient = (V(RW)T1(n)–V(RW)T2(n))/[V(RW)T1(n)(T1–T2)] x 106, with T1 & T2 being 2 temperatures, and
n from 0 to 255.
(7) Measured with wiper at tap position 255, RL grounded, using test circuit.
(8) tWC is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. It is the time
from a valid STOP condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of CS of a
valid “Store” operation of the Up/Down interface, to the end of the self-timed internal nonvolatile write cycle.
(9) The recommended power up sequence is to apply VCC/VSS first, then the potentiometer voltages. During power up, the data sheet
parameters for the DCP do not fully apply until tD after VCC reaches its final value. In order to prevent unwanted tap position
changes, or an inadvertant store, bring the CS pin high before or concurrently with the VCC pin on power up.
Test Circuit
Equivalent Circuit
Test Point
RTOTAL
RL
RH
CW
CH
RW
CL
Force
Current
RW
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X9252
PIN DESCRIPTIONS
UP OR DOWN CONTROL (U/D)
Bus Interface Pins
The U/D input pin is held HIGH during increment operations and held LOW during decrement operations.
SERIAL DATA INPUT/OUTPUT (SDA)
DCP SELECT (DS1-DS0)
The SDA is a bidirectional serial data input/output pin for
the 2-wire interface. It receives device address, operation
code, wiper register address and data from a 2-wire
external master device at the rising edge of the serial
clock SCL, and it shifts out data after each falling edge of
the serial clock SCL.
The DS1-DS0 select one of the four DCPs for an Up/
Down interface operation.
HARDWARE WRITE PROTECT INPUT (WP)
SDA requires an external pull-up resistor, since it’s an
open drain output.
When the WP pin is set low, “write” operations to non
volatile DCP Data Registers are disabled. This
includes both 2-wire interface non-volatile “Write”, and
Up/Down interface “Store” operations.
SERIAL CLOCK (SCL)
DCP Pins
This input is the serial clock of the 2-wire and Up/Down
interface.
RH0, RL0, RH1, RL1, RH2, RL2, RH3, AND RL3
DEVICE ADDRESS (A2–A0)
The Address inputs are used to set the least significant
3 bits of the 8-bit 2-wire interface slave address. A
match in the slave address serial data stream must be
made with the Address input pins in order to initiate
communication with the X9252. A maximum of 8
devices may occupy the 2-wire serial bus.
These pins are equivalent to the terminal connections
on mechanical potentiometers. Since there are 4
DCPs, there is one set of RH and RL for each DCP.
RW0, RW1, RW2, AND RW3
The wiper pins are equivalent to the wiper terminal of
mechanical potentiometers. Since there are four
DCPs, there are 4 RW pins.
CHIP SELECT (CS)
When the CS pin is low, increment or decrement
operations are possible using the SCL and U/D pins.
The 2-wire interface is disabled at this time. When CS
is high, the 2-wire interface is enabled.
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X9252
PRINCIPLES OF OPERATION
The X9252 is an integrated circuit incorporating four
resistor arrays, their associated registers and counters,
and the serial interface logic providing direct communication between the host and the digitally controlled
potentiometers. This section provides detail description
of the following:
– Resistor Array
– Up/Down Interface
– 2-wire Interface
Resistor Array Description
The X9252 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (RHi and RLi inputs). (See Figure 1.)
At both ends of each array and between each resistor
segment is a switch connected to the wiper (RWi) pin.
Within each individual array only one switch may be
turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select and enable one of 256 switches
(see Table 1). Note that each wiper has a dedicated
WCR. When all bits of a WCR are zeroes, the switch
closest to the corresponding RL pin is selected. When
all bits of a WCR are ones, the switch closest to the
corresponding RH pin is selected.
The WCR is volatile and may be written directly. There
are four non-volatile Data Registers(DR) associated
with each WCR. Each DR can be loaded into WCR. All
DRs and WCRs can be read or written.
Power Up and Down Requirements
During power up, CS must be high, to avoid inadvertant “store” operations. At power up, the contents of
Data Registers DR00, DR10, DR20, and DR30, are
loaded into the corresponding wiper counter register.
Figure 1. Detailed Block Diagram of one DCP
i = 0, 1, 2, and 3
Four
Non-Volatile
Data
Registers
DRi0, DRi1,
DRi2, and
DRi3
Volatile
8-bit
Wiper
Counter
Register
WCRi
WCR[7:0] 255
= FF hex
RHi
254
253
252
One
of
256
Decoder
WP
SCL
SDA
A2, A1, A0
CS
Interface Control and
Volatile Status Register (SR)
2
(Shared by the Four DCPs)
1
U/D
DS1, DS0
WCR[7:0]
= 00 hex
0
RLi
RWi
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X9252
UP/DOWN INTERFACE OPERATION
The SCL, U/D, CS, DS0 and DS1 inputs control the
movement of the wiper along the resistor array. With
CS set LOW the device is selected and enabled to
respond to the U/D and SCL inputs. HIGH to LOW
transitions on SCL will increment or decrement
(depending on the state of the U/D input) a wiper
counter register selected by DS0 and DS1. The output
of this counter is decoded to select one of 256 wiper
positions along the resistor array.
The value of the counter is stored in nonvolatile Data
Registers DRi0 whenever CS transitions HIGH while
the SCL and WP inputs are HIGH. “i” indicates the
DCP number selected with pins DS1 and DS0. During
a “Store” operation bits DRSel1 and DRSel0 in the
Status Register must be both “0”, which is their power
up default value. Other combinations are reserved and
must not be used.
The system may select the X9252, move the wiper,
and deselect the device without having to store the latest wiper position in nonvolatile memory. After the
wiper movement is performed as described above and
once the new position is reached, the system must
keep SCL LOW while taking CS HIGH. The new wiper
postion will be maintained until changed by the system
or until a power-down/up cycle recalled the previousely
stored data.
The state of U/D may be changed while CS remains
LOW. This allows the host system to enable the device
and then move the wiper up and down until the proper
trim is attained. The 2-wire interface is disabled while
CS remains LOW.
Table 1. DCP Selection for Up/Down Control
DS1
DS0
Selected DCP
0
0
DCP0
0
1
DCP1
1
0
DCP2
1
1
DCP3
MODE SELECTION FOR UP/DOWN CONTROL
CS
U/D
Mode
L
H
Wiper Up
L
L
Wiper Down
H
X
Store Wiper Position to nonvolatile memory if WP pin is
high. No store, return to standby, if WP pin is low.
X
X
Standby
L
X
No Store, Return to Standby
L
H
Wiper Up (not recommended)
L
L
Wiper Down
(not recommended)
H
This procedure allows the system to always power-up
to a preset value stored in nonvolatile memory; then
during system operation minor adjustments could be
made. The adjustments might be based on user preference, system parameter changes due to temperaure
drift, etc.
REV 1.4.1 7/29/03
SCL
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X9252
2-WIRE SERIAL INTERFACE
Protocol Overview
The device supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is called the master and the device being
controlled is called the slave. The master always
initiates data transfers, and provides the clock for both
transmit and receive operations. The X9252 operates
as a slave in all applications.
All 2-wire interface operations must begin with a
START, followed by a Slave Address byte. The Slave
Address selects the X9252, and specifies if a Read or
Write operation is to be performed.
All Communication over the 2-wire interface is
conducted by sending the MSB of each byte of data
first.
Serial Clock and Data
Data states on the SDA line can change only while
SCL is LOW. SDA state changes while SCL is HIGH
are reserved for indicating START and STOP
conditions. See Figure 2. On power up of the X9252,
the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not
respond to any command until this condition has been
met. See Figure 2.
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.
Figure 2. Valid Data Changes, Start, and Stop Conditions
SCL
SDA
START
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DATA
DATA
DATA
STABLE CHANGE STABLE
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STOP
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X9252
Serial Acknowledge
An ACK (Acknowledge), is a software convention used
to indicate a successful data transfer. The transmitting
device, either master or slave, releases the bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data. See Figure 3.
The device responds with an ACK after recognition of a
START condition followed by a valid Slave Address
byte. A valid Slave Address byte must contain the
Device Type Identifier 0101, and the Device Address
bits matching the logic state of pins A2, A1, and A0.
See Figure 4.
If a write operation is selected, the device responds
with an ACK after the receipt of each subsequent
eight-bit word.
In the read mode, the device transmits eight bits of
data, releases the SDA line, and then monitors the line
for an ACK. The device continues transmitting data if
an ACK is detected. The device terminates further data
transmissions if an ACK is not detected. The master
must then issue a STOP condition to place the device
into a known state.
Figure 3. Acknowledge Response From Receiver
SCL from
Master
1
8
9
SDA Output from
Transmitter
SDA Output from
Receiver
START
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ACK
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X9252
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to figure 4.). This byte
includes three parts:
then no ACK is returned. If the high voltage cycle is
completed, an ACK is returned and the master can
then proceed with a new Read or Write operation.
(Refer to figure 5.)
– The four MSBs (SA7-SA4) are the Device Type
Identifier, which must always be set to 0101 in order
to select the X9252.
Figure 5. Acknowledge Polling Sequence
Byte load completed by issuing
STOP. Enter ACK Polling
– The next three bits (SA3-SA1) are the Device
Address bits (AS2-AS0). To access any part of the
X9252’s memory, the value of bits AS2, AS1, and
AS0 must correspond to the logic levels at pins A2,
A1, and A0 respectively.
Issue START
– The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being
addressed. When the R/W bit is “1”, then a Read
operation is selected. A “0” selects a Write operation.
Issue Slave Address
Byte (Read or Write)
Figure 4. Slave Address (SA) Format
ACK returned?
SA7
0
SA6 SA5
1
0
Device Type
Identifier
Slave Address
Bit(s)
SA4
SA3
SA2
SA1
SA0
1
AS2
AS1
AS0
R/W
Device
Address
YES
SA3–SA1
Device Address
SA0
High Voltage
complete. Continue command
sequence.
Description
Device Type Identifier
NO
Issue STOP
Continue normal Read or Write
command sequence
Read or Write Operation Select
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is
correctly issued (including the final STOP condition),
the X9252 initiates an internal high voltage write cycle.
This cycle typically requires 5 ms. During this time, any
Read or Write command is ignored by the X9252.
Write Acknowledge Polling is used to determine
whether a high voltage write cycle is completed.
During acknowledge polling, the master first issues a
START condition followed by a Slave Address Byte.
The Slave Address Byte contains the X9252’s Device
Type Identifier and Device Address. The LSB of the
Slave Address (R/W) can be set to either 1 or 0 in this
case. If the device is busy within the high voltage cycle,
REV 1.4.1 7/29/03
NO
YES
Read or
Write
SA7–SA4
Issue STOP
PROCEED
2-WIRE SERIAL INTERFACE OPERATION
X9252 Digital Potentiometer Register Organization
Refer to the Functional Diagram on page 1. There are
four Digitally Controlled Potentiometers, referred to as
DCPi, i=0,1,2,3. Each potentiometer has one volatile
Wiper Control Register(WCR) with the corresponding
number, WCRi, i=0,1,2,3. Each potentiometer also has
four nonvolatile registers to store wiper position or
general data, these are numbered DRi0, DRi1, DRi2
and DRi3, i=0,1,2,3.
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X9252
The registers are organized in five pages of four, with
one page consisting of the WCRi (i=0-3), a second
page containing the DRi0 (i=0-3), a third page containing the DRi1, and so forth. These pages can be written
to four bytes at at time. In this manner all four potentiometer WCRs can be updated in a single serial write
(see “Page Write Operation” on page 17), as well as all
four registers of a given page in the DR array.
The unique feature of the X9252 device is that writing
or reading to a Data Register of a given DCP automatically updates/moves the WCR of that DCP with the
content of the DR. In this manner data can be moved
from a particular DCP register to that DCP’s WCR just
by performing a 2-wire read operation. Simultaneously, that data byte can be utilized by the host.
Status Register Organization
The Status Register (SR) is used in read and write
operations to select the appropriate DCP register.
Before any DCP register can be accessed, the SR
must be set to the correct value. It is accessed by
setting the Address Byte to 07h (Write Slave Address,
followed by Byte Address 07h). The SR is volatile and
defaults to 00h on power up. It is an 8-bit register
containing three control bits in the 3 LSBs as follows:
7
6
5
4
Reserved
3
2
1
DRSel1 DRSel0
Register Selected
DRSel1
DRSel0
NVEnable
WCRi
DRi0
DRi1
DRi2
DRi3
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Note:
X means either 0 or 1, i = 0,1,2, or 3
DCP Addressing for 2-wire Interface
Once the register number has been selected by a 2wire instruction, then the DCP number is determined
by the Address Byte of the following instruction. Note
again that this enables a complete page write of the
DRs of all four potentiometers at once. The register
addresses accessible in the X9252 include:
Table 3. Addressing for 2-wire Interface Address
Byte
Address (hex)
Contents
0
1
2
3
4
5
6
7
DCP 0
DCP 1
DCP 2
DCP 3
Not Used
Not Used
Not Used
Status Register
0
NVEnable
Bits DRSel0 and DRSel1 determine which Data Register of a DCP is selected in a given operation. NVEnable is used to select the volatile WCR if “0”, and one
of the nonvolatile DCP registers if “1”. Table 2 shows
this register organization. “Store” operations using the
Up/Down interface require that bits DRSel1 and
DRSel0 are set to “0”.
REV 1.4.1 7/29/03
Table 2. Status Register Contents for WCR and DR
Selection for 2-Wire Interface
All other address bits in the Address Byte must be set
to “0” during 2-wire write operations and their value
should be ignored when read.
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X9252
Byte Write Operation
For any Byte Write operation, the X9252 requires the
Slave Address byte, an Address Byte, and a Data Byte
(See Figure 6). After each of them, the X9252
responds with an ACK. The master then terminates the
transfer by generating a STOP condition. At this time, if
the write operation is to a volatile register (WCR, or
SR), the X9252 is ready for the next read or write
operation. If the write operation is to a nonvolatile
register (DR), and the WP pin is high, the X9252
begins the internal write cycle to the nonvolatile
memory. During the internal nonvolatile write cycle, the
X9252 does not respond to any requests from the
master. The SDA output is at high impedance.
The SR bits and WP pin determine the register being
accessed through the 2-wire interface. See Table 1 on
page 11.
As noted before, that any write operation to a Data
Register (DR), also writes to the WCR of the corresponding DCP.
For example, to write 3Ahex to the Data Register 1 of
DCP2 the following sequence is required:
START
Slave Address
ACK
Address Byte
ACK
Data Byte
ACK
STOP
START
Slave Address
ACK
Address Byte
ACK
Data Byte
ACK
STOP
0101 0000
(Hardware Address = 000,
and a Write command)
0000 0111
(Indicates Status Register
address)
0000 0011
(Data Register 1 and
NVEnable selected)
0101 0000
(Hardware address = 000,
Write command)
0000 0010
(Access DCP2)
0011 1010
(Write Data Byte 3Ah)
During the sequence of this example, WP pin must be
high, and A0, A1, and A2 pins must be low. When completed, the DR21 register will be set to 3Ah, and also
the WCR2.
Figure 6. Byte Write Sequence
Write
Signals from
the Master
Signal at SDA
Signals from
the Slave
REV 1.4.1 7/29/03
S
t
a
r
t
01 01
S
t
o
p
Data
Byte
Address
Byte
Slave
Address
0
A
C
K
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A
C
K
A
C
K
16 of 21
X9252
Page Write Operation
As stated previously, the memory is organized as a
single Status Register (SR), and four pages of four
registers each. Each page contains one Data Register
for each DCP. The order of the bytes within a page is
DR0i, followed by DR1i, followed by DR2i, and then
DR3i, with i being the Data Register number (0, 1, 2, or
3). Normally a page write operation will be used to
efficiently update all four data registers and WCR in a
single write command, starting at DCP0 and finishing
with DCP3.
In order to perform a Page Write operation to the memory array, the NVEnable bit in the SR must first be set
to “1”.
A Page Write operation is initiated in the same manner
as the byte write operation; but instead of terminating
the write cycle after the first data byte is transferred,
the master can transmit up to 4 bytes (See Figure 7).
After the receipt of each byte, the X9252 responds with
an ACK, and the internal DCP address counter is
incremented by one. The page address remains
constant. When the counter reaches the end of the
page (DR3i, 03hex), it “rolls over” and goes back to the
first byte of the same page (DR0i, 00hex).
For example, if the master writes 3 bytes to a page
starting at location DR22, the first 2 bytes are written to
locations DR22 and DR32, while the last byte is written
to locations DR02. Afterwards, the DCP counter would
point to location DR12. If the master supplies more
than 4 bytes of data, then new data overwrites the
previous data, one byte at a time.
The master terminates the loading of Data Bytes by
issuing a STOP condition, which initiates the
nonvolatile write cycle. As with the Byte Write
operation, all inputs are disabled until completion of the
internal write cycle. If the WP pin is high, the
nonvolatile write cycle doesn’t start and the bytes are
discarded.
Notice that the Data Bytes are also written to the WCR
of the corresponding DCPs, therefore in the above
example, WCR2, WCR3, and WCR0 are also written.
Figure 7. Page Write Operation
Write
Signals from
the Master
S
t
a
r
t
2<n<4
Address
Byte
Slave
Address
Data Byte (1)
S
t
o
p
Data Byte (n)
Signal at SDA
01 01
Signals from
the Slave
REV 1.4.1 7/29/03
0
A
C
K
A
C
K
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A
C
K
A
C
K
17 of 21
X9252
Move/Read Operation
The Move/Read operation simultaneously reads the
contents of a Data Register (DR) and moves the
contents into the corresponding DCP’s WCR. If the
DRs of more than one DCP are read, then the WCRs
of all those DCPs are updated with the content of their
corresponding DR. Move/Read operation consists of a
one byte, or three byte instruction followed by one or
more Data Bytes (See Figure 8). To read an arbitrary
byte, the master initiates the operation issuing the
following sequence: a START, the Slave Address byte
with the R/W bit set to “0”, an Address Byte, a second
START, and a second Slave Address byte with the R/W
bit set to “1”. After each of the three bytes, the X9252
responds with an ACK. Then the X9252 transmits Data
Bytes as long as the master responds with an ACK
during the SCL cycle following the eigth bit of each
byte. The master terminates the Move/Read operation
(issuing a STOP condition) following the last bit of the
last Data Byte.
The first byte being read is determined by the current
DCP address and by the Status Register bits,
according to Table 2 on page 15. If more than one byte
is read, the DCP address is incremented by one after
each byte, in the same way as during a Page Write
operation. After reaching DCP3, the DCP address
“rolls over” to DCP0.
On power up, the Address pointer is set to the Data
Register 0 of DCP0.
Figure 8. Move/Read Sequence
One or more Data Bytes
Signals
from the
Master
S
t
a
r
t
Signal at
SDA
Signals from
the Slave
Slave
Address
with
R/W=0
01 01
S
t
a
r
t
Address
Byte
Slave
Address
with
R/W=1
01 01
0
A
C
K
A
C
K
A
C
K
S
t
o
p
A
C
K
1
A
C
K
Setting the Current Address
First Read
Data Byte
Last Read
Data Byte
Current Address Read
Random Address Read
REV 1.4.1 7/29/03
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X9252
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
+5V
VO
100KΩ
–
10KΩ
10KΩ
}
VO
TL072
}
+
R1
R2
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
10KΩ
+5V
REV 1.4.1 7/29/03
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X9252
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
REV 1.4.1 7/29/03
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X9252
PACKAGING INFORMATION
24-Lead Plastic, TSSOP, Package Code V24
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
(4.16) (7.72)
Gage Plane
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
ALL MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
LIMITED WARRANTY
©Xicor, Inc. 2003 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, BiasLock and XDCP are also trademarks of
Xicor, Inc. All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.4.1 7/29/03
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Characteristics subject to change without notice.
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