X9258
®
Low Noise/Low Power/2-Wire Bus/256 Taps
Data Sheet
August 30, 2006
DESCRIPTION
Quad Digital Controlled Potentiometers
(XDCP™)
The X9258 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
FEATURES
•
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FN8168.4
Four potentiometers in one package
256 resistor taps/pot–0.4% resolution
2-wire serial interface
Wiper resistance, 40Ω typical @ V+ = 5V, V- = -5V
Four nonvolatile data registers for each pot
Nonvolatile storage of wiper position
Standby current <5µA max (total package)
Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V- = -2.7V to -5.5V
100kΩ, 50kΩ total pot resistance
High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention – 100 years
24 Ld SOIC, 24 Ld TSSOP
Dual supply version of X9259
Pb-free plus anneal available (RoHS compliant)
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
Pot 0
VCC
VSS
R0 R1
V+
V-
R2 R3
WP
SCL
SDA
A0
A1
A2
A3
VH0/RH0
Wiper
Counter
Register
(WCR)
VL0/RL0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VL2/RL2
VW0/RW0
Interface
and
Control
Circuitry
VH2/RH2
VW2/RW2
8
VW1/RW1
Data
R0 R1
R2 R3
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
VW3/RW3
VH1/RH1
R0 R1
VL1/RL1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VH3/RH3
VL3/RL3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9258
Ordering Information
PART NUMBER
PART
MARKING
X9258US24*
X9258US
X9258US24Z* (Note)
VCC LIMITS
(V)
5 ±10
POTENTIOMETER TEMPERATURE
RANGE
ORGANIZATION
(°C)
(kΩ)
50
PACKAGE
PKG.
DWG. #
0 to 70
24 Ld SOIC (300 mil)
M24.3
X9258US Z
0 to 70
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9258US24I*
X9258US I
-40 to 85
24 Ld SOIC (300 mil)
M24.3
X9258US24IZ* (Note)
X9258US ZI
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9258UV24
X9258UV
0 to 70
24 Ld TSSOP (4.4mm)
MDP0044
X9258UV24I
X9258UV I
-40 to 85
24 Ld TSSOP (4.4mm)
MDP0044
X9258UV24IZ (Note)
X9258UV ZI
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258TS24
X9258TS
X9258TS24Z (Note)
100
0 to 70
24 Ld SOIC (300 mil)
M24.3
X9258TS Z
0 to 70
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9258TS24I
X9258TS I
-40 to 85
24 Ld SOIC (300 mil)
M24.3
X9258TS24IZ (Note)
X9258TS ZI
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9258TV24I
X9258TV I
-40 to 85
24 Ld TSSOP (4.4mm)
MDP0044
X9258US24-2.7*
X9258US F
0 to 70
24 Ld SOIC (300 mil)
M24.3
0 to 70
24 Ld SOIC (300 mil) (Pb-free)
M24.3
2.7 to 5.5
50
X9258US24Z-2.7* (Note) X9258US ZF
X9258US24I-2.7*
X9258US G
-40 to 85
24 Ld SOIC (300 mil)
M24.3
X9258US24IZ-2.7*
(Note)
X9258US ZG
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9258UV24-2.7
X9258UV F
0 to 70
24 Ld TSSOP (4.4mm)
MDP0044
X9258UV24I-2.7
X9258UV G
-40 to 85
24 Ld TSSOP (4.4mm)
MDP0044
X9258UV24IZ-2.7 (Note) X9258UV ZG
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258UV24Z-2.7 (Note) X9258UV ZF
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
0 to 70
24 Ld SOIC (300 mil)
M24.3
0 to 70
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9258TS24-2.7*
X9258TS F
X9258TS24Z-2.7* (Note) X9258TS ZF
100
X9258TS24I-2.7*
X9258TS G
-40 to 85
24 Ld SOIC (300 mil)
M24.3
X9258TS24IZ-2.7*
(Note)
X9258TS ZG
-40 to 85
24 Ld SOIC (300 mil) (Pb-free)
M24.3
X9258TV24-2.7
X9258TV F
0 to 70
24 Ld TSSOP (4.4mm)
MDP0044
X9258TV24I-2.7
X9258TV G
-40 to 85
24 Ld TSSOP (4.4mm)
MDP0044
X9258TV24IZ-2.7 (Note) X9258TV ZG
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9258TV24Z-2.7 (Note) X9258TV ZF
0 to 70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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X9258
PIN CONFIGURATION
PIN DESCRIPTIONS
Host Interface Pins
SOIC/TSSOP
NC
1
24
A3
A0
VW3/RW3
2
23
SCL
3
22
VL2/RL2
VH3/RH3
4
21
VH2/RH2
VL3/RL3
5
20
VW2/RW2
V+
6
19
V–
VCC
7
18
VSS
VL0/RL0
SERIAL CLOCK (SCL)
The SCL input is used to clock data into and out of the
X9258.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
X9258
8
17
VW1/RW1
VH0/RH0
9
16
VH1/RH1
VW0/RW0
10
15
VL1/RL1
A2
11
14
A1
WP
12
13
SDA
DEVICE ADDRESS (A0 - A3)
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the address input in order to initiate
communication with the X9258. A maximum of 16
devices may occupy the 2-wire serial bus.
Potentiometer Pins
VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 VL3/RL3)
The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
VW/RW (VW0/RW0 - VW3/RW3)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages
for the DCP analog section.
PIN NAMES
Symbol
Description
SCL
Serial Clock
SDA
Serial Data
A0-A3
Device Address
VH0/RH0 - VH3/RH3,
VL0/RL0 - VL3/RL3
Potentiometer Pins
(terminal equivalent)
VW0/RW0 - VW3/RW3
Potentiometers Pins
(wiper equivalent)
WP
Hardware Write Protection
V+,V-
Analog Supplies
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection (Allowed)
PRINCIPLES OF OPERATION
The X9258 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the DCP potentiometers.
Serial Interface—2-Wire
The X9258 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
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August 30, 2006
X9258
and provide the clock for both transmit and receive
operations. Therefore, the X9258 will be considered a
slave device in all applications.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9258 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1). For the X9258 this is
fixed as 0101[B].
Figure 1. Slave Address
Device Type
Identifier
0
1
0
1
A3
A2
A1
A0
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9258 will respond with a final acknowledge.
Array Description
The X9258 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that
are connected in series. The physical ends of each
array are equivalent to the fixed terminals of a
mechanical potentiometer (VH/RH and VL/RL inputs).
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0 - A3 inputs. The X9258 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9258 to respond with an acknowledge. The
A0 - A3 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms nonvolatile write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9258
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9258 is still busy with the write operation no ACK will
be returned. If the X9258 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
8 bits of the WCR are decoded to select, and enable,
one of 256 switches.
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August 30, 2006
X9258
ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Issue STOP
No
Yes
Further
Operation?
No
Yes
Issue
Instruction
Issue STOP
Proceed
Proceed
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed tWRL. A transfer from the Wiper
Counter Register (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9258; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected data
register). The sequence of operations is shown in
Figure 4.
Instruction Structure
The next byte sent to the X9258 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 2.
Figure 2. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
P1
P0
Wiper Counter
Register Select
Instructions
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P1, P0)
select which one of the four potentiometers is to be
affected by the instruction.
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August 30, 2006
X9258
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1 R0 P1 P0
A
C
K
S
T
O
P
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of
the sequence and timing for this operation are shown
in Figures 5 and 6 respectively.
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9258 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the VH terminal.
Table 1. Instruction Set
Instruction Set
Instruction
I3
I2
I1
I0
R1
R0
P1
P0
Operation
Read Wiper Counter
Register
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write Wiper Counter
Register
1
0
1
0
0
0
1/0
1/0
Write new value to the Wiper Counter Register
pointed to by P1 - P0
Read Data Register
1
0
1
1
1/0
1/0
1/0
1/0
Read the contents of the Data Register pointed
to by P1 - P0 and R1 - R0
Write Data Register
1
1
0
0
1/0
1/0
1/0
1/0
Write new value to the Data Register pointed to
by P1 - P0 and R1 - R0
XFR Data Register to
Wiper Counter Register
1
1
0
1
1/0
1/0
1/0
1/0
Transfer the contents of the Data Register pointed
to by P1 - P0 and R1 - R0 to its associated Wiper
Counter Register
XFR Wiper Counter
Register to Data
Register
1
1
1
0
1/0
1/0
1/0
1/0
Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Data Register
pointed to by R1 - R0
Global XFR Data
Registers to Wiper
Counter Registers
0
0
0
1
1/0
1/0
0
0
Transfer the contents of the Data Registers
pointed to by R1 - R0 of all four pots to their respective Wiper Counter Registers
Global XFR Wiper
Counter Registers
to Data Register
1
0
0
0
1/0
1/0
0
0
Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by R1 - R0 of all four pots
Increment/Decrement
Wiper Counter Register
0
0
1
0
0
0
1/0
1/0
Note:
Enable Increment/decrement of the Control Latch
pointed to by P1 - P0
(1) 1/0 = data is one or zero
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August 30, 2006
X9258
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1 I0
R1 R0 P1 P0 A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Instruction Sequence
F
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
R1 R0 P1 P0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
tWRID
SCL
SDA
Voltage Out
VW/RW
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August 30, 2006
X9258
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
Figure 8. Detailed Potentiometer Block Diagram Detailed Operation
Serial Data Path
VH/RH
Serial
BUS
Input
From Interface
Circuitry
Register 0
Register 1
8
Register 2
8
Wiper
Counter
Register
(WCR)
Register 3
If WCR = 00[H] then VW/RW = VL/RL
If WCR = FF[H] then VW/RW = VH/RH
Parallel
BUS
Input
UP/DN
Modified SCL
C
o
u
n
t
e
r
D
e
c
o
d
e
INC/DEC
Logic
UP/DN
CLK
VL/RL
VW/RW
All DCP potentiometers share the serial interface and
share a common architecture. Each potentiometer has
a Wiper Counter Register and four Data Registers. A
detailed discussion of the register organization and
array operation follows.
Wiper Counter Register
The X9258 contains four Wiper Counter Registers,
one for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
8
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (R0) upon power-up.
FN8168.4
August 30, 2006
X9258
The WCR is a volatile register; that is, its contents are
lost when the X9258 is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be
different from the value present at power-down.
REGISTER DESCRIPTIONS
Data Registers, (8-Bit), Nonvolatile
WP7
NV
WP6 WP5 WP4 WP3 WP2 WP1
NV
NV
NV
NV
NV
NV
(MSB)
Data Registers
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the WCR. It should be noted
all operations changing data in one of these registers
is a nonvolatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
WP0
NV
(LSB)
Four 8-bit Data Registers for each DCP. (sixteen 8-bit
registers in total).
– {D7~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the wiper counter
register on power-up.
Wiper Counter Register, (8-Bit), Volatile
WP7
WP6 WP5 WP4 WP3 WP2 WP1
WP0
Instruction Format
Notes: (1)
(2)
(3)
(4)
(5)
“MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
“A3 ~ A0”: stands for the device addresses sent by the master.
“X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
“I”: stands for the increment operation, SDA held high during active SCL phase (high).
“D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR
S
opcode
addresses
A
C
P P
K 1 0 0 1 0 0 1 0
wiper position
S
(sent by slave on SDA)
A
C W W W W W W W W
K P P P P P P P P
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
Data Byte
S
(sent by master on SDA)
A
C W W W W W W W W
P P P P P P P P
K
7 6 5 4 3 2 1 0
S
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR
S
opcode
addresses
A
C
P P
1 0 1 0 0 0
K
1 0
Read Data Register (DR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
9
instruction DR and WCR
S
opcode
addresses
A
C
R R P P
K 1 0 1 1 1 0 1 0
Data Byte
S
(sent by slave on SDA)
A
C W W W W W W W W
P P P
K P P P P P
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
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August 30, 2006
X9258
Write Data Register (WR)
S device type
device
instruction DR and WCR
S
T identifier
addresses
opcode
addresses
A
A
C
R R P P
R 0 1 0 1 A A A A
1 1 0 0
3 2 1 0 K
1 0 1 0
T
Data Byte
S
(sent by master on SDA)
A
C W W W W W W W W
P P P P P P P P
K
7 6 5 4 3 2 1 0
S
A
C
K
S
T HIGH-VOLTAGE
O WRITE CYCLE
P
XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type
device
instruction DR and WCR
S
T identifier
addresses
opcode
addresses
A
A
C
R R P P
R 0 1 0 1 A A A A
1 1 0 1
3 2 1 0 K
1 0 1 0
T
S
A
C
K
S
T
O
P
XFR Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction DR and WCR
S
opcode
addresses
A
C
R R P P
1 1 1 0
K
1 0 1 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
S
opcode
A
C
K 0 0 1 0
WCR
addresses
0
0
P
1
increment/decrement
S
(sent by master on SDA)
A
P C I/ I/
I/ I/
. . . .
0 K D D
D D
S
T
O
P
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
DR
S
opcode
addresses
A
C
R R
0 0 0 1
0 0
K
1 0
S
A
C
K
S
T
O
P
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
T identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
10
instruction
DR
S
opcode
addresses
A
C
R R
1 0 0 0
0 0
K
1 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
FN8168.4
August 30, 2006
X9258
SYMBOL TABLE
INPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
11
120
OUTPUTS
RMIN =
100
Resistance (K)
WAVEFORM
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
80
VCC MAX
=1.8kΩ
IOL MIN
RMAX =
tR
CBUS
Max.
Resistance
60
40
20
0
Min.
Resistance
0
20
40
60
80 100 120
Bus Capacitance (pF)
FN8168.4
August 30, 2006
X9258
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address input
with respect to VSS ................................. -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH/RH ..............................................................V+
Any VL/RL.................................................................VLead temperature (soldering, 10s) .................. +300°C
IW (10s) ............................................................±15mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
0°C
-40°C
Commercial
Industrial
Max.
Device
X9258
X9258-2.7
+70°C
+85°C
Supply Voltage (VCC) Limits
5V ± 10%
2.7V to 5.5V
ANALOG CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Max.
Unit
End to end resistance tolerance
±20
%
Power rating
50
mW
25°C, each pot
IW
Wiper current
±7.5
mA
Wiper current = ± 1mA
RW
Wiper resistance
150
250
Ω
IW = ± 1mA @ V+ = 3V, V- = -3V
RW
Wiper resistance
40
100
Ω
IW = ± 1mA @ V+ = 5V, V- = -5V
V+
Voltage on V+ Pin
V
VVTERM
Parameter
Voltage on V- Pin
Min.
Typ.
X9258
+4.5
+5.5
X9258-2.7
+2.7
+5.5
X9258
-5.5
-4.5
X9258 -2.7
-5.5
-2.7
V-
V+
Voltage on any VH/RH or VL/RL pin
Noise
Resolution (4)
Temperature coefficient of RTOTAL
12
V
dBV
0.6
%
±1
MI(3)
±0.6
MI(3)
±300
Ratiometric Temperature Coefficient
CH/CL/CW Potentiometer Capacitance
V
-120
Absolute linearity (1)
Relative linearity (2)
Ref: 1kHz
Vw(n)(actual) - Vw(n)(expected)
Vw(n + 1) - [Vw(n) + MI]
ppm/°C
±20
10/10/25
Test Conditions
ppm/°C
pF
See Circuit #3
FN8168.4
August 30, 2006
X9258
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
ICC1
VCC supply current (Nonvolatile Write)
ICC2
VCC supply current (move
wiper, write, read)
ISB
VCC current (standby)
5
µA
SCL = SDA = VCC, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.1
V
VIL
Input LOW voltage
-0.5
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
1
100
Test Conditions
mA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
µA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
IOL = 3mA
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/255 or (VH/RH—VL/RL)/255, single pot
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
CI/O
(5)
CIN(5)
Test
Max.
Unit
Test Conditions
Input/output capacitance (SDA)
8
pF
VI/O = 0V
Input capacitance (A0, A1, A2, A3, and SCL)
6
pF
VIN = 0V
Min.
Max.
Unit
POWER-UP TIMING
Symbol
tPUR
Parameter
(6)
Power-up to initiation of read operation
1
ms
(6)
Power-up to initiation of write operation
5
ms
50
V/ms
tPUW
tR VCC(7)
VCC Power up ramp
0.2
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The VCC ramp rate spec is always in effect.
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
13
FN8168.4
August 30, 2006
X9258
A.C. TEST CONDITIONS
Test Circuit #3 SPICE Macro Model
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
Macro Model
RTOTAL
RH
CH
EQUIVALENT A.C. LOAD CIRCUIT
5V
2.7V
10pF
1533Ω
CW
CL
RL
10pF
25pF
RW
SDA Output
100pF
100pF
AC TIMING (Over recommended operating condition)
Symbol
Parameter
Min.
Max.
Unit
400
kHz
fSCL
Clock frequency
tCYC
Clock cycle time
2500
ns
tHIGH
Clock high time
600
ns
tLOW
Clock low time
1300
ns
tSU:STA
Start setup time
600
ns
tHD:STA
Start hold time
600
ns
tSU:STO
Stop setup time
600
ns
tSU:DAT
SDA data input setup time
100
ns
tHD:DAT
SDA data input hold time
30
ns
tR
SCL and SDA rise time
300
ns
tF
SCL and SDA fall time
300
ns
900
ns
tAA
SCL low to SDA data output valid time
tDH
SDA data output hold time
50
ns
Noise suppression time constant at SCL and SDA inputs
50
ns
1300
ns
TI
tBUF
Bus free rime (prior to any transmission)
tSU:WPA
WP, A0, A1, A2 and A3 setup time
0
ns
tHD:WPA
WP, A0, A1, A2 and A3 hold time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
tWR
High-voltage write cycle time (store instructions)
5
10
ms
14
FN8168.4
August 30, 2006
X9258
DCP TIMING
Symbol
Parameter
Max.
Unit
Wiper response time after the third (last) power supply is stable
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
10
µs
tWRPO
Note:
Min.
(8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS 2-WIRE INTERFACE
START and STOP Timing
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tAA
15
tDH
FN8168.4
August 30, 2006
X9258
DCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
VWx
DCP Timing (for Increment/Decrement Instruction)
SCL
SDA
Wiper Register Address
Inc/Dec
Inc/Dec
tWRID
VWx
Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
A2, A3
16
FN8168.4
August 30, 2006
X9258
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
VW/RW
I
TWO-TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
THREE-TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
Application Circuits
NONINVERTING AMPLIFIER
VS
VOLTAGE REGULATOR
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT
R1
COMPARATOR WITH HYSTERESIS
R2
VS
VS
–
+
100kΩ
–
VO
+
+12V
10kΩ
R1
}
10kΩ
}
TL072
10kΩ
VO
R2
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
-12V
17
FN8168.4
August 30, 2006
X9258
Application Circuits (continued)
ATTENUATOR
FILTER
C
VS
R2
R1
VO
–
–
VS
+
R
VO
+
R3
R4
R2
All RS = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
V O = G VS
-1/2 ≤ G ≤ +1/2
R2
}
VS
R1
}
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G V S
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
18
FN8168.4
August 30, 2006
X9258
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
(N/2)+1
N
PIN #1 I.D.
E
E1
0.20 C B A
1
(N/2)
B
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. E 12/02
NOTES:
SEATING
PLANE
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
SEE DETAIL “X”
c
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
19
FN8168.4
August 30, 2006
X9258
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
24
0°
24
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN8168.4
August 30, 2006