X9315
®
Low Noise, Low Power, 32 Taps
Data Sheet
September 15, 2005
Digitally Controlled Potentiometer
(XDCP™)
FN8179.1
Features
• Solid-state potentiometer
The Intersil X9315 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
• Control
• 3-wire serial interface
• 32 wiper tap points
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 31 resistive elements
- Temperature compensated
- End to end resistance range ± 20%
- Terminal voltage, 0 to VCC
• Low power CMOS
- VCC = 2.7V or 5V
- Active current, 50/400µA max.
- Standby current, 1µA max.
• High reliability
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
• Parameter Adjustments
• RTOTAL values = 10kΩ, 50kΩ, 100kΩ
• Signal Processing
• Packages
- 8 Ld SOIC, MSOP and PDIP
• Pb-free plus anneal available (RoHS compliant)
Block Diagram
U/D
INC
CS
VCC (Supply Voltage)
Control
and
Memory
RW/VW
Device Select
(CS)
RH/VH
31
30
29
RH/VH
Up/Down
(U/D)
Increment
(INC)
5-Bit
Up/Down
Counter
5-Bit
Nonvolatile
Memory
RL/VL
28
One
of
Thirty
Two
Decoder
Transfer
Gates
Resistor
Array
2
VSS (Ground)
General
VCC
VSS
Store and
Recall
Control
Circuitry
1
0
RL/VL
RW/VW
Detailed
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9315
Ordering Information
PART NUMBER
PART MARKING
VCC LIMITS
(V)
RTOTAL
(kΩ)
TEMP RANGE
(°C)
5 ±10%
10
0 to 70
8 Ld MSOP
8 Ld MSOP (Pb-free)
PACKAGE
X9315WM*
AAW
X9315WMZ* (Note)
DDT
0 to 70
X9315WMI*
AAX
-40 to 85
8 Ld MSOP
X9315WMIZ* (Note)
AKW
-40 to 85
8 Ld MSOP (Pb-free)
X9315WP
X9315WP
0 to 70
8 Ld PDIP
X9315WPI
X9315WP I
-40 to 85
8 Ld PDIP
X9315WS*
X9315W
0 to 70
8 Ld SOIC
X9315WSZ* (Note)
X9315W Z
0 to 70
8 Ld SOIC (Pb-free)
X9315WSI*
X9315W I
-40 to 85
8 Ld SOIC
X9315WSIZ* (Note)
X9315W Z I
-40 to 85
8 Ld SOIC (Pb-free)
X9315UM*
50
0 to 70
8 Ld MSOP
8 Ld MSOP (Pb-free)
X9315UMZ* (Note)
DDS
0 to 70
X9315UMI*
AEB
-40 to 85
8 Ld MSOP
X9315UMIZ* (Note)
DDR
-40 to 85
8 Ld MSOP (Pb-free)
X9315UP
X9315UP
0 to 70
8 Ld PDIP
X9315UPI
X9315UP I
-40 to 85
8 Ld PDIP
X9315US*
X9315U
0 to 70
8 Ld SOIC
X9315USZ* (Note)
X9315U Z
0 to 70
8 Ld SOIC (Pb-free)
X9315USI*
X9315U I
-40 to 85
8 Ld SOIC
X9315USIZ* (Note)
X9315U Z I
-40 to 85
8 Ld SOIC (Pb-free)
X9315TM*
AEJ
X9315TMZ* (Note)
0 to 70
8 Ld MSOP
DDN
0 to 70
8 Ld MSOP (Pb-free)
X9315TMI*
ADZ
-40 to 85
8 Ld MSOP
X9315TMIZ* (Note)
DDL
-40 to 85
8 Ld MSOP (Pb-free)
X9315TP
X9315TP
0 to 70
8 Ld PDIP
X9315TPI
X9315TP I
-40 to 85
8 Ld PDIP
X9315TS*
X9315T
0 to 70
8 Ld SOIC
X9315TSZ* (Note)
X9315T Z
0 to 70
8 Ld SOIC (Pb-free)
X9315TSI*
X9315T I
-40 to 85
8 Ld SOIC
X9315TSIZ* (Note)
X9315T Z I
-40 to 85
8 Ld SOIC (Pb-free)
2
100
FN8179.1
September 15, 2005
X9315
Ordering Information (Continued)
PART NUMBER
PART MARKING
VCC LIMITS
(V)
RTOTAL
(kΩ)
TEMP RANGE
(°C)
2.7-5.5
10
0 to 70
8 Ld PDIP
-40 to 85
8 Ld PDIP
PACKAGE
X9315TP-2.7
X9315TP F
X9315TPI-2.7
X9315TP G
X9315WM-2.7*
AAU
0 to 70
8 Ld MSOP
X9315WMZ-2.7* (Note)
AOI
0 to 70
8 Ld MSOP (Pb-free)
X9315WMI-2.7*
AAV
-40 to 85
8 Ld MSOP
-40 to 85
8 Ld MSOP (Pb-free)
X9315WMIZ-2.7* (Note)
X9315WP-2.7
X9315WP F
0 to 70
8 Ld PDIP
X9315WPI-2.7
X9315WP G
-40 to 85
8 Ld PDIP
X9315WS-2.7*
X9315W F
0 to 70
8 Ld SOIC
X9315WSZ-2.7* (Note)
X9315W Z F
0 to 70
8 Ld SOIC (Pb-free)
X9315WSI-2.7*
X9315W G
-40 to 85
8 Ld SOIC
X9315WSIZ-2.7* (Note)
X9315W Z G
-40 to 85
8 Ld SOIC (Pb-free)
X9315UM-2.7*
AEK
X9315UMZ-2.7* (Note)
50
0 to 70
8 Ld MSOP
AKU
0 to 70
8 Ld MSOP (Pb-free)
X9315UMI-2.7*
AEA
-40 to 85
8 Ld MSOP
X9315UMIZ-2.7* (Note)
AJG
-40 to 85
8 Ld MSOP (Pb-free)
X9315UP-2.7
0 to 70
8 Ld PDIP
X9315UPI-2.7
-40 to 85
8 Ld PDIP
X9315US-2.7*
X9315U F
0 to 70
8 Ld SOIC
X9315USZ-2.7* (Note)
X9315U Z F
0 to 70
8 Ld SOIC (Pb-free)
X9315USI-2.7*
X9315U G
-40 to 85
8 Ld SOIC
X9315USIZ-2.7* (Note)
X9315U Z G
-40 to 85
8 Ld SOIC (Pb-free)
X9315TM-2.7*
AEI
X9315TMZ-2.7* (Note)
100
0 to 70
8 Ld MSOP
DDP
0 to 70
8 Ld MSOP (Pb-free)
X9315TMI-2.7*
ADY
-40 to 85
8 Ld MSOP
X9315TMIZ-2.7* (Note)
DDM
-40 to 85
8 Ld MSOP (Pb-free)
X9315TS-2.7*
X9315T F
0 to 70
8 Ld SOIC
X9315TSZ-2.7* (Note)
X9315T Z F
0 to 70
8 Ld SOIC (Pb-free)
X9315TSI-2.7*
X9315T G
-40 to 85
8 Ld SOIC
X9315TSIZ-2.7* (Note)
X9315T Z G
-40 to 85
8 Ld SOIC (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel.
3
FN8179.1
September 15, 2005
X9315
Pin Descriptions
Pin Names
RH/VH and RL/VL
The high (RH/VH) and low (RL/VL) terminals of the X9315
are equivalent to the fixed terminals of a mechanical
potentiometer. The minimum voltage is VSS and the
maximum is VCC. The terminology of RL/VL and RH/VH
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D input, and not
the voltage potential on the terminal.
RW/VW
RW/Vw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
The wiper terminal series resistance is typically 200Ω at VCC
= 5V.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS is returned HIGH while the INC input is also HIGH. After
the store operation is complete the X9315 will be placed in
the low power standby mode until the device is selected
once again.
Pin Configuration
1
U/D
2
RH/VH
3
VSS
X9315
4
8
VCC
7
CS
6
RL/VL
5
RW/VW
Pin Names
SYMBOL
DESCRIPTION
RH/VH
High terminal
RW/VW
Wiper terminal
RL/VL
Low terminal
VSS
Ground
VCC
Supply voltage
U/D
Up/Down control input
4
DESCRIPTION
INC
Increment control input
CS
Chip Select control input
Principles of Operation
There are three sections of the X9315: the input control,
counter and decode section; the nonvolatile memory; and
the resistor array. The input control section operates just like
an up/down counter. The output of this counter is decoded to
turn on a single electronic switch connecting a point on the
resistor array to the wiper output. Under the proper
conditions the contents of the counter can be stored in
nonvolatile memory and retained for future use. The resistor
array is comprised of 31 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the connection at that
point to the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for tIW (INC to VW change). The
RTOTAL value for the device can temporarily be reduced by
a significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
Instructions and Programming
DIP/SOIC/MSOP
INC
SYMBOL
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW the device
is selected and enabled to respond to the U/D and INC
inputs. HIGH to LOW transitions on INC will increment or
decrement (depending on the state of the U/D input) a five
bit counter. The output of this counter is decoded to select
one of thirty two wiper positions along the resistive array.
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
The system may select the X9315, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until
FN8179.1
September 15, 2005
X9315
changed by the system or until a power-up/down cycle
recalled the previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc...
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper Up
L
L
Wiper Down
H
X
Store Wiper Position
X
X
Standby Current
L
X
No Store, Return to Standby
H
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
5
FN8179.1
September 15, 2005
X9315
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D, VH, VL and
VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
∆V = |VH–VL| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
Lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . 300°C
IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7.5mA
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC) (Note 4) Limits
X9315. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
X9315-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Potentiometer Characteristics
(Over recommended operating conditions unless otherwise stated.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
End to end resistance tolerance
MAX.
UNIT
±20
%
VVH
VH terminal voltage
0
VCC
V
VVL
VL terminal voltage
0
VCC
V
10
mW
Power rating
RTOTAL ≥ 10kΩ
RW
Wiper resistance
IW = 1mA, VCC = 5V
200
400
Ω
RW
Wiper resistance
IW = 1mA, VCC = 2.7V
400
1000
Ω
IW
Wiper current
±3.75
mA
Noise
Ref: 1kHz
Resolution
Absolute linearity(1)
Vw(n)(actual) - Vw(n)(expected)
Relative linearity(2)
Vw(n + 1) - [Vw(n) + MI]
RTOTAL temperature coefficient
-120
dBV
3
%
Potentiometer capacitances
MI(3)
±0.2
MI(3)
±300
Ratiometric temperature coefficient
CH/CL/CW
±1
ppm/°C
±20
See circuit #3
10/10/25
ppm/°C
pF
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (Vw(n)(actual) - Vw(n)(expected)) = ±1 Ml
Maximum.
(2) Relative linearity is a measure of the error in step size between taps = RW(n+1) - [Rw(n) + Ml] = ±0.2 Ml.
(3) 1 Ml = Minimum Increment = RTOT/31.
(4) Typical values are for TA = 25°C and nominal supply voltage.
(5) This parameter is periodically sampled and not 100% tested
DC Electrical Specifications
(Over recommended operating conditions unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP(4)
MAX
UNIT
ICC1
VCC active current (Increment)
CS = VIL, U/D = VIL or VIH and INC = 0.4V
@ max. tCYC
50
µA
ICC2
VCC active current (Store) (EEPROM
Store)
CS = VIH, U/D = VIL or VIH and INC = VIH
@ max. tWR
400
µA
ISB
Standby supply current
CS = VCC - 0.3V, U/D and INC = VSS or
VCC - 0.3V
1
µA
ILI
CS, INC, U/D input leakage current
VIN = VSS to VCC
±10
µA
VIH
CS, INC, U/D input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
CS, INC, U/D input LOW voltage
-0.5
VCC x 0.1
V
CIN(5)
CS, INC, U/D input capacitance
10
pF
6
VCC = 5V, VIN = VSS, TA = 25°C, f = 1MHz
FN8179.1
September 15, 2005
X9315
Endurance and Data Retention
PARAMETER
MIN
UNIT
Minimum endurance
100,000
Data changes per bit
Data retention
100
Years
Test Circuit #1
Test Circuit #2
Circuit #3 SPICE Macro Model
VH/RH
VH/RH
RTOTAL
Test Point
VS
RH
CW
CH
Test Point
VW/RW
V
VL
L/RL
RL
10pF
VW/RW
VW
VL/RL
CL
25pF
Force
Current
10pF
RW
AC Conditions of Test
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input reference levels
1.5V
AC Electrical Specifications
(Over recommended operating conditions unless otherwise specified)
LIMITS
SYMBOL
PARAMETER
MIN
TYP(6)
MAX
UNIT
tCl
CS to INC setup
100
ns
tlD
INC HIGH to U/D change
100
ns
tDI
U/D to INC setup
2.9
µs
tlL
INC LOW period
1
µs
tlH
INC HIGH period
1
µs
tlC
INC Inactive to CS inactive
1
µs
tCPH
CS Deselect time (NO STORE)
100
ns
tCPH
CS Deselect time (STORE)
10
ms
tIW
tCYC
tR, tF(7)
tPU(7)
tR VCC(7)
tWR
INC to Vw change
1
INC cycle time
5
4
µs
INC input rise and fall time
Power-up to wiper stable
VCC power-up rate
Store cycle
0.2
5
7
µs
500
µs
5
µs
50
V/ms
10
ms
FN8179.1
September 15, 2005
X9315
Power-up and Down Requirements
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL,
VW. The VCC ramp rate spec is always in effect.
AC Timing
CS
tCYC
tCI
tIL
(Store)
tCPH
tIC
tIH
90%
90%
10%
INC
tID
tF
DI
tR
U/D
tIW
MI
VW
(8)
Notes: (6) Typical values are for TA = 25°C and nominal supply voltage.
(7) This parameter is not 100% tested.
(8) MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position.
Performance Characteristics (Typical)
Typical Noise
0
-10
-20
-30
Noise (dB)
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0
10
20
30
40
50
60
70
80
90
100
110 120
130 140
150 160
170 180
190 200
Frequency (kHz)
8
FN8179.1
September 15, 2005
X9315
Typical Rtotal vs. Temperature
10000
9800
9600
9400
Rtotal
9200
9000
8800
8600
8400
8200
8000
-55
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
105 115 125 C°
95
Temperature
Typical Total Resistance Temperature Coefficient
0
-50
-100
-150
PPM
-200
-250
-300
-350
-55
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
26
28
30
115
125
°C
Temperature
Typical Wiper Resistance
800
700
600
Rw (Ω)
500
400
300
200
100
0
0
2
4
6
8
10
12
14
16
18
20
22
24
32
VCC = 2.7V
Tap
9
FN8179.1
September 15, 2005
X9315
Typical Absolute% Error per Tap Position
40.0%
Absolute% Error
30.0%
20.0%
10.0%
0.0%
-10.0%
-20.0%
-30.0%
-40.0%
0
3
6
9
12
15
18
21
18
21
24
27
30
Tap
Typical Relative% Error per Tap Position
20.0%
Relative% Error
15.0%
10.0%
5.0%
0.0%
-5.0%
-10.0%
-15.0%
-20.0%
0
3
6
9
12
15
24
27
30
Tap
Applications Information
Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages; (1) the variability and
reliability of a solid-state potentiometer, (2) the flexibility of
computer-based digital controls, and (3) the retentivity of
nonvolatile memory used for the storage of multiple
potentiometer settings or data.
10
FN8179.1
September 15, 2005
X9315
Basic Configurations of Electronic Potentiometers
VR
VR
VH
VW/RW
VL
I
Three terminal potentiometer;
variable voltage divider
Two terminal variable resistor;
variable current
Basic Circuits
Buffered Reference Voltage
Noninverting Amplifier
Cascading Techniques
R1
+V
+5V
+V
+V
VS
+5V
VW
VREF
VOUT
–
VO
–
OP-07
+
LM308A
+
-5V
X
RW/VW
R2
+V
-5V
R1
RW/VW
VOUT = VW/RW
(a)
Voltage Regulator
VIN
(b)
VO = (1 + R2/R1)VS
Comparator with Hysteresis
VO (REG)
317
VS
LT311A
R1
–
+
VO
Iadj
}
VO (REG) = 1.25V (1 + R2/R1) + Iadj R2
}
R2
R1
R2
VUL = {R1/(R1 + R2)} VO(max)
VLL = {R1/(R1 + R2)} VO(min)
(for additional circuits see AN115)
11
FN8179.1
September 15, 2005
X9315
Packaging Information
8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.0256 (0.65) Typ.
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
0.036 (0.91)
0.032 (0.81)
0.040 ± 0.002
(1.02 ± 0.05)
7° Typ.
0.008 (0.20)
0.004 (0.10)
0.0256" Typical
0.150 (3.81)
Ref.
0.193 (4.90)
Ref.
0.007 (0.18)
0.005 (0.13)
0.025"
Typical
0.220"
FOOTPRINT
0.020"
Typical
8 Places
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
12
FN8179.1
September 15, 2005
X9315
Packaging Information
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
.073 (1.84)
Max.
Typ. 0.010 (0.25)
0.060 (1.52)
0.020 (0.51)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0°
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
13
FN8179.1
September 15, 2005
X9315
Packaging Information
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"Typical
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
0.030"
Typical
8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
FN8179.1
September 15, 2005