XILINX XC3S500E

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Spartan-3E FPGA Family:
Complete Data Sheet
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DS312 March 21, 2005
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Module 1:
Introduction and Ordering Information
Module 3:
DC and Switching Characteristics
DS312-1 (v1.1) March 21, 2005
6 pages
DS312-3 (v1.0) March 1, 2005
18 pages
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Introduction
Features
Architectural Overview
Package Marking
Ordering Information
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Module 2:
Functional Description
DS312-2 (v1.1) March 21, 2005
96 pages
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Input/Output Blocks (IOBs)
- Overview
- SelectIO™ Signal Standards
Configurable Logic Block (CLB)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
Powering Spartan-3E FPGAs
DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
Switching Characteristics
- DCM Timing
- Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS312-4 (v1.1) March 21, 2005
72 pages
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Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
IMPORTANT NOTE: The Spartan™-3E FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy
navigation in this volume.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
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06
Spartan-3E FPGA Family:
Introduction and Ordering
Information
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DS312-1 (v1.1) March 21, 2005
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Advance Product Specification
Introduction
The Spartan™-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from
100,000 to 1.6 million system gates, as shown in Table 1.
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of configuration. These Spartan-3E enhancements, combined with
advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible,
setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home networking, display/projection, and digital television equipment.
The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
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Features
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Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
Proven advanced 90-nanometer process technology
Multi-voltage, multi-standard SelectIO™ interface pins
- Up to 376 I/O pins or 156 differential signal pairs
- LVCMOS, LVTTL, HSTL, and SSTL single-ended
signal standards
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- True LVDS, RSDS, mini-LVDS differential I/O
- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
- Enhanced Double Data Rate (DDR) support
Abundant, flexible logic resources
- Densities up to 33,192 logic cells, including
optional shift register or distributed RAM support
- Efficient wide multiplexers, wide logic
- Fast look-ahead carry logic
- Enhanced 18 x 18 multipliers with optional pipeline
- IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
- Up to 648 Kbits of fast block RAM
- Up to 231 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
- Clock skew elimination (delay locked loop)
- Frequency synthesis, multiplication, division
- High-resolution phase shifting
- Wide frequency range (5 MHz to over 300 MHz)
Eight global clocks and eight clocks for each half of
device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
- Low-cost, space-saving SPI serial Flash PROM
- x8 or x8/x16 parallel NOR Flash PROM
- Low-cost Xilinx Platform Flash with JTAG
Complete Xilinx ISE™, WebPACK™ development
system support
MicroBlaze™, PicoBlaze™ embedded processor cores
Fully compliant 32-/64-bit 33/66 MHz PCI support
Low-cost QFP and BGA packaging options
- Common footprints support easy density migration
- Pb-free packaging options
Table 1: Summary of Spartan-3E FPGA Attributes
CLB Array
(One CLB = Four Slices)
Total
CLBs
Total
Slices
Distributed
RAM bits(1)
Block
RAM
bits(1)
240
960
15K
72K
Maximum
User I/O
Maximum
Differential
I/O Pairs
108
40
Device
System
Gates
Equivalent
Logic
Cells
XC3S100E
100K
2,160
XC3S250E
250K
5,508
34
26
612
2,448
38K
216K
12
4
172
68
XC3S500E
500K
10,476
46
34
1,164
4,656
73K
360K
20
4
232
92
XC3S1200E
1200K
19,512
60
46
2,168
8,672
136K
504K
28
8
304
124
XC3S1600E
1600K
33,192
76
58
3,688
14,752
231K
648K
36
8
376
156
Rows Columns
22
16
Dedicated
Multipliers DCMs
4
2
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-1 (v1.1) March 21, 2005
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Introduction and Ordering Information
Architectural Overview
The Spartan-3E family architecture consists of five fundamental programmable functional elements:
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Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
•
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
These elements are organized as shown in Figure 1. A ring
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XC3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XC3S100E has only one DCM at the top and bottom, while
the XC3S1200E and XC3S1600E add two DCMs in the
middle of the left and right sides.
The Spartan-3E family features a rich network of traces that
interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the
routing.
Notes:
1.
The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as
indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom.
Figure 1: Spartan-3E Family Architecture
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Introduction and Ordering Information
Configuration
I/O Capabilities
Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional
elements and routing resources. The FPGA’s configuration
data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying
power, the configuration data is written to the FPGA using
any of seven different modes:
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination.
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Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
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Spartan-3E FPGAs support the following single-ended
standards:
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3.3V, low-voltage TTL, LVTTL
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz and 66 MHz
HSTL I and III at 1.8V, typically for memory applications
SSTL I at 1.8V and 2.5V, typically for memory
applications
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Spartan-3E FPGAs support the following differential standards:
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LVDS
Bus LVDS
mini-LVDS
RSDS
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
VQ100
VQG100
Device
CP132
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
XC3S100E
66
30
-
-
108
40
-
-
-
-
-
-
-
-
-
-
XC3S250E
66
30
92
41
108
40
158
65
172
68
-
-
-
-
-
-
XC3S500E
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-
92
41
-
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158
65
190
77
232
92
-
-
-
-
XC3S1200E
-
-
-
-
-
-
-
-
190
77
250
99
304
124
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-
XC3S1600E
-
-
-
-
-
-
-
-
-
-
250
99
304
124
376
156
Notes:
1.
All Spartan-3E devices in the same package are pin-compatible.
DS312-1 (v1.1) March 21, 2005
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Introduction and Ordering Information
Package Marking
Figure 2 provides a top marking example for Spartan-3E
FPGAs in the quad-flat packages. Figure 3 shows the top
marking for Spartan-3E FPGAs in BGA packages except
the 132-ball chip-scale package (CP132 and CPG132). The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator. Figure 4 shows
the top marking for Spartan-3E FPGAs in the CP132 and
CPG132 packages.
Use the seven digits of the Lot Code to access additional
information for a specific device using the Xilinx web-based
Genealogy Viewer.
Mask Revision Code
Fabrication Code
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SPARTAN
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Process Technology
Device Type
Package
XC3S250E TM
PQ208AGQ0525
D1234567A
Speed Grade
4C
Date Code
Lot Code
Temperature Range
Pin P1
DS312-1_06_032105
Figure 2: Spartan-3E QFP Example Package Marking
Mask Revision Code
BGA Ball A1
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SPARTAN
Device Type
Package
Fabrication Code
Process Code
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XC3S250ETM
FT256AGQ0525
D1234567A
4C
Date Code
Lot Code
Speed Grade
Temperature Range
DS312-1_02_032105
Figure 3: Spartan-3E BGA Example Package Marking
Ball A1
Lot Code
3S250E
F1234567-0525
PHILIPPINES
Package
C5 = CP132
C6 = CPG132
C5AGQ
Mask Revision Code
Device Type
Date Code
Temperature Range
4C
Speed Grade
Process Code
Fabrication Code
DS312-1_05_032105
Figure 4: Spartan-3E CP132 and CPG132 Example Package Marking
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Introduction and Ordering Information
Ordering Information
Spartan-3E FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a ‘G’ character in the ordering code.
Standard Packaging
Example:
XC3S250E -4 FT 256 C
Device Type
Temperature Range:
C = Commercial (TJ = 0oC to 85oC)
I = Industrial (TJ = -40oC to 100oC)
Speed Grade
Package Type
Number of Pins
DS312_03_011405
Pb-Free Packaging
Example:
XC3S250E -4 FT G 256 C
Device Type
Temperature Range:
C = Commercial (TJ = 0oC to 85oC)
I = Industrial (TJ = -40oC to 100oC)
Number of Pins
Pb-free
DS312_04_011405
Speed Grade
Package Type
Device
Speed Grade
Package Type / Number of Pins
Temperature Range (TJ )
XC3S100E
–4 Standard Performance
VQ(G)100 100-pin Very Thin Quad Flat Pack (VQFP)
C Commercial (0°C to 85°C)
XC3S250E
–5 High Performance
CP(G)132 132-ball Chip-Scale Package (CSP)
I Industrial (–40°C to 100°C)
XC3S500E
TQ(G)144 144-pin Thin Quad Flat Pack (TQFP)
XC3S1200E
PQ(G)208 208-pin Plastic Quad Flat Pack (PQFP)
XC3S1600E
FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
FG(G)320 320-ball Fine-Pitch Ball Grid Array (FBGA)
FG(G)400 400-ball Fine-Pitch Ball Grid Array (FBGA)
FG(G)484 484-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1.
The –5 speed grade is exclusively available in the Commercial temperature range.
DS312-1 (v1.1) March 21, 2005
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Introduction and Ordering Information
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
03/01/05
1.0
Initial Xilinx release.
03/21/05
1.1
Added XC3S250E in CP132 package to Table 2. Corrected number of differential I/O pairs
for CP132 package. Added package markings for QFP packages (Figure 2) and
CP132/CPG132 packages (Figure 4).
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1)
DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2)
DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3)
DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
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Spartan-3E FPGA Family:
Functional Description
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DS312-2 (v1.1) March 21, 2005
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Advance Product Specification
Introduction
As described in Architectural Overview, the Spartan™-3E
FPGA architecture consists of five fundamental functional
elements:
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Input/Output Blocks (IOBs)
Configurable Logic Block (CLB) and Slice
Resources
Block RAM
Dedicated Multipliers
Digital Clock Managers (DCMs)
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•
The following sections provide detailed information on each
of these functions. In addition, this section also describes
the following functions:
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•
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Clocking Infrastructure
Interconnect
Configuration
Powering Spartan-3E FPGAs
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the delay element, there are alternate routes through a
pair of storage elements to the IQ1 and IQ2 lines. The
IOB outputs I, IQ1, and IQ2 lead to the FPGA’s internal
logic. The delay element can be set to ensure a hold
time of zero (see Input Delay Functions).
The output path, starting with the O1 and O2 lines,
carries data from the FPGA’s internal logic through a
multiplexer and then a three-state driver to the IOB
pad. In addition to this direct path, the multiplexer
provides the option to insert a pair of storage elements.
The 3-state path determines when the output driver is
high impedance. The T1 and T2 lines carry data from
the FPGA’s internal logic through a multiplexer to the
output driver. In addition to this direct path, the
multiplexer provides the option to insert a pair of
storage elements.
All signal paths entering the IOB, including those
associated with the storage elements, have an inverter
option. Any inverter placed on these paths is
automatically absorbed into the IOB.
Input/Output Blocks (IOBs)
IOB Overview
The Input/Output Block (IOB) provides a programmable,
unidirectional or bidirectional interface between a package
pin and the FPGA’s internal logic. The IOB is similar to that
of the Spartan-3 family with the following differences:
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•
•
Input-only blocks are added
Programmable input delays are added to all blocks
DDR flip-flops can be shared between adjacent IOBs
The unidirectional input-only block has a subset of the full
IOB capabilities. Thus there are no connections or logic for
an output path. The following paragraphs assume that any
reference to output functionality does not apply to the
input-only blocks. The number of input-only blocks varies
with device size, but is never more than 25% of the total IOB
count.
Figure 1, page 2 is a simplified diagram of the IOB’s internal
structure. There are three main signal paths within the IOB:
the output path, input path, and 3-state path. Each path has
its own pair of storage elements that can act as either registers or latches. For more information, see Storage Element
Functions. The three main signal paths are as follows:
•
The input path carries data from the pad, which is
bonded to a package pin, through an optional
programmable delay element directly to the I line. After
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Functional Description
T
T1
D
Q
TFF1
CE
CK
SR
REV
DDR
MUX
TCE
T2
D
Q
TFF2
CE
CK
SR
REV
Three-state Path
ODDROUT1
O1
ODDRIN1
OTCLK1
D
CE
CK
SR
Q
Pull-Up
ODDRIN2
OTCLK2
ESD
REV
I/O
Pin
DDR
MUX
OCE
O2
VCCO
OFF1
Programmable
Output
Driver
Q
D
OFF2
CE
CK
SR
PullDown
ESD
REV
Keeper
Latch
Output Path
ODDROUT2
I
IQ1
IDDRIN1
IDDRIN2
ICLK1
ICE
LVCMOS, LVTTL, PCI
Programmable
Delay
D
Q
CK
SR
Single-ended Standards
using VREF
IFF1
CE
VREF
Pin
REV
Differential Standards
IQ2
D
IFF2
CE
ICLK2
CK
SR
I/O Pin
from
Adjacent
IOB
Q
REV
SR
REV
Input Path
DS312-2_19_030105
Notes:
1.
2.
All IOB signals communicating with the FPGA’s internal logic have the option of inverting polarity inside the IOB.
Signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
Figure 1: Simplified IOB Diagram
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Functional Description
Input Delay Functions
Each IOB has a programmable delay block that can delay
the input signal from 0 to nominally 4000 ps. In Figure 2, the
signal is first delayed by either 0 or 2000 ps (nominal) and is
then applied to an 8 tap delay line. This delay line has a
nominal value of 250 ps per tap. All 8 taps are available via
a multiplexer for use as an asynchronous input directly into
the FPGA fabric. In this way, the delay is programmable
from 0 to 4000 ps in 250 ps steps. Four of the 8 taps are
also available via a multiplexer to the D inputs of the synchronous storage elements. The delay inserted in the path
to the storage element can be varied from 0 to 4000 ps in
500 ps steps. The first, coarse delay element is common to
both asynchronous and synchronous paths, and must be
either used or not used for both paths.
The delay values are set up in the silicon once at configuration time—they are non-modifiable in device operation.
The primary use for the input delay element is as an adequate delay to ensure that there is no hold time requirement
when using the input flip-flop(s) with a global clock. The
necessary value for this function is chosen by the Xilinx software tools and depends on device size. If the design is
using a DCM in the clock path, then the delay element can
be safely set to zero in the user's design, and there is still no
hold time requirement.
Both asynchronous and synchronous values can be modified by the user, which is useful where extra delay is
required on clock or data inputs, for example, in interfaces to
various types of RAM.
See Module 3 of the Spartan-3E data sheet for exact values
for the delay elements.
Synchronous input (IQ1)
D Q
Synchronous input (IQ2)
D Q
PAD
Asynchronous input (I)
DS312-2_18_022205
Figure 2: Input Delay Elements
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Functional Description
Storage Element Functions
There are three pairs of storage elements in each IOB, one
pair for each of the three paths. It is possible to configure
each of these storage elements as an edge-triggered
D-type flip-flop (FD) or a level-sensitive latch (LD).
The storage-element pair on either the Output path or the
Three-State path can be used together with a special multiplexer to produce Double-Data-Rate (DDR) transmission.
This is accomplished by taking data synchronized to the
clock signal’s rising edge and converting it to bits synchronized on both the rising and the falling edge. The combination of two registers and a multiplexer is referred to as a
Double-Data-Rate D-type flip-flop (ODDR2).
Table 1 describes the signal paths associated with the storage element.
Table 1: Storage Element Signal Description
Storage
Element
Signal
Description
Function
D
Data input
Data at this input is stored on the active edge of CK and enabled by CE. For latch
operation when the input is enabled, data passes directly to the output Q.
Q
Data output
The data on this output reflects the state of the storage element. For operation as a latch
in transparent mode, Q mirrors the data at D.
CK
Clock input
Data is loaded into the storage element on this input’s active edge with CE asserted.
CE
Clock Enable input
When asserted, this input enables CK. If not connected, CE defaults to the asserted
state.
SR
Set/Reset input
This input forces the storage element into the state specified by the SRHIGH/SRLOW
attributes. The SYNC/ASYNC attribute setting determines if the SR input is
synchronized to the clock or not. If both SR and REV are active at the same time, the
storage element gets a value of 0.
REV
Reverse input
This input is used together with SR. It forces the storage element into the state opposite
from what SR does. The SYNC/ASYNC attribute setting determines whether the REV
input is synchronized to the clock or not. If both SR and REV are active at the same time,
the storage element gets a value of 0.
As shown in Figure 1, the upper registers in both the output
and three-state paths share a common clock. The OTCLK1
clock signal drives the CK clock inputs of the upper registers
on the output and three-state paths. Similarly, OTCLK2
drives the CK inputs for the lower registers on the output
and three-state paths. The upper and lower registers on the
input path have independent clock lines: ICLK1 and ICLK2.
The OCE enable line controls the CE inputs of the upper
and lower registers on the output path. Similarly, TCE con-
trols the CE inputs for the register pair on the three-state
path and ICE does the same for the register pair on the
input path.
The Set/Reset (SR) line entering the IOB controls all six
registers, as is the Reverse (REV) line.
In addition to the signal polarity controls described in IOB
Overview, each storage element additionally supports the
controls described in Table 2.
Table 2: Storage Element Options
Option Switch
4
Function
Specificity
FF/Latch
Chooses between an edge-triggered flip-flop
or a level-sensitive latch
Independent for each storage element
SYNC/ASYNC
Determines whether the SR set/reset control is
synchronous or asynchronous
Independent for each storage element
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Functional Description
Table 2: Storage Element Options
Option Switch
Function
Specificity
SRHIGH/SRLOW
Determines whether SR acts as a Set, which
forces the storage element to a logic "1"
(SRHIGH) or a Reset, which forces a logic "0"
(SRLOW)
Independent for each storage element, except
when using ODDR2. In the latter case, the selection
for the upper element will apply to both elements.
INIT1/INIT0
When Global Set/Reset (GSR) is asserted or
after configuration this option specifies the
initial state of the storage element, either set
(INIT1) or reset (INIT0). By default, choosing
SRLOW also selects INIT0; choosing SRHIGH
also selects INIT1.
Independent for each storage element, except
when using ODDR2, which uses two IOBs. In the
ODDR2 case, selecting INIT0 for one IOBs applies
to both elements within the IOB, although INIT1
could be selected for the elements in the other IOB.
Double-Data-Rate Transmission
The storage-element pair on the Three-State path (TFF1
and TFF2) also can be combined with a local multiplexer to
form a DDR primitive. This permits synchronizing the output
enable to both the rising and falling edges of a clock. This
DDR operation is realized in the same way as for the output
path.
Double-Data-Rate (DDR) transmission describes the technique of synchronizing signals to both the rising and falling
edges of the clock signal. Spartan-3E devices use register
pairs in all three IOB paths to perform DDR operations.
The pair of storage elements on the IOB’s Output path
(OFF1 and OFF2), used as registers, combine with a special multiplexer to form a DDR D-type flip-flop (ODDR2).
This primitive permits DDR transmission where output data
bits are synchronized to both the rising and falling edges of
a clock. DDR operation requires two clock signals (usually
50% duty cycle), one the inverted form of the other. These
signals trigger the two registers in alternating fashion, as
shown in Figure 3. The Digital Clock Manager (DCM) generates the two clock signals by mirroring an incoming signal,
and then shifting it 180 degrees. This approach ensures
minimal skew between the two signals. Alternatively, the
inverter inside the IOB can be used to invert the clock signal, thus only using one clock line and both rising and falling
edges of that clock line as the two clocks for the DDR
flip-flops.
The storage-element pair on the input path (IFF1 and IFF2)
allows an I/O to receive a DDR signal. An incoming DDR
clock signal triggers one register, and the inverted clock signal triggers the other register. The registers take turns capturing bits of the incoming DDR data signal. The primitive to
allow this functionality is called IDDR2.
Aside from high bandwidth data transfers, DDR outputs also
can be used to reproduce, or mirror, a clock signal on the
output. This approach is used to transmit clock and data signals together (source synchronously). A similar approach is
used to reproduce a clock signal at multiple outputs. The
advantage for both approaches is that skew across the outputs is minimal.
DCM
180˚ 0˚
DCM
0˚
FDDR
FDDR
D1
D1
Q1
Q1
CLK1
CLK1
DDR MUX
DDR MUX
Q
D2
Q
D2
Q2
Q2
CLK2
CLK2
DS312-2_20_021105
Figure 3: Two Methods for Clocking the DDR Register
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Functional Description
Register Cascade Feature
In the Spartan-3E family, one of the IOBs in a differential
pair can cascade either its input or output storage elements
with those in the other IOB of the differential pair. This is
intended to make DDR operation at high speed much simpler to implement. The new DDR connections that are available are shown in Figure 1 (dashed lines), and are only
available for routing between IOBs and are not accessible to
the FPGA fabric. Note that this feature is only available
when using differential I/O.
D
Q
D1
PAD
To Fabric
D
Q
IDDRIN2
IQ2
D
Q
D2
ICLK1
IDDR2
ICLK2
As a DDR input pair, the master IOB registers incoming
data on the rising edge of ICLK1 (= D1) and the rising edge
of ICLK2 (= D2), which is typically the same as the falling
edge of ICLK1. This data is then transferred into the FPGA
fabric. At some point, both signals must be brought into the
same clock domain, typically ICLK1. This can be difficult at
high frequencies because the available time is only one half
of a clock cycle assuming a 50% duty cycle. See Figure 4
for a graphical illustration of this function.
In the Spartan-3E device, the signal D2 can be cascaded
into the storage element of the adjacent slave IOB. There it
is re-registered to ICLK1, and only then fed to the FPGA
fabric where it is now already in the same time domain as
D1. Here, the FPGA fabric uses only the clock ICLK1 to process the received data. See Figure 5 for a graphical illustration of this function.
D
Q
D1
PAD
To Fabric
D
Q
D2
ICLK1
ICLK2
d
d
D1
D2
d+1 d+2 d+3 d+4 d+5
d-1
d+2
d+1
PAD
d
d+1
d+2
d+3
d+4
d+5
d+6
d+7
d+8
D1
d
d+2
d+4
d+6
d+8
D2
d-1
d+1
d+3
d+5
d+7
DS312-2_22_030105
Figure 5: Input DDR Using Spartan-3E Cascade Feature
ODDR2
As a DDR output pair, the master IOB registers data coming
from the FPGA fabric on the rising edge of OCLK1 (= D1)
and the rising edge of OCLK2 (= D2), which is typically the
same as the falling edge of OCLK1. These two bits of data
are multiplexed by the DDR mux and forwarded to the output pin. At some point in the FPGA fabric, the signal D2
must be brought into the clock domain OCLK2 from the
domain OCLK1. This can be difficult at high frequencies,
because the time available is only one half a clock cycle.
See Figure 6 for a graphical illustration of this function.
d+6 d+7 d+8
d+4
d+3
ICLK2
In the Spartan-3E device, the signal D2 can be cascaded
via the storage element of the adjacent slave IOB. Here, it is
registered by OCLK1 and then forwarded to the master IOB
where it is re-registered to OCLK2, selected as usual by the
DDR multiplexer, and then forwarded to the output pin. This
way the data for transmission can be processed using just
the clock OCLK1 in the FPGA fabric. See Figure 7 for a
graphical illustration of this function.
ICLK2
ICLK1
PAD
ICLK1
d+6
d+5
d+8
d+7
DS312-2_21_021105
Figure 4: Input DDR (without Cascade Feature)
6
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DS312-2 (v1.1) March 21, 2005
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Functional Description
D
D1
Q
Q
D
D1
PAD
PAD
From
Fabric
From
Fabric
D2
D
ODDROUT1
D2
Q
D
Q
Q
D
ODDRIN2
OCLK1
OCLK2
OCLK1
OCLK2
OCLK1
OCLK1
OCLK2
OCLK2
D1
D2
PAD
d
d+2
d+1
d+4
d+3
d
d+1
d+2
d+6
d+5
d+3
d+8
d+9
d+7
d+4
d+5
d+10
d+6
d+7
d+8
D1
d
D2 d+1
PAD
d
d+2
d+4
d+6
d+8
d+3
d+5
d+7
d+9
d+1
d+2
d+3
d+5
d+6
d+7
d+8
DS312-2_36_030105
DS312-2_23_030105
Figure 6: Output DDR (without Cascade Feature)
d+4
Figure 7: Output DDR Using Spartan-3E Cascade
Feature
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that support a wide range of I/O signaling standards (Table 3 and
Table 4). The majority of the I/Os also can be used to form
differential pairs to support any of the differential signaling
standards (Table 4).
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to “Entry Strategies for Xilinx Constraints” in the Xilinx Software Manuals and Help.
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. Special care must be taken to ensure the input voltages do not
exceed VCCO (see Module 3 for the specifications). For a
particular VCCO voltage, Table 3 and Table 4 list all of the
IOSTANDARDs that can be combined and if the IOSTANDARD is supported as an input only or can be used for both
inputs and outputs.
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Functional Description
Table 3: Single-Ended IOSTANDARD Bank Compatibility
VCCO Supply/Compatibility
Single-Ended
IOSTANDARD
Input Requirements
VREF for
Inputs
Board
Termination
Voltage (VTT)
1.2 V
1.5 V
1.8 V
2.5 V
3.0 V
3.3 V
LVTTL
-
-
-
-
-
Input/
Output
N/R
N/R
LVCMOS33
-
-
-
-
-
Input/
Output
N/R
N/R
LVCMOS25
-
-
-
Input/
Output
Input
Input
N/R
N/R
LVCMOS18
-
-
Input/
Output
Input
Input
Input
N/R
N/R
LVCMOS15
-
Input/
Output
Input
Input
Input
Input
N/R
N/R
LVCMOS12
Input/
Output
Input
Input
Input
Input
Input
N/R(1)
N/R
PCI33_3
-
-
-
-
Input/
Output
Input
N/R
N/R
PCI66_3
-
-
-
-
Input/
Output
Input
N/R
N/R
Input/
Output
Input
N/R
N/R
PCIX
HSTL_I_18
-
-
Input/
Output
Input
Input
Input
0.9
0.9
HSTL_III_18
-
-
Input/
Output
Input
Input
Input
1.1
1.8
SSTL18_I
-
-
Input/
Output
Input
Input
Input
0.9
0.9
SSTL2_I
-
-
-
Input/
Output
Input
Input
1.25
1.25
Notes:
1.
8
N/R - Not required for input operation.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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Functional Description
Table 4: Differential IOSTANDARD Bank Compatibility
VCCO Supply
Differential
IOSTANDARD
2.5V
3.3V
LVDS_25
Input,
On-chip Differential Termination,
Output(1)
Input
RSDS_25
Input,
On-chip Differential Termination,
Output(1)
Input
MINI_LVDS_25
Input,
On-chip Differential Termination,
Output(1)
Input
LVPECL_25
Input,
On-chip Differential Termination
Input
BLVDS_25
Input,
On-chip Differential Termination,
Output
Input
Input Requirements: VREF
N/R
(Not Required)
Notes:
Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling properties (for example, Common-Mode Rejection) of these standards permit exceptionally high data transfer rates. This
subsection introduces the differential signaling capabilities
of Spartan-3E devices.
Each device-package combination designates specific I/O
pairs specially optimized to support differential standards.
Differential pairs can be shown in the Pin and Area Constraints Editor (PACE) with the “Show Differential Pairs”
option. A unique L-number, part of the pin name, identifies
the line-pairs associated with each bank (see Module 4).
For each pair, the letters P and N designate the true and
inverted lines, respectively. For example, the pin names
IO_L43P_3 and IO_L43N_3 indicate the true and inverted
lines comprising the line pair L43 on Bank 3.
VCCO provides current to the outputs and additionally powers the On-Chip Differential Termination. VCCO must be
2.5V when using the On-Chip Differential Termination. The
VREF lines are not required for differential operation.
(See Module 3 for the specific range). The on-chip input differential termination in Spartan-3E devices eliminates the
external 100Ω termination resistor commonly found in differential receiver circuits. Use differential termination for
LVDS, mini-LVDS, and BLVDS as applications permit.
On-chip Differential Termination is available in banks with
VCCO = 2.5V and is not supported on dedicated input pins.
Set the DIFF_TERM attribute to TRUE to enable Differential
Termination on a differential I/O pin pair.
The DIFF_TERM attribute uses the following syntax in the
UCF file:
INST <I/O_BUFFER_INSTANTIATION_NAME>
DIFF_TERM = “<TRUE/FALSE>”;
Spartan-3E
Differential
Output
Spartan-3E
Differential Input
Z0 = 50Ω
100Ω
HSTL and SSTL inputs use the Reference Voltage (VREF) to
bias the input-switching threshold. Once a configuration
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use HSTL/SSTL, a few specifically reserved
I/O pins on the same bank automatically convert to VREF
inputs. For banks that do not contain HSTL or SSTL, VREF
pins remain available for user I/Os or input pins.
Z0 = 50Ω
Spartan-3E
Differential
Output
Z0 = 50Ω
100Ω
1.
Spartan-3E
Differential Input
with On-Chip
Differential
Terminator
Z0 = 50Ω
To further understand how to combine multiple IOSTANDARDs within a bank, refer to IOBs Organized into Banks,
page 10.
DS312-2_24_021505
Figure 8: Differential Inputs and Outputs
On-Chip Differential Termination
Pull-Up and Pull-Down Resistors
Spartan-3E devices provide an on-chip 100Ω differential
termination across the input differential receiver terminals
Pull-up and pull-down resistors inside each IOB optionally
force a floating I/O pin to a determined state. Pull-up and
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Functional Description
pull-down resistors are commonly applied to unused I/Os,
inputs, and three-state outputs, but can be used on any I/O.
The pull-up resistor connects an I/O to VCCO through a
resistor. The resistance value depends on the VCCO voltage
(see Module 3 for the specifications). The pull-down resistor
similarly connects an I/O to ground with a resistor. The PULLUP and PULLDOWN attributes and library primitives turn
on these optional resistors.
By default, PULLDOWN resistors terminate all unused I/Os.
Unused I/Os can alternatively be set to PULLUP or FLOAT.
To change the unused I/O Pad setting, set the Bitstream
Generator (BitGen) option UnusedPin to PULLUP, PULLDOWN, or FLOAT. The UnusedPin option is accessed
through the Properties for Generate Programming File in
ISE.
During configuration a Low logic level on HSWAP activates
the pull-up resistors for all I/Os not used directly in the
selected configuration mode.
Keeper Circuit
Each I/O has an optional keeper circuit (see Figure 9) that
keeps bus lines from floating when not being actively driven.
The KEEPER circuit retains the last logic level on a line after
all drivers have been turned off. Apply the KEEPER
attribute or use the KEEPER library primitive to use the
KEEPER circuitry. Pull-up and pull-down resistors override
the KEEPER settings.
Weak Pull-up
To adjust the drive strength for each output set the DRIVE
attribute to the desired drive strength: 2, 4, 6, 8, 12, and 16.
Table 5: Programmable Output Drive Current
Signal
Standard
Output Drive Current (mA)
2
4
6
8
12
16
LVTTL
LVCMOS33
LVCMOS25
-
-
-
-
-
-
-
-
LVCMOS18
LVCMOS15
LVCMOS12
-
-
High output current drive strength and FAST output slew
rates generally result in fastest I/O performance. However,
these same settings generally also result in transmission
line effects on the printed circuit board (PCB) for all but the
shortest board traces. Each IOB has independent slew rate
and drive strength controls. Use the slowest slew rate and
lowest output drive current that meets the performance
requirements for the end application.
Likewise, due to lead inductance, a given package supports
a limited number of simultaneous switching outputs (SSOs)
when using fast, high-drive outputs. Only use fast,
high-drive outputs when required by the application.
IOBs Organized into Banks
Output Path
The Spartan-3E architecture organizes IOBs into four I/O
banks as shown in Figure 10. Each bank maintains separate VCCO and VREF supplies. The separate supplies allow
each bank to independently set VCCO. Similarly, the VREF
supplies may be set for each bank. Refer to Table 3 and
Table 4 for VCCO and VREF requirements.
Input Path
Keeper
Weak Pull-down
DS312-2_25_022805
Figure 9: Keeper Circuit
Slew Rate Control and Drive Strength
Each IOB has a slew-rate control that sets the output
switching edge-rate for LVCMOS and LVTTL outputs. The
SLEW attribute controls the slew rate and can either be set
to SLOW (default) or FAST.
Each LVCMOS and LVTTL output additionally supports up
to six different drive current strengths as shown in Table 5.
10
When working with Spartan-3E devices, most of the differential I/O standards are compatible and can be combined
within any given bank. Each bank can support any two of
the following differential standards: LVDS_25 outputs,
MINI_LVDS_25 outputs, and RSDS_25 outputs. As an
example, LVDS_25 outputs, RSDS_25 outputs, and any
other differential inputs while using on-chip differential termination are a valid combination. A combination not allowed
is a single bank with LVDS_25 outputs, RSDS_25 outputs,
and MINI_LVDS_25 outputs.
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DS312-2 (v1.1) March 21, 2005
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Functional Description
are outlined for each package, such as pins that are unconnected on one device but connected on another in the same
package or pins that are dedicated inputs on one package
but full I/O on another. When designing the printed circuit
board (PCB), plan for potential future upgrades and package migration.
Bank 1
Bank 3
Bank 0
The Spartan-3E family is not pin-compatible with any previous Xilinx FPGA family.
Dedicated Inputs
Bank 2
1. All VCCO pins on the FPGA must be connected even if a
bank is unused.
Dedicated Inputs are IOBs used only as inputs. Pin names
designate a Dedicated Input if the name starts with IP, for
example, IP or IP_Lxxx_x. Dedicated inputs retain the full
functionality of the IOB for input functions with a single
exception for differential inputs (IP_Lxxx_x). For the differential Dedicated Inputs, the on-chip differential termination
is not available. To replace the on-chip differential termination, choose a differential pair that supports outputs
(IO_Lxxx_x) or use an external 100Ω termination resistor on
the board.
2. All VCCO lines associated within a bank must be set to
the same voltage level.
ESD Protection
DS312-2_26_021205
Figure 10: Spartan-3E I/O Banks (top view)
I/O Banking Rules
When assigning I/Os to banks, these VCCO rules must be
followed:
3. The VCCO levels used by all standards assigned to the
I/Os of any given bank must agree. The Xilinx
development software checks for this. Table 3 and
Table 4 describe how different standards use the VCCO
supply.
4. If a bank does not have any VCCO requirements,
connect VCCO to an available voltage, such as 2.5V or
3.3V. Some configuration modes might place additional
VCCO requirements. Refer to Configuration, page 56
for more information.
If any of the standards assigned to the Inputs of the bank
use VREF, then the following additional rules must be
observed:
1. All VREF pins must be connected within a bank.
2. All VREF lines associated with the bank must be set to
the same voltage level.
3. The VREF levels used by all standards assigned to the
Inputs of the bank must agree. The Xilinx development
software checks for this. Table 3 describes how different
standards use the VREF supply.
If VREF is not required to bias the input switching thresholds,
all associated VREF pins within the bank can be used as
user I/Os or input pins.
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: one diode
extends P-to-N from the pad to VCCO and a second diode
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes limits the ability of Spartan-3E I/Os to tolerate high signal voltages. The VIN absolute maximum rating in Table 1 of
Module 3 specifies the voltage range that I/Os can tolerate.
Supply Voltages for the IOBs
The IOBs are powered by three supplies:
1. The VCCO supplies, one for each of the FPGA’s I/O
banks, power the output drivers. The voltage on the
VCCO pins determines the voltage swing of the output
signal.
2. VCCINT is the main power supply for the FPGA’s internal
logic.
3. VCCAUX is an auxiliary source of power, primarily to
optimize the performance of various FPGA functions
such as I/O switching.
Package Footprint Compatibility
The I/Os During Power-On, Configuration, and
User Mode
Sometimes, applications outgrow the logic capacity of a
specific Spartan-3E FPGA. Fortunately, the Spartan-3E
family is designed so that multiple part types are available in
pin-compatible package footprints, as described in Module
4. In some cases, there are subtle differences between
devices available in the same footprint. These differences
All I/Os have ESD clamp diodes to their respective VCCO
supply and from GND, as shown in Figure 1. The VCCINT
(1.2V), VCCAUX (2.5V), and VCCO supplies can be applied in
any order. Before the FPGA can start its configuration process, VCCINT, VCCO Bank 2, and VCCAUX must have
reached their respective minimum recommended operating
DS312-2 (v1.1) March 21, 2005
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Functional Description
levels (see Table 2 of Module 3). At this time, all I/O drivers
are in a high-impedance state. VCCO Bank 2, VCCINT, and
VCCAUX serve as inputs to the internal Power-On Reset circuit (POR).
A Low level applied to the HSWAP input enables pull-up
resistors on User I/Os from power-on throughout configuration. A High level on HSWAP disables the pull-up resistors,
allowing the I/Os to float. HSWAP contains a weak pull-up
and defaults to High if left floating. As soon as power is
applied, the FPGA begins initializing its configuration memory. At the same time, the FPGA internally asserts the Global Set-Reset (GSR), which asynchronously resets all IOB
storage elements to a default Low state.
Upon the completion of initialization and the beginning of
configuration, INIT_B goes High, sampling the M0, M1, and
M2 inputs to determine the configuration mode. At this point
in time, the configuration data is loaded into the FPGA. The
I/O drivers remain in a high-impedance state (with or without pull-up resistors, as determined by the HSWAP input)
throughout configuration.
At the end of configuration, the GSR net is released, placing
the IOB registers in a Low state by default, unless the
12
loaded design reverses the polarity of their respective SR
inputs.
The Global Three State (GTS) net is released during
Start-Up, marking the end of configuration and the beginning of design operation in the User mode. After the GTS
net is released, all user I/Os go active while all unused I/Os
are weakly pulled down (PULLDOWN). The designer can
control how the unused I/Os are terminated after GTS is
released by setting the Bitstream Generator (BitGen) option
UnusedPin to PULLUP, PULLDOWN, or FLOAT.
One clock cycle later (default), the Global Write Enable
(GWE) net is released allowing the RAM and registers to
change states. Once in User mode, any pull-up resistors
enabled by HSWAP revert to the user settings and HSWAP
is available as a general-purpose I/O. For more information
on PULLUP and PULLDOWN, see Pull-Up and Pull-Down
Resistors.
JTAG Boundary-Scan Capability
All Spartan-3E IOBs support boundary-scan testing compatible with IEEE 1149.1/1532 standards. See JTAG Mode,
page 86 for more information on programming via JTAG.
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DS312-2 (v1.1) March 21, 2005
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Functional Description
Configurable Logic Block (CLB) and
Slice Resources
CLB Overview
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB contains four slices, and
each slice contains two Look-Up Tables (LUTs) to implement logic and two dedicated storage elements that can be
used as flip-flops or latches. The LUTs can be used as a
16x1 memory (RAM16) or as a 16-bit shift register (SRL16),
Spartan-3E
FPGA
and additional multiplexers and carry logic simplify wide
logic and arithmetic functions. Most general-purpose logic
in a design is automatically mapped to the slice resources in
the CLBs. Each CLB is identical, and the Spartan-3E family
CLB structure is identical to that for the Spartan-3 family.
CLB Array
The CLBs are arranged in a regular array of rows and columns as shown in Figure 11.
Each density varies by the number of rows and columns of
CLBs (see Table 6).
X0Y3
X1Y3
X2Y3
X3Y3
X0Y2
X1Y2
X2Y2
X3Y2
X0Y1
X1Y1
X2Y1
X3Y1
X0Y0
X1Y0
X2Y0
X3Y0
IOBs
CLB
Slice
DS312-2_31_021205
Figure 11: CLB Locations
Table 6: Spartan-3E CLB Resources
Device
CLB
Rows
CLB
Columns
CLB
Total(1)
Slices
LUTs /
Flip-Flops
Equivalent
Logic Cells
RAM16 /
SRL16
Distributed
RAM Bits
XC3S100E
22
16
240
960
1920
2160
960
15360
XC3S250E
34
26
612
2448
4896
5508
2448
39168
XC3S500E
46
34
1164
4656
9312
10476
4656
74496
XC3S1200E
60
46
2168
8672
17344
19512
8672
138752
XC3S1600E
76
58
3688
14752
29504
33192
14752
236032
Notes:
1.
The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are
embedded in the array (see Module 1, Figure 1).
Slices
Each CLB comprises four interconnected slices, as shown
in Figure 13. These slices are grouped in pairs. Each pair is
organized as a column with an independent carry chain.
The left pair supports both logic and memory functions and
its slices are called SLICEM. The right pair supports logic
only and its slices are called SLICEL. Therefore half the
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
LUTs support both logic and memory (including both
RAM16 and SRL16 shift registers) while half support logic
only, and the two types alternate throughout the array columns. The SLICEL reduces the size of the CLB and lowers
the cost of the device, and can also provide a performance
advantage over the SLICEM.
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Functional Description
.
WF[4:1]
DS312-2_32_021205
Notes:
1.
2.
Options to invert signal polarity as well as other options that enable lines for various functions are not shown.
The index i can be 6, 7, or 8, depending on the slice. The upper SLICEL has an F8MUX, and the upper SLICEM has
an F7MUX. The lower SLICEL and SLICEM both have an F6MUX.
Figure 12: Simplified Diagram of the Left-Hand SLICEM
14
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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Functional Description
Left-Hand SLICEM
(Logic or Distributed RAM
or Shift Register)
Right-Hand SLICEL
(Logic Only)
COUT
CLB
SLICE
X1Y1
SLICE
X1Y0
COUT
Switch
Matrix
Interconnect
to Neighbors
CIN
SLICE
X0Y1
SHIFTOUT
SHIFTIN
SLICE
X0Y0
CIN
DS099-2_05_082104
Figure 13: Arrangement of Slices within the CLB
Slice Location Designations
Slice Overview
The Xilinx development software designates the location of
a slice according to its X and Y coordinates, starting in the
bottom left corner, as shown in Figure 11. The letter ’X’ followed by a number identifies columns of slices, incrementing from the left side of the die to the right. The letter ’Y’
followed by a number identifies the position of each slice in
a pair as well as indicating the CLB row, incrementing from
the bottom of the die. Figure 13 shows the CLB located in
the lower left-hand corner of the die. The SLICEM always
has an even ’X’ number, and the SLICEL always has an odd
’X’ number.
A slice includes two LUT function generators and two storage elements, along with additional logic, as shown in
Figure 14.
SRL16
RAM16
LUT4 (G)
Both SLICEM and SLICEL have the following elements in
common to provide logic, arithmetic, and ROM functions:
•
•
•
•
Two 4-input LUT function generators, F and G
Two storage elements
Two wide-function multiplexers, F5MUX and FiMUX
Carry and arithmetic logic
FiMUX
Carry
FiMUX
LUT4 (G)
Register
F5MUX
SRL16
RAM16
LUT4 (F)
Carry
Carry
Register
F5MUX
Carry
Register
Register
LUT4 (F)
Arithmetic Logic
Arithmetic Logic
SLICEM
SLICEL
DS312-2_13_020905
Figure 14: Resources in a Slice
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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15
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Functional Description
Enable (CE), Slice Write Enable (SLICEWE1), and
Reset/Set (RS) are shared in common between the two
halves.
The SLICEM pair supports two additional functions:
•
•
Two 16x1 distributed RAM blocks, RAM16
Two 16-bit shift registers, SRL16
Each of these elements is described in more detail in the following sections.
Logic Cells
The combination of a LUT and a storage element is known
as a "Logic Cell". The additional features in a slice, such as
the wide multiplexers, carry logic, and arithmetic gates, add
to the capacity of a slice, implementing logic that would otherwise require additional LUTs. Benchmarks have shown
that the overall slice is equivalent to 2.25 simple logic cells.
This calculation provides the equivalent logic cell count
shown in Table 6.
Slice Details
Figure 16 is a detailed diagram of the SLICEM. It represents
a superset of the elements and connections to be found in
all slices. The dashed and gray lines (blue when viewed in
color) indicate the resources found only in the SLICEM and
not in the SLICEL.
Each slice has two halves, which are differentiated as top
and bottom to keep them distinct from the upper and lower
slices in a CLB. The control inputs for the clock (CLK), Clock
The LUTs located in the top and bottom portions of the slice
are referred to as "G" and "F", respectively, or the "G-LUT"
and the "F-LUT". The storage elements in the top and bottom portions of the slice are called FFY and FFX, respectively.
Each slice has two multiplexers with F5MUX in the bottom
portion of the slice and FiMUX in the top portion. Depending
on the slice, the FiMUX takes on the name F6MUX,
F7MUX, or F8MUX, according to its position in the multiplexer chain. The lower SLICEL and SLICEM both have an
F6MUX. The upper SLICEM has an F7MUX, and the upper
SLICEL has an F8MUX.
The carry chain enters the bottom of the slice as CIN and
exits at the top as COUT. Five multiplexers control the chain:
CYINIT, CY0F, and CYMUXF in the bottom portion and
CY0G and CYMUXG in the top portion. The dedicated arithmetic logic includes the exclusive-OR gates XORF and
XORG (bottom and top portions of the slice, respectively)
as well as the AND gates FAND and GAND (bottom and top
portions, respectively).
See Table 7 for a description of all the slice input and output
signals.
Table 7: Slice Inputs and Outputs
Name
Location
Direction
Description
F[4:1]
SLICEL/M Bottom
Input
F-LUT and FAND inputs
G[4:1]
SLICEL/M Top
Input
G-LUT and GAND inputs or Write Address (SLICEM)
BX
SLICEL/M Bottom
Input
Bypass to or output (SLICEM) or storage element, or control input to
F5MUX, input to carry logic, or data input to RAM (SLICEM)
BY
SLICEL/M Top
Input
Bypass to or output (SLICEM) or storage element, or control input to
FiMUX, input to carry logic, or data input to RAM (SLICEM)
BXOUT
SLICEM Bottom
Output
BX bypass output
BYOUT
SLICEM Top
Output
BY bypass output
ALTDIG
SLICEM Top
Input
DIG
SLICEM Top
Output
SLICEWE1
SLICEM Common
Input
F5
SLICEL/M Bottom
Output
FXINA
SLICEL/M Top
Input
Input to FiMUX; direct feedback from F5MUX or another FiMUX
FXINB
SLICEL/M Top
Input
Input to FiMUX; direct feedback from F5MUX or another FiMUX
Fi
SLICEL/M Top
Output
CE
SLICEL/M Common
Input
FFX/Y Clock Enable
SR
SLICEL/M Common
Input
FFX/Y Set or Reset or RAM Write Enable (SLICEM)
16
Alternate data input to RAM
ALTDIG or SHIFTIN bypass output
RAM Write Enable
Output from F5MUX; direct feedback to FiMUX
Output from FiMUX; direct feedback to another FiMUX
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Functional Description
Table 7: Slice Inputs and Outputs (Continued)
Name
Location
Direction
CLK
SLICEL/M Common
Input
FFX/Y Clock or RAM Clock (SLICEM)
SHIFTIN
SLICEM Top
Input
Data input to G-LUT RAM
SHIFTOUT
SLICEM Bottom
CIN
SLICEL/M Bottom
COUT
SLICEL/M Top
Output
Carry chain output
X
SLICEL/M Bottom
Output
Combinatorial output
Y
SLICEL/M Top
Output
Combinatorial output
XB
SLICEL/M Bottom
Output
Combinatorial output from carry or F-LUT SRL16 (SLICEM)
YB
SLICEL/M Top
Output
Combinatorial output from carry or G-LUT SRL16 (SLICEM)
XQ
SLICEL/M Bottom
Output
FFX output
YQ
SLICEL/M Top
Output
FFY output
Output
Input
Description
Shift data output from F-LUT RAM
Carry chain input
Main Logic Paths
Central to the operation of each slice are two nearly identical data paths at the top and bottom of the slice. The
description that follows uses names associated with the bottom path. (The top path names appear in parentheses.) The
basic path originates at an interconnect switch matrix outside the CLB. See Interconnect for more information on the
switch matrix and the routing connections.
Four lines, F1 through F4 (or G1 through G4 on the upper
path), enter the slice and connect directly to the LUT. Once
inside the slice, the lower 4-bit path passes through a LUT
"F" (or "G") that performs logic operations. The LUT Data
output, "D", offers five possible paths:
1. Exit the slice via line "X" (or "Y") and return to
interconnect.
2. Inside the slice, "X" (or "Y") serves as an input to the
DXMUX (or DYMUX) which feeds the data input, "D", of
the FFY (or FFX) storage element. The "Q" output of
the storage element drives the line XQ (or YQ) which
exits the slice.
BY in the top half) can take any of several possible
branches:
1. Bypass both the LUT and the storage element, and
then exit the slice as BXOUT (or BYOUT) and return to
interconnect.
2. Bypass the LUT, and then pass through a storage
element via the D input before exiting as XQ (or YQ).
3. Control the wide function multiplexer F5MUX (or
FiMUX).
4. Via multiplexers, serve as an input to the carry chain.
5. Drive the DI input of the LUT.
6. BY can control the REV inputs of both the FFY and FFX
storage elements. See Storage Element Functions.
7. Finally, the DIG_MUX multiplexer can switch BY onto
the DIG line, which exits the slice.
The control inputs CLK, CE, SR, BX and BY have programmable polarity. The LUT inputs do not need programmable
polarity because their function can be inverted inside the
LUT.
3. Control the CYMUXF (or CYMUXG) multiplexer on the
carry chain.
The sections that follow provide more detail on individual
functions of the slice.
4. With the carry chain, serve as an input to the XORF (or
XORG) exclusive-OR gate that performs arithmetic
operations, producing a result on "X" (or "Y").
Look-Up Tables
5. Drive the multiplexer F5MUX to implement logic
functions wider than four bits. The "D" outputs of both
the F-LUT and G-LUT serve as data inputs to this
multiplexer.
In addition to the main logic paths described above, there
are two bypass paths that enter the slice as BX and BY.
Once inside the FPGA, BX in the bottom half of the slice (or
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
The Look-Up Table or LUT is a RAM-based function generator and is the main resource for implementing logic functions. Furthermore, the LUTs in each SLICEM pair can be
configured as Distributed RAM or a 16-bit shift register, as
described later.
Each of the two LUTs (F and G) in a slice have four logic
inputs (A1-A4) and a single output (D). Any four-variable
Boolean logic operation can be implemented in one LUT.
Functions with more inputs can be implemented by cascad-
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17
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Functional Description
ing LUTs or by using the wide function multiplexers that are
described later.
The output of the LUT can connect to the wide multiplexer
logic, the carry and arithmetic logic, or directly to a CLB output or to the CLB storage element. See Figure 15.
Y
G[4:1]
D
A[4:1]
Wide Multiplexers
Wide-function multiplexers effectively combine LUTs in
order to permit more complex logic operations. Each slice
has two of these multiplexers with F5MUX in the bottom portion of the slice and FiMUX in the top portion. The F5MUX
multiplexes the two LUTs in a slice. The FiMUX multiplexes
two CLB inputs which connect directly to the F5MUX and
FiMUX results from the same slice or from other slices. See
Figure 16.
YQ
FFY
G-LUT
X
4
F[4:1]
A[4:1]
D
XQ
FFX
F-LUT
DS312-2_33_022205
Figure 15: LUT Resources in a Slice
FiMUX
FXINA
1
FXINB
0
FX (Local Feedback to FXIN)
Y (General Interconnect)
BY
YQ
D Q
F5MUX
F[4:1]
LUT
1
G[4:1]
LUT
0
F5 (Local Feedback to FXIN)
X (General Interconnect)
BX
XQ
D Q
x312-2_34_021205
Figure 16: Dedicated Multiplexers in Spartan-3E CLB
Depending on the slice, FiMUX takes on the name F6MUX,
F7MUX, or F8MUX. The designation indicates the number
of inputs possible without restriction on the function. For
example, an F7MUX can generate any function of seven
inputs. Figure 17 shows the names of the multiplexers in
each position in the Spartan-3E CLB. The figure also
includes the direct connections within the CLB, along with
the F7MUX connection to the CLB below.
Each mux can create logic functions of more inputs than
indicated by its name. The F5MUX, for example, can gener-
18
ate any function of five inputs, with four inputs duplicated to
two LUTs and the fifth input controlling the mux. Because
each LUT can implement independent 2:1 muxes, the
F5MUX can combine them to create a 4:1 mux, which is a
six-input function. If the two LUTs have completely independent sets of inputs, some functions of all nine inputs can be
implemented. Table 8 shows the connections for each multiplexer and the number of inputs possible for different types
of functions.
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Functional Description
FXINB
F8
X
F5
F5
FXINA
FXINB
F6
FX
FXINA
F5
FXINB
FXINA
F7
F5
FX
F5
F5
F6
FX
F5
F5
FXINB
FXINA
DS312-2_38_021305
Figure 17: Muxes and Dedicated Feedback in
Spartan-3E CLB
Table 8: Mux Capabilities
Total Number of Inputs per Function
Mux
Usage
Input Source
For Any
Function
For Mux
For Limited
Functions
F5MUX
F5MUX
LUTs
5
6 (4:1 mux)
9
FiMUX
F6MUX
F5MUX
6
11 (8:1 mux)
19
F7MUX
F6MUX
7
20 (16:1 mux)
39
F8MUX
F7MUX
8
37 (32:1 mux)
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Advance Product Specification
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Functional Description
The wide multiplexers can be used by the automatic tools or
instantiated in a design using a component such as the
F5MUX. The symbol, signals, and function are described
below. The description is similar for the F6MUX, F7MUX,
and F8MUX. Each has versions with a general output, local
output, or both.
I0
0
I1
1
LO
O
S
DS312-2_35_021205
Figure 18: F5MUX with Local and General Outputs
Outputs
S
I0
I1
O
LO
0
1
X
1
1
0
0
X
0
0
1
X
1
1
1
1
X
0
0
0
For more details on using the multiplexers, see XAPP466:
"Using Dedicated Multiplexers in Spartan-3 FPGAs".
The carry chain, together with various dedicated arithmetic
logic gates, support fast and efficient implementations of
math operations. The carry logic is automatically used for
most arithmetic functions in a design. The gates and multiplexers of the carry and arithmetic logic can also be used for
general-purpose logic, including simple wide Boolean functions.
Function
I0
Input selected when S is Low
I1
Input selected when S is High
S
Select input
LO
Local Output that connects to the F5 or FX CLB
pins, which use local feedback to the FXIN
inputs to the FiMUX for cascading
O
General Output that connects to the
general-purpose combinatorial or registered
outputs of the CLB
20
Inputs
Carry and Arithmetic Logic
Table 9: F5MUX Inputs and Outputs
Signal
Table 10: F5MUX Function
The carry chain enters the slice as CIN and exits as COUT,
controlled by several multiplexers. The carry chain connects
directly from one CLB to the CLB above. The carry chain
can be initialized at any point from the BX (or BY) inputs.
The dedicated arithmetic logic includes the exclusive-OR
gates XORF and XORG (upper and lower portions of the
slice, respectively) as well as the AND gates GAND and
FAND (upper and lower portions, respectively). These gates
work in conjunction with the LUTs to implement efficient
arithmetic functions, including counters and multipliers, typically at two bits per slice. See Figure 19 and Table 11.
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Functional Description
COUT
YB
1
G[4:1]
CYMUXG
A[4:1]
G1
G2
Y
CYSELG
G-LUT
YQ
D
XORG
FFY
CY0G
GAND
1
0
BY
XB
1
4
F[4:1]
CYMUXF
A[4:1]
F1
F2
X
CYSELF
F-LUT
XQ
D
XORF
FFX
CY0F
FAND
CYINIT
1
0
BX
CIN
DS312-2_14_021305
Figure 19: Carry Logic
Table 11: Carry Logic Functions
Function
Description
CYINIT
Initializes carry chain for a slice. Fixed selection of:
• CIN carry input from the slice below
• BX input
CY0F
Carry generation for bottom half of slice. Fixed selection of:
• F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated)
• FAND gate for multiplication
• BX input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
CY0G
Carry generation for top half of slice. Fixed selection of:
• G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated)
• GAND gate for multiplication
• BY input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
CYMUXF
Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of:
• CYINIT carry propagation (CYSELF = 1)
• CY0F carry generation (CYSELF = 0)
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Functional Description
Table 11: Carry Logic Functions (Continued)
Function
Description
CYMUXG
Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of:
• CYMUXF carry propagation (CYSELG = 1)
• CY0G carry generation (CYSELG = 0)
CYSELF
Carry generation or propagation select for bottom half of slice. Fixed selection of:
• F-LUT output (typically XOR result)
• Fixed "1" to always propagate
CYSELG
Carry generation or propagation select for top half of slice. Fixed selection of:
• G-LUT output (typically XOR result)
• Fixed "1" to always propagate
XORF
Sum generation for bottom half of slice. Inputs from:
• F-LUT
• CYINIT carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
XORG
Sum generation for top half of slice. Inputs from:
• G-LUT
• CYMUXF carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
FAND
Multiplier partial product for bottom half of slice. Inputs:
• F-LUT F1 input
• F-LUT F2 input
Result is sent through CY0F to become the carry generate signal into CYMUXF
GAND
Multiplier partial product for top half of slice. Inputs:
• G-LUT G1 input
• G-LUT G2 input
Result is sent through CY0G to become the carry generate signal into CYMUXG
The basic usage of the carry logic is to generate a half-sum
in the LUT via an XOR function, which generates or propagates a carry out COUT via the carry mux CYMUXF (or
CYMUXG), and then complete the sum with the dedicated
XORF (or XORG) gate and the carry input CIN. This structure allows two bits of an arithmetic function in each slice.
The CYMUXF (or CYMUXG) can be instantiated using the
MUXCY element, and the XORF (or XORG) can be instantiated using the XORCY element.
LUT
The FAND (or GAND) gate is used for partial product multiplication and can be instantiated using the MULT_AND
component. Partial products are generated by two-input
AND gates and then added. The carry logic is efficient for
the adder, but one of the inputs must be outside the LUT as
shown in Figure 20. The FAND (or GAND) gate is used to
duplicate one of the partial products, while the LUT generates both partial products and the XOR function, as shown
in Figure 21.
LUT
COUT
B
MUXCY
A
COUT
Am
Bn+1
Am+1
Bn
Sum
Pm+1
XORCY
CIN
MULT_AND
DS312-2_37_021305
Figure 20: Using the MUXCY and XORCY in the Carry
Logic
22
CIN
DS312-2_39_021305
Figure 21: Using the MULT_AND for Multiplication in
Carry Logic
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Functional Description
Storage Elements
tom portions of the slice are called FFY and FFX, respectively. FFY has a fixed multiplexer on the D input selecting
either the combinatorial output Y or the bypass signal BY.
FFX selects between the combinatorial output X or the
bypass signal BX.
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive transparent latch, provides a means for synchronizing data to a clock signal,
among other uses. The storage elements in the top and bot-
The functionality of a slice storage element is identical to
that described earlier for the I/O storage elements. All signals have programmable polarity; the default active-High
function is described.
The MULT_AND is useful for small multipliers. Larger multipliers can be built using the dedicated 18x18 multiplier
blocks (see Dedicated Multipliers).
Table 12: Storage Element Signals
Signal
Description
D
Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High
during the Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate
enable (GE) are High and R and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low
gate transition is stored in the latch. The data on the Q output of the latch remains unchanged as long as G or
GE remains Low.
Q
Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch.
C
Clock for edge-triggered flip-flops.
G
Gate for level-sensitive latches.
CE
Clock Enable for flip-flops.
GE
Gate Enable for latches.
S
Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the
Low-to-High clock (C) transition. A latch output is immediately set, output High.
R
Synchronous Reset (Q = Low); has precedence over Set.
PRE
Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High,
during the Low-to-High clock (C) transition. A latch output is immediately set, output High.
CLR
Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low
SR
CLB input for R, S, CLR, or PRE
REV
CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
The control inputs R, S, CE, and C are all shared between
the two flip-flops in a slice.
Table 13: FD Flip-Flop Functionality with Synchronous
Reset, Set, and Clock Enable
Inputs
S
FDRSE
D
CE
C
Q
R
Outputs
R
S
CE
D
C
Q
1
X
X
X
↑
0
0
1
X
X
↑
1
0
0
0
X
X
No Change
0
0
1
1
↑
1
0
0
1
0
↑
0
DS312-2_40_021305
Figure 22: FD Flip-Flop Component with Synchronous
Reset, Set, and Clock Enable
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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23
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Functional Description
Initialization
Description
ing a 16x1 configuration in one LUT. Multiple SLICEM LUTs
can be combined in various ways to store larger amounts of
data, including 16x4, 32x2, or 64x1 configurations in one
CLB. The fifth and sixth address lines required for the
32-deep and 64-deep configurations, respectively, are
implemented using the BX and BY inputs, which connect to
the write enable logic for writing and the F5MUX and
F6MUX for reading.
SR
Set/Reset input. Forces the storage element
into the state specified by the attribute SRHIGH
or SRLOW. SRHIGH forces a logic “1” when SR
is asserted. SRLOW forces a logic “0”. For each
slice, set and reset can be set to be
synchronous or asynchronous.
Writing to distributed RAM is always synchronous to the
SLICEM clock (WCLK for distributed RAM) and enabled by
the SLICEM SR input which functions as the active-High
Write Enable (WE). The read operation is asynchronous,
and, therefore, during a write, the output initially reflects the
old data at the address being written.
REV
Reverse of Set/Reset input. A second input
(BY) forces the storage element into the
opposite state. The reset condition is
predominant over the set condition if both are
active. Same synchronous/asynchronous
setting as for SR.
GSR
Global Set/Reset. GSR defaults to active High
but can be inverted by adding an inverter in
front of the GSR input of the
STARTUP_SPARTAN3E element. The initial
state after configuration or GSR is defined by a
separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and
setting the SRHIGH attribute sets INIT1.
The distributed RAM outputs can be captured using the
flip-flops within the SLICEM element. The WE write-enable
control for the RAM and the CE clock-enable control for the
flip-flop are independent, but the WCLK and CLK clock
inputs are shared. Because the RAM read operation is
asynchronous, the output data always reflects the currently
addressed RAM location.
The CLB storage elements are initialized at power-up, during configuration, by the global GSR signal, and by the individual SR or REV inputs to the CLB.
Table 14: Slice Storage Element Initialization
Signal
Distributed RAM
The LUTs in the SLICEM can be programmed as distributed
RAM. This type of memory affords moderate amounts of
data buffering anywhere along a data path. One SLICEM
LUT stores 16 bits (RAM16). The four LUT inputs F[4:1] or
G[4:1] become the address lines labeled A[4:1] in the
device model and A[3:0] in the design components, provid-
A dual-port option combines two LUTs so that memory
access is possible from two independent data lines. The
same data is written to both 16x1 memories but they have
independent read address lines and outputs. The dual-port
function is implemented by cascading the G-LUT address
lines, which are used for both read and write, to the F-LUT
write address lines (WF[4:1] in Figure 12), and by cascading the G-LUT data input D1 through the DIF_MUX in
Figure 12 and to the D1 input on the F-LUT. One CLB provides a 16x1 dual-port memory as shown in Figure 23.
Any write operation on the D input and any read operation
on the SPO output can occur simultaneously with and independently from a read operation on the second read-only
port, DPO.
SLICEM
D
A[3:0]
16x1
LUT
RAM
(Read/
Write)
WE
SPO
Optional
Register
WCLK
DPRA[3:0]
DPO
16x1
LUT
RAM
(Read
Only)
Optional
Register
DS312-2_41_021305
Figure 23: RAM16X1D Dual-Port Usage
24
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Table 16: Distributed RAM Signals (Continued)
RAM16X1D
WE
D
WCLK
A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3
SPO
Signal
Description
DPO
A0, A1, A2, A3
(A4, A5)
The address inputs select the memory
cells for read or write. The width of the
port determines the required address
inputs.
D
The data input provides the new data
value to be written into the RAM.
O, SPO, and
DPO
The data output O on single-port RAM
or the SPO and DPO outputs on
dual-port RAM reflects the contents of
the memory cells referenced by the
address inputs. Following an active
write clock edge, the data out (O or
SPO) reflects the newly written data.
DS312-2_42_021305
Figure 24: Dual-Port RAM Component
Table 15: Dual-Port RAM Function
Inputs
Outputs
WE (mode)
WCLK
D
SPO
DPO
0 (read)
X
X
data_a
data_d
1 (read)
0
X
data_a
data_d
1 (read)
1
X
data_a
data_d
1 (write)
↑
D
D
data_d
1 (read)
↓
X
data_a
data_d
Notes:
1.
2.
For more information on distributed RAM, see XAPP464:
"Using Look-Up Tables as Distributed RAM in Spartan-3
FPGAs".
Table 16: Distributed RAM Signals
WCLK
WE
Description
The clock is used for synchronous
writes. The data and the address input
pins have setup times referenced to the
WCLK pin. Active on the positive edge
by default with built-in programmable
polarity.
The enable pin affects the write
functionality of the port. An inactive
Write Enable prevents any writing to
memory cells. An active Write Enable
causes the clock edge to write the data
input signal to the memory location
pointed to by the address inputs. Active
High by default with built-in
programmable polarity.
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
The global write enable signal, GWE, is asserted automatically at the end of device configuration to enable all writable
elements. The GWE signal guarantees that the initialized
distributed RAM contents are not disturbed during the configuration process.
The distributed RAM is useful for smaller amounts of memory. Larger memory requirements can use the dedicated
18Kbit RAM blocks (see Block RAM).
data_a = word addressed by bits A3-A0.
data_d = word addressed by bits DPRA3-DPRA0.
Signal
The INIT attribute can be used to preload the memory with
data during FPGA configuration. The default initial contents
for RAM is all zeros. If the WE is held Low, the element can
be considered a ROM. The ROM function is possible even
in the SLICEL.
Shift Registers
It is possible to program each SLICEM LUT as a 16-bit shift
register (see Figure 25). Used in this way, each LUT can
delay serial data anywhere from 1 to 16 clock cycles without
using any of the dedicated flip-flops. The resulting programmable delays can be used to balance the timing of data
pipelines.
The SLICEM LUTs cascade from the G-LUT to the F-LUT
through the DIFMUX (see Figure 12). SHIFTIN and
SHIFTOUT lines cascade a SLICEM to the SLICEM below
to form larger shift registers. The four SLICEM LUTs of a
single CLB can be combined to produce delays up to 64
clock cycles. It is also possible to combine shift registers
across more than one CLB.
www.xilinx.com
25
R
Functional Description
I
SRLC16
SHIFTIN
SRLC16E
D
CE
CLK
A0
A1
A2
A3
SHIFT-REG
A[3:0]
4
A[3:0]
Output
D
MC15
D
WS
Q
DI
Registered
Output
Q
Q15
DS312-2_43_021305
DI (BY)
WSG
CE (SR)
CLK
Figure 26: SRL16 Shift Register Component with
Cascade and Clock Enable
(optional)
WE
CK
SHIFTOUT
or YB
X465_03_040203
Figure 25: Logic Cell SRL16 Structure
Each shift register provides a shift output MC15 for the last
bit in each LUT, in addition to providing addressable access
to any bit in the shift register through the normal D output.
The address inputs A[3:0] are the same as the distributed
RAM address lines, which come from the LUT inputs F[4:1]
or G[4:1]. At the end of the shift register, the CLB flip-flop
can be used to provide one more shift delay for the addressable bit.
The shift register element is known as the SRL16 (Shift
Register LUT 16-bit), with a ‘C’ added to signify a cascade
ability (Q15 output) and ‘E’ to indicate a Clock Enable. See
Figure 26 for an example of the SRLC16E component.
26
The functionality of the shift register is shown in Table 17.
The SRL16 shifts on the rising edge of the clock input when
the Clock Enable control is High. This shift register cannot
be initialized either during configuration or during operation
except by shifting data into it. The clock enable and clock
inputs are shared between the two LUTs in a SLICEM. The
clock enable input is automatically kept active if unused.
Table 17: SRL16 Shift Register Function
Inputs
Outputs
Am
CLK
CE
D
Q
Q15
Am
X
0
X
Q[Am]
Q[15]
Am
↑
1
D
Q[Am-1]
Q[15]
Notes:
1.
m = 0, 1, 2, 3.
For more information on the SRL16, refer to XAPP465:
"Using Look-Up Tables as Shift Registers (SRL16) in
Spartan-3 FPGAs".
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Block RAM
Spartan-3E devices incorporate 4 to 36 dedicated block
RAMs, which are organized as dual-port configurable
18 Kbit blocks. Functionally, the block RAM is identical to
the Spartan-3 architecture block RAM. Block RAM synchronously stores large amounts of data while distributed RAM,
previously described, is better suited for buffering small
amounts of data anywhere along signal paths. This section
describes basic block RAM functions. For detailed implementation information, refer to XAPP463: "Using Block
RAM in Spartan-3 Series FPGAs".
Each block RAM is configurable by setting the content’s initial values, default signal value of the output registers, port
aspect ratios, and write modes. Block RAM can be used in
single-port or dual-port modes.
block RAM’s shared connectivity with the multipliers are
located in XAPP463.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical
data ports called A and B permit independent access to the
common block RAM, which has a maximum capacity of
18,432 bits, or 16,384 bits with no parity bits (see parity bits
description in Table 19). Each port has its own dedicated
set of data, control, and clock lines for synchronous read
and write operations. There are four basic data paths, as
shown in Figure 27:
1. Write to and read from Port A
2. Write to and read from Port B
3. Data transfer from Port A to Port B
4. Data transfer from Port B to Port A
Read 3
Write
4 Read
Write
Spartan-3E
Dual-Port
Block RAM
Port B
The block RAMs are located together with the multipliers on
the die in one or two columns depending on the size of the
device. The XC3S100E has one column of block RAM. The
Spartan-3E devices ranging from the XC3S250E to
XC3S1600E have two columns of block RAM. Table 18
shows the number of RAM blocks, the data storage capacity, and the number of columns for each device. Row(s) of
CLBs are located above and below each block RAM column.
Port A
Arrangement of RAM Blocks on Die
Write
Write
Read
Read
2
1
Table 18: Number of RAM Blocks by Device
DS312-2_01_020705
Total
Number of
RAM
Blocks
Total
Addressable
Locations
(bits)
Number
of
Columns
XC3S100E
4
73,728
1
XC3S250E
12
221,184
2
XC3S500E
20
368,640
2
XC3S1200E
28
516,096
2
XC3S1600E
36
663,552
2
Device
Immediately adjacent to each block RAM is an embedded
18x18 hardware multiplier. The upper 16 bits of the block
RAM's Port A Data input bus are shared with the upper 16
bits of the A multiplicand input bus of the multiplier. Similarly,
the upper 16 bits of Port B's data input bus are shared with
the B multiplicand input bus of the multiplier. Details on the
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
Figure 27: Block RAM Data Paths
Number of Ports
A choice among primitives determines whether the block
RAM functions as dual- or single-port memory. A name of
the form RAMB16_S[wA]_S[wB] calls out the dual-port primitive, where the integers wA and wB specify the total data
path width at ports A and B, respectively. Thus, a
RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A
and an 18-bit Port B. A name of the form RAMB16_S[w]
identifies the single-port primitive, where the integer w
specifies the total data path width of the lone port A. A
RAMB16_S18 is a single-port RAM with an 18-bit port.
Port Aspect Ratios
Each port of the block RAM can be configured independently to select a number of different possible widths for the
data input (DI) and data output (DO) signals as shown in
Table 19.
www.xilinx.com
27
R
Functional Description
Table 19: Port Aspect Ratios
Total Data
Path Width
(w bits)
DI/DO Data
Bus Width
(w-p bits)1
DIP/DOP
Parity Bus
Width
(p bits)
ADDR
Bus
Width
(r bits)2
DI/DO
[w-p-1:0]
DIP/DOP
[p-1:0]
ADDR
[r-1:0]
No. of
Addressable
Locations (n)3
Block RAM
Capacity
(w*n bits)4
1
1
0
14
[0:0]
-
[13:0]
16,384
16,384
2
2
0
13
[1:0]
-
[12:0]
8,192
16,384
4
4
0
12
[3:0]
-
[11:0]
4,096
16,384
9
8
1
11
[7:0]
[0:0]
[10:0]
2,048
18,432
18
16
2
10
[15:0]
[1:0]
[9:0]
1,024
18,432
36
32
4
9
[31:0]
[3:0]
[8:0]
512
18,432
Notes:
1.
2.
3.
4.
The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p).
The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as:
r = 14 – [log(w–p)/log(2)].
The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2r.
The product of w and n yields the total block RAM capacity.
If the data bus width of Port A differs from that of Port B, the
block RAM automatically performs a bus-matching function
as described in Figure 28. When data is written to a port
with a narrow bus and then read from a port with a wide bus,
the latter port effectively combines “narrow” words to form
“wide” words. Similarly, when data is written into a port with
a wide bus and then read from a port with a narrow bus, the
latter port divides “wide” words to form “narrow” words. Par-
28
ity bits are not available if the data port width is configured
as x4, x2, or x1. For example, if a x36 data word (32 data, 4
parity) is addressed as two x18 halfwords (16 data, 2 parity), the parity bits associated with each data byte are
mapped within the block RAM to the appropriate parity bits.
The same effect happens when the x36 data word is
mapped as four x9 words.
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Parity
Data
35 34 33 32 31
512x36
P3 P2 P1 P0
24 23
Byte 3
Address
16 15
Byte 2
8 7
17 16 15
1Kx18
Pa
r
(16 ity O
K
2K bits ption
bits
a
d
pa ata, l
r ity
)
0
Byte 1
Byte 0
0
8 7
0
P3 P2
Byte 3
Byte 2
P1 P0
Byte 1
Byte 0
8
2Kx9
1
0
7
0
P3
Byte 3
P2
Byte 2
P1
Byte 1
P0
Byte 0
3
2
1
0
3 2 1 0
7 6 5 34
y te1 0
3B 2
7
6
7 6 5 04
te
3B2y 1 0
1
0
4Kx4
6
4
2
0
Byte 3
F
E
D
C
7
5
3
1
6
4
2
0
3
2
1
0
8Kx2
Byte 0
No Parity
(16Kbits data)
1 0
7
5
3
1
Byte 3
0
7
6
5
4
1F
1E
1D
1C
3
2
1
0
3
2
1
0
Byte 0
16Kx1
DS312-2_02_020705
Figure 28: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
Block RAM Port Signal Definitions
Representations
of
the
dual-port
primitive
RAMB16_S[wA]_S[wB] and the single-port primitive
RAMB16_S[w] with their associated signals are shown in
Figure 29a and Figure 29b, respectively. These signals are
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
defined in Table 20. The control signals (WE, EN, CLK, and
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
www.xilinx.com
29
R
Functional Description
WEA
ENA
SSRA
CLKA
ADDRA[rA–1:0]
DIA[wA–pA–1:0]
DIPA[pA–1:0]
RAMB16_wA_wB
DOPA[pA–1:0]
DOA[wA–pA–1:0]
WEB
ENB
SSRB
CLKB
ADDRB[rB–1:0]
DIB[wB–pB–1:0]
DIPB[pB–1:0]
DOPB[pB–1:0]
DOB[wB–pB–1:0]
WE
EN
SSR
CLK
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
(a) Dual-Port
RAMB16_Sw
DOP[p–1:0]
DO[w–p–1:0]
(b) Single-Port
DS312-2_03_021305
Notes:
1.
2.
3.
4.
wA and wB are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
pA and pB are integers that indicate the number of data path lines serving as parity bits.
rA and rB are integers representing the address bus width at ports A and B, respectively.
The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 29: Block RAM Primitives
Table 20: Block RAM Port Signals
Signal
Description
Address Bus
Data Input Bus
Port A
Signal
Name
Port B
Signal
Name
Direction
ADDRA
ADDRB
Input
The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path
determines the number of available address lines (r), as per
Table 18.
DIA
DIB
Input
Data at the DI input bus is written to the RAM location specified
by the address input bus (ADDR) during the active edge of the
CLK input, when the clock enable (EN) and write enable (WE)
inputs are active.
Function
It is possible to configure a port’s DI input bus width (w-p) based
on Table 18. This selection applies to both the DI and DO paths
of a given port.
Parity Data
Input(s)
30
DIPA
DIPB
Input
Parity inputs represent additional bits included in the data input
path. Although referred to herein as “parity” bits, the parity inputs
and outputs have no special functionality for generating or
checking parity and can be used as additional data bits. The
number of parity bits ‘p’ included in the DI (same as for the DO
bus) depends on a port’s total data path width (w). See Table 18.
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Table 20: Block RAM Port Signals (Continued)
Signal
Description
Port A
Signal
Name
Port B
Signal
Name
Direction
Data Output Bus
DOA
DOB
Output
Function
Data is written to the DO output bus from the RAM location
specified by the address input bus, ADDR. See the DI signal
description for DO port width configurations.
Basic data access occurs on the active edge of the CLK when
WE is inactive and EN is active. The DO outputs mirror the data
stored in the address ADDR memory location. Data access with
WE active if the WRITE_MODE attribute is set to the value:
WRITE_FIRST, which accesses data after the write takes place.
READ_FIRST accesses data before the write occurs. A third
attribute, NO_CHANGE, latches the DO outputs upon the
assertion of WE. See Block RAM Data Operations for details on
the WRITE_MODE attribute.
Parity Data
Output(s)
DOPA
DOPB
Output
Parity outputs represent additional bits included in the data input
path. The number of parity bits ‘p’ included in the DI bus (same
as for the DO bus) depends on a port’s total data path width (w).
See the DIP signal description for configuration details.
Write Enable
WEA
WEB
Input
When asserted together with EN, this input enables the writing of
data to the RAM. When WE is inactive with EN asserted, read
operations are still possible. In this case, a latch passes data
from the addressed memory location to the DO outputs.
Clock Enable
ENA
ENB
Input
When asserted, this input enables the CLK signal to perform
read and write operations to the block RAM. When inactive, the
block RAM does not perform any read or write operations.
Set/Reset
SSRA
SSRB
Input
When asserted, this pin forces the DO output latch to the value
of the SRVAL attribute. It is synchronized to the CLK signal.
Clock
CLKA
CLKB
Input
This input accepts the clock signal to which read and write
operations are synchronized. All associated port inputs are
required to meet setup times with respect to the clock signal’s
active edge. The data output bus responds after a clock-to-out
delay referenced to the clock signal’s active edge.
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in Table 21.
Table 21: Block RAM Attributes
Function
Attribute
Possible Values
Initial Content for Data Memory, Loaded
during Configuration
INITxx (INIT_00 through
INIT3F)
Each initialization string defines 32 hex values
of the 16384-bit data memory of the block RAM.
Initial Content for Parity Memory, Loaded
during Configuration
INITPxx (INITP_00
through INITP0F)
Each initialization string defines 32 hex values
of the 2048-bit parity data memory of the block
RAM.
Data Output Latch Initialization
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
INIT (single-port)
INITA, INITB (dual-port)
www.xilinx.com
Hex value the width of the chosen port.
31
R
Functional Description
Table 21: Block RAM Attributes (Continued)
Function
Attribute
Data Output Latch Synchronous
Set/Reset Value
Possible Values
SRVAL (single-port)
SRVAL_A, SRVAL_B
(dual-port)
Data Output Latch Behavior during Write
(see Block RAM Data Operations)
WRITE_FIRST, READ_FIRST, NO_CHANGE
WRITE_MODE
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports. Table 22 describes the data operations of each port as a result of the block RAM control signals in their default active-High edges.
Hex value the width of the chosen port.
The waveforms for the write operation are shown in the top
half of Figure 30, Figure 31, and Figure 32. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
Table 22: Block RAM Function Table
Input Signals
GSR
EN
SSR
WE
CLK
Output Signals
ADDR
DIP
DI
DOP
RAM Data
DO
Parity
Data
X
INITP_xx
INIT_xx
INIT
No Chg
No Chg
No Chg
No Chg
No Chg
SRVAL
No Chg
No Chg
SRVAL
RAM(addr)
← pdata
RAM(addr)
← data
RAM(data)
No Chg
No Chg
Immediately After Configuration
Loaded During Configuration
X
Global Set/Reset Immediately After Configuration
1
X
X
X
X
X
X
X
INIT
RAM Disabled
0
0
X
X
X
X
X
X
No Chg
Synchronous Set/Reset
0
1
1
0
↑
X
X
X
SRVAL
Synchronous Set/Reset During Write RAM
0
1
1
1
↑
addr
pdata
Data
SRVAL
Read RAM, no Write Operation
0
1
0
0
↑
addr
X
X
RAM(pdata)
Write RAM, Simultaneous Read Operation
0
1
0
1
↑
addr
pdata
Data
WRITE_MODE = WRITE_FIRST
pdata
data
RAM(addr)
← pdata
RAM(addr)
← data
WRITE_MODE = READ_FIRST
RAM(data)
RAM(data)
RAM(addr)
← pdata
RAM(addr)
← pdata
WRITE_MODE = NO_CHANGE
No Chg
32
www.xilinx.com
No Chg
RAM(addr)
← pdata
RAM(addr)
← pdata
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
There are a number of different conditions under which data
can be accessed at the DO outputs. Basic data access
always occurs when the WE input is inactive. Under this
condition, data stored in the memory location addressed by
the ADDR lines passes through a output latch to the DO
outputs. The timing for basic data access is shown in the
portions of Figure 30, Figure 31, and Figure 32 during
which WE is Low.
Data also can be accessed on the DO outputs when asserting the WE input based on the value of the WRITE_MODE
attribute as described in Table 23.
Table 23: WRITE_MODE Effect on Data Output Latches During Write Operations
Write Mode
Effect on Opposite Port
(dual-port only with same address)
Effect on Same Port
WRITE_FIRST
Read After Write
Data on DI and DIP inputs is written into
specified RAM location and simultaneously
appears on DO and DOP outputs.
Invalidates data on DO and DOP outputs.
READ_FIRST
Read Before Write
Data from specified RAM location appears on
DO and DOP outputs.
Data from specified RAM location appears on
DO and DOP outputs.
Data on DI and DIP inputs is written into
specified location.
NO_CHANGE
No Read on Write
Data on DO and DOP outputs remains
unchanged.
Invalidates data on DO and DOP outputs.
Data on DI and DIP inputs is written into
specified location.
Data_in
DI
Internal
Memory
DO
Data_out = Data_in
CLK
WE
DI
XXXX
ADDR
DO
aa
0000
1111
2222
bb
cc
MEM(aa)
1111
XXXX
dd
2222
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS312-2_05_020905
Figure 30: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Setting the WRITE_MODE attribute to a value of
WRITE_FIRST, data is written to the addressed memory
location on an enabled active CLK edge and is also passed
to the DO outputs. WRITE_FIRST timing is shown in the
portion of Figure 30 during which WE is High.
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
Setting the WRITE_MODE attribute to a value of
READ_FIRST, data already stored in the addressed location passes to the DO outputs before that location is overwritten with new data from the DI inputs on an enabled
active CLK edge. READ_FIRST timing is shown in the portion of Figure 31 during which WE is High.
www.xilinx.com
33
R
Functional Description
Data_in
DI
Internal
Memory
DO
Prior stored data
CLK
WE
DI
XXXX
ADDR
DO
aa
0000
1111
2222
bb
cc
MEM(aa)
old MEM(bb)
XXXX
dd
old MEM(cc)
MEM(dd)
EN
DISABLED
WRITE
MEM(bb)=1111
READ
WRITE
MEM(cc)=2222
READ
DS312-2_06_020905
Figure 31: Waveforms of Block RAM Data Operations with READ_FIRST Selected
Data_in
DI
Internal
Memory
DO
No change during write
CLK
WE
DI
XXXX
ADDR
DO
aa
0000
1111
2222
bb
cc
MEM(aa)
XXXX
dd
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS312-2_07_020905
Figure 32: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Setting the WRITE_MODE attribute to a value of
NO_CHANGE, puts the DO outputs in a latched state when
asserting WE. Under this condition, the DO outputs retain
34
the data driven just before WE is asserted. NO_CHANGE
timing is shown in the portion of Figure 32 during which WE
is High.
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Dedicated Multipliers
The Spartan-3E devices provide 4 to 36 dedicated multiplier
blocks per device. The multipliers are located together with
the block RAM in one or two columns depending on device
density. See Arrangement of RAM Blocks on Die for
details on the location of these blocks and their connectivity.
The multiplier blocks primarily perform two’s complement
numerical multiplication but can also perform some less
obvious applications such as simple data storage and barrel
shifting. Logic slices also implement efficient small multipliers and thereby supplement the dedicated multipliers. The
Spartan-3E dedicated multiplier blocks have additional features beyond those provided in Spartan-3 FPGAs.
Each multiplier performs the principle operation P = A × B,
where ‘A’ and ‘B’ are 18-bit words in two’s complement
form, and ‘P’ is the full-precision 36-bit product, also in two’s
complement form. The 18-bit inputs represent values ranging from -131,07210 to +131,07110 with a resulting product
ranging from -17,179,738,11210 to +17,179,869,18410.
Implement multipliers with inputs less than 18 bits by
sign-extending the inputs (i.e., replicating the most-significant bit). Wider multiplication operations are performed by
combining the dedicated multipliers and slice-based logic in
any viable combination or by time-sharing a single multiplier. Perform unsigned multiplication by restricting the
inputs to the positive range. Tie the most-significant bit Low
and represent the unsigned value in the remaining 17
lesser-significant bits.
As shown in Figure 33, each multiplier block has optional
registers on each of the multiplier inputs and the output. The
registers are named AREG, BREG, and PREG and can be
used in any combination. The clock input is common to all
the registers within a block, but each register has an independent clock enable and synchronous reset controls making them ideal for storing data samples and coefficients.
When used for pipelining, the registers boost the multiplier
clock rate, beneficial for higher performance applications.
Figure 33 illustrates the principle features of the multiplier
block.
AREG
(Optional)
CEA
A[17:0]
CE
D
Q
PREG
(Optional)
RST
CEP
X
RSTA
D
BREG
(Optional)
CEB
B[17:0]
CE
Q
P[35:0]
RST
CE
D
RSTP
Q
RST
RSTB
DS312-2_27_021205
CLK
Figure 33: Principle Ports and Functions of Dedicated Multiplier Blocks
Use the MULT18X18SIO primitive shown in Figure 34 to
instantiate a multiplier within a design. Although high-level
logic synthesis software usually automatically infers a multiplier, adding the pipeline registers usually requires the
MULT18X18SIO primitive. Connect the appropriate signals
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
to the MULT18X18SIO multiplier ports and set the individual
AREG, BREG, and PREG attributes to ‘1’ to insert the associated register, or to 0 to remove it and make the signal path
combinatorial.
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35
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Functional Description
The MULT18X18SIO primitive has two additional ports
called BCIN and BCOUT to cascade or share the multiplier’s ‘B’ input among several multiplier bocks. The 18-bit
BCIN "cascade" input port offers an alternate input source
from the more typical ‘B’ input. The B_INPUT attribute specifies whether the specific implementation uses the BCIN or
‘B’ input path. Setting B_INPUT to DIRECT chooses the ‘B’
input. Setting B_INPUT to CASCADE selects the alternate
BCIN input. The BREG register then optionally holds the
selected input value, if required.
MULT18X18SIO
A[17:0]
P[35:0]
B[17:0]
CEA
CEB
CEP
CLK
RSTA
RSTB
BCOUT is an 18-bit output port that always reflects the
value that is applied to the multiplier’s second input, which is
either the ‘B’ input, the cascaded value from the BCIN input,
or the output of the BREG if it is inserted.
RSTP
BCOUT[17:0]
BCIN[17:0]
DS312-2_28_021205
Figure 35 illustrates the four possible configurations using
different settings for the B_INPUT attribute and the BREG
attribute.
Figure 34: MULT18X18SIO Primitive
BCOUT[17:0]
BCOUT[17:0]
BREG
CEB
X
CE
D
X
Q
BREG = 0
B_INPUT = CASCADE
CLK
RST
BREG = 1
B_INPUT = CASCADE
RSTB
BCIN[17:0]
BCIN[17:0]
BCOUT[17:0]
BCOUT[17:0]
BREG
CEB
B[17:0]
X
X
CE
D
B[17:0]
Q
BREG = 0
B_INPUT = DIRECT
CLK
RST
RSTB
BREG = 1
B_INPUT = DIRECT
DS312-2_29_021505
Figure 35: Four Configurations of the B Input
36
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Functional Description
The BCIN and BCOUT ports have associated dedicated
routing that connects adjacent multipliers within the same
column. Via the cascade connection, the BCOUT port of
one multiplier block drives the BCIN port of the multiplier
block directly above it. There is no connection to the BCIN
port of the bottom-most multiplier block in a column or a
connection from the BCOUT port of the top-most block in a
column. As an example, Figure 36 shows the multiplier cascade capability within the XC3S100E FPGA, which has a
single column of multiplier, four blocks tall. For clarity, the
figure omits the register control inputs.
BCOUT
A
P
B
B_INPUT = CASCADE
BCIN
BCOUT
A
P
B
B_INPUT = CASCADE
BCIN
BCOUT
A
P
B
B_INPUT = CASCADE
BCIN
BCOUT
A
P
B
B_INPUT = DIRECT
BCIN
DS312-2_30_021505
Figure 36: Multiplier Cascade Connection
When using the BREG register, the cascade connection
forms a shift register structure typically used in DSP algorithms such as direct-form FIR filters. When the BREG register is omitted, the cascade structure essentially feeds the
same input value to more than one multiplier. This parallel
connection serves to create wide-input multipliers, implement transpose FIR filters, and is used in any application
that requires that several multipliers have the same input
value.
DS312-2 (v1.1) March 21, 2005
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37
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Functional Description
Table 24 defines each port of the MULT18X18SIO primitive.
Table 24: MULT18X18SIO Embedded Multiplier Primitives Description
Signal Name
Direction
Function
A[17:0]
Input
The primary 18-bit two’s complement value for multiplication. The block multiplies by
this value asynchronously if the optional AREG and PREG registers are omitted.
When AREG and/or PREG are used, the value provided on this port is qualified by
the rising edge of CLK, subject to the appropriate register controls.
B[17:0]
Input
The second 18-bit two’s complement value for multiplication if the B_INPUT attribute
is set to DIRECT. The block multiplies by this value asynchronously if the optional
BREG and PREG registers are omitted. When BREG and/or PREG are used, the
value provided on this port is qualified by the rising edge of CLK, subject to the
appropriate register controls.
BCIN[17:0]
Input
The second 18-bit two’s complement value for multiplication if the B_INPUT attribute
is set to CASCADE. The block multiplies by this value asynchronously if the optional
BREG and PREG registers are omitted. When BREG and/or PREG are used, the
value provided on this port is qualified by the rising edge of CLK, subject to the
appropriate register controls.
P[35:0]
Output
The 36-bit two’s complement product resulting from the multiplication of the two input
values applied to the multiplier. If the optional AREG, BREG and PREG registers are
omitted, the output operates asynchronously. Use of PREG causes this output to
respond to the rising edge of CLK with the value qualified by CEP and RSTP. If PREG
is omitted, but AREG and BREG are used, this output responds to the rising edge of
CLK with the value qualified by CEA, RSTA, CEB, and RSTB. If PREG is omitted and
only one of AREG or BREG is used, this output responds to both asynchronous and
synchronous events.
BCOUT[17:0]
Output
The value being applied to the second input of the multiplier. When the optional
BREG register is omitted, this output responds asynchronously in response to
changes at the B[17:0] or BCIN[17:0] ports according to the setting of the B_INPUT
attribute. If BREG is used, this output responds to the rising edge of CLK with the
value qualified by CEB and RSTB.
CEA
Input
Clock enable qualifier for the optional AREG register. The value provided on the
A[17:0] port is captured by AREG in response to a rising edge of CLK when this
signal is High, provided that RSTA is Low.
RSTA
Input
Synchronous reset for the optional AREG register. AREG content is forced to the
value zero in response to a rising edge of CLK when this signal is High.
CEB
Input
Clock enable qualifier for the optional BREG register. The value provided on the
B[17:0] or BCIN[17:0] port is captured by BREG in response to a rising edge of CLK
when this signal is High, provided that RSTB is Low.
RSTB
Input
Synchronous reset for the optional BREG register. BREG content is forced to the
value zero in response to a rising edge of CLK when this signal is High.
CEP
Input
Clock enable qualifier for the optional PREG register. The value provided on the
output of the multiplier port is captured by PREG in response to a rising edge of CLK
when this signal is High, provided that RSTP is Low.
RSTP
Input
Synchronous reset for the optional PREG register. PREG content is forced to the
value zero in response to a rising edge of CLK when this signal is High.
Notes:
1.
38
The control signals CLK, CEA, RSTA, CEB, RSTB, CEP, and RSTP have the option of inverted polarity.
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Functional Description
Digital Clock Managers (DCMs)
The DCM supports three major functions:
•
Differences from the Spartan-3 Architecture
•
•
•
Clock-skew Elimination: Clock skew describes the
extent to which clock signals may, under normal
circumstances, deviate from zero-phase alignment. It
occurs when slight differences in path delays cause the
clock signal to arrive at different points on the die at
different times. This clock skew can increase set-up
and hold time requirements as well as clock-to-out
time, which may be undesirable in applications
operating at a high frequency, when timing is critical.
The DCM eliminates clock skew by aligning the output
clock signal it generates with another version of the
clock signal that is fed back. As a result, the two clock
signals establish a zero-phase relationship. This
effectively cancels out clock distribution delays that
might lie in the signal path leading from the clock
output of the DCM to its feedback input.
Frequency Synthesis: Provided with an input signal,
the DCM can generate a wide range of different output
clock frequencies. This is accomplished by either
multiplying and/or dividing the frequency of the input
clock signal by any of several different factors.
Phase Shifting: The DCM provides the ability to shift
the phase of all its output clock signals with respect to
its input clock signal.
Spartan-3E FPGAs have two, four, or eight DCMs,
depending on device size.
The Spartan-3E DCM has a maximum phase shift
range of ±180°. The Spartan-3 DCM range is ±360°.
The Spartan-3E DLL supports lower input frequencies,
down to 5 MHz. Spartan-3 DLLs supports down to 24
MHz.
Overview
Spartan-3E Digital Clock Managers (DCMs) provide flexible, complete control over clock frequency, phase shift and
skew. To accomplish this, the DCM employs a Delay-Locked
Loop (DLL), a fully digital control system that uses feedback
to maintain clock signal characteristics with a high degree of
precision despite normal variations in operating temperature and voltage. This section provides a fundamental
description of the DCM. See XAPP462: "Using Digital Clock
Managers (DCMs) in Spartan-3 Series FPGAs" for further
information.
The XC3S100E FPGA has two DCMs, one at the top and
one at the bottom of the device. The XC3S250E and
XC3S500E FPGAs each include four DCMs, two at the top
and two at the bottom. The XC3S1200E and XC3S1600E
FPGAs contain eight DCMs with two on each edge (see
also Figure 42). The DCM in Spartan-3E FPGAs is surrounded by CLBs within the logic array and is no longer
located at the top and bottom of a column of block RAM as
in the Spartan-3 architecture,. The Digital Clock Manager is
instantiated into a design as the “DCM” primitive.
•
•
The DCM has four functional components: the
Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), the Phase Shifter (PS), and the Status Logic.
Each component has its associated signals, as shown in
Figure 37.
DCM
PSINCDEC
PSEN
PSCLK
Phase
Shifter
Delay Taps
Input Stage
Output Stage
CLK0
CLKIN
CLKFB
PSDONE
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
DFS
DLL
RST
Status
Logic
Clock
Distribution
Delay
8
LOCKED
STATUS [7:0]
DS099-2_07_040103
Figure 37: DCM Functional Blocks and Associated Signals
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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39
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Functional Description
CLKIN
Delay
1
Delay
2
Delay
n-1
Delay
n
Output Section
CLK0
Control
CLKFB
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
LOCKED
Phase
Detection
RST
DS099-2_08_041103
Figure 38: Simplified Functional Diagram of DLL
Table 25: DLL Signals
Signal
Direction
Description
CLKIN
Input
Accepts original clock signal.
CLKFB
Input
Accepts either CLK0 or CLK2X as the feedback signal. (Set CLK_FEEDBACK attribute
accordingly).
CLK0
Output
Generates a clock signal with same frequency and phase as CLKIN.
CLK90
Output
Generates a clock signal with same frequency as CLKIN, only phase-shifted 90°.
CLK180
Output
Generates a clock signal with same frequency as CLKIN, only phase-shifted 180°.
CLK270
Output
Generates a clock signal with same frequency as CLKIN, only phase-shifted 270°.
CLK2X
Output
Generates a clock signal with same phase as CLKIN, only twice the frequency.
CLK2X180
Output
Generates a clock signal with twice the frequency of CLKIN, phase-shifted 180° with
respect to CLKIN.
CLKDV
Output
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency
clock signal that is phase-aligned to CLKIN.
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to eliminate clock skew. The main signal path of the DLL consists of
an input stage, followed by a series of discrete delay elements or taps, which in turn leads to an output stage. This
path together with logic for phase detection and control
forms a system complete with feedback as shown in
Figure 38. In Spartan-3E FPGAs, the DLL is implemented
using a counter-based delay line.
The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
described in Table 25. The clock outputs drive simulta40
neously. Signals that initialize and report the state of the
DLL are discussed in the Status Logic Component section.
The clock signal supplied to the CLKIN input serves as a
reference waveform. The DLL seeks to align the rising-edge
of feedback signal at the CLKFB input with the rising-edge
of CLKIN input. When eliminating clock skew, the common
approach to using the DLL is as follows: The CLK0 signal is
passed through the clock distribution network to all the registers it synchronizes. These registers are either internal or
external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via a
feedback line called CLKFB. The control block inside the
DLL measures the phase error between CLKFB and CLKIN.
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Functional Description
This phase error is a measure of the clock skew that the
clock distribution network introduces. The control block activates the appropriate number of delay elements to cancel
out the clock skew. Once the DLL has brought the CLK0 signal in phase with the CLKIN signal, it asserts the LOCKED
output, indicating a lock on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the
DLL component through the use of the attributes described
in Table 26. Each attribute is described in detail in the sections that follow:
Table 26: DLL Attributes
Attribute
Description
Values
CLK_FEEDBACK
Chooses either the CLK0 or CLK2X output to
drive the CLKFB input
NONE, 1X, 2X
CLKIN_DIVIDE_BY_2
Halves the frequency of the CLKIN signal just
as it enters the DCM
TRUE, FALSE
CLKDV_DIVIDE
Selects the constant used to divide the CLKIN
input frequency to generate the CLKDV
output frequency
1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0,
6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14,
15, and 16
DUTY_CYCLE_CORRECTION
Enables 50% duty cycle correction for the
CLK0, CLK90, CLK180, and CLK270 outputs
TRUE, FALSE
DLL Clock Input Connections
An external clock source enters the FPGA using a Global
Clock Input Buffer (IBUFG), which directly accesses the global clock network or via an Input Buffer (IBUF). Clock signals within the FPGA drive a global clock net using a Global
Clock Multiplexer Buffer (BUFGMUX). The global clock net
connects directly to the CLKIN input. The internal and external connections are shown in Figure 39a and Figure 39c,
respectively. A differential clock (e.g., LVDS) can serve as
an input to CLKIN.
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can simultaneously drive four of the BUFGMUX buffers on the same die
edge. All DCM clock outputs can simultaneously drive general routing resources, including interconnect leading to
OBUF buffers.
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
The feedback loop is essential for DLL operation and is
established by driving the CLKFB input with either the CLK0
or the CLK2X signal so that any undesirable clock distribution delay is included in the loop. It is possible to use either
of these two signals for synchronizing any of the seven DLL
outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X,
or CLK2X180. The value assigned to the CLK_FEEDBACK
attribute must agree with the physical feedback connection:
a value of 1X for the CLK0 case, 2X for the CLK2X case. If
the DCM is used in an application that does not require the
DLL — that is, only the DFS is used — then there is no
required feedback loop so CLK_FEEDBACK is set to
NONE.
There are two basic cases that determine how to connect
the DLL clock outputs and feedback connections: on-chip
synchronization and off-chip synchronization, which are
illustrated in Figure 39a through Figure 39d.
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41
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Functional Description
FPGA
FPGA
BUFGMUX
BUFGMUX
BUFG
CLKIN
DCM
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
CLKFB
BUFG
CLKIN
DCM
Clock
Net Delay
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK2X180
CLK2X
CLKFB
CLK0
BUFGMUX
BUFGMUX
CLK2X
CLK0
(a) On-Chip with CLK0 Feedback
(b) On-Chip with CLK2X Feedback
FPGA
IBUFG
CLKIN
DCM
CLKFB
Clock
Net Delay
FPGA
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
OBUF
IBUFG
CLKIN
Clock
Net Delay
DCM
CLKFB
CLK0
OBUF
IBUFG
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK2X180
OBUF
Clock
Net Delay
CLK2X
IBUFG
OBUF
CLK2X
CLK0
(c) Off-Chip with CLK0 Feedback
(d) Off-Chip with CLK2X Feedback
DS099-2_09_082104
Figure 39: Input Clock, Output Clock, and Feedback Connections for the DLL
In the on-chip synchronization case in Figure 39a and
Figure 39b, it is possible to connect any of the DLL’s seven
output clock signals through general routing resources to
the FPGA’s internal registers. Either a Global Clock Buffer
(BUFG) or a BUFGMUX affords access to the global clock
network. As shown in Figure 39a, the feedback loop is created by routing CLK0 (or CLK2X, in Figure 39b to a global
clock net, which in turn drives the CLKFB input.
In the off-chip synchronization case in Figure 39c and
Figure 39d, CLK0 (or CLK2X) plus any of the DLL’s other
output clock signals exit the FPGA using output buffers
(OBUF) to drive an external clock network plus registers on
the board. As shown in Figure 39c, the feedback loop is
formed by feeding CLK0 (or CLK2X, in Figure 39d) back
into the FPGA using an IBUFG, which directly accesses the
global clock network, or an IBUF. Then, the global clock net
is connected directly to the CLKFB input.
Accommodating High Input Frequencies
If the frequency of the CLKIN signal is high such that it
exceeds the maximum permitted, divide it down to an
acceptable value using the CLKIN_DIVIDE_BY_2 attribute.
When this attribute is set to TRUE, the CLKIN frequency is
divided by a factor of two just as it enters the DCM.
42
Coarse Phase Shift Outputs of the DLL Component
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180, and
CLK270 outputs for 90°, 180°, and 270° phase-shifted signals, respectively. These signals are described in Table 25.
Their relative timing is shown in Figure 40. For control in
finer increments than 90°, see Phase Shifter (PS).
Basic Frequency Synthesis Outputs of the DLL
Component
The DLL component provides basic options for frequency
multiplication and division in addition to the more flexible
synthesis capability of the DFS component, described in a
later section. These operations result in output clock signals
with frequencies that are either a fraction (for division) or a
multiple (for multiplication) of the incoming clock frequency.
The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also doubles the frequency, but is 180° out-of-phase with respect to
CLKIN. The CLKDIV output generates a clock frequency
that is a predetermined fraction of the CLKIN frequency.
The CLKDV_DIVIDE attribute determines the factor used to
divide the CLKIN frequency. The attribute can be set to var-
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Functional Description
ious values as described in Table 26. The basic frequency
synthesis outputs are described in Table 25.
Duty Cycle Correction of DLL Clock Outputs
The CLK2X(1), CLK2X180, and CLKDV(2) output signals
ordinarily exhibit a 50% duty cycle – even if the incoming
CLKIN signal has a different duty cycle. Fifty-percent duty
cycle means that the High and Low times of each clock
cycle are equal. The DUTY_CYCLE_CORRECTION
attribute determines whether or not duty cycle correction is
applied to the CLK0, CLK90, CLK180, and CLK270 outputs.
If DUTY_CYCLE_CORRECTION is set to TRUE, then the
duty cycle of these four outputs is corrected to 50%. If
DUTY_CYCLE_CORRECTION is set to FALSE, then these
outputs exhibit the same duty cycle as the CLKIN signal.
Figure 40 compares the characteristics of the DLL’s output
signals to those of the CLKIN signal.
The CLK2X output generates a 25% duty cycle clock at the
same frequency as the CLKIN signal until the DLL has
achieved lock.
The duty cycle of the CLKDV outputs may differ somewhat
from 50% (i.e., the signal is High for less than 50% of the
period) when the CLKDV_DIVIDE attribute is set to a
non-integer value and the DLL is operating in the High Frequency mode.
2. The fCLKFX frequency calculated from the above
expression accords with the DCM’s operating frequency
specifications.
For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE
= 3, then the frequency of the output clock signal is 5/3 that
of the input clock signal.
Phase:
o
0
o
o
o
90 180 270
o
o
o
90 180 270
o
0
Input Signal (30% Duty Cycle)
t
CLKIN
Output Signal - Duty Cycle is Always Corrected
CLK2X
CLK2X180
(1)
CLKDV
Output Signal - Attribute Corrects Duty Cycle
Digital Frequency Synthesizer (DFS)
The DFS component generates clock signals the frequency
of which is a product of the clock frequency at the CLKIN
input and a ratio of two user-determined integers. Because
of the wide range of possible output frequencies such a ratio
permits, the DFS feature provides still further flexibility than
the DLL’s basic synthesis options as described in the preceding section. The DFS component’s two dedicated outputs, CLKFX and CLKFX180, are defined in Table 28.
The signal at the CLKFX180 output is essentially an inversion of the CLKFX signal. These two outputs always exhibit
a 50% duty cycle. This is true even when the CLKIN signal
does not. These DFS clock outputs are driven at the same
time as the DLL’s seven clock outputs.
The numerator of the ratio is the integer value assigned to
the attribute CLKFX_MULTIPLY and the denominator is the
integer value assigned to the attribute CLKFX_DIVIDE.
These attributes are described in Table 27.
The output frequency (fCLKFX) can be expressed as a function of the incoming clock frequency (fCLKIN) as follows:
DUTY_CYCLE_CORRECTION = FALSE
CLK0
CLK90
CLK180
CLK270
DUTY_CYCLE_CORRECTION = TRUE
CLK0
CLK90
CLK180
CLK270
fCLKFX = fCLKIN*(CLKFX_MULTIPLY/CLKFX_DIVIDE) (3)
Regarding the two attributes, it is possible to assign any
combination of integer values, provided that two conditions
are met:
1. The two values fall within their corresponding ranges,
as specified in Table 27.
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
o
0
DS099-2_10_031303
Figure 40: Characteristics of the DLL Clock Outputs
DFS With or Without the DLL
The DFS component can be used with or without the DLL
component: Without the DLL, the DFS component multiplies or divides the CLKIN signal frequency according to the
respective CLKFX_MULTIPLY and CLKFX_DIVIDE values,
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43
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Functional Description
generating a clock with the new target frequency on the
CLKFX and CLKFX180 outputs. Though classified as
belonging to the DLL component, the CLKIN input is shared
with the DFS component. This case does not employ feedback loop. Therefore, it cannot correct for clock distribution
delay.
With the DLL, the DFS operates as described in the preceding case, only with the additional benefit of eliminating the
clock distribution delay. In this case, a feedback loop from
the CLK0 output to the CLKFB input must be present.
The DLL and DFS components work together to achieve
this phase correction as follows: Given values for the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL
selects the delay element for which the output clock edge
coincides with the input clock edge whenever mathematically possible. For example, when CLKFX_MULTIPLY = 5
and CLKFX_DIVIDE = 3, the input and output clock edges
coincide every three input periods, which is equivalent in
time to five output periods.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values
achieve faster lock times. With no factors common to the
two attributes, alignment occurs once with every number of
cycles equal to the CLKFX_DIVIDE value. Therefore, it is
recommended that the user reduce these values by factoring
wherever
possible.
For
example,
given
CLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6, removing
a factor of three yields CLKFX_MULTIPLY = 3 and
CLKFX_DIVIDE = 2. While both value-pairs result in the
multiplication of clock frequency by 3/2, the latter value-pair
enables the DLL to lock more quickly.
Table 27: DFS Attributes
Attribute
Description
Values
CLKFX_MULTIPLY
Frequency
multiplier
constant
Integer from
2 to 32,
inclusive
CLKFX_DIVIDE
Frequency divisor
constant
Integer from
1 to 32,
inclusive
Table 28: DFS Signals
Signal
Direction
Description
CLKFX
Output
Multiplies the CLKIN frequency
by the attribute-value ratio
(CLKFX_MULTIPLY/
CLKFX_DIVIDE) to generate a
clock signal with a new target
frequency.
CLKFX180
Output
Generates a clock signal with
same frequency as CLKFX,
only shifted 180° out-of-phase.
44
DFS Clock Output Connections
There are two basic cases that determine how to connect
the DFS clock outputs: on-chip and off-chip, which are illustrated in Figure 39a and Figure 39c, respectively. This is
similar to what has already been described for the DLL component. See DLL Clock Output and Feedback Connections.
In the on-chip case, it is possible to connect either of the
DFS’s two output clock signals through general routing
resources to the FPGA’s internal registers. Either a Global
Clock Buffer (BUFG) or a BUFGMUX affords access to the
global clock network. The optional feedback loop is formed
in this way, routing CLK0 to a global clock net, which in turn
drives the CLKFB input.
In the off-chip case, the DFS’s two output clock signals, plus
CLK0 for an optional feedback loop, can exit the FPGA
using output buffers (OBUF) to drive a clock network plus
registers on the board. The feedback loop is formed by
feeding the CLK0 signal back into the FPGA using an
IBUFG, which directly accesses the global clock network, or
an IBUF. Then the global clock net is connected directly to
the CLKFB input.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase
of a DCM clock output signal relative to the CLKIN signal:
First, there are nine clock outputs that employ the DLL to
achieve a desired phase relationship: CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, CLKDV CLKFX, and
CLKFX180. These outputs afford “coarse” phase control.
The second approach uses the PS component described in
this section to provide a still finer degree of control. The PS
component accomplishes this by introducing a "fine phase
shift" (TPS) between the CLKFB and CLKIN signals inside
the DLL component. The user can control this fine phase
shift down to a resolution of 1/512 of a CLKIN cycle or one
tap delay (DCM_TAP), whichever is greater. When in use,
the PS component shifts the phase of all nine DCM clock
output signals together. If the PS component is used
together with a DCM clock output such as the CLK90,
CLK180, CLK270, CLK2X180, and CLKFX180, then the
fine phase shift of the former gets added to the coarse
phase shift of the latter.
PS Component Enabling and Mode Selection
The CLKOUT_PHASE_SHIFT attribute enables the PS
component for use in addition to selecting between two
operating modes. As described in Table 29, this attribute
has three possible values: NONE, FIXED, and VARIABLE.
When CLKOUT_PHASE_SHIFT is set to NONE, the PS
component is disabled and its inputs, PSEN, PSCLK, and
PSINCDEC, must be tied to GND. The set of waveforms in
Figure 41a shows the disabled case, where the DLL maintains a zero-phase alignment of signals CLKFB and CLKIN
upon which the PS component has no effect. The PS com-
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Functional Description
ponent is enabled by setting the attribute to either the
FIXED or VARIABLE values, which select the Fixed Phase
mode and the Variable Phase mode, respectively. These
two modes are described in the sections that follow.
Table 29: PS Attributes
Attribute
Description
Values
CLKOUT_PHASE_SHIFT
Disables the PS component or chooses between
Fixed Phase and Variable Phase modes.
NONE, FIXED, VARIABLE
PHASE_SHIFT
Determines size and direction of initial fine phase
shift.
Integers from –255 to +255
Determining the Fine Phase Shift
The Fixed Phase Mode
The user controls the phase shift of CLKFB relative to
CLKIN by setting and/or adjusting the value of the
PHASE_SHIFT attribute. This value must be an integer
ranging from –255 to +255. This corresponds to a phase
shift range of –180 to +180 degrees, which is different from
the original Spartan-3 DCM. The PS component uses this
value to calculate the desired fine phase shift (TPS) as a
fraction of the CLKIN period (TCLKIN). Given values for
PHASE_SHIFT and TCLKIN, it is possible to calculate TPS
as follows:
This mode fixes the desired fine phase shift to a fraction of
the TCLKIN, as determined by Equation (4) and its
user-selected PHASE_SHIFT value P. The set of waveforms in Figure 41b illustrates the relationship between
CLKFB and CLKIN in the Fixed Phase mode. In the Fixed
Phase mode, the PSEN, PSCLK, and PSINCDEC inputs
are not used and must be tied to GND.
In Figure 41:
•
TPS = (PHASE_SHIFT/512) * TCLKIN (4)
Both the Fixed Phase and Variable Phase operating modes
employ this calculation. If the PHASE_SHIFT value is zero,
then CLKFB and CLKIN are in phase, the same as when the
PS component is disabled. When the PHASE_SHIFT value
is positive, the CLKFB signal is shifted later in time with
respect to CLKIN. If the attribute value is negative, the
CLKFB signal is shifted earlier in time with respect to
CLKIN.
DS312-2 (v1.1) March 21, 2005
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•
•
P represents the integer value ranging from –255 to
+255 to which the PHASE_SHIFT attribute is assigned.
(P = approximately -90 as shown)
N is an integer value ranging from (P – 255) to
(+255 – P) that represents the net phase shift effect
from a series of increment and/or decrement
operations.
N = {Total number of increments} – {Total number of
decrements} provided the user does not try to
increment past + 255 or decrement past -255. A
positive value for N indicates a net increment; a
negative value indicates a net decrement.
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45
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Functional Description
a. CLKOUT_PHASE_SHIFT = NONE
CLKIN
CLKFB
b. CLKOUT_PHASE_SHIFT = FIXED
CLKIN
–255
Shift Range over all P Values:
0
+255
P
512 * TCLKIN
CLKFB
c. CLKOUT_PHASE_SHIFT = VARIABLE
CLKIN
–255
Shift Range over all P Values:
0
+255
P
* TCLKIN
512
CLKFB before
Increment
Shift Range over all N Values:
N
*T
512 CLKIN
CLKFB after
Increment
DS312-2_61_021505
Figure 41: Phase Shifter Waveforms
The Variable Phase Mode
The Variable Phase mode dynamically adjusts the fine
phase shift over time using three inputs to the PS compo-
nent (PSEN, PSCLK, and PSINCDEC), as defined in
Table 30.
Table 30: Signals for Variable Phase Mode
Signal
Direction
Description
PSEN(1)
Input
Enables PSCLK for variable phase adjustment.
PSCLK(1)
Input
Clock to synchronize phase shift adjustment.
PSINCDEC(1)
Input
Chooses between increment and decrement for phase adjustment. It is
synchronized to the PSCLK signal.
PSDONE
Output
Goes High to indicate that present phase adjustment is complete and PS component
is ready for next phase adjustment request. It is synchronized to the PSCLK signal.
Notes:
1.
46
It is possible to program this input for either a true or inverted polarity.
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Just following device configuration, the PS component initially determines TPS by evaluating Equation (4) for the
value assigned to the PHASE_SHIFT attribute. Then to
dynamically adjust that phase shift, use the three PS inputs
to increase or decrease the fine phase shift.
PSINCDEC is synchronized to the PSCLK clock signal,
which is enabled by asserting PSEN. It is possible to drive
the PSCLK input with the CLKIN signal or any other clock
signal. A request for phase adjustment is entered as follows:
For each PSCLK cycle that PSINCDEC is High, the PS
component adds 1/512 of a CLKIN cycle to TPS. Similarly,
for each enabled PSCLK cycle that PSINCDEC is Low, the
PS component subtracts 1/512 of a CLKIN cycle from TPS.
The phase adjustment may require as many as 100 CLKIN
cycles plus three PSCLK cycles to take effect, at which
point the output PSDONE goes High for one PSCLK cycle.
This pulse indicates that the PS component has finished the
present adjustment and is now ready for the next request.
Asserting the Reset (RST) input, returns TPS to its original
shift time, as determined by the PHASE_SHIFT attribute
value. The set of waveforms in Figure 41c illustrates the
relationship between CLKFB and CLKIN in the Variable
Phase mode.
The Status Logic Component
The Status Logic component not only reports on the state of
the DCM but also provides a means of resetting the DCM to
an initial known state. The signals associated with the Status Logic component are described in Table 31.
As a rule, the Reset (RST) input is asserted only upon configuring the device or changing the CLKIN frequency. A
DCM reset does not affect attribute values (e.g.,
CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, tie
RST to GND.
The eight bits of the STATUS bus are defined in Table 32.
Table 31: Status Logic Signals
Signal
Direction
Description
RST
Input
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for
a delay of zero. Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0]
Output
The bit values on the STATUS bus provide information regarding the state of DLL and
PS operation
LOCKED
Output
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two
signals are out-of-phase when Low.
Table 32: DCM Status Bus
Bit
Name
Description
0
Reserved
-
1
CLKIN Stopped
A value of 1 indicates that the CLKIN input signal is not toggling. A value of 0 indicates toggling.
This bit functions only when the CLKFB input is connected.(1)
2
CLKFX Stopped
A value of 1 indicates that the CLKFX output is not toggling. A value of 0 indicates toggling.
This bit functions only when the CLKFX or CLKFX180 output are connected.
Reserved
-
3-6
Notes:
1.
If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit does not go High when the CLKIN signal stops.
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Functional Description
Stabilizing DCM Clocks Before User Mode
Clock Buffers/Multiplexers
The STARTUP_WAIT attribute shown in Table 33 optionally
delays the end of the FPGA’s configuration process until
after the DCM locks to the incoming clock frequency. This
option ensures that the FPGA remains in the Startup phase
of configuration until all clock outputs generated by the
DCM are stable. When all the DCMs with their
STARTUP_WAIT attribute set to TRUE assert the LOCKED
signal, then the FPGA completes its configuration process
and proceeds to user mode. The associated bitstream generator (BitGen) option LCK_cycle specifies one of the six
cycles in the Startup phase. The selected cycle defines the
point at which configuration halts until the all the LOCKED
outputs go High. Also see Start-Up, page 91.
Clock Buffers/Multiplexers either drive clock input signals
directly onto a clock line (BUFG) or optionally provide a multiplexer to switch between two unrelated, possibly asynchronous clock signals (BUFGMUX).
Each BUFGMUX element, shown in Figure 43, is a 2-to-1
multiplexer. The select line, S, chooses which of the two
inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in Table 34. The switching from one clock to the
other is glitch-less, and done in such a way that the output
High and Low times are never shorter than the shortest
High or Low time of either input clock.
Table 34: BUFGMUX Select Mechanism
Table 33: STARTUP_WAIT Attribute
Attribute
Description
STARTUP_WAIT
Delays transition
from configuration
to user mode until
DCM locks to
input clock.
Values
TRUE, FALSE
The Spartan-3E clocking infrastructure, shown in Figure 42,
provides a series of low-capacitance, low-skew interconnect
lines well-suited to carrying high-frequency signals throughout the FPGA. The infrastructure also includes the clock
inputs and BUFGMUX clock buffers/multiplexers. The Xilinx
Place-and-Route (PAR) software automatically routes
high-fanout clock signals using these resources.
Clock Inputs
Clock pins accept external clock signals and connect directly
to DCMs and BUFGMUX elements. Each Spartan-3E FPGA
has:
•
•
16 Global Clock inputs (GCLK0 through GCLK15)
located along the top and bottom edges of the FPGA
8 Right-Half Clock inputs (RHCLK0 through RHCLK7)
located along the right edge
8 Left-Half Clock inputs (LHCLK0 through LHCLK7)
located along the left edge
Clock inputs optionally connect directly to DCMs using dedicated connections. Table 35 shows the clock inputs that
feed a specific DCM within a given Spartan-3E part number.
Different Spartan-3E FPGA densities have different numbers of DCMs.
Each clock input is also optionally a user-I/O pin and connects to internal interconnect. Some clock pad pins are
input-only pins as indicated in Module 4 of the Spartan-3E
Data Sheet.
48
O Output
0
I0 Input
1
I1 Input
The BUFG clock buffer primitive drives a single clock signal
onto the clock network and is essentially the same element
as a BUFGMUX, just without the clock select mechanism.
Similarly, the BUFGCE primitive creates an enabled clock
buffer using the BUFGMUX select mechanism.
Clocking Infrastructure
•
S Input
The I0 and I1 inputs to an BUFGMUX element originate
from clock input pins, DCMs, or Double-Line interconnect,
as shown in Figure 43. As shown in Figure 42, there are 24
BUFGMUX elements distributed around the four edges of
the device. Clock signals from the four BUFGMUX elements
at the top edge and the four at the bottom edge are truly global and connect to all clocking quadrants. The eight
left-edge BUFGMUX elements only connect to the two clock
quadrants in the left half of the device. Similarly, the eight
right-edge BUFGMUX elements only connect to the right
half of the device.
BUFGMUX elements are organized in pairs and share I0
and I1 connections with adjacent BUFGMUX elements from
a common clock switch matrix as shown in Figure 43. For
example, the input on I0 of one BUFGMUX also a shared
input to I1 of the adjacent BUFGMUX.
The clock switch matrix for the left- and right-edge BUFGMUX elements receive signals from any of the three following sources: an LHCLK or RHCLK pin as appropriate, a
Double-Line interconnect, or a DCM in the XC3S1200E and
XC3S1600E devices.
By contrast, the clock switch matrixes on the top and bottom
edges receive signals from any of the five following sources:
two GCLK pins, two DCM outputs, or one Double-Line interconnect.
Table 36 indicates permissible connections between clock
inputs and BUFGMUX elements. The four BUFGMUX elements on the top edge are paired together and share inputs
from the eight global clock inputs along the top edge. Each
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Functional Description
The connections for the bottom-edge BUFGMUX elements
is similar to the top-edge connections.
BUFGMUX pair connects to four of the eight global clock
inputs, as shown in Figure 42. This optionally allows differential inputs to the global clock inputs without wasting a
BUFGMUX element.
On the left and right edges, only two clock inputs feed each
pair of BUFGMUX elements.
Global Clock Inputs
GCLK11 GCLK7
GCLK9 GCLK5
GCLK10 GCLK6
BUFGMUX
pair
8
XC3S1200E (X3Y2)
XC3S1600E (X3Y2)
•
4
F
4
F
•
E
D
•
Figure 44a
8
8
Horizontal
8
Spine
Figure 44b
Figure 44a
Figure 44b
•
•
C
Bottom Spine
X0Y9
X0Y8
X0Y5
DCM
8
4
8
4
•
8
E
Right Spine
8
•
D
C
4
DCM
B
Bottom Right Quadrant (BR)
4
DCM
XC3S250E (X0Y0)
XC3S500E (X0Y0)
XC3S1200E (X1Y0)
XC3S1600E (X1Y0)
D
C
B
4
A
4
4
X1Y0 X1Y1
GCLK2 GCLK14
X2Y0 X2Y1
A
X3Y2
4
Bottom Left Quadrant (BL)
4
RHCLK1 RHCLK0
B
•
X3Y3
•
4
XC3S1200E (X3Y1)
XC3S1600E (X3Y1)
4
4
A
4
Right-Half Clock Inputs
X0Y6 X0Y7
•
G
4
•
X3Y5 X3Y4
X0Y4
H
Top Right Quadrant (TR)
Top Spine
4
DCM
X0Y2 X0Y3
E
RHCLK5 RHCLK4 RHCLK3 RHCLK2
LHCLK3 LHCLK2
F
X3Y6
Left-Half Clock Inputs
G
Clock Line
in Quadrant
X3Y7
LHCLK5 LHCLK4
4
H
•
XC3S1200E (X0Y1)
XC3S1600E (X0Y1)
LHCLK7 LHCLK6
4
XC3S100E (X0Y1)
XC3S250E (X1Y1)
XC3S500E (X1Y1)
XC3S1200E (X2Y3)
XC3S1600E (X2Y3)
4
Left Spine
4
4
X2Y10 X2Y11
Top Left Quadrant (TL)
DCM
4
X1Y10 X1Y11
G
XC3S1200E (X0Y2)
XC3S1600E (X0Y2)
4
4
RHCLK7 RHCLK6
H
XC3S250E (X0Y1)
XC3S500E (X0Y1)
XC3S1200E (X1Y3)
XC3S1600E (X1Y3)
X3Y9 X3Y8
LHCLK1 LHCLK0
DCM
DCM
BUFGMUX
4
GCLK8 GCLK4
DCM
XC3S100E (X0Y0)
XC3S250E (X1Y0)
XC3S500E (X1Y0)
XC3S1200E (X2Y0)
XC3S1600E (X2Y0)
GCLK0 GCLK12
GCLK3 GCLK15
GCLK1 GCLK13
Global Clock Inputs
DS312-2_04_030205
Notes:
1.
2.
Number of DCMs and locations of these DCM varies for different device densities.
The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right
and one on the bottom right of the die.
Figure 42: Spartan-3E Internal Quadrant-Based Clock Network (Top View)
DS312-2 (v1.1) March 21, 2005
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Functional Description
Table 35: Direct Connections from Clock Inputs to DCMs and Associated DCM Location String
Clock Input
XC3S100E
XC3S250E/XC3S500E
XC3S1200E/XC3S1600E
GCLK[3:0]
DCM_X0Y0
DCM_X1Y0
DCM_X2Y0
RHCLK[3:0]
N/A
N/A
DCM_X3Y1
RHCLK[7:4]
N/A
N/A
DCM_X3Y2
GCLK[7:4]
DCM_X0Y1
DCM_X1Y1
DCM_X2Y2
GCLK[11:8]
N/A
DCM_X0Y1
DCM_X1Y3
LHCLK[3:0]
N/A
N/A
DCM_X0Y2
LHCLK[7:4]
N/A
N/A
DCM_X0Y1
GCLK[15:12]
N/A
DCM_X0Y0
DCM_X1Y0
Table 36: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadrant
Clock
Line(1)
Location(2)
I0 Input
I1 Input
Location(2)
I0 Input
I1 Input
Location(2)
I0 Input
I1 Input
A
X0Y2
LHCLK7
LHCLK6
X2Y1
GCLK0 or
GCLK12
GCLK1 or
GCLK13
X3Y2
RHCLK0
RHCLK1
B
X0Y3
LHCLK6
LHCLK7
X2Y0
GCLK1 or
GCLK13
GCLK0 or
GCLK12
X3Y3
RHCLK1
RHCLK0
C
X0Y4
LHCLK5
LHCLK4
X1Y1
GCLK2 or
GCLK14
GCLK3 or
GCLK15
X3Y4
RHCLK2
RHCLK3
D
X0Y5
LHCLK4
LHCLK5
X1Y0
GCLK3 or
GCLK15
GCLK2 or
GCLK14
X3Y5
RHCLK3
RHCLK2
E
X0Y6
LHCLK3
LHCLK2
X2Y11
GCLK4 or
GCLK8
GCLK5 or
GCLK9
X3Y6
RHCLK4
RHCLK5
F
X0Y7
LHCLK2
LHCLK3
X2Y10
GCLK5 or
GCLK9
GCLK4 or
GCLK8
X3Y7
RHCLK5
RHCLK4
G
X0Y8
LHCLK1
LHCLK0
X1Y11
GCLK6 or
GCLK10
GCLK7 or
GCLK11
X3Y8
RHCLK6
RHCLK7
H
X0Y9
LHCLK0
LHCLK1
X1Y10
GCLK7 or
GCLK11
GCLK6 or
GCLK10
X3Y9
RHCLK7
RHCLK6
Left-Half BUFGMUX
Top or Bottom BUFGMUX
Right-Half BUFGMUX
Notes:
1.
2.
50
See Quadrant Clock Routing for connectivity details for the eight quadrant clocks.
See Figure 42 for specific BUFGMUX locations and Figure 44 for information on how BUFGMUX elements drive onto a specific clock line
within a quadrant.
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Functional Description
Left-/Right-Half BUFGMUX
Top/Bottom (Global) BUFGMUX
CLK Switch
Matrix
CLK Switch
Matrix
BUFGMUX
S
I0
I1
BUFGMUX
S
I0
0 O
1
I1
I0 0
O
I1
1
I0
S
S
I1
LHCLK or
RHCLK input
1st GCLK pin
Double Line
1st DCM output
DCM output*
*(XC3S1200E and
and XC3S1600E only)
0 O
1
0 O
1
Double Line
2nd DCM output
2nd GCLK pin
DS312-2_16_022505
Figure 43: Clock Switch Matrix to BUFGMUX Pair Connectivity
Quadrant Clock Routing
The four quadrants of the device are:
The clock routing within the FPGA is quadrant-based, as
shown in Figure 42. Each clock quadrant supports eight
total clock signals, labeled ‘A’ through ‘H’ in Table 36 and
Figure 44. The clock source for an individual clock line originates either from a global BUFGMUX element along the
top and bottom edges or from a BUFGMUX element along
the associated edge, as shown in Figure 44. The clock lines
feed the synchronous resource elements (CLBs, IOBs,
block RAM, multipliers, and DCMs) within the quadrant.
•
•
•
•
DS312-2 (v1.1) March 21, 2005
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Top Right (TR)
Bottom Right (BR)
Bottom Left (BL)
Top Left (TL)
Note that the quadrant clock notation (TR, BR, BL, TL) is
separate from that used for similar IOB placement constraints.
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Functional Description
BUFGMUX Output
X2Y1 (Global)
X0Y2 (Left Half)
X2Y0 (Global)
X0Y3 (Left Half)
X1Y1 (Global)
X0Y4 (Left Half)
X1Y0 (Global)
X0Y5 (Left Half)
X2Y11 (Global)
X0Y6 (Left Half)
X2Y10 (Global)
X0Y7 (Left Half)
X1Y11 (Global)
X0Y8 (Left Half)
X1Y10 (Global)
X0Y9 (Left Half)
Clock Line
A
B
C
D
E
F
G
H
a. Left (TL and BL Quadrants) Half of Die
BUFGMUX Output
X2Y1 (Global)
X3Y2 (Right Half)
X2Y0 (Global)
X3Y3 (Right Half)
X1Y1 (Global)
X3Y4 (Right Half)
X1Y0 (Global)
X3Y5 (Right Half)
X2Y11 (Global)
X3Y6 (Right Half)
X2Y10 (Global)
X3Y7 (Right Half)
X1Y11 (Global)
X3Y8 (Right Half)
X1Y10 (Global)
X3Y9 (Right Half)
Clock Line
A
B
C
D
E
F
G
H
b. Right (TR and BR Quadrants) Half of Die
DS312-2_17_030105
Figure 44: Clock Sources for the Eight Clock Lines within a Clock Quadrant
The outputs of the top or bottom BUFGMUX elements connect to two vertical spines, each comprising four vertical
clock lines as shown in Figure 42. At the center of the die,
these clock signals connect to the eight-line horizontal clock
spine.
Outputs of the left and right BUFGMUX elements are routed
onto the left or right horizontal spines, each comprising
eight horizontal clock lines.
Each of the eight clock signals in a clock quadrant derives
either from a global clock signal or a half clock signal. In
other words, there are up to 24 total potential clock inputs to
the FPGA, eight of which can connect to clocked elements
52
in a single clock quadrant. Figure 44 shows how the clock
lines in each quadrant are selected from associated BUFGMUX sources. For example, if quadrant clock ‘A’ in the bottom left (BL) quadrant originates from BUFGMUX_X2Y1,
then the clock signal from BUFGMUX_X0Y2 is unavailable
in the bottom left quadrant. However, the top left (TL) quadrant clock ‘A’ can still solely use the output from either
BUFGMUX_X2Y1 or BUFGMUX_X0Y2 as the source.
To minimize the dynamic power dissipation of the clock network, the Xilinx development software automatically disables all clock segments not in use.
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Functional Description
Interconnect
Interconnect is the programmable network of signal pathways between the inputs and outputs of functional elements
within the FPGA, such as IOBs, CLBs, DCMs, block RAM,
etc.
Interconnect, also called routing, is segmented for optimal
connectivity. Functionally, interconnect resources are identical to that of the Spartan-3 architecture. There are four
kinds of interconnects: long lines, hex lines, double lines,
and direct lines. The Xilinx Place and Route (PAR) software
exploits the rich interconnect array to deliver optimal system
performance and the fastest compile times.
Switch
Matrix
Switch
Matrix
CLB
The switch matrix connects to the different kinds of interconnects across the device. An interconnect tile, shown in
Figure 45, is defined as a single switch matrix connected to
a functional element, such as a CLB, IOB, or DCM. If a functional element spans across multiple switch matrices such
as the block RAM or multipliers, then an interconnect tile is
defined by the number of switch matrices connected to that
functional element. A Spartan-3E device can be represented as an array of interconnect tiles where interconnect
resources are for the channel between any two adjacent
interconnect tile rows or columns as shown in Figure 46.
Switch
Matrix
Switch
Matrix
18Kb
Block
RAM
IOB
Switch
Matrix
Switch
Matrix
DCM
MULT
18 x 18
Switch
Matrix
DS312_08_020905
Figure 45: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
DS312_09_020905
Figure 46: Array of Interconnect Tiles in Spartan-3E FPGA
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Functional Description
There are four type of general-purpose interconnect available in each channel, as shown in Figure 47 and described
below.
Long Lines
Each set of 24 long line signals spans the die both horizontally and vertically and connects to one out of every six interconnect tiles. At any tile, four of the long lines drive or
receive signals from a switch matrix. Because of their low
capacitance, these lines are well-suited for carrying
high-frequency signals with minimal loading effects (e.g.
skew). If all global clock lines are already committed and
additional clock signals remain to be assigned, long lines
serve as a good alternative.
Global Controls (STARTUP_SPARTAN3E)
In addition to the general-purpose interconnect, Spartan-3E
FPGAs have two global logic control signals, as described
in Table 37. These signals are available to the FPGA application via the STARTUP_SPARTAN3E primitive.
Table 37: Spartan-3E Global Logic Control Signals
Global
Control Input
Description
GSR
When driven High, asynchronously
places all registers and flip-flops in their
initial state (see Initialization, page 24).
Asserted automatically during the FPGA
configuration process (see Start-Up,
page 91).
GTS
When driven High, asynchronously
forces all I/O pins to a high-impedance
state (Hi-Z, three-state).
Hex Lines
Each set of eight hex lines are connected to one out of
every three tiles, both horizontally and vertically. Thirty-two
hex lines are available between any given interconnect tile.
Hex lines are only driven from one end of the route.
Double Lines
Each set of eight double lines are connected to every other
tile, both horizontally and vertically. in all four directions.
Thirty-two double lines available between any given interconnect tile. Double lines are more connections and more
flexibility, compared to long line and hex lines.
Direct Connections
Direct connect lines route signals to neighboring tiles: vertically, horizontally, and diagonally. These lines most often
drive a signal from a "source" tile to a double, hex, or long
line and conversely from the longer interconnect back to a
direct line accessing a "destination" tile.
The STARTUP_SPARTAN3E primitive also includes two
other signals used specifically during configuration. The
MBT signals are for Dynamically Loading Multiple Configuration Images Using MultiBoot Option, page 78. The
CLK input is an alternate clock for configuration Start-Up,
page 91.
6
CLB
CLB
6
CLB
CLB
6
CLB
6
CLB
••
•
CLB
••
•
CLB
••
•
CLB
••
•
24
••
•
Horizontal and
Vertical Long Lines
(horizontal channel
shown as an example)
The Global Set/Reset (GSR) signal replaces the global
reset signal included in many ASIC-style designs. Use the
GSR control instead of a separate global reset signal in the
design to free up CLB inputs, resulting in a smaller, more
efficient design. Similarly, the GSR signal is asserted automatically during the FPGA configuration process, guaranteeing that the FPGA starts-up in a known state.
CLB
6
DS312-2_10_022305
Horizontal and
Vertical Hex Lines
(horizontal channel
shown as an example)
8
CLB
CLB
CLB
CLB
CLB
CLB
CLB
DS312-2_11_020905
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles
54
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Functional Description
Horizontal and
Vertical Double
Lines
(horizontal channel
shown as an example)
8
CLB
CLB
CLB
DS312-2_15_022305
Direct Connections
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
DS312-2_12_020905
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles
DS312-2 (v1.1) March 21, 2005
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55
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Functional Description
Configuration
borrowed and returned to the application as general-purpose user I/Os after configuration completes.
Differences from Spartan-3 FPGAs
Spartan-3E FPGAs offer several configuration options to
minimize the impact of configuration on the overall system
design. In some configuration modes, the FPGA generates
a clock and loads itself from an external memory source,
either serially or via a byte-wide data path. Alternatively, an
external host such as a microprocessor downloads the
FPGA’s configuration data using a simple synchronous
serial interface or via a byte-wide peripheral-style interface.
Furthermore, multiple-FPGA designs share a single configuration memory source, creating a structure called a daisy
chain.
In general, Spartan-3E FPGA configuration modes are a
superset to those available in Spartan-3 FPGAs. Two new
modes added in Spartan-3E FPGAs provide a glue-less
configuration interface to industry-standard parallel NOR
Flash and SPI serial Flash memories. Unlike Spartan-3
FPGAs, nearly all of the Spartan-3E configuration pins
become available as user I/Os after configuration.
Configuration Process
The function of a Spartan-3E FPGA is defined by loading
application-specific configuration data into the FPGA’s
internal, reprogrammable CMOS configuration latches
(CCLs), similar to the way a microprocessor’s function is
defined by its application program. For FPGAs, this configuration process uses a subset of the device pins, some of
which are dedicated to configuration; other pins are merely
Three FPGA pins—M2, M1, and M0—select the desired
configuration mode. The mode pin settings appear in
Table 38. The mode pin values are sampled during the start
of configuration when the FPGA’s INIT_B output goes High.
After the FPGA completes configuration, the mode pins are
available as user I/Os.
Table 38: Spartan-3E Configuration Mode Pin Settings
Master
Serial
SPI
BPI
Slave Parallel
Slave Serial
JTAG
<0:0:0>
<0:0:1>
<0:1:0>=Up
<0:1:1>=Down
<1:1:0>
<1:1:1>
<1:0:1>
Serial
Serial
Byte-wide
Byte-wide
Serial
Serial
Configuration memory
source
Xilinx
Platform
Flash
Industry-standard
SPI Serial Flash
Industry-standard
parallel NOR
Flash
Any source via
microcontroller,
CPU, Xilinx
parallel
Platform Flash,
etc.
Any source via
microcontroller,
CPU, Xilinx
Platform Flash,
etc.
Any source via
microcontroller,
CPU, etc. and
System Ace CF
Clock source
Internal
oscillator
Internal oscillator
Internal oscillator
External clock
on CCLK pin
External clock
on CCLK pin
External clock
on TCK pin
8
13
46
21
8
0
Slave Serial
Slave Serial
Slave Parallel
Slave Parallel
or Memory
Mapped
Slave Serial
JTAG
Possible using
XCFxxP Platform
Flash, which
optionally
generates CCLK
Possible using
XCFxxP Platform
Flash, which
optionally
generates CCLK
M[2:0] mode pin
settings
Data width
Total I/O pins
borrowed during
configuration
Configuration mode
for downstream
daisy-chained FPGAs
Self-configuring
applications (no
external download
host)
Uses low-cost,
industry-standard
Flash
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Functional Description
A specific Spartan-3E part type always requires a constant
number of configuration bits, regardless of design complexity, as shown in Table 39. The configuration file size for a
multiple-FPGA daisy-chain design equals the sum of the
individual file sizes.
Table 39: Number of Bits to Program a Spartan-3E
FPGA (Uncompressed Bitstreams)
Device
Number of Configuration
Bits
XC3S100E
581,344
XC3S250E
1,352,192
XC3S500E
2,267,136
XC3S1200E
3,832,320
XC3S1600E
5,957,760
Pin Behavior During Configuration
Table 40 shows how various pins behave during the FPGA
configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
function. In JTAG configuration mode, no user-I/O pins are
borrowed for configuration.
All I/O pins are high impedance (floating, three-stated, Hi-Z)
during the configuration process. These pins are indicated
in Table 40 as shaded table entries or cells. If the HSWAP
input is Low, these pins have a pull-up resistor to their associated VCCO supply that is active throughout configuration.
After configuration, pull-up and pull-down resistors are
available in the FPGA application as described in Pull-Up
and Pull-Down Resistors, page 9.
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK.
Table 40: Pin Behavior during Configuration
Pin Name
Master
Serial
SPI (Serial
Flash)
BPI (Parallel
NOR Flash)
JTAG
Slave
Parallel
Slave Serial
Supply/
I/O Bank
TDI
TDI
TDI
TDI
TDI
TDI
TDI
VCCAUX
TMS
TMS
TMS
TMS
TMS
TMS
TMS
VCCAUX
TCK
TCK
TCK
TCK
TCK
TCK
TCK
VCCAUX
TDO
TDO
TDO
TDO
TDO
TDO
TDO
VCCAUX
PROG_B
PROG_B
PROG_B
PROG_B
PROG_B
PROG_B
PROG_B
VCCAUX
DONE
DONE
DONE
DONE
DONE
DONE
DONE
VCCAUX
HSWAP
HSWAP
HSWAP
HSWAP
HSWAP
HSWAP
HSWAP
0
M2
0
0
0
1
1
1
2
M1
0
0
1
0
1
1
2
M0
0
1
0 = Up
1
0
1
2
1 = Down
CCLK
CCLK (O)
CCLK (O)
CCLK (O)
CCLK (I)
CCLK (I)
2
INIT_B
INIT_B
INIT_B
INIT_B
INIT_B
INIT_B
2
CSO_B
CSO_B
CSO_B
DOUT
BUSY
BUSY
MOSI
CSI_B
CSI_B
2
D7
D7
D7
2
D6
D6
D6
2
D5
D5
D5
2
D4
D4
D4
2
CSO_B
DOUT/BUSY
DOUT
MOSI/CSI_B
DS312-2 (v1.1) March 21, 2005
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DOUT
2
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Functional Description
Table 40: Pin Behavior during Configuration (Continued)
Pin Name
SPI (Serial
Flash)
BPI (Parallel
NOR Flash)
JTAG
Slave
Parallel
Slave Serial
Supply/
I/O Bank
D3
D3
D3
2
D2
D2
D2
2
D1
D1
D1
2
D0
D0
RDWR_B
RDWR_B
RDWR_B
A23
A23
2
A22
A22
2
A21
A21
2
A20
A20
2
D0/DIN
58
Master
Serial
DIN
DIN
DIN
2
2
A19/VS2
VS2
A19
2
A18/VS1
VS1
A18
2
A17/VS0
VS0
A17
2
A16
A16
1
A15
A15
1
A14
A14
1
A13
A13
1
A12
A12
1
A11
A11
1
A10
A10
1
A9
A9
1
A8
A8
1
A7
A7
1
A6
A6
1
A5
A5
1
A4
A4
1
A3
A3
1
A2
A2
1
A1
A1
1
A0
A0
1
LDC0
LDC0
LDC0
1
LDC1
LDC1
LDC1
1
LDC2
LDC2
LDC2
1
HDC
HDC
HDC
1
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Functional Description
Table 41 shows the default I/O standard setting for the various configuration pins during the configuration process. The
configuration interface is designed primarily for 2.5V operation when the VCCO_2 (and VCCO_1 in BPI mode) connects to 2.5V.
The configuration pins also operate at other voltages by setting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V or
1.8V. The change on the VCCO supply also changes the I/O
drive characteristics. For example, with VCCO = 3.3V, the
output current when driving High, IOH, increases to approximately 12 to 16 mA, while the current when driving Low,
IOL, remains 8 mA. At VCCO = 1.8V, the output current
when driving High, IOH, decreases slightly to approximately
6 to 8 mA. Again, the current when driving Low, IOL, remains
8 mA.
Table 41: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V)
Pin(s)
I/O Standard
Output Drive
Slew Rate
All, including CCLK
LVCMOS25
8 mA
Slow
Master Serial Mode
In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E
FPGA configures itself from an attached Xilinx Platform
Flash PROM, as illustrated in Figure 48. The FPGA supplies the CCLK output clock from its internal oscillator to the
attached Platform Flash PROM. In response, the Platform
Flash PROM supplies bit-serial data to the FPGA’s DIN
input and the FPGA accepts this data on each rising CCLK
edge.
+1.2V
Serial Master
Mode
‘0’
‘0’
‘0’
VCCO_2
DIN
CCLK
DOUT
INIT_B
M2
M1
M0
VCCO_0
V
VCCINT
D0
CLK
+2.5V
330
Spartan-3E
XCFxxS = +3.3V
XCFxxP = +1.8V
VCCO
Platform Flash
XCFxx
CE
+2.5V
JTAG
TDI
TMS
TCK
TDO
V
OE/RESET
4.7k
P
V
4.7k
VCCINT
HSWAP
VCCO_0
CEO
CF
VCCAUX
TDO
TDI
TMS
TCK
+2.5V
VCCJ
TDO
TDI
TMS
TCK
+2.5V
GND
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_44_021405
Figure 48: Master Serial Mode using Platform Flash PROM
DS312-2 (v1.1) March 21, 2005
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Functional Description
The mode select pins, M[2:0], must all be Low when sampled, when the FPGA’s INIT_B output goes High. After configuration, when the FPGA’s DONE output goes High, the
mode select pins are available as full-featured user-I/O pins.
FPGA configuration. After configuration, when the FPGA’s
DONE output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
P Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins during configuration or High to disable the pull-up resistors. The HSWAP
control must remain at a constant logic level throughout
The FPGA's DOUT pin is used in daisy-chain applications,
described later. In a single-FPGA application, the FPGA’s
DOUT pin is not used but is actively driving during the configuration process.
Table 42: Serial Master Mode Connections
Pin Name
HSWAP
FPGA Direction
Input
P
Description
User I/O Pull-Up Control. When Low
during configuration, enables pull-up
resistors in all I/O pins to respective I/O
bank VCCO input.
During Configuration
After Configuration
Drive at valid logic level
throughout configuration.
User I/O
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 0, M1 = 0, M0 = 0.
Sampled when INIT_B goes
High.
User I/O
DIN
Input
Serial Data Input.
Receives serial data from
PROM’s D0 output.
User I/O
CCLK
Output
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity.
Drives PROM’s CLK clock
input.
User I/O
DOUT
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration,
this pin connects to DIN input
of the next FPGA in the chain.
User I/O
INIT_B
Open-drain
bidirectional I/O
Initialization Indicator. Active Low. Goes
Low at start of configuration during
Initialization memory clearing process.
Released at end of memory clearing,
when mode select pins are sampled.
Requires external 4.7 kΩ pull-up resistor
to VCCO_2.
Connects to PROM’s
OE/RESET input. FPGA
clears PROM’s address
counter at start of
configuration, enables
outputs during configuration.
PROM also holds FPGA in
Initialization state until PROM
reaches Power-On Reset
(POR) state. If CRC error
detected during
configuration, FPGA drives
INIT_B Low.
User I/O
60
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Functional Description
Table 42: Serial Master Mode Connections (Continued)
Pin Name
DONE
PROG_B
FPGA Direction
Description
During Configuration
After Configuration
Open-drain
bidirectional I/O
FPGA Configuration Done. Low during
configuration. Goes High when FPGA
successfully completes configuration.
Requires external 330 Ω pull-up resistor
to 2.5V.
Connects to PROM’s
chip-enable (CE) input.
Enables PROM during
configuration. Disables
PROM after configuration.
Pulled High via
external pull-up.
When High, indicates
that the FPGA
successfully
configured.
Input
Program FPGA. Active Low. When
asserted Low for 300 ns or longer, forces
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up resistor
to 2.5V. If driving externally, use an
open-drain or open-collector driver.
Must be High during
configuration to allow
configuration to start.
Connects to PROM’s CF pin,
allowing JTAG PROM
programming algorithm to
reprogram the FPGA.
Drive PROG_B Low
and release to
reprogram FPGA.
Voltage Compatibility
The PROM’s VCCINT supply must be either 3.3V for the
serial XCFxxS Platform Flash PROMs or 1.8V for the
serial/parallel XCFxxP PROMs.
V The FPGA’s VCCO_2 supply input and the Platform
Flash PROM’s VCCO supply input must be the same voltage, ideally +2.5V. Both devices also support 1.8V and 3.3V
interfaces but the FPGA’s PROG_B and DONE pins require
special attention as they are powered by the FPGA’s
VCCAUX supply, nominally 2.5V. See application note
XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs"
for additional information.
Supported Platform Flash PROMs
Table 43 shows the smallest available Platform Flash
PROM to program a single Spartan-3E FPGA. A multiple-FPGA daisy-chain application requires a Platform Flash
PROM large enough to contain the sum of the various
FPGA file sizes.
Table 43: Number of Bits to Program a Spartan-3E
FPGA and Smallest Platform Flash PROM
Device
Number of
Configuration
Bits
Smallest Available
Platform Flash
XC3S100E
581,344
XCF01S
XC3S250E
1,352,192
XCF02S
XC3S500E
2,267,136
XCF04S
XC3S1200E
3,832,320
XCF04S
XC3S1600E
5,957,760
XCF08P
or 2 x XCF04S
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
The XC3S1600E requires an 8 Mbit PROM. There are two
possible solutions. Either use a single 8 Mbit XCF08P parallel/serial PROM or cascade two 4 Mbit XCF04S serial
PROMs. The two XCF04S PROMs use a 3.3V VCCINT supply while the XCF08P requires a 1.8V VCCINT supply. If the
board does not already have a 1.8V supply available, the
two cascaded XCF04S PROM solution is recommended.
CCLK Frequency
In Master Serial mode, the FPGA’s internal oscillator generates the configuration clock frequency. The FPGA provides
this clock on its CCLK output pin, driving the PROM’s CLK
input pin. The FPGA starts configuration at its lowest frequency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bitstream. The maximum frequency is specified using the
ConfigRate bitstream generator option. Table 44 shows the
maximum ConfigRate settings, approximately equal to
MHz, for various Platform Flash devices and I/O voltages.
For the serial XCFxxS PROMs, the maximum frequency
also depends on the interface voltage.
Table 44: Maximum ConfigRate Settings for Platform
Flash
Platform Flash
Part Number
I/O Voltage
(VCCO_2, VCCO)
Maximum
ConfigRate
Setting
XCF01S
XCF02S
XCF04S
3.3V or 2.5V
25
1.8V
12
3.3V, 2.5V, or 1.8V
25
XCF08P
XCF16P
XCF32P
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Functional Description
CCLK
+1.2V
VCCINT
VCCO_0
VCCO_2
DIN
CCLK
DOUT
INIT_B
M2
M1
M0
XCFxxS = +3.3V
XCFxxP = +1.8V
V
VCCINT
D0
CLK
V
VCCO
‘1’
‘1’
‘1’
M2
M1
M0
CF
VCCJ
TDO
TDI
TMS
TCK
V
V
DOUT
Spartan-3E
FPGA
+2.5V
+2.5V
VCCO_0
DOUT
INIT_B
CCLK
DIN
CEO
+2.5V
VCCINT
VCCO_0
VCCO_2
Platform Flash
XCFxx
CE
VCCAUX
TDO
TDI
TMS
TCK
HSWAP
Slave
Serial
Mode
OE/RESET
Spartan-3E
FPGA
+2.5V
JTAG
TDI
TMS
TCK
TDO
P
VCCO_0
VCCAUX
TDO
TDI
TMS
TCK
+2.5V
GND
PROG_B
DONE
PROG_B
330
GND
4.7k
Serial Master
Mode
‘0’
‘0’
‘0’
HSWAP
4.7k
P
+1.2V
PROG_B
Recommend
open-drain
driver
DONE
GND
PROG_B
TCK
TMS
DONE
INIT_B
DS312-2_45_021405
Figure 49: Daisy-Chaining from Master Serial Mode
Daisy-Chaining
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain,
as shown in Figure 49. Use Master Serial mode
(M[2:0] = <0:0:0>) for the FPGA connected to the Platform
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
all other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes loading its configuration data from the Platform Flash, the master device supplies data using its DOUT output pin to the
next device in the daisy-chain, on the falling CCLK edge.
JTAG Interface
Both the Spartan-3E FPGA and the Platform Flash PROM
have a four-wire IEEE 1149.1/1532 JTAG port. Both devices
share the TCK clock input and the TMS mode select input.
The devices may connect in either order on the JTAG chain
with the TDO output of one device feeding the TDI input of
the following device in the chain. The TDO output of the last
device in the JTAG chain drives the JTAG connector.
The JTAG interface on Spartan-3E FPGAs is powered by
the 2.5V VCCAUX supply. Consequently, the PROM’s VCCJ
supply input must also be 2.5V. To create a 3.3V JTAG interface, please refer to application note XAPP453: "The 3.3V
Configuration of Spartan-3 FPGAs" for additional information.
In-System Programming Support
provided by the Xilinx iMPACT programming software and
the associated Xilinx Parallel Cable IV, MultiPRO, or Platform Cable USB programming cables.
Storing Additional User Data in Platform Flash
After configuration, the FPGA application can continue to
use the Master Serial interface pins to communicate with
the Platform Flash PROM. If desired, use a larger Platform
Flash PROM to hold additional non-volatile application data,
such as MicroBlaze processor code, or other user data such
as serial numbers and Ethernet MAC IDs. The FPGA first
configures from Platform Flash PROM. Then using FPGA
logic after configuration, the FPGA copies MicroBlaze code
from Platform Flash into external DDR SDRAM for code
execution.
See XAPP694: "Reading User Data from Configuration
PROMs" and XAPP482: "MicroBlaze Platform Flash/PROM
Boot Loader and User Data Storage" for specific details on
how to implement such an interface.
SPI Serial Flash Mode
In SPI Serial Flash mode (M[2:0] = <0:0:0>), the Spartan-3E
FPGA configures itself from an attached industry-standard
SPI serial Flash PROM, as illustrated in Figure 50 and
Figure 52. The FPGA supplies the CCLK output clock from
its internal oscillator to the clock input of the attached SPI
Flash PROM.
Both the FPGA and the Platform Flash PROM are in-system
programmable via the JTAG chain. Download support is
62
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
+1.2V
VCCINT
VCCO_0
VCCO_2
MOSI
DIN
CSO_B
SPI Mode
M2
M1
M0
‘1’
S
‘1’
+2.5V
JTAG
TDI
TMS
TCK
TDO
VS2
VS1
VS0
VCC
W
‘1’
Spartan-3E
FPGA
TDI
TMS
TCK
DATA_IN
DATA_OUT
SELECT
WR_PROTECT
HOLD
CLOCK
GND
+3.3V
CCLK
DOUT
INIT_B
VCCAUX
TDO
P
4.7k
Variant Select
+3.3V
I
+2.5V
+2.5V
330
‘0’
‘0’
‘1’
VCCO_0
SPI
Serial
Flash
PROG_B
4.7k
HSWAP
4.7k
P
+3.3V
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_46_021405
Figure 50: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B)
S Although SPI is a standard four-wire interface, various
available SPI Flash PROMs use different command protocols. The FPGA’s variant select pins, VS[2:0], define how
the FPGA communicates with the SPI Flash, including
which SPI Flash command the FPGA issues to start the
read operation and the number of dummy bytes inserted
before the FPGA expects to receive valid data from the SPI
Flash. Table 45 shows the available SPI Flash PROMs
expected to operate with Spartan-3E FPGAs. Other compatible devices might work but have not been tested for suitability with Spartan-3E FPGAs. All other VS[2:0] values are
reserved for future use.
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
Figure 50 shows the general connection diagram for those
SPI Flash PROMs that support the 0x03 READ command
or the 0x0B FAST READ commands.
Figure 51 shows the connection diagram for Atmel
DataFlash serial PROMs, which also use an SPI-based protocol.
Figure 54 demonstrates how to configure multiple FPGAs
with different configurations, all stored in a single SPI Flash.
The diagram uses standard SPI Flash memories but the
same general technique applies for Atmel DataFlash.
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63
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Functional Description
+1.2V
SPI Mode
M2
M1
M0
Variant Select
‘1’
‘1’
‘0’
+2.5V
JTAG
TDI
TMS
TCK
TDO
VS2
VS1
VS0
+3.3V
I
VCC
W
‘1’
Spartan-3E
FPGA
VCCAUX
TDO
SI
SO
CS
WP
RESET
RDY/BUSY
SCK
PROG_B
Power-on monitor is only required if
+3.3V (VCCO_2) supply is last supply
in power-on sequence, after VCCINT
and VCCAUX. Must delay FPGA
configuration for > 20 ms after SPI
DataFlash reaches its minimum VCC.
Force FPGA INIT_B input or PROG_B
input Low with an open-drain or opencollector driver.
GND
+3.3V
CCLK
DOUT
INIT_B
TDI
TMS
TCK
P
+3.3V
INIT_B
+2.5V
+2.5V
330Ω
‘0’
‘0’
‘1’
VCCO_0
Atmel
AT45DB
DataFlash
4.7kΩ
VCCO_2
MOSI
DIN
CSO_B
4.7k
VCCINT
HSWAP
VCCO_0
4.7kΩ
P
+3.3V
Power-On
Monitor
or
DONE
+3.3V
GND
PROG_B
PROG_B
Recommend
open-drain
driver
Power-On
Monitor
DS312-2_50a_022305
Figure 51: Atmel SPI-based DataFlash Configuration Interface
64
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Table 45: Variant Select Codes for SPI Serial Flash PROMs
VS2
VS1
1
1
1
0
SPI Read
Command
VS0
1
1
FAST READ (0x0B)
(see Figure 50)
READ (0x03)
(see Figure 50)
Dummy
Bytes
SPI Serial Flash Vendor
SPI Flash Family
STMicroelectronics (ST)
M25Pxx
NexFlash
NX25Pxx
1
SST25LFxxxA
Silicon Storage Technology (SST)
SST25VFxxxA
Programmable Microelectronics Corp. (PMC)
Pm25LVxxx
STMicroelectronics (ST)
M25Pxx
NexFlash
NX25Pxx
SST25LFxxxA
0
Silicon Storage Technology (SST)
SST25VFxxxA
SST25VFxxx
1
1
0
Others
READ ARRAY
(0xE8)
(see Figure 51)
3
Programmable Microelectronics Corp. (PMC)
Pm25LVxxx
Atmel Corporation
AT45DB DataFlash
Reserved
W Table 46 shows the connections between the SPI Flash
PROM and the FPGA’s SPI configuration interface. Each
SPI Flash PROM vendor uses slightly different signal naming. The SPI Flash PROM’s write protect and hold controls
are not used by the FPGA during configuration. However,
the HOLD pin must be High during the configuration process. The PROM’s write protect input must be High in order
to write or program the Flash memory.
Table 46: SPI Flash PROM Connections and Pin Naming
SPI Flash Pin
FPGA Connection
STMicro
NexFlash
Silicon
Storage
Technology
Atmel
DataFlash
DATA_IN
MOSI
D
DI
SI
SI
DATA_OUT
DIN
Q
DO
SO
SO
SELECT
CSO_B
S
CS
CE#
CS
CLOCK
CCLK
C
CLK
SCK
SCK
Not required for FPGA configuration. Must be
High to program SPI Flash. Optional
connection to FPGA user I/O after
configuration.
W
WP
WP#
WP
Not required for FPGA configuration but must
be High during configuration. Optional
connection to FPGA user I/O after
configuration. Not applicable to Atmel
DataFlash.
HOLD
HOLD
HOLD#
N/A
WR_PROTECT
W
HOLD
(see Figure 50)
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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65
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Functional Description
Table 46: SPI Flash PROM Connections and Pin Naming (Continued)
FPGA Connection
STMicro
NexFlash
Silicon
Storage
Technology
Only applicable to Atmel DataFlash. Not
required for FPGA configuration but must be
High during configuration. Optional
connection to FPGA user I/O after
configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct
programming of the DataFlash.
N/A
N/A
N/A
RESET
Only applicable to Atmel DataFlash and only
available on certain packages. Not required
for FPGA configuration. Output from
DataFlash PROM. Optional connection to
FPGA user I/O after configuration.
N/A
N/A
N/A
RDY/BUSY
SPI Flash Pin
RESET
(see Figure 51)
RDY/BUSY
(see Figure 51)
The mode select pins, M[2:0], and the variant select pins,
VS[2:0] are sampled when the FPGA’s INIT_B output goes
High and must be at defined logic levels during this time.
After configuration, when the FPGA’s DONE output goes
High, these pins are all available as full-featured user-I/O
pins.
Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to disP
Atmel
DataFlash
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
In a single-FPGA application, the FPGA’s DOUT pin is not
used but is actively driving during the configuration process.
Table 47: Serial Peripheral Interface (SPI) Connections
Pin Name
HSWAP
FPGA Direction
Description
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
P
During Configuration
After Configuration
Drive at valid logic level
throughout configuration.
User I/O
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 0, M1 = 0, M0 = 1.
Sampled when INIT_B goes
High.
User I/O
VS[2:0]
Input
Variant Select. Instructs the
FPGA how to communicate with
the attached SPI Flash PROM.
Must be at the logic levels
shown in Table 45. Sampled
when INIT_B goes High.
User I/O
Serial Data Output.
FPGA sends SPI Flash memory
read commands and starting
address to the PROM’s serial
data input.
User I/O
Serial Data Input.
FPGA receives serial data from
PROM’s serial data output.
User I/O
S
MOSI
DIN
66
Output
Input
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Table 47: Serial Peripheral Interface (SPI) Connections (Continued)
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
CSO_B
Output
Chip Select Output. Active Low.
Connects to the SPI Flash
PROM’s chip-select input. If
HSWAP = 1, connect this signal
to a 4.7 kΩ pull-up resistor to
3.3V.
Drive CSO_B High after
configuration to disable the
SPI Flash and reclaim the
MOSI, DIN, and CCLK pins.
Optionally, re-use this pin
and MOSI, DIN, and CCLK
to continue communicating
with SPI Flash.
CCLK
Output
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long
or has multiple connections,
terminate this output to maintain
signal integrity.
Drives PROM’s clock input.
User I/O
DOUT
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of the
next FPGA in the chain.
User I/O
INIT_B
Open-drain
bidirectional I/O
Initialization Indicator. Active
Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
Active during configuration. If
SPI Flash PROM requires > 2
ms to awake after powering on,
hold INIT_B Low until PROM is
ready. If CRC error detected
during configuration, FPGA
drives INIT_B Low.
User I/O
DONE
Open-drain
bidirectional I/O
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
Low indicates that the FPGA is
not yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Input
Program FPGA. Active Low.
When asserted Low for 300 ns or
longer, forces the FPGA to restart
its configuration process by
clearing configuration memory and
resetting the DONE and INIT_B
pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up
resistor to 2.5V. If driving
externally, use an open-drain or
open-collector driver.
Must be High to allow
configuration to start.
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to SPI
Flash PROM pins.
PROG_B
Voltage Compatibility
Available SPI Flash PROMs use a single 3.3V supply voltage. All of the FPGA’s SPI Flash interface signals are within
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
I/O Bank 2. Consequently, the FPGA’s VCCO_2 supply voltage must also be 3.3V to match the SPI Flash PROM.
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Functional Description
Power-On Precautions if 3.3V Supply is Last in
Sequence
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in Figure 63. The FPGA waits for its three
power supplies — VCCINT, VCCAUX, and VCCO to I/O
Bank 2 (VCCO_2) — to reach their respective power-on
thresholds before beginning the configuration process.
The SPI Flash PROM is powered by the same voltage supply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
accessed until their VCC supply reaches its minimum data
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 µs as shown in
Table 48. For other vendors, it is as much as 20 ms.
Table 48: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
SPI Flash PROM
Part Number
Vendor
Data Sheet Minimum Time from VCC, min. to Select = Low
Symbol
Value
Units
STMicroelectronics
M25Pxx
TVSL
10
µs
NexFlash
NX25xx
TVSL
10
µs
Silicon Storage Technology
SST25LFxx
TPU-READ
10
µs
Programmable
Microelectronics Corporation
Pm25LVxxx
TVCS
50
µs
Atmel Corporation
AT45DBxx
20
ms
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other VCCINT
and VCCAUX supplies, and consequently, there is no issue.
However, if the 3.3V supply feeding the FPGA's VCCO_2
supply is last in the sequence, a potential race occurs
between the FPGA and the SPI Flash PROM, as shown in
Figure 52.
If the FPGA's VCCINT and VCCAUX supplies are already
valid, then the FPGA waits for VCCO_2 to reach its minimum threshold voltage before starting configuration. This
threshold voltage is labeled as VCCO2T in Module 3 and
ranges from approximately 0.4V to 1.0V, substantially lower
than the SPI Flash PROM's minimum voltage. Once all
three FPGA supplies reach their respective Power On
Reset (POR) thresholds, the FPGA starts the configuration
process and begins initializing its internal configuration
memory. Initialization requires approximately 1 ms (TPOR,
minimum in Module 3), after which the FPGA deasserts
INIT_B, selects the SPI Flash PROM, and starts sending
the appropriate read command. The SPI Flash PROM must
be ready for read operations at this time.
If the 3.3V supply is last in the sequence and does not ramp
fast enough, or if the SPI Flash PROM cannot be ready
when required by the FPGA, delay the FPGA configuration
process by holding either the FPGA's PROG_B input or
INIT_B input Low, as highlighted in Figure 51. Release the
FPGA when the SPI Flash PROM is ready. For example, a
simple R-C delay circuit attached to the INIT_B pin forces
the FPGA to wait for a preselected amount of time. Alternately, a Power Good signal from the 3.3V supply or a system reset signal accomplishes the same purpose. Use an
open-drain or open-collector output when driving PROG_B
or INIT_B.
3.3V Supply
SPI Flash cannot be selected
SPI Flash PROM
minimum voltage
FPGA VCCO_2 minimum
Power On Reset Voltage
(VCCO2T )
(VCCINT, VCCAUX
already valid)
SPI Flash available for
read operations
SPI Flash
PROM CS
delay (tVSL )
FPGA initializes configuration
memory (TPOR)
Time
SPI Flash PROM must
be ready for FPGA
access otherwise delay
FPGA configuration
FPGA accesses
SPI Flash PROM
DS312-2_50b_022405
Figure 52: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
68
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
SPI Flash PROM Density Requirements
Table 49 shows the smallest usable SPI Flash PROM to
program a single Spartan-3E FPGA. Commercially available SPI Flash PROMs range in density from 1 Mbit to 128
Mbits. A multiple-FPGA daisy-chained application requires
a SPI Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-density SPI Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the SPI Flash
PROM can also store application code for a MicroBlaze™
RISC processor core integrated in the Spartan-3E FPGA.
See Using the SPI Flash Interface after Configuration.
Table 49: Number of Bits to Program a Spartan-3E
FPGA and Smallest SPI Flash PROM
Device
Number of
Configuration
Bits
Smallest Usable
SPI Flash PROM
XC3S100E
581,344
1 Mbit
XC3S250E
1,352,192
2 Mbit
XC3S500E
2,267,136
4 Mbit
XC3S1200E
3,832,320
4 Mbit
XC3S1600E
5,957,760
8 Mbit
CCLK Frequency
In SPI Flash mode, the FPGA’s internal oscillator generates
the configuration clock frequency. The FPGA provides this
clock on its CCLK output pin, driving the PROM’s clock input
pin. The FPGA starts configuration at its lowest frequency
and increases its frequency for the remainder of the configuration process if so specified in the configuration bitstream.
The maximum frequency is specified using the ConfigRate
bitstream generator option. The maximum frequency supported by the FPGA configuration logic depends on the tim-
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
ing for the SPI Flash device. Without examining the timing
for a specific SPI Flash PROM, use ConfigRate = 12,
which is approximately 12 MHz. SPI Flash PROMs that support the FAST READ command support higher data rates.
Some such PROMs support up to ConfigRate = 25 and
beyond but require careful data sheet analysis.
Using the SPI Flash Interface after Configuration
After the FPGA successfully completes configuration, all of
the pins connected to the SPI Flash PROM are available as
user-I/O pins.
If not using the SPI Flash PROM after configuration, drive
CSO_B High to disable the PROM. The MOSI, DIN, and
CCLK pins are then available to the FPGA application.
Because all the interface pins are user I/O after configuration, the FPGA application can continue to use the SPI
Flash interface pins to communicate with the SPI Flash
PROM, as shown in Figure 53. SPI Flash PROMs offer random-accessible, byte-addressable, read/write, non-volatile
storage to the FPGA application.
SPI Flash PROMs are available in densities ranging from
1 Mbit up to 128 Mbits. However, a single Spartan-3E FPGA
requires less than 6 Mbits. If desired, use a larger SPI Flash
PROM to contain additional non-volatile application data,
such as MicroBlaze processor code, or other user data such
as serial numbers and Ethernet MAC IDs. In the example
shown in Figure 53, the FPGA configures from SPI Flash
PROM. Then using FPGA logic after configuration, the
FPGA copies MicroBlaze code from SPI Flash into external
DDR SDRAM for code execution. Similarly, the FPGA application can store non-volatile application data within the SPI
Flash PROM.
The FPGA configuration data is stored starting at location 0.
Store any additional data beginning in the next available SPI
Flash PROM sector or page. Do not mix configuration data
and user data in the same sector or page.
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Functional Description
Spartan-3E FPGA
MOSI
DIN
FPGA-based
SPI Master CCLK
CSO_B
DATA_IN
DATA_OUT
CLOCK
SELECT
+3.3V
User-I/O
4.7kΩ
DDR SDRAM
SPI Serial Flash PROM
SPI Peripherals
DATA_IN
DATA_OUT
CLOCK
SELECT
User Data
FFFFF
MicroBlaze
Code
FPGA
Configuration
0
• A/D Converter
• D/A Converter
• CAN Controller
• Temperature Sensor
• Displays
• Temperature Sensor
• Microcontroller
• ASSP
To other SPI slave peripherals
DS312-2_47_022205
Figure 53: Using the SPI Flash Interface After Configuration
Similarly, the SPI bus can be expanded to additional SPI
peripherals. Because SPI is a common industry-standard
interface, there are a variety of SPI-based peripherals available, including analog-to-digital (A/D) converters, digital-to-analog (D/A) converters, CAN controllers, and
temperature sensors.
The MOSI, DIN, and CCLK pins are common to all SPI
peripherals. Connect the select input on each additional SPI
peripheral to one of the FPGA user I/O pins. If HSWAP = 0
during configuration, the FPGA holds the select line High. If
HSWAP = 1, connect the select line to +3.3V via an external
4.7 kΩ pull-up resistor to avoid spurious read or write operations. After configuration, drive the select line Low to select
the desired SPI peripheral. Refer to the individual SPI
70
peripheral data sheet for specific interface and communication protocol requirements.
Daisy-Chaining
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain,
as shown in Figure 54. Use SPI Flash mode
(M[2:0] = <0:0:1>) for the FPGA connected to the Platform
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
all other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes loading its configuration data from the SPI Flash PROM, the
master device uses its DOUT output pin to supply data to
the next device in the daisy-chain, on the falling CCLK edge.
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DS312-2 (v1.1) March 21, 2005
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Functional Description
CCLK
+1.2V
VCCINT
HSWAP
VCCO_0
VCCO_2
MOSI
DIN
CSO_B
SPI Mode
M2
M1
M0
‘1’
S
‘1’
+2.5V
JTAG
TDI
TMS
TCK
TDO
VS2
VS1
VS0
+3.3V
I
P
VCC
DATA_IN
DATA_OUT
SELECT
WR_PROTECT
HOLD
CLOCK
W
‘1’
Spartan-3E
FPGA
VCCAUX
TDO
VCCINT
VCCO_0
VCCO_2
Slave
Serial
Mode
‘1’
‘1’
‘1’
+3.3V
DONE
DOUT
DOUT
INIT_B
VCCAUX
TDO
TDI
TMS
TCK
PROG_B
330
+3.3V
Spartan-3E
FPGA
+2.5V
GND
VCCO_0
M2
M1
M0
CCLK
DIN
+2.5V
PROG_B
HSWAP
GND
CCLK
DOUT
INIT_B
TDI
TMS
TCK
P
4.7k
Variant Select
VCCO_0
SPI
Serial
Flash
4.7k
‘0’
‘0’
‘1’
4.7k
P
+1.2V
+3.3V
+2.5V
DONE
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_48_021405
Figure 54: Daisy-Chaining from SPI Flash Mode
In-System Programming Support
I In a production application, the SPI Flash PROM is usually pre-programmed before it is mounted on the printed circuit board. In-system programming support is available
from some third-party PROM programmers using a socket
adapter with attached wires. To gain access to the SPI
Flash signals, drive the FPGA’s PROG_B input Low with an
open-drain driver. This action places all FPGA I/O pins,
including those attached to the SPI Flash, in high-impedance (Hi-Z). If the HSWAP input is High, the I/Os have
pull-up resistors to the VCCO input on their respective I/O
bank. The external programming hardware then has direct
access to the SPI Flash pins. The programming access
points are highlighted in the gray box in Figure 50,
Figure 51, and Figure 54.
Byte-Wide Peripheral Interface (BPI) Parallel
Flash Mode
In
Byte-wide
Peripheral
Interface
(BPI)
mode
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA configures itself from an industry-standard parallel NOR Flash
PROM, as illustrated in Figure 55. The FPGA generates up
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
to a 24-bit address lines to access an attached parallel
Flash. Only 20 address lines are generated for Spartan-3E
FPGAs in the TQ144 package. The BPI mode is not available for Spartan-3E FPGAs in the VQ100 package.
The interface is designed for standard parallel NOR Flash
PROMs and supports both byte-wide (x8) and
byte-wide/halfword (x8/x16) PROMs. The interface does not
support halfword-only (x16) PROMs. The interface works
equally wells with other memories that use a similar interface such as SRAM, NVRAM, EEPROM, EPROM, or
masked ROM but is primarily designed for Flash memory.
There is another type of Flash memory called NAND Flash,
which is commonly used in memory cards for digital cameras, etc. Spartan-3E FPGAs do not configure directly from
NAND Flash memories.
The FPGA’s internal oscillator controls the interface timing
and the FPGA supplies the clock on the CCLK output pin.
However, the CCLK signal is not used in single FPGA applications. Similarly, the FPGA drives three pins Low during
configuration (LDC[2:0]) and one pin High during configuration (HDC) to the PROM’s control inputs.
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Functional Description
+1.2V
VCCINT
HSWAP
VCCO_0
VCCO_1
LDC0
LDC1
HDC
LDC2
A[16:0]
Not available
in VQ100
package
VCCO_2
D[7:0]
A[23:17]
M2
M1
M0
+2.5V
JTAG
TDI
TMS
TCK
TDO
VCCO
x8 or
CE#
OE# x8/x16
Flash
WE#
PROM
BYTE#
D
V
V
Spartan-3E BUSY
FPGA
CCLK
‘0’
‘0’
I
CSI_B
RDWR_B
CSO_B
INIT_B
VCCAUX
TDO
+2.5V
+2.5V
330Ω
TDI
TMS
TCK
DQ[7:0]
A[n:0]
GND
PROG_B
4.7kΩ
A
V
DQ[15:7]
BPI Mode
‘0’
‘1’
VCCO_0
4.7kΩ
P
V
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_49_022305
Figure 55: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
A During configuration, the value of the M0 mode pin
determines how the FPGA generates addresses, as shown
Table 50. When M0 = 0, the FPGA generates addresses
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA generates addresses starting at 0xFF_FFFF (all ones) and decrements the address on every falling CCLK edge.
Table 50: BPI Addressing Control
M2
M1
0
1
M0
Start Address
Addressing
0
0
Incrementing
1
0xFF_FFFF
Decrementing
This addressing flexibility allows the FPGA to share the parallel Flash PROM with an external or embedded processor.
72
Depending on the specific processor architecture, the processor boots either from the top or bottom of memory. The
FPGA is flexible and boots from the opposite end of memory from the processor. Only the processor or the FPGA can
boot at any given time. The FPGA can configure first, holding the processor in reset or the processor can boot first,
asserting the FPGA’s PROG_B pin.
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are available as full-featured user-I/O pins.
P Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to disable the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
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Functional Description
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
actively drives during configuration and is available as a
user I/O after configuration.
The RDWR_B and CSI_B must be Low throughout the configuration process. After configuration, these pins also
become user I/O.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Furthermore, the
bidirectional SelectMAP configuration peripheral interface
(see Slave Parallel Mode) is available after configuration.
To continue using SelectMAP mode, set the Persist bitstream generator option to Yes. An external host can then
read and verify configuration data.
In a single-FPGA application, the FPGA’s CSO_B and
CCLK pins are not used but are actively driving during the
configuration process. The BUSY pin is not used but also
Table 51: Byte-Wide Peripheral Interface (BPI) Connections
Pin Name
HSWAP
FPGA Direction
Description
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
P
During Configuration
After Configuration
Drive at valid logic level
throughout configuration.
User I/O
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 0, M1 = 1. Set M0 = 0 to
start at address 0, increment
addresses. Set M0 = 1 to start at
address 0xFFFFFF and
decrement addresses. Sampled
when INIT_B goes High.
User I/O
CSI_B
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B
Input
Read/Write Control. Active Low
write enable. Read functionality
typically only used after
configuration, if bitstream option
Persist=Yes.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
A
LDC0
Output
PROM Chip Enable
Connect to PROM chip-select
input (CE#). FPGA drives this
signal Low throughout
configuration.
User I/O
LDC1
Output
PROM Output Enable
Connect to PROM output-enable
input (OE#). FPGA drives this
signal Low throughout
configuration.
User I/O
HDC
Output
PROM Write Enable
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
User I/O
LDC2
D
Output
PROM Byte Mode
This signal is not used for x8
PROMs. For PROMs with a
x8/x16 data width control,
connect to PROM byte-mode
input (BYTE#). See Precautions
Using x8/x16 Flash PROMs.
FPGA drives this signal Low
throughout configuration.
User I/O. Drive this pin
High after configuration to
use a x8/x16 PROM in
x16 mode.
DS312-2 (v1.1) March 21, 2005
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Functional Description
Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name
A[23:0]
FPGA Direction
Output
Description
During Configuration
Address
After Configuration
Connect to PROM address
inputs. High order address lines
may not be available in all
packages and not all may be
required. Number of address
lines required depends on the
size of the attached Flash PROM.
FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
User I/O
Only 20 address lines are
available in TQ144 package.
D[7:0]
Input
Data Input
FPGA receives byte-wide data on
these pins in response the
address presented on A[23:0].
Data captured by FPGA
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
User I/O
BUSY
Output
Busy Indicator. Typically only
used after configuration, if
bitstream option Persist=Yes.
Not used during configuration but
actively drives.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CCLK
Output
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long
or has multiple connections,
terminate this output to maintain
signal integrity.
Not used in single FPGA
applications but actively drives. In
a daisy-chain configuration,
drives the CCLK inputs of all other
FPGAs in the daisy-chain.
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
INIT_B
Open-drain
bidirectional I/O
Initialization Indicator. Active
Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
User I/O
74
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Functional Description
Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name
DONE
FPGA Direction
Description
Open-drain
bidirectional I/O
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
Low indicates that the FPGA is
not yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Input
Program FPGA. Active Low.
When asserted Low for 300 ns or
longer, forces the FPGA to restart
its configuration process by
clearing configuration memory and
resetting the DONE and INIT_B
pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up
resistor to 2.5V. If driving
externally, use an open-drain or
open-collector driver.
Must be High to allow
configuration to start.
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to
Flash PROM pins.
PROG_B
During Configuration
Voltage Compatibility
V The FPGA’s parallel Flash interface signals are within
I/O Banks 1 and 2. The majority of parallel Flash PROMs
use a single 3.3V supply voltage. Consequently, in most
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages
must also be 3.3V to match the parallel Flash PROM. There
are some 1.8V parallel Flash PROMs available and the
FPGA interfaces with these devices if the VCCO_1 and
VCCO_2 supplies are also 1.8V.
Supported Parallel NOR Flash PROM Densities
Table 52 indicates the smallest usable parallel Flash PROM
to program a single Spartan-3E FPGA. Parallel Flash density is specified in bits but addressed as bytes. The FPGA
presents up to 24 address lines during configuration but not
all are required for single FPGA applications. Table 52
After Configuration
shows the minimum required number of address lines
between the FPGA and parallel Flash PROM. The actual
number of address line required depends on the density of
the attached parallel Flash PROM.
A multiple-FPGA daisy-chained application requires a parallel Flash PROM large enough to contain the sum of the
FPGA file sizes. An application may also use a larger-density parallel Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the parallel Flash
PROM could also contain the application code for a MicroBlaze RISC processor core implemented within the Spartan-3E FPGA. After configuration, the MicroBlaze processor
could execute directly from external Flash or could copy the
code to other, faster system memory before executing the
code.
Table 52: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Device
Uncompressed
File Sizes (bits)
Smallest Usable Parallel
Flash PROM
Minimum Required Address
Lines
XC3S100E
581,344
1 Mbit
A[16:0]
XC3S250E
1,352,192
2 Mbit
A[17:0]
XC3S500E
2,267,136
4 Mbit
A[18:0]
XC3S1200E
3,832,320
4 Mbit
A[18:0]
XC3S1600E
5,957,760
8 Mbit
A[19:0]
CCLK Frequency
In BPI mode, the FPGA’s internal oscillator generates the
configuration clock frequency that controls all the interface
timing. The FPGA starts configuration at its lowest frequency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
stream. The maximum frequency is specified using the
ConfigRate bitstream generator option. Table 53 shows the
maximum ConfigRate settings, approximately equal to
MHz, for various PROM read access times. Despite using
slower ConfigRate settings, BPI mode is equally fast as the
other configuration modes. In BPI mode, data is accessed
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75
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Functional Description
at the ConfigRate frequency and internally serialized with
an 8X clock frequency.
Table 53: Maximum ConfigRate Settings for Parallel
Flash PROMs
Flash Read Access Time
Maximum ConfigRate
Setting
< 200 ns
3
< 90 ns
6
Using the BPI Interface after Configuration
After the FPGA successfully completes configuration, all of
the pins connected to the parallel Flash PROM are available
as user I/Os.
If not using the parallel Flash PROM after configuration,
drive LDC0 High to disable the PROM’s chip-select input.
The remainder of the BPI pins then become available to the
FPGA application, including all 24 address lines, the eight
data lines, and the LDC2, LDC1, and HDC control pins.
Because all the interface pins are user I/Os after configuration, the FPGA application can continue to use the interface
pins to communicate with the parallel Flash PROM. Parallel
Flash PROMs are available in densities ranging from 1 Mbit
up to 128 Mbits and beyond. However, a single Spartan-3E
FPGA requires less than 6 Mbits for configuration. If
desired, use a larger parallel Flash PROM to contain additional non-volatile application data, such as MicroBlaze processor code, or other user data such as serial numbers,
Ethernet MAC IDs, etc. In such an example, the FPGA configures from parallel Flash PROM. Then using FPGA logic
after configuration, a MicroBlaze processor embedded
within the FPGA can either execute code directly from parallel Flash PROM or copy the code to external DDR
SDRAM and execute from DDR SDRAM. Similarly, the
FPGA application can store non-volatile application data
within the parallel Flash PROM.
The FPGA configuration data is stored starting at either at
location 0 or the top of memory (addresses all ones) or at
both locations for MultiBoot mode. Store any additional data
beginning in other available parallel Flash PROM sectors.
Do not mix configuration data and user data in the same
sector.
Similarly, the parallel Flash PROM interface can be
expanded to additional parallel peripherals.
The address, data, and LDC1 (OE#) and HDC (WE#) control signals are common to all parallel peripherals. Connect
the chip-select input on each additional peripheral to one of
the FPGA user I/O pins. If HSWAP = 0 during configuration,
the FPGA holds the chip-select line High via an internal
pull-up resistor. If HSWAP = 1, connect the select line to
+3.3V via an external 4.7 kΩ pull-up resistor to avoid spuri-
76
ous read or write operations. After configuration, drive the
select line Low to select the desired peripheral. Refer to the
individual peripheral data sheet for specific interface and
communication protocol requirements.
The FPGA optionally supports a 16-bit peripheral interface
by driving the LDC2 (BYTE#) control pin High after configuration. See Precautions Using x8/x16 Flash PROMs for
additional information.
The FPGA provides up to 24 address lines during configuration, addressing up to 128 Mbits (16 Mbytes). If using a
larger parallel PROM, connect the upper address lines to
FPGA user I/O. During configuration, the upper address
lines will be pulled High if HSWAP = 0. Otherwise, use
external pull-up or pull-down resistors on these address
lines to define their values during configuration.
Precautions Using x8/x16 Flash PROMs
D Most low- to mid-density PROMs are byte-wide (x8)
only. Many higher-density Flash PROMs support both
byte-wide (x8) and halfword-wide (x16) data paths and
include a mode input called BYTE# that switches between
x8 or x16. During configuration, Spartan-3E FPGAs only
support byte-wide data. However, after configuration, the
FPGA supports either x8 or x16 modes. In x16 mode, up to
eight additional user I/O pins are required for the upper data
bits, D[15:8].
Connecting a Spartan-3E FPGA to a x8/x16 Flash PROM is
simple, but does require a precaution. Various Flash PROM
vendors use slightly different interfaces to support both x8
and x16 modes. Some vendors (Intel, Micron, some STMicroelectronics devices) use a straightforward interface with
pin naming that matches the FPGA connections. However,
the PROM’s A0 pin is wasted in x16 applications and a separate FPGA user-I/O pin is required for the D15 data line.
Fortunately, the FPGA A0 pin is still available as a user I/O
after configuration, even though it connects to the Flash
PROM.
Other vendors (AMD, Atmel, Silicon Storage Technology,
some STMicroelectronics devices) use a pin-efficient interface but change the function of one pin, called IO15/A-1,
depending if the PROM is in x8 or x16 mode. In x8 mode,
BYTE# = 0, this pin is the least-significant address line. The
A0 address line selects the halfword location. The A-1
address line selects the byte location. When in x16 mode,
BYTE# = 1, the IO15/A-1 pin becomes the most-significant
data bit, D15 because byte addressing is not required in this
mode. Check to see if the Flash PROM has a pin named
“IO15/A-1" or "DQ15/A-1". If so, be careful to connect
x8/x16 Flash PROMs correctly, as shown in Table 54. Also,
remember that the D[14:8] data connections require FPGA
user I/O pins but that the D15 data is already connected for
the FPGA’s A0 pin.
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Functional Description
Table 54: FPGA Connections to Flash PROM with "IO15/A-1" Pin
FPGA Pin
Connection to Flash PROM with
IO15/A-1 Pin
x8 Flash PROM Interface After
FPGA Configuration
x16 Flash PROM Interface After
FPGA Configuration
LDC2
BYTE#
Drive LDC2 Low or leave
unconnected and tie PROM
BYTE# input to GND
Drive LCD2 High
LDC1
OE#
Active-Low Flash PROM
output-enable control
Active-Low Flash PROM
output-enable control
LDC0
CS#
Active-Low Flash PROM
chip-select control
Active-Low Flash PROM
chip-select control
HDC
WE#
Flash PROM write-enable
control
Flash PROM write-enable control
A[23:1]
A[n:0]
A[n:0]
A[n:0]
A0
IO15/A-1
IO15/A-1 is least-significant
address input
IO15/A-1 is most-significant data
line, IO15
D[7:0]
IO[7:0]
IO[7:0]
IO[7:0]
User I/O
Upper data lines IO[14:8] not
required unless used as x16 Flash
interface after configuration
Upper data lines IO[14:8] not
required
IO[14:8]
Daisy-Chaining
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain,
as shown in Figure 56. Use BPI mode (M[2:0] = <0:1:0> or
<0:1:1>) for the FPGA connected to the parallel NOR Flash
PROM and Slave Parallel mode (M[2:0] = <1:1:0>) for all
other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes loading its configuration data from the parallel Flash PROM, the
master device continues generating addresses to the Flash
PROM and asserts its CSO_B output Low, enabling the
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
next FPGA in the daisy-chain. The next FPGA then receives
parallel configuration data from the Flash PROM. The master FPGA’s CCLK output synchronizes data capture.
The downstream devices in Slave Parallel mode also
actively drive their LDC[2:0] and HDC outputs during configuration, although these signal are not used for configuration. These pins are in I/O Bank 1, powered by VCCO_1.
Because these pins do not connect elsewhere in the configuration circuit, the voltage on VCCO_1 can be whatever is
required by the end application.
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Functional Description
CCLK
D[7:0]
+1.2V
P
VCCINT
HSWAP
VCCO_0
VCCO_1
LDC0
LDC1
HDC
LDC2
A[16:0]
Not available
in VQ100
package
A
V
VCCO_0
V
P
I
VCCO_2
D[7:0]
A[23:17]
M2
M1
M0
x8 or
CE#
OE# x8/x16
Flash
WE#
PROM
BYTE#
D
Slave
Parallel
Mode
V
DQ[7:0]
A[n:0]
GND
CSO_B
INIT_B
VCCAUX
TDO
TDI
TMS
TCK
M2
M1
M0
‘0’
CCLK FPGA
CSI_B
RDWR_B
+2.5V
V
+2.5V
DONE
PROG_B
330
GND
VCCO_1
V
CSO_B
CSO_B
INIT_B
VCCAUX
TDO
TDI
TMS
TCK
4.7k
PROG_B
VCCO_2
D[7:0]
‘1’
‘1’
‘0’
VCCO_0
Spartan-3E BUSY
4.7k
2.5V
JTAG
TDI
TMS
TCK
TDO
CSI_B
RDWR_B
VCCINT
VCCO_0
VCCO_1
LDC0
LDC1
HDC
LDC2
Spartan-3E BUSY
FPGA
CCLK
‘0’
‘0’
HSWAP
VCC
DQ[15:7]
BPI Mode
‘0’
‘1’
+1.2V
+2.5V
DONE
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_50_021405
Figure 56: Daisy-Chaining from BPI Flash Mode
In-System Programming Support
I
In a production application, the parallel Flash PROM is
usually preprogrammed before it is mounted on the printed
circuit board. In-system programming support is available
from third-party boundary-scan tool vendors and from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the parallel Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the parallel Flash, in high-impedance (Hi-Z). If
the HSWAP input is High, the I/Os have pull-up resistors to
the VCCO input on their respective I/O bank. The external
programming hardware then has direct access to the parallel Flash pins. The programming access points are highlighted in the gray boxes in Figure 55 and Figure 56.
The FPGA itself can also be used as a parallel Flash PROM
programmer during development and test phases. Initially,
an FPGA-based programmer is downloaded into the FPGA
via JTAG. Then the FPGA performs the Flash PROM programming algorithms and receives programming data from
the host via the FPGA’s JTAG interface. See Chapter 11 in
"Embedded System Tools Reference Manual".
78
Dynamically Loading Multiple Configuration
Images Using MultiBoot Option
After the FPGA configures itself using BPI mode from one
end of the parallel Flash PROM, then the FPGA can trigger
a MultiBoot event and reconfigure itself from the opposite
end of the parallel Flash PROM. MultiBoot is only available
when using BPI mode and only for applications with a single
Spartan-3E FPGA.
By default, MultiBoot mode is disabled. To trigger a MultiBoot event, assert a Low pulse lasting at least 300 ns on the
MultiBoot Trigger (MBT) input to the STARTUP_SPARTAN3E
library primitive. Figure 57 shows an example usage. At
power up, the FPGA loads itself from the attached parallel
Flash PROM. In this example, the M0 mode pin is Low so
the FPGA starts at address 0 and increments through the
Flash PROM memory locations. After the FPGA completes
configuration, the application loaded into the FPGA performs a board-level or system test using FPGA logic. If the
test is successful, the FPGA triggers a MultiBoot event,
causing the FPGA to reconfigure from the opposite end of
the Flash PROM memory. This second configuration contains the FPGA application for normal operation.
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Functional Description
Parallel Flash PROM
Parallel Flash PROM
FFFFFF
General
FPGA
Application
FFFFFF
General
FPGA
Application
STARTUP_SPARTAN3E
GSR
User Area
User Area
GTS
MBT
> 300 ns
CLK
Diagnostics
FPGA
Application
Diagnostics
FPGA
Application
Reconfigure
0
0
First Configuration
Second Configuration
DS312-2_51_021405
Figure 57: Use MultiBoot to Load Alternate Configuration Images
Similarly, the general FPGA application could trigger a
MultiBoot event at any time to reload the diagnostics design.
In another potential application, the initial design loaded into
the FPGA image contains a “golden” or “fail-safe” configuration image, which then communicates with the outside world
and checks for a newer image. If there is a new configuration revision and the new image verifies as good, the
“golden” configuration triggers a MultiBoot event to load the
new image.
When a MultiBoot event is triggered, the FPGA then again
drives its configuration pins as described in Table 51. How-
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
ever, the FPGA does not assert the PROG_B pin. The system design must ensure that no other device drives on
these same pins during the reconfiguration process. The
FPGA’s DONE, LDC[2:0], or HDC pins can temporarily disable any conflicting drivers during reconfiguration.
Slave Parallel Mode
In Slave Parallel mode (M[2:0] = <1:1:0>), an external host
such as a microprocessor or microcontroller writes
byte-wide configuration data into the FPGA, using a typical
peripheral interface as shown in Figure 58.
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Functional Description
+1.2V
HSWAP
VCCINT
VCCO_0
VCCO_1
LDC0
LDC1
HDC
LDC2
Slave
Parallel
Mode
Intelligent
Download Host
Configuration
Memory
Source
• Internal memory
• Disk drive
• Over network
• Over RF link
VCC
D[7:0]
BUSY
SELECT
READ/WRITE
CLOCK
PROG_B
DONE
INIT_B
VCCO_2
V
Spartan-3E
D[7:0]
FPGA
BUSY
CSI_B
CSO_B
INIT_B
RDWR_B
CCLK
VCCAUX
TDO
TDI
TMS
TCK
GND
• Microcontroller
• Processor
• Tester
• Computer
V
M2
M1
M0
+2.5V
+2.5V
DONE
PROG_B
GND
PROG_B
Recommend
open-drain +2.5V
driver
JTAG
TDI
TMS
TCK
TDO
4.7kΩ
‘1’
‘1’
‘0’
VCCO_1
330Ω
V
VCCO_0
4.7k
P
DS312-2_52_022205
Figure 58: Slave Parallel Configuration Mode
The external download host starts the configuration process
by pulsing PROG_B and monitoring that the INIT_B pin
goes High, indicating that the FPGA is ready to receive its
first data. The host asserts the active-Low chip-select signal
(CSI_B) and the active-Low Write signal (RDWR_B). The
host then continues supplying data and clock signals until
either the FPGA’s DONE pin goes High, indicating a successful configuration, or until the FPGA’s INIT_B pin goes
Low, indicating a configuration error.
The FPGA captures data on the rising CCLK edge. If the
CCLK frequency exceeds 50 MHz, then the host must also
monitor the FPGA’s BUSY output. If the FPGA asserts
BUSY High, the host must hold the data for an additional
clock cycle, until BUSY returns Low. If the CCLK frequency
80
is 50 MHz or below, the BUSY pin may be ignored but
actively drives during configuration.
The configuration process requires more clock cycles than
indicated from the configuration file size. Additional clocks
are required during the FPGA’s start-up sequence, especially if the FPGA is programmed to wait for selected Digital
Clock Managers (DCMs) to lock to their respective clock
inputs (see Start-Up, page 91).
If the Slave Parallel interface is only used to configure the
FPGA, never to read data back, then the RDWR_B signal
can also be eliminated from the interface. However,
RDWR_B must remain Low during configuration.
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Functional Description
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Alternatively, the
bidirectional SelectMAP configuration interface is available
after configuration. To continue using SelectMAP mode, set
the Persist bitstream generator option to Yes. The external
host can then read and verify configuration data.
The Slave Parallel mode is also used with BPI mode to create multi-FPGA daisy-chains. The lead FPGA is set for BPI
mode configuration; all the downstream daisy-chain FPGAs
are set for Slave Parallel configuration, as highlighted in
Figure 56.
Table 55: Slave Parallel Mode Connections
Pin Name
HSWAP
FPGA Direction
Input
Description
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
During Configuration
After Configuration
Drive at valid logic level
throughout configuration.
User I/O
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 1, M1 = 1, M0 = 0 Sampled
when INIT_B goes High.
User I/O
D[7:0]
Input
Data Input.
Byte-wide data provided by host.
FPGA captures data on rising
CCLK edge.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
BUSY
Output
Busy Indicator.
If CCLK frequency is < 50 MHz,
this pin may be ignored. When
High, indicates that the FPGA is
not ready to receive additional
configuration data. Host must
hold data an additional clock
cycle.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CSI_B
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B
Input
Read/Write Control. Active Low
write enable.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CCLK
Input
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity.
External clock.
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
LDC[2:0]
Output
Low During Configuration.
These pins are not used during
configuration. Low throughout
configuration.
User I/O
HDC
Output
High During Configuration.
This pin is not used during
configuration. High throughout
configuration.
User I/O
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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81
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Functional Description
Table 55: Slave Parallel Mode Connections (Continued)
Pin Name
FPGA Direction
CSO_B
Output
INIT_B
DONE
PROG_B
Description
During Configuration
After Configuration
Chip Select Output. Active Low.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects
to the CSI_B pin of the next
FPGA in the chain. Actively
drives.
User I/O
Open-drain
bidirectional I/O
Initialization Indicator. Active Low.
Goes Low at start of configuration
during Initialization memory
clearing process. Released at end
of memory clearing, when mode
select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
User I/O
Open-drain
bidirectional I/O
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
Low indicates that the FPGA is
not yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Input
Program FPGA. Active Low. When
asserted Low for 300 ns or longer,
forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High. Requires
external 4.7 kΩ pull-up resistor to
2.5V. If driving externally, use an
open-drain or open-collector driver.
Must be High to allow
configuration to start.
Drive PROG_B Low and
release to reprogram
FPGA.
Voltage Compatibility
Daisy-Chaining
V Most Slave Parallel interface signals are within the
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 1.8V, 2.5V, or 3.3V to match
the requirements of the external host, ideally 2.5V. Using
1.8V or 3.3V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V VCCAUX supply. See application note XAPP453: "The
3.3V Configuration of Spartan-3 FPGAs" for additional information.
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain.
Use Slave Parallel mode (M[2:0] = <1:1:0>) for all FPGAs in
the daisy-chain. The schematic in Figure 59 is optimized for
FPGA downloading and does not support the SelectMAP
read interface. The FPGA’s RDWR_B pin must be Low during configuration.
The LDC[2:0] and HDC signal are active in I/O Bank 1 but
are not used in the interface. Consequently, VCCO_1 can
be set the appropriate voltage for the application.
82
After the lead FPGA is filled with its configuration data, the
lead FPGA enables the next FPGA in the daisy-chain by
asserting is chip-select output, CSO_B.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
D[7:0]
CCLK
+1.2V
VCCINT
VCCO_0
VCCO_1
LDC0
LDC1
HDC
LDC2
Slave
Parallel
Mode
Configuration
Memory
Source
• Internal memory
• Disk drive
• Over network
• Over RF link
VCC
DATA[7:0]
BUSY
SELECT
READ/WRITE
CLOCK
PROG_B
DONE
INIT_B
GND
• Microcontroller
• Processor
• Tester
‘1’
‘1’
‘0’
VCCO_2
M2
M1
M0
Spartan-3E
D[7:0]
FPGA
‘0’
BUSY
CSI_B
RDWR_B
CCLK
V
Slave
Parallel
Mode
V
‘1’
‘1’
‘0’
VCCAUX
TDO
‘0’
VCCO_1
LDC0
LDC1
HDC
LDC2
VCCO_2
+2.5V
VCCO_1
V
D[7:0]
FPGA
BUSY
CSI_B
CSO_B
RDWR_B
INIT_B
CCLK
VCCAUX
TDO
TDI
TMS
TCK
PROG_B
Recommend
open-drain
2.5V
driver
JTAG
TDI
TMS
TCK
TDO
CSO_B
+2.5V
DONE
PROG_B
GND
VCCO_0
M2
M1
M0
+2.5V
DONE
PROG_B
VCCINT
VCCO_0
Spartan-3E
CSO_B
INIT_B
TDI
TMS
TCK
HSWAP
VCCO_1
330Ω
V
Intelligent
Download Host
P
VCCO_0
4.7kΩ
HSWAP
4.7kΩ
P
+1.2V
GND
PROG_B
DONE
INIT_B
TMS
TCK
DS312-2_53_022305
Figure 59: Daisy-Chaining using Slave Parallel Mode
Slave Serial Mode
In Slave Serial mode (M[2:0] = <1:1:1>), an external host
such as a microprocessor or microcontroller writes serial
configuration data into the FPGA, using the synchronous
serial interface shown in Figure 60. The serial configuration
data is presented on the FPGA’s DIN input pin with sufficient setup time before each rising edge of the externally
generated CCLK clock input.
The intelligent host starts the configuration process by pulsing PROG_B and monitoring that the INIT_B pin goes High,
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
indicating that the FPGA is ready to receive its first data.
The host then continues supplying data and clock signals
until either the DONE pin goes High, indicating a successful
configuration, or until the INIT_B pin goes Low, indicating a
configuration error. The configuration process requires
more clock cycles than indicated from the configuration file
size. Additional clocks are required during the FPGA’s
start-up sequence, especially if the FPGA is programmed to
wait for selected Digital Clock Managers (DCMs) to lock to
their respective clock inputs (see Start-Up, page 91).
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83
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Functional Description
+1.2V
HSWAP
VCCINT
VCCO_0
VCCO_2
Slave
Serial
Mode
• Internal memory
• Disk drive
• Over network
• Over RF link
VCC
CLOCK
SERIAL_OUT
PROG_B
DONE
INIT_B
V
M2
M1
M0
CCLK
DIN
Spartan-3E
FPGA
DOUT
INIT_B
VCCAUX
TDO
TDI
TMS
TCK
GND
• Microcontroller
• Processor
• Tester
• Computer
+2.5V
+2.5V
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO
4.7kΩ
Configuration
Memory
Source
V
4.7kΩ
‘1’
‘1’
‘1’
Intelligent
V
Download Host
VCCO_0
330Ω
P
DS312-2_54_022305
Figure 60: Slave Serial Configuration
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are available as full-featured user-I/O pins.
84
P Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to disable the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Table 56: Slave Serial Mode Connections
Pin Name
HSWAP
FPGA Direction
Description
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
During Configuration
After Configuration
Drive at valid logic level
throughout configuration.
User I/O
0: Pull-up during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 1, M1 = 1, M0 = 1 Sampled
when INIT_B goes High.
User I/O
DIN
Input
Data Input.
Serial data provided by host.
FPGA captures data on rising
CCLK edge.
User I/O
CCLK
Input
Configuration Clock. If CCLK
PCB trace is long or has multiple
connections, terminate this output
to maintain signal integrity.
External clock.
User I/O
INIT_B
Open-drain
bidirectional I/O
Initialization Indicator. Active
Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
User I/O
DONE
Open-drain
bidirectional I/O
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully
completes configuration.
Requires external 330 Ω pull-up
resistor to 2.5V.
Low indicates that the FPGA is
not yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Input
Program FPGA. Active Low.
When asserted Low for 300 ns or
longer, forces the FPGA to restart
its configuration process by
clearing configuration memory
and resetting the DONE and
INIT_B pins once PROG_B
returns High. Requires external
4.7 kΩ pull-up resistor to 2.5V. If
driving externally, use an
open-drain or open-collector
driver.
Must be High to allow
configuration to start.
Drive PROG_B Low and
release to reprogram
FPGA.
PROG_B
Voltage Compatibility
V
Daisy-Chaining
Most Slave Serial interface signals are within the
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match
the requirements of the external host, ideally 2.5V. Using
3.3V or 1.8V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V VCCAUX supply. See application note XAPP453: "The
3.3V Configuration of Spartan-3 FPGAs" for additional information.
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain,
as shown in Figure 61. Use Slave Serial mode
(M[2:0] = <1:1:1>) for all FPGAs in the daisy-chain. After
the lead FPGA is filled with its configuration data, the lead
FPGA passes configuration data via its DOUT output pin to
the next FPGA on the falling CCLK edge.
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85
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Functional Description
CCLK
+1.2V
HSWAP
VCCINT
VCCO_0
VCCO_2
Slave
Serial
Mode
• Internal memory
• Disk drive
• Over network
• Over RF link
VCC
CLOCK
SERIAL_OUT
PROG_B
DONE
INIT_B
GND
• Microcontroller
• Processor
• Tester
• Computer
M2
M1
M0
CCLK
DIN
‘1’
‘1’
‘1’
Spartan-3E
FPGA
VCCAUX
TDO
VCCO_0
VCCO_2
VCCO_2
Spartan-3E
FPGA
DONE
VCCAUX
TDO
TDI
TMS
TCK
PROG_B
GND
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO
DOUT
DOUT
INIT_B
+2.5V
+2.5V
PROG_B
VCCINT
VCCO_0
M2
M1
M0
CCLK
DIN
DOUT
INIT_B
TDI
TMS
TCK
HSWAP
Slave
Serial
Mode
V
330
Configuration
Memory
Source
‘1’
‘1’
‘1’
V
4.7k
Intelligent
V
Download Host
P
VCCO_0
4.7k
P
+1.2V
+2.5V
DONE
GND
PROG_B
DONE
INIT_B
TMS
TCK
DS312-2_55_022305
Figure 61: Daisy-Chaining using Slave Serial Mode
JTAG Mode
The Spartan-3E FPGA has a dedicated four-wire IEEE
1149.1/1532 JTAG port that is always available any time the
FPGA is powered and regardless of the mode pin settings.
However, when the FPGA mode pins are set for JTAG mode
(M[2:0] = <1:0:1>), the FPGA waits to be configured via the
JTAG port after a power-on event or when PROG_B is
asserted. Selecting the JTAG mode simply disables the
86
other configuration modes. No other pins are required as
part of the configuration interface.
Figure 62 illustrates a JTAG-only configuration interface.
The JTAG interface is easily cascaded to any number of
FPGAs by connecting the TDO output of one device to the
TDI input of the next device in the chain. The TDO output of
the last device in the chain loops back to the port connector.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
P
+1.2V
+1.2V
VCCINT
HSWAP
VCCO_0
VCCO_0
VCCINT
HSWAP
VCCO_0
VCCO_0
VCCO_2
VCCO_2
VCCO_2
VCCO_2
JTAG
Mode
‘1’
‘0’
‘1’
P
JTAG
Mode
M2
M1
M0
VCCAUX
TDO
TDI
TMS
TCK
PROG_B
+2.5V
JTAG
TDI
TMS
TCK
TDO
‘1’
‘0’
‘1’
Spartan-3E
FPGA
M2
M1
M0
Spartan-3E
FPGA
+2.5V
VCCAUX
TDO
TDI
TMS
TCK
DONE
PROG_B
GND
+2.5V
DONE
GND
TMS
TCK
DS312-2_56_021405
Figure 62: JTAG Configuration Mode
Voltage Compatibility
The 2.5V VCCAUX supply powers the JTAG interface. All of
the user I/Os are separately powered by their respective
VCCO_# supplies.
When connecting the Spartan-3E JTAG port to a 3.3V interface, the JTAG input pins must be current-limited to 10 mA
or less using series resistors. Similarly, the TDO pin is a
CMOS output powered from +2.5V. The TDO output can
directly drive a 3.3V input but with reduced noise immunity.
See application note XAPP453: "The 3.3V Configuration of
Spartan-3 FPGAs" for additional information.
Maximum Bitstream Size for Daisy-Chains
The maximum bitstream length supported by Spartan-3E
FPGAs in serial daisy-chains is 4,294,967,264 bits (4
Gbits), roughly equivalent to a daisy-chain with 720
XC3S1600E FPGAs. This is a limit only for serial
daisy-chains where configuration data is passed via the
FPGA’s DOUT pin. There is no such limit for JTAG chains.
Configuration Sequence
The Spartan-3E configuration process is three-stage process that begins after the FPGA powers on (a POR event)
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
or after the PROG_B input is asserted. Power-On Reset
(POR) occurs after the VCCINT, VCCAUX, and the VCCO Bank
2 supplies reach their respective input threshold levels.
After either a POR or PROG_B event, the three-stage configuration process begins.
1. The FPGA clears (initializes) the internal configuration
memory.
2. Configuration data is loaded into the internal memory.
3. The user-application is activated by a start-up process.
Figure 63 is a generalized block diagram of the Spartan-3E
configuration logic, showing the interaction of different
device inputs and Bitstream Generator (BitGen) options. A
flow diagram for the configuration sequence of the Serial
and Parallel modes appears in Figure 64. Figure 65 shows
the Boundary-Scan or JTAG configuration sequence.
Initialization
Configuration automatically begins after power-on or after
asserting the FPGA PROG_B pin, unless delayed using the
FPGA’s INIT_B pin. The FPGA holds the open-drain INIT_B
signal Low while it clears its internal configuration memory.
Externally holding the INIT_B pin Low forces the configuration sequencer to wait until INIT_B again goes High.
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87
88
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0
TCK
M2
M1
1
Glitch Filter
V CCAUXT
VCCINTT
V CCO2T
CCLK
PROG_B
VCCAUX
VCCINT
VCCO_2
Internal
Oscillator
ConfigRate
0
1
POWER_GOOD
= Design Attribute
Option
Power On Reset (POR)
= Bitstream Generator (BitGen) Option
Option
LOCKED
DONE
JTAG_CLOCK
WAIT
All DCMs
RESET
*
ERROR
StartupClk
USER
USER
Configuration Error
Detection
(CRC Checker)
ENABLE
USER_CLOCK
CRC
DONE
Load application
data into CMOS
configuration latches
ENABLE
CONFIGURATION
INTERNAL_CONFIGURATION_CLOCK
RESET
CLEARING_MEMORY
Clear internal CMOS
configuration latches
ENABLE
INITIALIZATION
STARTUP_WAIT=TRUE
DCM in User
Application
*
*
DONE
*
WAIT
DonePipe
GWE
GSR
GTS
GWE_cycle
GTS_cycle
DONE_cycle
These connections are available via the
STARTUP_SPARTAN3E library primitive.
RESET
GSR_IN
GTS_IN
ENABLE
Enable application logic and
I/O pins
DCMs_LOCKED
LCK_cycle
STARTUP
DriveDone
EN
EN
INIT_B
Disable write
operations to
storage elements
Hold all storage
elements reset
Force all I/Os Hi-Z
DONE
Functional Description
R
DS312-2_57_022405
Figure 63: Generalized Spartan-3E FPGA Configuration Logic Block Diagram
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
and VCCO Bank 4 > 1V
No
Yes
Yes
Clear configuration
memory
PROG_B = Low
No
No
INIT_ B = High?
Yes
Sample mode pins
M[2:0] and VS[2:0]
pins are sampled on
INIT_B rising edge
Load configuration
data frames
CRC
correct?
No
INIT_B goes Low.
Abort Start-Up
Yes
Start-Up
sequence
DONE pin goes High,
signaling end of
configuration
User mode
No
Reconfigure?
Yes
DS312-2_58_021404
Figure 64: General Configuration Process
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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89
R
Functional Description
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
and VCCO Bank 4 > 1V
Load
JPROG
instruction
No
Yes
Clear
configuration
memory
Yes
PROG_B = Low
No
No
INIT_B = High?
Yes
Sample
mode pins
(JTAG port becomes
available)
Load CFG_IN
instruction
Load configuration
data frames
CRC
correct?
No
INIT_B goes Low.
Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
Yes
Reconfigure?
No
DS312-2_59_022505
Figure 65: Boundary-Scan Configuration Flow Diagram
90
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
R
Functional Description
Start-Up
The FPGA signals when the memory-clearing phase is
complete by releasing the open-drain INIT_B pin, allowing
the pin to go High via the external pull-up resistor to
VCCO_2.
At the end of configuration, the Global Set/Reset (GSR) signal is pulsed, placing all flip-flops in a known state. After
configuration completes, the FPGA switches over to the
user application loaded into the FPGA. The sequence and
timing of how the FPGA switches over is programmable as
is the clock source controlling the sequence.
Loading Configuration Data
Configuration data is then written to the FPGA’s internal
memory. The FPGA holds the Global Set/Reset (GSR) signal active throughout configuration, holding all FPGA
flip-flops in a reset state. The FPGA signals when the entire
configuration process completes be releasing the DONE
pin, allowing it to go High.
The default start-up sequence appears in Figure 66, where
the Global Three-State signal (GTS) is released one clock
cycle after DONE goes High. This sequence allows the
DONE signal to enable or disable any external logic used
during configuration before the user application in the FPGA
starts driving output signals. One clock cycle later, the Global Write Enable (GWE) signal is released. This allows signals to propagate within the FPGA before any clocked
storage elements such as flip-flops and block ROM are
enabled.
The FPGA configuration sequence can also be initiated by
asserting the PROG_B. Once release, the FPGA begins
clearing its internal configuration memory, and progresses
through the remainder of the configuration process.
Default Cycles
Start-Up Clock
Phase
0
1
2
3
4
5
6 7
DONE
GTS
GWE
Sync-to-DONE
Start-Up Clock
Phase
0
1
2
3
4
5
6 7
DONE High
DONE
GTS
GWE
DS312-2_60_022305
Figure 66: Default Start-Up Sequence
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
91
R
Functional Description
The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain, forcing the FPGAs to start synchronously. Similarly, the start-up
sequence can be paused at any stage, waiting for selected
DCMs to lock to their respective input clock signals. See
also Stabilizing DCM Clocks Before User Mode, page 48.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed RAM, and block
RAM resources. This capability is used for real-time debugging.
The start-up sequence can by synchronized to a clock
within
the
FPGA
application
using
the
STARTUP_SPARTAN3E library primitive and by setting the
StartupClk bitstream generator option. The FPGA application can optionally assert the Global Set/Reset (GSR) and
Global Three-State signal (GTS) signals via the
STARTUP_SPARTAN3E primitive.
Bitstream Generator (BitGen) Options
To synchronously control when registers values are captured for readback, using the CAPTURE_SPARTAN3 library
primitive, which applies for both Spartan-3 and Spartan-3E
FPGA families.
Various Spartan-3E FPGA functions are controlled by specific bits in the configuration bitstream image. These values
are specified when creating the bitstream image with the
Bitstream Generator (BitGen) software.
Table 57 provides a list of all BitGen options for Spartan-3E
FPGAs.
Readback
Using Slave Parallel mode, configuration data from the
FPGA can be read back. Readback is supported only in the
Slave Parallel and JTAG modes.
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options
Pins/Function
Affected
Values
(default)
ConfigRate
CCLK,
Configuration
3, 6,
12, 25
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency and the new setting is loaded as part of the configuration bitstream. The
software default value is 6 (~6 MHz).
StartupClk
Configuration,
Startup
Cclk
Default. The CCLK signal (internally or externally generated) controls the startup
sequence when the FPGA transitions from configuration mode to the user mode. See
Start-Up, page 91.
UserClk
A clock signal from within the FPGA application controls the startup sequence when
the FPGA transitions from configuration mode to the user mode. See Start-Up,
page 91. The FPGA application supplies the user clock on the CLK pin on the
STARTUP_SPARTAN3E primitive.
Jtag
The JTAG TCK input controls the startup sequence when the FPGA transitions from
configuration mode to the user mode. See Start-Up, page 91.
Option Name
UnusedPin
DONE_cycle
92
Unused I/O
Pins
DONE pin,
Configuration
Startup
Pulldown
Description
Default. All unused I/O pins have a pull-down resistor to GND.
Pullup
All unused I/O pins have a pull-up resistor to the VCCO_# supply for its associated I/O
bank.
Pullnone
All unused I/O pins are left floating (Hi-Z, high-impedance, three-state). Use external
pull-up or pull-down resistors or logic to apply a valid signal level.
1, 2, 3, 4,
5, 6
Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
Start-Up, page 91.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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Functional Description
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Option Name
GWE_cycle
GTS_cycle
LCK_cycle
DonePin
Pins/Function
Affected
Values
(default)
All flip-flops,
LUT RAMs,
and SRL16
shift registers,
Block RAM,
Configuration
Startup
1, 2, 3, 4,
5, 6
All I/O pins,
Configuration
DCMs,
Configuration
Startup
DONE pin
DonePipe
ProgPin
TckPin
TdiPin
DONE pin
DONE pin
PROG_B pin
JTAG TCK pin
JTAG TDI pin
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
Selects the Configuration Startup phase that asserts the internal write-enable signal to
all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read
and write operations. See Start-Up, page 91.
Done
Waits for the DONE pin input to go High before asserting the internal write-enable
signal to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and
write operations are enabled at this time.
Keep
Retains the current GWE_cycle setting for partial reconfiguration applications.
1, 2, 3, 4,
5, 6
Selects the Configuration Startup phase that releases the internal three-state control,
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so
configured, after this point. See Start-Up, page 91.
Done
Waits for the DONE pin input to go High before releasing the internal three-state
control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive,
if so configured, after this point.
Keep
Retains the current GTS_cycle setting for partial reconfiguration applications.
NoWait
The FPGA does not wait for selected DCMs to lock before completing configuration.
0, 1, 2, 3,
4, 5, 6
If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE,
the FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
Pullup
Pullnone
DriveDone
Description
Internally connects a pull-up resistor between DONE pin and VCCAUX. An external
330 Ω pull-up resistor to VCCAUX is still recommended.
No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to
VCCAUX is required.
No
When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to VCCAUX for a valid logic High.
Yes
When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
No
The input path from DONE pin input back to the Startup sequencer is not pipelined.
Yes
This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
Pullup
Internally connects a pull-up resistor or between PROG_B pin and VCCAUX. An
external 4.7 kΩ pull-up resistor to VCCAUX is still recommended.
Pullnone
No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to
VCCAUX is required.
Pullup
Internally connects a pull-up resistor between JTAG TCK pin and VCCAUX.
Pulldown
Internally connects a pull-down resistor between JTAG TCK pin and GND.
Pullnone
No internal pull-up resistor on JTAG TCK pin.
Pullup
Internally connects a pull-up resistor between JTAG TDI pin and VCCAUX.
Pulldown
Internally connects a pull-down resistor between JTAG TDI pin and GND.
Pullnone
No internal pull-up resistor on JTAG TDI pin.
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93
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Functional Description
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Option Name
Pins/Function
Affected
Values
(default)
TdoPin
JTAG TDO pin
Pullup
TmsPin
JTAG TMS pin
Description
Internally connects a pull-up resistor between JTAG TDO pin and VCCAUX.
Pulldown
Internally connects a pull-down resistor between JTAG TDO pin and GND.
Pullnone
No internal pull-up resistor on JTAG TDO pin.
Pullup
Internally connects a pull-up resistor between JTAG TMS pin and VCCAUX.
Pulldown
Internally connects a pull-down resistor between JTAG TMS pin and GND.
Pullnone
No internal pull-up resistor on JTAG TMS pin.
UserID
JTAG User ID
register
User
string
The 32-bit JTAG User ID register value is loaded during configuration. The default
value is all ones, 0xFFFF_FFFF hexadecimal. To specify another value, enter an
8-character hexadecimal value.
Security
JTAG,
SelectMAP,
Readback,
Partial
reconfiguration
None
Readback and partial reconfiguration are available via the JTAG port or via the
SelectMAP interface, if the Persist option is set to Yes.
Level1
Readback function is disabled. Partial reconfiguration is still available via the JTAG port
or via the SelectMAP interface, if the Persist option is set to Yes.
Level
Readback function is disabled. Partial reconfiguration is disabled.
CRC
Persist
94
Configuration
SelectMAP
interface pins,
BPI mode,
Slave mode,
Configuration
Enable
Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA
asserts INIT_B Low and DONE pin stays Low.
Disable
Turn off CRC checking.
No
All BPI and Slave mode configuration pins are available as user-I/O after configuration.
Yes
This option is required for Readback and partial reconfiguration using the SelectMAP
interface. The SelectMAP interface pins (see Slave Parallel Mode, page 79) are
reserved after configuration and are not available as user-I/O.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
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Functional Description
Powering Spartan-3E FPGAs
Voltage Supplies
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple
voltage supply inputs, as shown in Table 58. There are two
supply inputs for internal logic functions, VCCINT and
VCCAUX. Each of the four I/O banks has a separate VCCO
supply input that powers the output buffers within the associated I/O bank. All of the VCCO connections to a specific I/O
bank must be connected and must connect to the same
voltage.
Table 58: Spartan-3E Voltage Supplies
Supply
Input
Nominal Supply
Voltage
Description
VCCINT
Internal core supply voltage. Supplies all internal logic functions such as
CLBs, block RAM, multipliers, etc. Input to Power-On Reset (POR) circuit.
1.2V
VCCAUX
Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs),
differential drivers, dedicated configuration pins, JTAG interface. Input to
Power-On Reset (POR) circuit.
2.5V
VCCO_0
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the
FPGA.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
VCCO_1
Supplies the output buffers in I/O Bank 1, the bank along the right edge of the
FPGA. In Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode,
connects to the save voltage as the Flash PROM.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
VCCO_2
Supplies the output buffers in I/O Bank 2 the bank along the bottom edge of
the FPGA. Connects to the same voltage as the FPGA configuration source.
Input to Power-On Reset (POR) circuit.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
VCCO_3
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the
FPGA.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
In a 3.3V-only application, all four VCCO supplies connect to
3.3V. However, Spartan-3E FPGAs provide the ability to
bridge between different I/O voltages and standards by
applying different voltages to the VCCO inputs of different
banks. Refer to I/O Banking Rules for which I/O standards
can be intermixed within a single I/O bank.
Each I/O bank also has an separate, optional input voltage
reference supply, called VREF. If the I/O bank includes an
I/O standard that requires a voltage reference such as
HSTL or SSTL, then all VREF pins within the I/O bank must
be connected to the same voltage.
Voltage Regulators
Various power supply manufacturers offer complete power
solutions for Xilinx FPGAs including some with integrated
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
three-rail regulators specifically designed for Spartan-3 and
Spartan-3E FPGAs. The Xilinx Power Corner web site provides links to vendor solution guides and Xilinx power estimation and analysis tools.
Power Distribution System (PDS) Design and
Decoupling/Bypass Capacitors
Good power distribution system (PDS) design is important
for all FPGA designs, but especially so for high performance
applications, greater than 100 MHz. Proper design results in
better overall performance, lower clock and DCM jitter, and
a generally more robust system. Before designing the
printed circuit board (PCB) for the FPGA design, please
review XAPP623: "Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors".
www.xilinx.com
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Functional Description
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
03/01/05
1.0
Initial Xilinx release.
03/21/05
1.1
Updated Figure 42. Modified title on Table 33 and Table 39.
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1)
DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2)
DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3)
DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
96
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
018
Spartan-3E FPGA Family:
DC and Switching
Characteristics
R
DS312-3 (v1.0) March 1, 2005
0
0
Advance Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the characteristics of other families. Values are subject to change. Use as
estimates, not for production.
Preliminary: Based on characterization. Further changes
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. The following
applies unless otherwise noted: The parameter values
published in this module apply to all Spartan™-3E
devices. AC and DC characteristics are specified using
the same numbers for both commercial and industrial
grades.
If a particular Spartan-3E FPGA differs in functional
behavior or electrical characteristic from this data
sheet, those differences are described in a separate
errata document. The errata documents for Spartan-3E
FPGAs are living documents and are available online.
Table 1: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Max
Units
VCCINT
Internal supply voltage
–0.5
1.32
V
VCCAUX
Auxiliary supply voltage
–0.5
3.00
V
VCCO
Output driver supply voltage
–0.5
3.75
V
VREF
Input reference voltage
–0.5
VCCO + 0.5(3)
V
–0.5
+ 0.5(3)
V
VIN(2)
Voltage applied to all User I/O pins and
Dual-Purpose pins
Driver in a high-impedance state
Voltage applied to all Dedicated pins
VESD
Electrostatic Discharge Voltage
VCCO
–0.5
VCCAUX + 0.5(4)
V
Human body model
–2000
+2000
V
Charged device model
–500
+500
V
Machine model
–200
+200
V
TJ
Junction temperature
-
125
°C
TSTG
Storage temperature
–65
150
°C
Notes:
1.
2.
3.
4.
5.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not
implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
As a rule, the VIN limits apply to both the DC and AC components of signals. Simple application solutions are available that show how to
handle overshoot/undershoot as well as achieve PCI compliance. Refer to the following application notes: "Virtex™-II Pro and Spartan-3
3.3V PCI Reference Design" (XAPP653) and "Using 3.3V I/O Guidelines in a Virtex-II Pro Design" (XAPP659).
Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ VCCO rails. Meeting the VIN max limit ensures that the
internal diode junctions that exist between these pins and their associated VCCO rails do not turn on. Table 4 specifies the VCCO range used
to determine the max limit. When VCCO is at its maximum recommended operating level (3.45V), VIN max is 3.95V. The maximum voltage
that avoids oxide stress is VINX = 4.05V. As long as the VIN max specification is met, oxide stress is not possible.
All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures
that the internal diode junctions that exist between each of these pins and the VCCAUX rail do not turn on. Table 4 specifies the VCCAUX range
used to determine the max limit. When VCCAUX is at its maximum recommended operating level (2.625V), VIN max < 3.125V. As long as the
VIN max specification is met, oxide stress is not possible.
For soldering guidelines, see "Device Packaging and Thermal Characteristics" at www.xilinx.com/bvdocs/userguides/ug112.pdf. Also see
"Implementation and Solder Reflow Guidelines for Pb-Free Packages" at www.xilinx.com/bvdocs/appnotes/xapp427.pdf.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-3 (v1.0) March 1, 2005
Advance Product Specification
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DC and Switching Characteristics
Table 2: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.4
1.0
V
VCCAUXT
Threshold for the VCCAUX supply
0.8
2.0
V
VCCO2T
Threshold for the VCCO Bank 2 supply
0.4
1.0
V
Notes:
1.
2.
VCCINT, VCCAUX, and VCCO supplies may be applied in any order.
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 3: Power Voltage Levels Necessary for Preserving RAM Contents
Symbol
Description
Min
Units
VDRINT
VCCINT level required to retain RAM data
1.0
V
VDRAUX
VCCAUX level required to retain RAM data
2.0
V
VCCO level required to retain RAM data
1.0
V
VDRO
Notes:
1.
RAM contents include configuration data.
Table 4: General Recommended Operating Conditions
Symbol
TJ
Description
Junction temperature
Commercial
Industrial
Min
Nom
Max
Units
0
-
85
°C
–40
-
100
°C
VCCINT
Internal supply voltage
1.140
1.200
1.260
V
VCCO (1)
Output driver supply voltage
1.140
-
3.450
V
Auxiliary supply voltage
2.375
2.500
2.625
V
VCCAUX (2)
Notes:
1.
2.
2
The VCCO range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended VCCO range
specific to each of the single-ended I/O standards is given in Table 7, and that specific to the differential standards is given in Table 9.
Only during DCM operation, it is recommended that the rate of change of VCCAUX not exceed 10 mV/ms.
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DS312-3 (v1.0) March 1, 2005
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DC and Switching Characteristics
Table 5: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
Description
Test Conditions
Min
Typ
Max
Units
–10
-
+10
µA
IL(2)
Leakage current at User I/O,
Dual-Purpose, and Dedicated pins
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
IRPU(3)
Current through pull-up resistor at
User I/O, Dual-Purpose, and
Dedicated pins
VIN = 0V, VCCO = 3.3V
mA
VIN = 0V, VCCO = 3.0V
mA
VIN = 0V, VCCO = 2.5V
mA
VIN = 0V, VCCO = 1.8V
mA
VIN = 0V, VCCO = 1.5V
mA
VIN = 0V, VCCO = 1.2V
mA
VIN = VCCO
mA
IRPD(3)
Current through pull-down resistor at
User I/O, Dual-Purpose, and
Dedicated pins
IREF
VREF current per pin
CIN
Input capacitance
All VCCO levels
–10
-
+10
µA
3
-
10
pF
Notes:
1.
2.
3.
The numbers in this table are based on the conditions set forth in Table 4.
The IL specification applies to every I/O pin throughout power-on as long as the voltage on that pin stays between the absolute VIN minimum
and maximum values (Table 1). For hot-swap applications, at the time of card connection, be sure to keep all I/O voltages within this range
before applying VCCO power. Also consider applying VCCO power before the connection of data lines occurs. When the FPGA is completely
unpowered, the impedance at the I/O pins is high.
This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.
DS312-3 (v1.0) March 1, 2005
Advance Product Specification
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DC and Switching Characteristics
Table 6: Quiescent Supply Current Characteristics
Symbol
ICCINTQ
ICCOQ
ICCAUXQ
Description
Quiescent VCCINT supply current
Quiescent VCCO supply current
Quiescent VCCAUX supply current
Device
Typ(4)
Max
Units
XC3S100E
15
mA
XC3S250E
38
mA
XC3S500E
68
mA
XC3S1200E
98
mA
XC3S1600E
108
mA
XC3S100E
1.0
mA
XC3S250E
1.5
mA
XC3S500E
1.7
mA
XC3S1200E
1.8
mA
XC3S1600E
2.2
mA
XC3S100E
10
mA
XC3S250E
15
mA
XC3S500E
25
mA
XC3S1200E
35
mA
XC3S1600E
45
mA
Notes:
1.
2.
3.
4.
4
The numbers in this table are based on the conditions set forth in Table 4. Quiescent supply current is measured with all I/O drivers in a
high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. For typical values, the ambient temperature (TA) is
25°C with VCCINT = 1.2V, VCCO = 2.5V, and VCCAUX = 2.5V. The FPGA is programmed with a "blank" configuration data file (i.e., a design
with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements),
measured quiescent current levels may be higher than the values in the table.
There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
Spartan-3E Web Power Tool, a future web-based application, provides quick, approximate, typical estimates, and does not require a netlist
of the design. b) XPower, which will be included in a future release of the Xilinx development software, takes a netlist as input to provide
more accurate maximum and typical estimates.
The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
All typical quiescent current values are early estimates.
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DS312-3 (v1.0) March 1, 2005
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DC and Switching Characteristics
Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD
Attribute
VCCO for Drivers(2)
VREF
VIL
VIH
Min (V)
Nom (V)
Max (V)
Min (V)
Nom (V)
Max (V)
Max (V)
Min (V)
HSTL_I_18
1.7
1.8
1.9
0.8
0.9
1.1
VREF - 0.1
VREF + 0.1
HSTL_III_18
1.7
1.8
1.9
-
1.1
-
VREF - 0.1
VREF + 0.1
LVCMOS12(4)
1.1
1.2
1.3
-
-
-
0.38
0.8
LVCMOS15(4)
1.4
1.5
1.6
-
-
-
0.38
0.8
LVCMOS18(4)
1.65
1.8
1.95
-
-
-
0.38
0.8
LVCMOS25(4,5)
2.3
2.5
2.7
-
-
-
0.7
1.7
LVCMOS33(4)
3.0
3.3
3.45
-
-
-
0.8
2.0
LVTTL
3.0
3.3
3.45
-
-
-
0.8
2.0
PCI33_3(7)
-
3.0
-
-
-
-
0.9
1.5
PCI66_3(7)
-
3.0
-
-
-
-
0.9
1.5
PCIX(7)
-
TBD
-
-
-
-
TBD
TBD
SSTL18_I
1.70
1.80
1.90
0.833
0.900
0.969
VREF - 0.125
VREF + 0.125
SSTL2_I
2.3
2.5
2.7
1.15
1.25
1.35
VREF - 0.15
VREF + 0.15
Notes:
1.
Descriptions of the symbols used in this table are as follows:
VCCO -- the supply voltage for output drivers
VREF -- the reference voltage for setting the input switching threshold
VIL -- the input voltage that indicates a Low logic level
VIH -- the input voltage that indicates a High logic level
2.
3.
4.
5.
6.
7.
The VCCO rails supply only output drivers, not input circuits.
For device operation, the maximum signal voltage (VIH max) may be as high as VIN max. See Table 1.
There is approximately 100 mV of hysteresis on inputs using any LVCMOS standard.
All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the VCCAUX rail (2.5V).
The Dual-Purpose configuration pins use the LVCMOS25 standard before the User mode. When using these pins as part of a standard 2.5V
configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.
The Global Clock Inputs (GCLK0-GCLK15, RHCLK0-RHCLK7, and LHCLK0-LHCLK7) are Dual-Purpose pins to which any signal standard
may be assigned.
For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design" (XAPP653).
DS312-3 (v1.0) March 1, 2005
Advance Product Specification
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DC and Switching Characteristics
Table 8: DC Characteristics of User I/Os Using Single-Ended Standards
Test Conditions
IOL
IOH
VOL
VOH
(mA)
(mA)
Max (V)
Min (V)
HSTL_I_18
8
–8
0.4
VCCO - 0.4
HSTL_III_18
24
–8
0.4
VCCO - 0.4
IOSTANDARD Attribute
LVCMOS12(3)
2
2
–2
0.4
VCCO - 0.4
LVCMOS15(3)
2
2
–2
0.4
VCCO - 0.4
4
4
–4
6
6
–6
2
2
–2
0.4
VCCO - 0.4
4
4
–4
6
6
–6
8
8
–8
2
2
–2
0.4
VCCO - 0.4
4
4
–4
6
6
–6
8
8
–8
12
12
–12
2
2
–2
0.4
VCCO - 0.4
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16
16
–16
2
2
–2
0.4
2.4
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16
16
–16
PCI33_3(5)
1.5
–0.5
0.10VCCO
0.90VCCO
PCI66_3(5)
1.5
–0.5
0.10VCCO
0.90VCCO
TBD
TBD
TBD
TBD
6.7
–6.7
VTT - 0.475
VTT + 0.475
LVCMOS18(3)
LVCMOS25(3,4)
LVCMOS33(3)
LVTTL(3)
PCIX
SSTL18_I
6
Logic Level Characteristics
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DC and Switching Characteristics
Table 8: DC Characteristics of User I/Os Using Single-Ended Standards (Continued)
Test Conditions
IOSTANDARD Attribute
SSTL2_I
Logic Level Characteristics
IOL
IOH
VOL
VOH
(mA)
(mA)
Max (V)
Min (V)
8.1
–8.1
VTT - 0.61
VTT + 0.61
Notes:
1.
2.
The numbers in this table are based on the conditions set forth in Table 4 and Table 7.
Descriptions of the symbols used in this table are as follows:
IOL -- the output current condition under which VOL is tested
IOH -- the output current condition under which VOH is tested
VOL -- the output voltage that indicates a Low logic level
VOH -- the output voltage that indicates a High logic level
VIL -- the input voltage that indicates a Low logic level
VIH -- the input voltage that indicates a High logic level
VCCO -- the supply voltage for output drivers
VREF -- the reference voltage for setting the input switching threshold
VTT -- the voltage applied to a resistor termination
3.
4.
5.
For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes.
All Dedicated output pins (DONE and TDO) as well as Dual-Purpose totem-pole output pins (CCLK, D0-D7, BUSY/DOUT, CSO_B, MOSI,
HDC, LDC0-LDC2, and A0-A23) exhibit the characteristics of LVCMOS25 with Slow slew rate; all have 8 mA drive except CCLK, which has
12 mA drive.
Tested according to the relevant PCI specifications. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design"
(XAPP653).
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DC and Switching Characteristics
VINP
Internal
Logic
VINN
VINN
VID
50%
VINP
Differential
I/O Pair Pins
P
N
VICM
GND level
VICM = Input common mode voltage =
VINP + VINN
2
VID = Differential input voltage = VINP - VINN
DS099-3_01_012304
Figure 1: Differential Input Voltages
Table 9: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
VCCO for Drivers(1)
IOSTANDARD
Attribute
VID
VICM
VIH
VIL
Min
(V)
Nom
(V)
Max
(V)
Min
(mV)
Nom
(mV)
Max
(mV)
Min
(V)
Nom
(V)
Max
(V)
Min
(V)
Max
(V)
Min
(V)
Max
(V)
LVDS_25
2.375
2.50
2.625
100
350
600
0.30
1.25
2.20
-
-
-
-
BLVDS_25
2.375
2.50
2.625
100
350
600
0.30
1.25
2.20
-
-
-
-
MINI_LVDS_25
2.375
2.50
2.625
200
-
600
0.30
-
2.2
100
800
1000
0.3
1.2
2.2
0.8
2.0
0.5
1.7
100
200
-
0.3
1.20
1.4
-
-
-
-
LVPECL_25(2)
RSDS_25
Inputs Only
2.375
2.50
2.625
Notes:
1.
2.
3.
8
The VCCO rails supply only differential output drivers, not input circuits.
Spartan-3E devices support this standard for inputs only, not for outputs.
VREF inputs are not used for any of the differential I/O standards.
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DC and Switching Characteristics
VOUTP
Internal
Logic
P
N
VOUTN
Differential
I/O Pair Pins
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
VOUTP + VOUTN
VOCM = Output common mode voltage =
2
VOD = Output differential voltage = VOUTP - VOUTN
VOH = Output voltage indicating a High logic level
VOL = Output voltage indicating a Low logic level
DS312-3_03_021505
Figure 2: Differential Output Voltages
Table 10: DC Characteristics of User I/Os Using Differential Signal Standards
∆VOD
VOD
IOSTANDARD
Attribute
∆VOCM
VOCM
Min
(mV)
Typ
(mV)
Max
(mV)
Min
(mV)
Max
(mV)
Min
(V)
LVDS_25
250
350
450
-
-
1.125
-
BLVDS_25
250
350
450
-
-
-
MINI_LVDS_25
300
-
600
-
50
RSDS_25
100
-
400
-
-
VOH
VOL
Min
(mV)
Max
(mV)
Min
(V)
Max
(V)
1.375
-
-
1.25
1.25
1.20
-
-
-
-
-
1.0
-
1.4
-
50
1.15
1.25
1.1
-
1.4
-
-
1.15
1.35
Typ (V) Max (V)
Notes:
1.
2.
3.
The numbers in this table are based on the conditions set forth in Table 4 and Table 9.
Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the
differential signal pair.
At any given time, no more than two differential standards may be assigned to each bank.
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DC and Switching Characteristics
Switching Characteristics
All Spartan-3E FPGAs ship in two speed grades: –4 and the
higher performance –5. Switching characteristics in this
document may be designated as Advance, Preliminary, or
Production, as shown in Table 11. Each category is defined
as follows:
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this designation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production
before faster speed grades.
Production-quality systems must use FPGA designs compiled using a speed file designated as Production status.
FPGAs designs using a less mature speed file designation
should only be used during system prototyping or pre-production qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be
used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, Xilinx recommends
rerunning the Xilinx ISE software on the FPGA design. This
ensures that the FPGA design incorporates the latest timing
information and software updates.
All specified limits are representative of worst-case supply
voltage and junction temperature conditions. Unless otherwise noted, the following applies: Parameter values apply to
all Spartan-3E devices. All parameters representing voltages are measured with respect to GND.
Timing parameters and their representative values are
selected for inclusion below either because they are important as general design requirements or they indicate fundamental device performance characteristics. The Spartan-3E
speed files (v1.10), part of the Xilinx Development Software,
are the original source for many but not all of the values.
The speed grade designations for these files are shown in
Table 11. For more complete, more precise, and worst-case
10
data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and
back-annotated to the simulation netlist.
Table 11: Spartan-3E v1.10 Speed Grade Designations
Device
Preview
XC3S100E
–4
XC3S250E
–4
XC3S500E
–4
XC3S1200E
–4
XC3S1600E
–4
System
Usage
Advance
Preliminary
Prototyping Only
Production
Production
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables (Table 12 and Table 13) apply to any application that
only employs the DLL component. When the DFS and/or
the PS components are used together with the DLL, then
the specifications listed in the DFS and PS tables supersede any corresponding ones in the DLL tables. (See
Table 14 and Table 15 for the DFS; tables for the PS are not
yet available.) DLL specifications that do not change with
the addition of DFS or PS functions are presented in
Table 12 and Table 13.
All DCM clock output signals exhibit an approximate duty
cycle of 50%.
Period jitter and cycle-cycle jitter are two (of many) different
ways of characterizing clock jitter. Both specifications
describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average
clock period of all clock cycles in the collection of clock periods sampled (usually from 100,000 to more than a million
samples for specification purposes). In a histogram of
period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean
value is zero.
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Table 12: Recommended Operating Conditions for the DLL
Speed Grade
-5
Symbol
Description
-4
Min
Max
Min
Max
Units
5
326
5(2)
280
MHz
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency for the CLKIN input
Notes:
1.
2.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
Use of the DFS permits lower FCLKIN frequencies. See Table 14.
Table 13: Switching Characteristics for the DLL
Speed Grade
-5
Symbol
Description
-4
Min
Max
Min
Max
Units
Frequency for the CLK0 and CLK180 outputs
5
326
5
280
MHz
Frequency for the CLK90 and CLK270 outputs
5
165
5
165
MHz
Frequency for the CLK2X and CLK2X180
outputs
10
400
10
330
MHz
Output Frequency Ranges
CLKOUT_FREQ_1X
CLKOUT_FREQ_2X
Notes:
1.
2.
The numbers in this table are based on the operating conditions set forth in Table 4 and Table 12.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
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DC and Switching Characteristics
Table 14: Recommended Operating Conditions for the DFS
Speed Grade
-5
Symbol
Description
-4
Min
Max
Min
Max
Units
0.2
326
0.2
326
MHz
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
Notes:
1.
2.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are in use.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 12.
Table 15: Switching Characteristics for the DFS
Speed Grade
-5
Symbol
Output Frequency Ranges
CLKOUT_FREQ_FX
-4
Description
Min
Max
Min
Max
Units
Frequency for the CLKFX and CLKFX180 outputs
5
326
5
280
MHz
Notes:
1.
2.
12
The numbers in this table are based on the operating conditions set forth in Table 4 and Table 14.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.
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Configuration and JTAG Timing
1.2V
VCCINT
(Supply)
1.0V
VCCAUX
(Supply)
2.0V
VCCO Bank 2
(Supply)
1.0V
2.5V
TPOR
PROG_B
(Input)
TPROG
INIT_B
(Open-Drain)
TPL
TICCK
CCLK
(Output)
DS312-3_01_020505
Notes:
1.
2.
3.
The VCCINT, VCCAUX, and VCCO supplies may be applied in any order.
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 3: Waveforms for Power-On and the Beginning of Configuration
Table 16: Power-On Timing and the Beginning of Configuration
All Speed Grades
Symbol
TPOR(2)
Description
Device
The time from the application of VCCINT, VCCAUX, and VCCO
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
Min
Max
Units
XC3S100E
-
5
ms
XC3S250E
-
5
ms
XC3S500E
-
5
ms
XC3S1200E
-
5
ms
XC3S1600E
TPROG
TPL
(2)
-
7
ms
0.3
-
µs
XC3S100E
-
2
ms
XC3S250E
-
2
ms
XC3S500E
-
2
ms
XC3S1200E
-
2
ms
-
3
ms
0.5
4.0
µs
The width of the low-going pulse on the PROG_B pin
All
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S1600E
TICCK(3)
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All
Notes:
1.
2.
3.
The numbers in this table are based on the operating conditions set forth in Table 4. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
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R
DC and Switching Characteristics
PROG_B
(Input)
INIT_B
(Open-Drain)
TCCL
TCCH
CCLK
(Input/Output)
TDCC
DIN
(Input)
1/FCCSER
TCCD
Bit 0
Bit 1
Bit n+1
Bit n
TCCO
DOUT
(Output)
Bit n-64
Bit n-63
DS099-3_04_071604
Figure 4: Waveforms for Master and Slave Serial Configuration
Table 17: Timing for the Master and Slave Serial Configuration Modes
Symbol
Slave/
Master
Description
All Speed Grades
Min
Max
Units
Both
1.5
12.0
ns
Both
10.0
-
ns
Both
0
-
ns
Slave
5.0
-
ns
5.0
-
ns
No bitstream compression
-
66(2)
MHz
With bitstream compression
-
20
MHz
–50%
+50%
-
Clock-to-Output Times
TCCO
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
Setup Times
TDCC
The time from the setup of data at the DIN pin to the rising transition
at the CCLK pin
Hold Times
TCCD
The time from the rising transition at the CCLK pin to the point when
data is last held at the DIN pin
Clock Timing
TCCH
The High pulse width at the CCLK input pin
TCCL
The Low pulse width at the CCLK input pin
FCCSER
Frequency of the clock signal at
the CCLK input pin
∆FCCSER
Variation from the CCLK output frequency set using the ConfigRate
BitGen option
Master
Notes:
1.
2.
14
The numbers in this table are based on the operating conditions set forth in Table 4.
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
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DC and Switching Characteristics
PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC
TSMCCCS
CS_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TCCH
TCCL
CCLK
(Input)
TSMDCC
D0 - D7
(Inputs)
1/FCCPAR
TSMCCD
Byte 0
Byte 1
Byte n
TSMCKBY
Byte n+1
TSMCKBY
High-Z
BUSY
(Output)
High-Z
BUSY
DS312-3_02_020805
Notes:
1.
It is possible to abort configuration by pulling CS_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CS_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 5: Waveforms for Slave Parallel Configuration
Table 18: Timing for the Slave Parallel Configuration Mode
All Speed Grades
Symbol
Description
Min
Max
Units
The time from the rising transition on the CCLK pin to a signal transition at the
BUSY pin
-
12.0
ns
TSMDCC
The time from the setup of data at the D0-D7 pins to the rising transition at the
CCLK pin
10.0
-
ns
TSMCSCC
The time from the setup of a logic level at the CS_B pin to the rising transition
at the CCLK pin
10.0
-
ns
TSMCCW(2)
The time from the setup of a logic level at the RDWR_B pin to the rising
transition at the CCLK pin
10.0
-
ns
Clock-to-Output Times
TSMCKBY
Setup Times
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DC and Switching Characteristics
Table 18: Timing for the Slave Parallel Configuration Mode (Continued)
All Speed Grades
Symbol
Description
Min
Max
Units
Hold Times
TSMCCD
The time from the rising transition at the CCLK pin to the point when data is
last held at the D0-D7 pins
0
-
ns
TSMCCCS
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the CS_B pin
0
-
ns
TSMWCC
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the RDWR_B pin
0
-
ns
TCCH
The High pulse width at the CCLK input pin
5
-
ns
TCCL
The Low pulse width at the CCLK input pin
5
-
ns
FCCPAR
Frequency of the clock
signal at the CCLK input
pin
Not using the BUSY pin(2)
-
50
MHz
Using the BUSY pin
-
66
MHz
-
20
MHz
Clock Timing
No bitstream
compression
With bitstream compression
Notes:
1.
2.
3.
16
The numbers in this table are based on the operating conditions set forth in Table 4.
In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
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TCCH
TCCL
TCK
(Input)
1/FTCK
TTCKTMS
TTMSTCK
TMS
(Input)
TTDITCK
TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS099_06_040703
Figure 6: JTAG Waveforms
Table 19: Timing for the JTAG Test Access Port
All Speed Grades
Symbol
Description
Min
Max
Units
The time from the falling transition on the TCK pin
to data appearing at the TDO pin
1.0
11.0
ns
TTDITCK
The time from the setup of data at the TDI pin to
the rising transition at the TCK pin
7.0
-
ns
TTMSTCK
The time from the setup of a logic level at the TMS
pin to the rising transition at the TCK pin
7.0
-
ns
TTCKTDI
The time from the rising transition at the TCK pin
to the point when data is last held at the TDI pin
0
-
ns
TTCKTMS
The time from the rising transition at the TCK pin
to the point when a logic level is last held at the
TMS pin
0
-
ns
TCCH
The High pulse width at the TCK pin
5
-
ns
TCCL
The Low pulse width at the TCK pin
5
-
ns
FTCK
Frequency of the TCK signal
-
33
MHz
Clock-to-Output Times
TTCKTDO
Setup Times
Hold Times
Clock Timing
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 4.
DS312-3 (v1.0) March 1, 2005
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DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
Version
03/01/05
1.0
Revision
Initial Xilinx release.
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1)
DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2)
DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3)
DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
18
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Spartan-3E FPGA Family:
Pinout Descriptions
R
DS312-4 (v1.1) March 21, 2005
0
0
Advance Product Specification
Introduction
Pin Types
This section describes the various pins on a Spartan™-3E
FPGA and how they connect within the supported component packages.
A majority of the pins on a Spartan-3E FPGA are general-purpose, user-defined I/O pins. There are, however, up
to 11 different functional types of pins on Spartan-3E packages, as outlined in Table 1. In the package footprint drawings that follow, the individual pins are color-coded
according to pin type as in the table.
Table 1: Types of Pins on Spartan-3E FPGAs
Type /
Color Code
Description
Pin Name(s) in Type
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to
form differential I/Os.
IO
IO_Lxxy_#
INPUT
Unrestricted, general-purpose input-only pin. This pin does not have an output
structure.
IP
IP_Lxxy_#
DUAL
Dual-purpose pin used in some configuration modes during the configuration
process and then usually available as a user I/O after configuration. If the pin is
not used during configuration, this pin behaves as an I/O-type pin. Some of the
dual-purpose pins are also global or edge clock inputs (GCLK).
M[2:0]
HSWAP
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
BUSY/DOUT
INIT_B
A[23:20]
A19/VS2
A18/VS1
A17/VS0
A[16:0]
LDC[2:0]
HDC
VREF
Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins
in the same bank, provides a reference voltage input for certain I/O standards.
If used for a reference voltage within a bank, all VREF pins within the bank must
be connected.
IP/VREF_#
IP_Lxx_#/VREF_#
GCLK
LHCLK
RHCLK
Either a user-I/O pin or an input to a specific clock buffer driver. Every package
has 16 global clock inputs that optionally clock the entire device. The RHCLK
inputs optionally clock the right-hand side of the device. The LHCLK inputs
optionally clock the left-hand side of the device. Some of the clock pins are
shared with the dual-purpose configuration pins and are considered DUAL-type.
GCLK[15:0],
LHCLK[7:0],
RHCLK[7:0]
CONFIG
Dedicated configuration pin. Not available as a user-I/O pin. Every package has
two dedicated configuration pins. These pins are powered by VCCAUX.
DONE, PROG_B
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All other trademarks are the property of their respective owners.
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Pinout Descriptions
Table 1: Types of Pins on Spartan-3E FPGAs
Type /
Color Code
Description
Pin Name(s) in Type
JTAG
Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four
dedicated JTAG pins. These pins are powered by VCCAUX.
TDI, TMS, TCK, TDO
GND
Dedicated ground pin. The number of GND pins depends on the package used.
All must be connected.
GND
VCCAUX
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on
the package used. All must be connected to +2.5V.
VCCAUX
VCCINT
Dedicated internal core logic power supply pin. The number of VCCINT pins
depends on the package used. All must be connected to +1.2V.
VCCINT
VCCO
Along with all the other VCCO pins in the same bank, this pin supplies power to
the output buffers within the I/O bank and sets the input threshold voltage for
some I/O standards.
VCCO_#
N.C.
This package pin is not connected in this specific device/package combination
but may be connected in larger devices in the same package.
N.C.
Notes:
1.
# = I/O bank number, an integer between 0 and 3.
I/Os with Lxxy_# are part of a differential output pair. ‘L’ indicates differential output capability. The “xx” field is a
two-digit integer, unique to each bank that identifies a differential pin-pair. The ‘y’ field is either ‘P’ for the true signal or
‘N’ for the inverted signal in the differential pair. The ‘#’ field
is the I/O bank number.
significance. Figure 1 provides a specific example showing
a differential input to and a differential output from Bank 1.
‘L’ indicates that the pin is part of a differentiaL pair.
"xx" is a two-digit integer, unique for each bank, that
identifies a differential pin-pair.
‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the
inverted. These two pins form one differential pin-pair.
Differential Pair Labeling
A pin supports differential standards if the pin is labeled in
the format “Lxxy_#”. The pin name suffix has the following
‘#’ is an integer, 0 through 3, indicating the associated
I/O bank.
Pair Number
Bank 0
Bank Number
Spartan-3E
FPGA
IO_L38N_1
Bank 1
Bank 3
IO_L38P_1
Positive Polarity,
True Driver
IO_L39P_1
IO_L39N_1
Bank 2
Negative Polarity,
Inverted Driver
DS312-4_00_022305
Figure 1: Differential Pair Labeling
2
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Pinout Descriptions
Package Overview
Table 2 shows the eight low-cost, space-saving production
package styles for the Spartan-3E family. Each package
style is available as a standard and an environmentally-friendly lead-free (Pb-free) option. The Pb-free packages include an extra ‘G’ in the package style name. For
example, the standard "VQ100" package becomes
"VQG100" when ordered as the Pb-free option. The
mechanical dimensions of the standard and Pb-free packages are similar, as shown in the mechanical drawings provided in Table 4.
Not all Spartan-3E densities are available in all packages.
For a specific package, however, there is a common footprint that supports all the devices available in that package.
See the footprint diagrams that follow.
Table 2: Spartan-3E Family Package Options
Maximum
I/O
Pitch
(mm)
Area (mm)
Height
(mm)
Very-thin Quad Flat Pack (VQFP)
66
0.5
16 x 16
1.20
132
Chip-Scale Package (CSP)
92
0.5
8x8
1.10
TQ144 / TQG144
144
Thin Quad Flat Pack (TQFP)
108
0.5
22 x 22
1.60
PQ208 / PQG208
208
Plastic Quad Flat Pack (PQFP)
158
0.5
30.6 x 30.6
4.10
FT256 / FTG256
256
Fine-pitch, Thin Ball Grid Array (FBGA)
190
1.0
17 x 17
1.55
FG320 / FGG320
320
Fine-pitch Ball Grid Array (FBGA)
250
1.0
19 x 19
2.00
FG400 / FGG400
400
Fine-pitch Ball Grid Array (FBGA)
304
1.0
21 x 21
2.60
FG484 / FGG484
484
Fine-pitch Ball Grid Array (FBGA)
376
1.0
23 x 23
2.60
Package
Leads
VQ100 / VQG100
100
CP132 / CPG132
Type
Selecting the Right Package Option
Spartan-3 FPGAs are available in both quad-flat pack
(QFP) and ball grid array (BGA) packaging options. While
QFP packaging offers the lowest absolute cost, the BGA
packages are superior in almost every other aspect, as
summarized in Table 3. Consequently, Xilinx recommends
using BGA packaging whenever possible.
Table 3: QFP and BGA Comparison
Characteristic
Quad Flat Pack (QFP)
Ball Grid Array (BGA)
158
376
Good
Better
Fair
Better
Limited
Better
Fair
Better
4
6
Possible
Difficult
Maximum User I/O
Packing Density (Logic/Area)
Signal Integrity
Simultaneous Switching Output (SSO) Support
Thermal Dissipation
Minimum Printed Circuit Board (PCB) Layers
Hand Assembly/Rework
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Pinout Descriptions
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx website at the specified location in
Table 4.
Table 4: Xilinx Package Mechanical Drawings
Package
Web Link (URL)
VQ100 / VQG100
http://www.xilinx.com/bvdocs/packages/vq100.pdf
CP132 / CPG132
http://www.xilinx.com/bvdocs/packages/cp132.pdf
TQ144 / TQG144
http://www.xilinx.com/bvdocs/packages/tq144.pdf
PQ208 / PQG208
http://www.xilinx.com/bvdocs/packages/pq208.pdf
FT256 / FTG256
http://www.xilinx.com/bvdocs/packages/ft256.pdf
FG320 / FGG320
http://www.xilinx.com/bvdocs/packages/fg320.pdf
FG400 / FGG400
http://www.xilinx.com/bvdocs/packages/fg400.pdf
FG484 / FGG484
http://www.xilinx.com/bvdocs/packages/fg484.pdf
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in Table 5.
Table 5: Power and Ground Supply Pins by Package
Package
4
VCCINT
VCCAUX
VCCO
GND
VQ100
4
4
8
12
CP132
6
4
8
16
TQ144
4
4
9
13
PQ208
4
8
12
20
FT256
8
8
16
28
FG320
8
8
20
28
FG400
16
8
24
42
FG484
16
10
28
48
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in Table 6. The table shows the maximum number of single-ended I/O pins available, assuming
that all I/O-, INPUT-, DUAL-, VREF-, and GCLK-type pins
are used as general-purpose I/O. Likewise, the table shows
the maximum number of differential pin-pairs available on
the package. Finally, the table shows how the total maximum user-I/Os are distributed by pin type, including the
number of unconnected—i.e., N.C.—pins on the device.
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Pinout Descriptions
Table 6: Maximum User I/O by Package
Maximum
User I/Os
Maximum
Differential
Pairs
I/O
INPUT
DUAL
VREF
GCLK
N.C.
66
30
16
1
21
4
24
0
66
30
16
1
21
4
24
0
92
41
22
0
46
8
16
0
92
41
22
0
46
8
16
0
108
40
22
19
42
9
16
0
108
40
20
21
42
9
16
0
158
65
58
25
46
13
16
0
XC3S500E
158
65
58
25
46
13
16
0
XC3S250E
172
68
62
33
46
15
16
16
190
77
76
33
46
19
16
0
XC3S1200E
190
77
78
31
46
19
16
0
XC3S500E
232
92
102
48
46
20
16
18
250
99
120
47
46
21
16
0
250
99
119
48
46
21
16
0
304
124
156
62
46
24
16
0
304
124
156
62
46
24
16
0
376
156
214
72
46
28
16
0
Device
Package
XC3S100E
All Possible I/Os by Type
VQ100
XC3S250E
XC3S250E
CP132
XC3S500E
XC3S100E
TQ144
XC3S250E
XC3S250E
PQ208
XC3S500E
XC3S1200E
FT256
FG320
XC3S1600E
XC3S1200E
FG400
XC3S1600E
XC3S1600E
FG484
Electronic versions of the package pinout tables and footprints are available for download from the Xilinx web site.
Download the files from the following location: Using a
spreadsheet program, the data can be sorted and reformat-
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
ted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
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Pinout Descriptions
VQ100: 100-lead Very-thin Quad Flat
Package
The XC3S100E and the XC3S250E devices are available in
the 100-lead very-thin quad flat package, VQ100. Both
devices share a common footprint for this package as
shown in Table 7 and Figure 2.
Table 7: VQ100 Package Pinout
XC3S100E
XC3S250E
Pin Name
Bank
VQ100
Pin
Number
Type
0
VCCO_0
P97
VCCO
1
IO_L01N_1
P54
I/O
1
IO_L01P_1
P53
I/O
1
IO_L02N_1
P58
I/O
1
IO_L02P_1
P57
I/O
The VQ100 package does not support the Byte-wide
Peripheral Interface (BPI) configuration mode. Consequently, the VQ100 footprint has fewer DUAL-type pins than
other packages.
1
IO_L03N_1/RHCLK1
P61
RHCLK
1
IO_L03P_1/RHCLK0
P60
RHCLK
1
IO_L04N_1/RHCLK3
P63
RHCLK
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
1
IO_L04P_1/RHCLK2
P62
RHCLK
1
IO_L05N_1/RHCLK5
P66
RHCLK
1
IO_L05P_1/RHCLK4
P65
RHCLK
Table 7 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
Pinout Table
1
IO_L06N_1/RHCLK7
P68
RHCLK
Table 7 shows the pinout for production Spartan-3E FPGAs
in the VQ100 package. The XC3S100 engineering samples
have a slightly different pinout, as described in Table 9.
1
IO_L06P_1/RHCLK6
P67
RHCLK
1
IO_L07N_1
P71
I/O
Table 7: VQ100 Package Pinout
1
IO_L07P_1
P70
I/O
1
IP/VREF_1
P69
VREF
1
VCCO_1
P55
VCCO
1
VCCO_1
P73
VCCO
2
IO/D5
P34
DUAL
2
IO/M1
P42
DUAL
2
IO_L01N_2/INIT_B
P25
DUAL
2
IO_L01P_2/CSO_B
P24
DUAL
2
IO_L02N_2/MOSI/CSI_B
P27
DUAL
2
IO_L02P_2/DOUT/BUSY
P26
DUAL
2
IO_L03N_2/D6/GCLK13
P33
DUAL/GCLK
2
IO_L03P_2/D7/GCLK12
P32
DUAL/GCLK
2
IO_L04N_2/D3/GCLK15
P36
DUAL/GCLK
2
IO_L04P_2/D4/GCLK14
P35
DUAL/GCLK
2
IO_L06N_2/D1/GCLK3
P41
DUAL/GCLK
2
IO_L06P_2/D2/GCLK2
P40
DUAL/GCLK
2
IO_L07N_2/DIN/D0
P44
DUAL
2
IO_L07P_2/M0
P43
DUAL
2
IO_L08N_2/VS1
P48
DUAL
2
IO_L08P_2/VS2
P47
DUAL
XC3S100E
XC3S250E
Pin Name
Bank
6
VQ100
Pin
Number
Type
0
IO
P92
I/O
0
IO_L01N_0
P79
I/O
0
IO_L01P_0
P78
I/O
0
IO_L02N_0/GCLK5
P84
GCLK
0
IO_L02P_0/GCLK4
P83
GCLK
0
IO_L03N_0/GCLK7
P86
GCLK
0
IO_L03P_0/GCLK6
P85
GCLK
0
IO_L05N_0/GCLK11
P91
GCLK
0
IO_L05P_0/GCLK10
P90
GCLK
0
IO_L06N_0/VREF_0
P95
VREF
0
IO_L06P_0
P94
I/O
0
IO_L07N_0/HSWAP
P99
DUAL
0
IO_L07P_0
P98
I/O
0
IP_L04N_0/GCLK9
P89
GCLK
0
IP_L04P_0/GCLK8
P88
GCLK
0
VCCO_0
P82
VCCO
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Table 7: VQ100 Package Pinout
XC3S100E
XC3S250E
Pin Name
Bank
Table 7: VQ100 Package Pinout
VQ100
Pin
Number
Type
Bank
XC3S100E
XC3S250E
Pin Name
VQ100
Pin
Number
Type
2
IO_L09N_2/CCLK
P50
DUAL
GND
GND
P87
GND
2
IO_L09P_2/VS0
P49
DUAL
GND
GND
P93
GND
2
IP/VREF_2
P30
VREF
VCCAUX DONE
P51
CONFIG
2
IP_L05N_2/M2/GCLK1
P39
DUAL/GCLK
VCCAUX PROG_B
P1
CONFIG
2
IP_L05P_2/RDWR_B/
GCLK0
P38
DUAL/GCLK
VCCAUX TCK
P77
JTAG
VCCAUX TDI
P100
JTAG
2
VCCO_2
P31
VCCO
VCCAUX TDO
P76
JTAG
2
VCCO_2
P45
VCCO
VCCAUX TMS
P75
JTAG
3
IO_L01N_3
P3
I/O
VCCAUX VCCAUX
P21
VCCAUX
3
IO_L01P_3
P2
I/O
VCCAUX VCCAUX
P46
VCCAUX
3
IO_L02N_3/VREF_3
P5
VREF
VCCAUX VCCAUX
P74
VCCAUX
3
IO_L02P_3
P4
I/O
VCCAUX VCCAUX
P96
VCCAUX
3
IO_L03N_3/LHCLK1
P10
LHCLK
VCCINT
VCCINT
P6
VCCINT
3
IO_L03P_3/LHCLK0
P9
LHCLK
VCCINT
VCCINT
P28
VCCINT
3
IO_L04N_3/LHCLK3
P12
LHCLK
VCCINT
VCCINT
P56
VCCINT
3
IO_L04P_3/LHCLK2
P11
LHCLK
VCCINT
VCCINT
P80
VCCINT
3
IO_L05N_3/LHCLK5
P16
LHCLK
3
IO_L05P_3/LHCLK4
P15
LHCLK
3
IO_L06N_3/LHCLK7
P18
LHCLK
3
IO_L06P_3/LHCLK6
P17
LHCLK
3
IO_L07N_3
P23
I/O
3
IO_L07P_3
P22
I/O
3
IP
P13
INPUT
3
VCCO_3
P8
VCCO
3
VCCO_3
P20
VCCO
GND
GND
P7
GND
GND
GND
P14
GND
GND
GND
P19
GND
GND
GND
P29
GND
GND
GND
P37
GND
GND
GND
P52
GND
GND
GND
P59
GND
GND
GND
P64
GND
GND
GND
P72
GND
GND
GND
P81
GND
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Pinout Descriptions
User I/Os by Bank
Table 8 indicates how the 66 available user-I/O pins are distributed between the four I/O banks on the VQ100 package.
Table 8: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
15
5
0
1
1
8
Right
1
15
6
0
0
1
8
Bottom
2
19
0
0
18
1
0
Left
3
17
5
1
2
1
8
66
16
1
21
4
24
TOTAL
Footprint Migration Differences
The production XC3S100E and XC3S250E FPGAs have
identical footprints in the VQ100 package. Designs can
migrate between the XC3S100E and XC3S250E without
further consideration.
The pinout changed slightly between the XC3S100E engineering samples and the production devices, as shown in
Table 9. In the engineering samples, the mode select pins
M1 and M0 overlap with two global clock inputs feeding the
bottom-edge global buffers and DCMs. In the production
devices, the mode pins are swapped with parallel mode
data pins, D1 and D2. This way, these two mode pins do not
interfere with global clock inputs.
8
Table 9: XC3S100E Pinout Changes between
Production Devices and Engineering Samples
VQ100 Pin
XC3S100E
Production
Devices
XC3S100E
Engineering
Samples
P40
D2/GCLK2
M1/GCLK2
P41
D1/GCLK3
M0/GCLK3
P42
M1
D2
P43
M0
D1
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VQ100 Footprint
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TDI
IO_L07N_0/HSWAP
IO_L07P_0
VCCO_0
VCCAUX
IO_L06N_0/VREF_0
IO_L06P_0
GND
IO
IO_L05N_0/GCLK11
IO_L05P_0/GCLK10
IP_L04N_0/GCLK9
IP_L04P_0/GCLK8
GND
IO_L03N_0/GCLK7
IO_L03P_0/GCLK6
IO_L02N_0/GCLK5
IO_L02P_0/GCLK4
VCCO_0
GND
VCCINT
IO_L01N_0
IO_L01P_0
TCK
TDO
In Figure 2, note pin 1 indicator in top-left corner and logo
orientation. The engineering sample footprint is slightly different.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IO_L01P_2/CSO_B
IO_L01N_2/INIT_B
24
25
Bank 1
IO_L01N_3
IO_L02P_3
IO_L02N_3/VREF_3
VCCINT
GND
VCCO_3
IO_L03P_3/LHCLK0
IO_L03N_3/LHCLK1
IO_L04P_3/LHCLK2
IO_L04N_3/LHCLK3
IP
GND
IO_L05P_3/LHCLK4
IO_L05N_3/LHCLK5
IO_L06P_3/LHCLK6
IO_L06N_3/LHCLK7
GND
VCCO_3
VCCAUX
IO_L07P_3
IO_L07N_3
Bank 0
Bank 3
1
2
Bank 2
75
74
TMS
VCCAUX
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VCCO_1
GND
IO_L07N_1
IO_L07P_1
IP/VREF_1
IO_L06N_1/RHCLK7
IO_L06P_1/RHCLK6
IO_L05N_1/RHCLK5
IO_L05P_1/RHCLK4
GND
IO_L04N_1/RHCLK3
IO_L04P_1/RHCLK2
IO_L03N_1/RHCLK1
IO_L03P_1/RHCLK0
GND
IO_L02N_1
IO_L02P_1
VCCINT
VCCO_1
IO_L01N_1
IO_L01P_1
52
51
GND
DONE
IO_L02P_2/DOUT/BUSY
IO_L02N_2/MOSI/CSI_B
VCCINT
GND
IP/VREF_2
VCCO_2
IO_L03P_2/D7/GCLK12
IO_L03N_2/D6/GCLK13
IO/D5
IO_L04P_2/D4/GCLK14
IO_L04N_2/D3/GCLK15
GND
IP_L05P_2/RDWR_B/GCLK0
IP_L05N_2/M2/GCLK1
IO_L06P_2/D2/GCLK2
IO_L06N_2/D1/GCLK3
IO/M1
IO_L07P_2/M0
IO_L07N_2/DIN/D0
VCCO_2
VCCAUX
IO_L08P_2/VS2
IO_L08N_2/VS1
IO_L09P_2/VS0
IO_L09N_2/CCLK
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PROG_B
IO_L01P_3
DS312-4_02_030705
Figure 2: VQ100 Package Production Footprint (top view). Engineering Samples have slightly different footprint.
16
I/O: Unrestricted,
general-purpose user I/O
21
DUAL: Configuration pin, then
possible user-I/O
4
VREF: User I/O or input
voltage reference for bank
1
INPUT: Unrestricted,
general-purpose input pin
24
GCLK: User I/O, input, or
global buffer input
8
VCCO: Output voltage supply
for bank
2
CONFIG: Dedicated
configuration pins
4
JTAG: Dedicated JTAG port
pins
4
VCCINT: Internal core supply
voltage (+1.2V)
0
N.C.: Not connected
12
GND: Ground
4
VCCAUX: Auxiliary supply
voltage (+2.5V)
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Pinout Descriptions
CP132: 132-ball Chip-scale Package
The XC3S250E and the XC3S500E FPGAs are available in
the 132-lead chip-scale package, CP132. Both devices
share a common footprint for this package as shown in
Table 10 and Figure 3.
Table 10 lists all the CP132 package pins. They are sorted
by bank number and then by pin name. Pins that form a differential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
Physically, the D14 and K2 balls on the XC3S250E FPGA
are not connected but should be connected to VCCINT to
maintain density migration compatibility.
Table 10: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
Bank
CP132
Ball
Type
0
IP_L06N_0/GCLK9
C8
GCLK
0
IP_L06P_0/GCLK8
B8
GCLK
0
VCCO_0
A6
VCCO
0
VCCO_0
B10
VCCO
1
IO/A0
F12
DUAL
1
IO/VREF_1
K13
VREF
1
IO_L01N_1/A15
N14
DUAL
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
1
IO_L01P_1/A16
N13
DUAL
1
IO_L02N_1/A13
M13
DUAL
Pinout Table
1
IO_L02P_1/A14
M12
DUAL
1
IO_L03N_1/A11
L14
DUAL
1
IO_L03P_1/A12
L13
DUAL
1
IO_L04N_1/A9/RHCLK1
J12
RHCLK/
DUAL
1
IO_L04P_1/A10/RHCLK0
K14
RHCLK/
DUAL
1
IO_L05N_1/A7/RHCLK3/
TRDY1
J14
RHCLK/
DUAL
1
IO_L05P_1/A8/RHCLK2
J13
RHCLK/
DUAL
1
IO_L06N_1/A5/RHCLK5
H12
RHCLK/
DUAL
1
IO_L06P_1/A6/RHCLK4/
IRDY1
H13
RHCLK/
DUAL
1
IO_L07N_1/A3/RHCLK7
G13
RHCLK/
DUAL
1
IO_L07P_1/A4/RHCLK6
G14
RHCLK/
DUAL
Table 10: CP132 Package Pinout
Bank
10
XC3S250E
XC3S500E
Pin Name
CP132
Ball
Type
0
IO_L01N_0
C12
I/O
0
IO_L01P_0
A13
I/O
0
IO_L02N_0
A12
I/O
0
IO_L02P_0
B12
I/O
0
IO_L03N_0/VREF_0
B11
VREF
0
IO_L03P_0
C11
I/O
0
IO_L04N_0/GCLK5
C9
GCLK
0
IO_L04P_0/GCLK4
A10
GCLK
0
IO_L05N_0/GCLK7
A9
GCLK
0
IO_L05P_0/GCLK6
B9
GCLK
0
IO_L07N_0/GCLK11
B7
GCLK
0
IO_L07P_0/GCLK10
A7
GCLK
1
IO_L08N_1/A1
F13
DUAL
0
IO_L08N_0/VREF_0
C6
VREF
1
IO_L08P_1/A2
F14
DUAL
0
IO_L08P_0
B6
I/O
1
IO_L09N_1/LDC0
D12
DUAL
0
IO_L09N_0
C5
I/O
1
IO_L09P_1/HDC
D13
DUAL
0
IO_L09P_0
B5
I/O
1
IO_L10N_1/LDC2
C13
DUAL
0
IO_L10N_0
C4
I/O
1
IO_L10P_1/LDC1
C14
DUAL
0
IO_L10P_0
B4
I/O
1
IP/VREF_1
G12
VREF
0
IO_L11N_0/HSWAP
B3
DUAL
1
VCCO_1
E13
VCCO
0
IO_L11P_0
A3
I/O
1
VCCO_1
M14
VCCO
2
IO/D5
P4
DUAL
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 10: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
Bank
Table 10: CP132 Package Pinout
CP132
Ball
Type
Bank
XC3S250E
XC3S500E
Pin Name
CP132
Ball
Type
2
IO/M1
N7
DUAL
3
IO_L01P_3
B2
I/O
2
IO/VREF_2
P11
VREF
3
IO_L02N_3
C2
I/O
2
IO_L01N_2/INIT_B
N1
DUAL
3
IO_L02P_3
C3
I/O
2
IO_L01P_2/CSO_B
M2
DUAL
3
IO_L03N_3
D1
I/O
2
IO_L02N_2/MOSI/CSI_B
N2
DUAL
3
IO_L03P_3
D2
I/O
2
IO_L02P_2/DOUT/BUSY
P1
DUAL
3
IO_L04N_3/LHCLK1
F2
LHCLK
2
IO_L03N_2/D6/GCLK13
N4
DUAL/
GCLK
3
IO_L04P_3/LHCLK0
F3
LHCLK
3
IO_L05N_3/LHCLK3/IRDY2
G1
LHCLK
2
IO_L03P_2/D7/GCLK12
M4
DUAL/
GCLK
3
IO_L05P_3/LHCLK2
F1
LHCLK
2
IO_L04N_2/D3/GCLK15
N5
DUAL/
GCLK
3
IO_L06N_3/LHCLK5
H1
LHCLK
3
IO_L06P_3/LHCLK4/TRDY2
G3
LHCLK
3
IO_L07N_3/LHCLK7
H3
LHCLK
3
IO_L07P_3/LHCLK6
H2
LHCLK
3
IO_L08N_3
L2
I/O
3
IO_L08P_3
L1
I/O
3
IO_L09N_3
M1
I/O
3
IO_L09P_3
L3
I/O
3
IP/VREF_3
E2
VREF
3
VCCO_3
E1
VCCO
3
VCCO_3
J2
VCCO
GND
GND
A4
GND
GND
GND
A8
GND
GND
GND
C1
GND
GND
GND
C7
GND
GND
GND
C10
GND
GND
GND
E3
GND
GND
GND
E14
GND
GND
GND
G2
GND
GND
GND
H14
GND
GND
GND
J1
GND
2
IO_L04P_2/D4/GCLK14
M5
DUAL/
GCLK
2
IO_L06N_2/D1/GCLK3
P7
DUAL/
GCLK
2
IO_L06P_2/D2/GCLK2
P6
DUAL/
GCLK
2
IO_L07N_2/DIN/D0
N8
DUAL
2
IO_L07P_2/M0
P8
DUAL
2
IO_L08N_2/A22
M9
DUAL
2
IO_L08P_2/A23
N9
DUAL
2
IO_L09N_2/A20
M10
DUAL
2
IO_L09P_2/A21
N10
DUAL
2
IO_L10N_2/VS1/A18
M11
DUAL
2
IO_L10P_2/VS2/A19
N11
DUAL
2
IO_L11N_2/CCLK
N12
DUAL
2
IO_L11P_2/VS0/A17
P12
DUAL
2
IP/VREF_2
N3
VREF
2
IP_L05N_2/M2/GCLK1
N6
DUAL/
GCLK
2
IP_L05P_2/RDWR_B/
GCLK0
M6
DUAL/
GCLK
2
VCCO_2
M8
VCCO
GND
GND
K12
GND
2
VCCO_2
P3
VCCO
GND
GND
M3
GND
3
IO
J3
I/O
GND
GND
M7
GND
3
IO/VREF_3
K3
VREF
GND
GND
P5
GND
3
IO_L01N_3
B1
I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
11
R
Pinout Descriptions
Table 10: CP132 Package Pinout
Table 10: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
Bank
CP132
Ball
Type
XC3S250E
XC3S500E
Pin Name
Bank
CP132
Ball
Type
GND
GND
P10
GND
VCCAUX VCCAUX
P9
VCCAUX
GND
GND
P14
GND
VCCINT
VCCINT
A11
VCCINT
VCCAUX DONE
P13
CONFIG
VCCINT
VCCINT
D3
VCCINT
VCCAUX PROG_B
A1
CONFIG
VCCINT
VCCINT
D14
VCCINT
VCCAUX TCK
B13
JTAG
VCCINT
VCCINT
K2
VCCINT
VCCAUX TDI
A2
JTAG
VCCINT
VCCINT
L12
VCCINT
VCCAUX TDO
A14
JTAG
VCCINT
VCCINT
P2
VCCINT
VCCAUX TMS
B14
JTAG
VCCAUX VCCAUX
A5
VCCAUX
VCCAUX VCCAUX
E12
VCCAUX
VCCAUX VCCAUX
K1
VCCAUX
User I/Os by Bank
Table 20 indicates how the 92 available user-I/O pins are
distributed between the four I/O banks on the CP132 package.
Table 11: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
22
11
0
1
2
8
Right
1
23
0
0
21
2
0
Bottom
2
26
0
0
24
2
0
Left
3
21
11
0
0
2
8
92
22
0
46
8
16
TOTAL
Footprint Migration Differences
The production XC3S250E and XC3S500E FPGAs have
identical footprints in the CP132 package. Designs can
12
migrate between the XC3S250E and XC3S500E without
further consideration.
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
CP132 Footprint
Bank 0
A
B
C
Bank 3
D
PROG_B
2
TDI
I/O
I/O
L01N_3
L01P_3
GND
3
I/O
L11P_0
4
6
GND
VCCAUX
I/O
I/O
I/O
L09P_0
L08P_0
I/O
I/O
I/O
I/O
L02P_3
L10N_0
L09N_0
I/O
I/O
L03P_3
INPUT
VCCO_0
L10P_0
L02N_3
L03N_3
7
8
9
10
I/O
I/O
L05N_0
GCLK7
L04P_0
GCLK4
VCCINT
VCCO_0
L03N_0
VREF_0
I/O
I/O
L11N_0
HSWAP
5
L07P_0
GCLK10
I/O
INPUT
I/O
L07N_0
GCLK11
L06P_0
GCLK8
L05P_0
GCLK6
INPUT
I/O
GND
L06N_0
GCLK9
L04N_0
GCLK5
I/O
L08N_0
VREF_0
GND
11
I/O
GND
12
13
I/O
I/O
L02N_0
L01P_0
I/O
L02P_0
I/O
I/O
L03P_0
L01N_0
TCK
14
TDO
TMS
I/O
I/O
L10N_1
LDC2
L10P_1
LDC1
I/O
I/O
VCCINT
L09N_1
LDC0
L09P_1
HDC
VCCINT
GND
VCCAUX
VCCO_1
GND
E
VCCO_3
I/O
I/O
I/O
F
L05P_3
LHCLK2
L04N_3
LHCLK1
L04P_3
LHCLK0
G
L05N_3
LHCLK3
IRDY2
GND
L06P_3
LHCLK4
TRDY2
I/O
I/O
I/O
H
L06N_3
LHCLK5
L07P_3
LHCLK6
L07N_3
LHCLK7
L06N_1
A5
RHCLK5
I/O
I/O
J
GND
VCCO_3
I/O
L04N_1
A9
RHCLK1
L05P_1
A8
RHCLK2
L05N_1
A7
RHCLK3
TRDY1
K
VCCAUX
VCCINT
I/O
L04P_1
A10
RHCLK0
VREF_3
I/O
L
M
I/O
I/O
L09P_3
I/O
N
L01N_2
INIT_B
P
L02P_2
DOUT
BUSY
I/O
I/O
GND
VCCINT
I/O
I/O
INPUT
GND
L03P_2
D7
GCLK12
L04P_2
D4
GCLK14
L05P_2
RDWR_B
GCLK0
INPUT
I/O
I/O
INPUT
L03N_2
D6
GCLK13
L04N_2
D3
GCLK15
L05N_2
M2
GCLK1
I/O
I/O
GND
L06P_2
D2
GCLK2
L06N_2
D1
GCLK3
I/O
L02N_2
MOSI
CSI_B
VREF_1
VREF_3
L08N_3
L01P_2
CSO_B
INPUT
I/O
I/O
L09N_3
A0
I/O
L08P_3
I/O
I/O
VREF_2
I/O
VCCINT VCCO_2
I/O
D5
GND
VCCO_2
I/O
L07N_2
DIN
D0
M1
I/O
I/O
L08N_2
A22
L09N_2
A20
I/O
I/O
I/O
L08P_2
A23
L09P_2
A21
VCCAUX
GND
I/O
L07P_2
M0
I/O
L10N_2
VS1
A18
I/O
I/O
I/O
L08N_1
A1
L08P_1
A2
I/O
I/O
L07N_1
A3
RHCLK7
L07P_1
A4
RHCLK6
I/O
L06P_1
A6
RHCLK4
IRDY1
VREF_1
GND
I/O
I/O
I/O
I/O
L03P_1
A12
L03N_1
A11
I/O
I/O
L02P_1
A14
L02N_1
A13
VCCO_1
L10P_2
VS2
A19
I/O
I/O
I/O
L11N_2
CCLK
L01P_1
A16
L01N_1
A15
I/O
L11P_2
VS0
A17
DONE
GND
VREF_2
Bank 2
Bank 1
1
I/O
DS312-4_07_031105
Figure 3: CP132 Package Footprint (top view)
22
I/O: Unrestricted,
general-purpose user I/O
42
DUAL: Configuration pin, then
possible user I/O
8
VREF: User I/O or input
voltage reference for bank
0
INPUT: Unrestricted,
general-purpose input pin
16
GCLK: User I/O, input, or
global buffer input
8
VCCO: Output voltage supply
for bank
2
CONFIG: Dedicated
configuration pins
4
JTAG: Dedicated JTAG port
pins
6
VCCINT: Internal core supply
voltage (+1.2V)
0
N.C.: Not connected
16
GND: Ground
4
VCCAUX: Auxiliary supply
voltage (+2.5V)
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
13
R
Pinout Descriptions
TQ144: 144-lead Thin Quad Flat
Package
mode. In larger packages, there are 24 BPI address outputs.
The XC3S100E and the XC3S250E FPGAs are available in
the 144-lead thin quad flat package, TQ144. Both devices
share a common footprint for this package as shown in
Table 12 and Figure 4.
Table 12 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 12 shows the pinout for production Spartan-3E
FPGAs in the VQ100 package. The XC3S100 engineering
samples have a slightly different pinout, as described in
Table 15.
The TQ144 package only supports 20 address output pins
in the Byte-wide Peripheral Interface (BPI) configuration
Table 12: TQ144 Package Pinout
Bank
14
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
Type
0
IO
IO
P132
I/O
0
IO/VREF_0
IO/VREF_0
P124
VREF
0
IO_L01N_0
IO_L01N_0
P113
I/O
0
IO_L01P_0
IO_L01P_0
P112
I/O
0
IO_L02N_0
IO_L02N_0
P117
I/O
0
IO_L02P_0
IO_L02P_0
P116
I/O
0
IO_L04N_0/GCLK5
IO_L04N_0/GCLK5
P123
GCLK
0
IO_L04P_0/GCLK4
IO_L04P_0/GCLK4
P122
GCLK
0
IO_L05N_0/GCLK7
IO_L05N_0/GCLK7
P126
GCLK
0
IO_L05P_0/GCLK6
IO_L05P_0/GCLK6
P125
GCLK
0
IO_L07N_0/GCLK11
IO_L07N_0/GCLK11
P131
GCLK
0
IO_L07P_0/GCLK10
IO_L07P_0/GCLK10
P130
GCLK
0
IO_L08N_0/VREF_0
IO_L08N_0/VREF_0
P135
VREF
0
IO_L08P_0
IO_L08P_0
P134
I/O
0
IO_L09N_0
IO_L09N_0
P140
I/O
0
IO_L09P_0
IO_L09P_0
P139
I/O
0
IO_L10N_0/HSWAP
IO_L10N_0/HSWAP
P143
DUAL
0
IO_L10P_0
IO_L10P_0
P142
I/O
0
IP
IP
P111
INPUT
0
IP
IP
P114
INPUT
0
IP
IP
P136
INPUT
0
IP
IP
P141
INPUT
0
IP_L03N_0
IP_L03N_0
P120
INPUT
0
IP_L03P_0
IP_L03P_0
P119
INPUT
0
IP_L06N_0/GCLK9
IP_L06N_0/GCLK9
P129
GCLK
0
IP_L06P_0/GCLK8
IP_L06P_0/GCLK8
P128
GCLK
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
Type
0
VCCO_0
VCCO_0
P121
VCCO
0
VCCO_0
VCCO_0
P138
VCCO
1
IO/A0
IO/A0
P98
DUAL
1
IO/VREF_1
IO/VREF_1
P83
VREF
1
IO_L01N_1/A15
IO_L01N_1/A15
P75
DUAL
1
IO_L01P_1/A16
IO_L01P_1/A16
P74
DUAL
1
IO_L02N_1/A13
IO_L02N_1/A13
P77
DUAL
1
IO_L02P_1/A14
IO_L02P_1/A14
P76
DUAL
1
IO_L03N_1/A11
IO_L03N_1/A11
P82
DUAL
1
IO_L03P_1/A12
IO_L03P_1/A12
P81
DUAL
1
IO_L04N_1/A9/RHCLK1
IO_L04N_1/A9/RHCLK1
P86
RHCLK/DUAL
1
IO_L04P_1/A10/RHCLK0
IO_L04P_1/A10/RHCLK0
P85
RHCLK/DUAL
1
IO_L05N_1/A7/RHCLK3/TRDY1
IO_L05N_1/A7/RHCLK3
P88
RHCLK/DUAL
1
IO_L05P_1/A8/RHCLK2
IO_L05P_1/A8/RHCLK2
P87
RHCLK/DUAL
1
IO_L06N_1/A5/RHCLK5
IO_L06N_1/A5/RHCLK5
P92
RHCLK/DUAL
1
IO_L06P_1/A6/RHCLK4/IRDY1
IO_L06P_1/A6/RHCLK4
P91
RHCLK/DUAL
1
IO_L07N_1/A3/RHCLK7
IO_L07N_1/A3/RHCLK7
P94
RHCLK/DUAL
1
IO_L07P_1/A4/RHCLK6
IO_L07P_1/A4/RHCLK6
P93
RHCLK/DUAL
1
IO_L08N_1/A1
IO_L08N_1/A1
P97
DUAL
1
IO_L08P_1/A2
IO_L08P_1/A2
P96
DUAL
1
IO_L09N_1/LDC0
IO_L09N_1/LDC0
P104
DUAL
1
IO_L09P_1/HDC
IO_L09P_1/HDC
P103
DUAL
1
IO_L10N_1/LDC2
IO_L10N_1/LDC2
P106
DUAL
1
IO_L10P_1/LDC1
IO_L10P_1/LDC1
P105
DUAL
1
IP
IP
P78
INPUT
1
IP
IP
P84
INPUT
1
IP
IP
P89
INPUT
1
IP
IP
P101
INPUT
1
IP
IP
P107
INPUT
1
IP/VREF_1
IP/VREF_1
P95
VREF
1
VCCO_1
VCCO_1
P79
VCCO
1
VCCO_1
VCCO_1
P100
VCCO
2
IO/D5
IO/D5
P52
DUAL
2
IO/M1
IO/M1
P60
DUAL
2
IP/VREF_2
IO/VREF_2
P66
100E: VREF(INPUT)
250E: VREF(I/O)
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
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15
R
Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
Type
2
IO_L01N_2/INIT_B
IO_L01N_2/INIT_B
P40
DUAL
2
IO_L01P_2/CSO_B
IO_L01P_2/CSO_B
P39
DUAL
2
IO_L02N_2/MOSI/CSI_B
IO_L02N_2/MOSI/CSI_B
P44
DUAL
2
IO_L02P_2/DOUT/BUSY
IO_L02P_2/DOUT/BUSY
P43
DUAL
2
IO_L04N_2/D6/GCLK13
IO_L04N_2/D6/GCLK13
P51
DUAL/GCLK
2
IO_L04P_2/D7/GCLK12
IO_L04P_2/D7/GCLK12
P50
DUAL/GCLK
2
IO_L05N_2/D3/GCLK15
IO_L05N_2/D3/GCLK15
P54
DUAL/GCLK
2
IO_L05P_2/D4/GCLK14
IO_L05P_2/D4/GCLK14
P53
DUAL/GCLK
2
IO_L07N_2/D1/GCLK3
IO_L07N_2/D1/GCLK3
P59
DUAL/GCLK
2
IO_L07P_2/D2/GCLK2
IO_L07P_2/D2/GCLK2
P58
DUAL/GCLK
2
IO_L08N_2/DIN/D0
IO_L08N_2/DIN/D0
P63
DUAL
2
IO_L08P_2/M0
IO_L08P_2/M0
P62
DUAL
2
IO_L09N_2/VS1/A18
IO_L09N_2/VS1/A18
P68
DUAL
2
IO_L09P_2/VS2/A19
IO_L09P_2/VS2/A19
P67
DUAL
2
IO_L10N_2/CCLK
IO_L10N_2/CCLK
P71
DUAL
2
IO_L10P_2/VS0/A17
IO_L10P_2/VS0/A17
P70
DUAL
2
IP
IP
P38
INPUT
2
IP
IP
P41
INPUT
2
IP
IP
P69
INPUT
2
IP_L03N_2/VREF_2
IP_L03N_2/VREF_2
P48
VREF
2
IP_L03P_2
IP_L03P_2
P47
INPUT
2
IP_L06N_2/M2/GCLK1
IP_L06N_2/M2/GCLK1
P57
DUAL/GCLK
2
IP_L06P_2/RDWR_B/GCLK0
IP_L06P_2/RDWR_B/GCLK0
P56
DUAL/GCLK
2
VCCO_2
VCCO_2
P42
VCCO
2
VCCO_2
VCCO_2
P49
VCCO
2
VCCO_2
VCCO_2
P64
VCCO
3
IP/VREF_3
IO/VREF_3
P31
100E: VREF(INPUT)
250E: VREF(I/O)
16
3
IO_L01N_3
IO_L01N_3
P3
I/O
3
IO_L01P_3
IO_L01P_3
P2
I/O
3
IO_L02N_3/VREF_3
IO_L02N_3/VREF_3
P5
VREF
3
IO_L02P_3
IO_L02P_3
P4
I/O
3
IO_L03N_3
IO_L03N_3
P8
I/O
3
IO_L03P_3
IO_L03P_3
P7
I/O
3
IO_L04N_3/LHCLK1
IO_L04N_3/LHCLK1
P15
LHCLK
3
IO_L04P_3/LHCLK0
IO_L04P_3/LHCLK0
P14
LHCLK
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
Type
3
IO_L05N_3/LHCLK3/IRDY2
IO_L05N_3/LHCLK3
P17
LHCLK
3
IO_L05P_3/LHCLK2
IO_L05P_3/LHCLK2
P16
LHCLK
3
IO_L06N_3/LHCLK5
IO_L06N_3/LHCLK5
P21
LHCLK
3
IO_L06P_3/LHCLK4/TRDY2
IO_L06P_3/LHCLK4
P20
LHCLK
3
IO_L07N_3/LHCLK7
IO_L07N_3/LHCLK7
P23
LHCLK
3
IO_L07P_3/LHCLK6
IO_L07P_3/LHCLK6
P22
LHCLK
3
IO_L08N_3
IO_L08N_3
P26
I/O
3
IO_L08P_3
IO_L08P_3
P25
I/O
3
IO_L09N_3
IO_L09N_3
P33
I/O
3
IO_L09P_3
IO_L09P_3
P32
I/O
3
IO_L10N_3
IO_L10N_3
P35
I/O
3
IO_L10P_3
IO_L10P_3
P34
I/O
3
IP
IP
P6
INPUT
3
IO
IP
P10
100E: I/O
250E: INPUT
3
IP
IP
P18
INPUT
3
IP
IP
P24
INPUT
3
IO
IP
P29
100E: I/O
250E: INPUT
3
IP
IP
P36
INPUT
3
IP/VREF_3
IP/VREF_3
P12
VREF
3
VCCO_3
VCCO_3
P13
VCCO
3
VCCO_3
VCCO_3
P28
VCCO
GND
GND
GND
P11
GND
GND
GND
GND
P19
GND
GND
GND
GND
P27
GND
GND
GND
GND
P37
GND
GND
GND
GND
P46
GND
GND
GND
GND
P55
GND
GND
GND
GND
P61
GND
GND
GND
GND
P73
GND
GND
GND
GND
P90
GND
GND
GND
GND
P99
GND
GND
GND
GND
P118
GND
GND
GND
GND
P127
GND
GND
GND
GND
P133
GND
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
17
R
Pinout Descriptions
Table 12: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
XC3S250E Pin Name
TQ144 Pin
Type
VCCAUX
DONE
DONE
P72
CONFIG
VCCAUX
PROG_B
PROG_B
P1
CONFIG
VCCAUX
TCK
TCK
P110
JTAG
VCCAUX
TDI
TDI
P144
JTAG
VCCAUX
TDO
TDO
P109
JTAG
VCCAUX
TMS
TMS
P108
JTAG
VCCAUX
VCCAUX
VCCAUX
P30
VCCAUX
VCCAUX
VCCAUX
VCCAUX
P65
VCCAUX
VCCAUX
VCCAUX
VCCAUX
P102
VCCAUX
VCCAUX
VCCAUX
VCCAUX
P137
VCCAUX
VCCINT
VCCINT
VCCINT
P9
VCCINT
VCCINT
VCCINT
VCCINT
P45
VCCINT
VCCINT
VCCINT
VCCINT
P80
VCCINT
VCCINT
VCCINT
VCCINT
P115
VCCINT
User I/Os by Bank
Table 13 and Table 14 indicate how the 108 available
user-I/O pins are distributed between the four I/O banks on
the TQ144 package.
Table 13: User I/Os Per Bank for the XC3S100E in the TQ144 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
26
9
6
1
2
8
Right
1
28
0
5
21
2
0
Bottom
2
26
0
4
20
2
0
Left
3
28
13
4
0
3
8
108
22
19
42
9
16
TOTAL
Table 14: User I/Os Per Bank for the XC3S250E in TQ144 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
26
9
6
1
2
8
Right
1
28
0
5
21
2
0
Bottom
2
26
0
4
20
2
0
Left
3
28
11
6
0
3
8
108
20
21
42
9
16
TOTAL
18
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Footprint Migration Differences
Table 15 summarizes any footprint and functionality differences between the XC3S100E and the XC3S250E FPGAs
that may affect easy migration between devices. There are
four such pins. All other pins not listed in Table 15 unconditionally migrate between Spartan-3E devices available in
the TQ144 package.
The arrows indicate the direction for easy migration. For
example, a left-facing arrow indicates that the pin on the
XC3S250E unconditionally migrates to the pin on the
XC3S100E. It may be possible to migrate the opposite
direction depending on the I/O configuration. For example,
an I/O pin (Type = I/O) can migrate to an input-only pin
(Type = INPUT) if the I/O pin is configured as an input.
Table 15: TQ144 Footprint Migration Differences
TQ144 Pin
Bank
XC3S100E Type
Migration
P10
3
I/O
INPUT
P29
3
I/O
INPUT
P31
3
VREF(INPUT)
VREF(I/O)
P66
2
VREF(INPUT)
VREF(I/O)
DIFFERENCES
XC3S250E Type
4
Legend:
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be
possible depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be
possible depending on how the pin is configured for the device on the left.
The pinout changed slightly between the XC3S100E engineering samples and the production devices, as shown in
Table 16. In the engineering samples, the mode select pins
M1 and M0 overlap with two global clock inputs feeding the
bottom edge global buffers and DCMs. In the production
devices, the mode pins are swapped with parallel mode
data pins, D1 and D2. This way, these two mode pins do not
interfere with global clock inputs.
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
Table 16: XC3S100E Pinout Changes between
Production Devices and Engineering Samples
TQ144 Pin
XC3S100E
Production
Devices
XC3S100E
Engineering
Samples
P58
D2/GCLK2
M1/GCLK2
P59
D1/GCLK3
M0/GCLK3
P60
M1
D2
P62
M0
D1
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19
R
Pinout Descriptions
TQ144 Footprint
PROG_B
IO_L01P_3
1
2
110 TCK
109 TDO
112 IO_L01P_0
111 IP
114 IP
113 IO_L01N_0
116 IO_L02P_0
115 VCCINT
118 GND
117 IO_L02N_0
120 IP_L03N_0
119 IP_L03P_0
122 IO_L04P_0/GCLK4
121 VCCO_0
126 IO_L05N_0/GCLK7
125 IO_L05P_0/GCLK6
Bank 0
108 TMS
107 IP
Bank 2
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IO_L01P_2/CSO_B
IO_L01N_2/INIT_B
IP
VCCO_2
IO_L02P_2/DOUT/BUSY
IO_L02N_2/MOSI/CSI_B
VCCINT
GND
IP_L03P_2
IP_L03N_2/VREF_2
VCCO_2
IO_L04P_2/D7/GCLK12
IO_L04N_2/D6/GCLK13
IO/D5
IO_L05P_2/D4/GCLK14
IO_L05N_2/D3/GCLK15
GND
IP_L06P_2/RDWR_B/GCLK0
IP_L06N_2/M2/GCLK1
IO_L07P_2/D2/GCLK2
IO_L07N_2/D1/GCLK3
IO/M1
GND
IO_L08P_2/M0
IO_L08N_2/DIN/D0
VCCO_2
VCCAUX
) IO/VREF_2
IO_L09P_2/VS2/A19
IO_L09N_2/VS1/A18
IP
IO_L10P_2/VS0/A17
IO_L10N_2/CCLK
DONE
(
37
38
Bank 3
Bank 1
IO_L01N_3
IO_L02P_3
IO_L02N_3/VREF_3
IP
IO_L03P_3
IO_L03N_3
VCCINT
(
) IP
GND
IP
3
4
5
6
7
8
9
10
GND 11
IP/VREF_3 12
VCCO_3 13
IO_L04P_3/LHCLK0 14
IO_L04N_3/LHCLK1 15
IO_L05P_3/LHCLK2 16
IO_L05N_3/LHCLK3 17
IP 18
GND 19
IO_L06P_3/LHCLK4 20
IO_L06N_3/LHCLK5 21
IO_L07P_3/LHCLK6 22
IO_L07N_3/LHCLK7 23
IP 24
IO_L08P_3 25
IO_L08N_3 26
GND 27
VCCO_3 28
(
) IP 29
VCCAUX 30
(
) IO/VREF_3 31
IO_L09P_3 32
IO_L09N_3 33
IO_L10P_3 34
IO_L10N_3 35
IP 36
128 IP_L06P_0/GCLK8
127 GND
130 IO_L07P_0/GCLK10
129 IP_L06N_0/GCLK9
132 IO
131 IO_L07N_0/GCLK11
134 IO_L08P_0
133 GND
136 IP
135 IO_L08N_0/VREF_0
138 VCCO_0
137 VCCAUX
140 IO_L09N_0
139 IO_L09P_0
142 IO_L10P_0
141 IP
144 TDI
143 IO_L10N_0/HSWAP
Note pin 1 indicator in top-left corner and logo orientation.
Double arrows (
) indicates a pinout migration difference
124 IO/VREF_0
123 IO_L04N_0/GCLK5
between the XC3S100E and XC3S250E. Engineering sample footprint is slightly different.
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IO_L09N_1/LDC0
IO_L09P_1/HDC
VCCAUX
IP
VCCO_1
GND
IO/A0
IO_L08N_1/A1
IO_L08P_1/A2
IP/VREF_1
IO_L07N_1/A3/RHCLK7
IO_L07P_1/A4/RHCLK6
IO_L06N_1/A5/RHCLK5
IO_L06P_1/A6/RHCLK4
GND
IP
IO_L05N_1/A7/RHCLK3
IO_L05P_1/A8/RHCLK2
IO_L04N_1/A9/RHCLK1
IO_L04P_1/A10/RHCLK0
IP
IO/VREF_1
IO_L03N_1/A11
IO_L03P_1/A12
VCCINT
VCCO_1
IP
IO_L02N_1/A13
IO_L02P_1/A14
IO_L01N_1/A15
IO_L01P_1/A16
GND
DS312-4_01_030705
Figure 4: TQ144 Package Production Footprint (top view)
20
I/O: Unrestricted,
general-purpose user I/O
42
DUAL: Configuration pin, then
possible user I/O
9
VREF: User I/O or input
voltage reference for bank
21
INPUT: Unrestricted,
general-purpose input pin
16
GCLK: User I/O, input, or
global buffer input
9
VCCO: Output voltage supply
for bank
JTAG: Dedicated JTAG port
pins
4
VCCINT: Internal core supply
voltage (+1.2V)
GND: Ground
4
VCCAUX: Auxiliary supply
voltage (+2.5V)
20
2
CONFIG: Dedicated
configuration pins
4
0
N.C.: Not connected
13
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
PQ208: 208-pin Plastic Quad Flat
Package
Table 17: PQ208 Package Pinout
The 208-pin plastic quad flat package, PQ208, supports two
different Spartan-3E FPGAs, including the XC3S250E and
the XC3S500E.
Table 17 lists all the PQ208 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 17: PQ208 Package Pinout
XC3S250E
XC3S500E
Pin Name
Bank
XC3S250E
XC3S500E
Pin Name
Bank
PQ208
Pin
Type
0
IO_L13P_0
P196
I/O
0
IO_L14N_0/VREF_0
P200
VREF
0
IO_L14P_0
P199
I/O
0
IO_L15N_0
P203
I/O
0
IO_L15P_0
P202
I/O
0
IO_L16N_0/HSWAP
P206
DUAL
0
IO_L16P_0
P205
I/O
0
IP
P159
INPUT
0
IP
P169
INPUT
0
IP
P194
INPUT
0
IP
P204
INPUT
PQ208
Pin
Type
0
IP_L06N_0
P175
INPUT
0
IO
P187
I/O
0
IP_L06P_0
P174
INPUT
0
IO/VREF_0
P179
VREF
0
IP_L09N_0/GCLK9
P184
GCLK
0
IO_L01N_0
P161
I/O
0
IP_L09P_0/GCLK8
P183
GCLK
0
IO_L01P_0
P160
I/O
0
VCCO_0
P176
VCCO
0
IO_L02N_0/VREF_0
P163
VREF
0
VCCO_0
P191
VCCO
0
IO_L02P_0
P162
I/O
0
VCCO_0
P201
VCCO
0
IO_L03N_0
P165
I/O
1
IO_L01N_1/A15
P107
DUAL
0
IO_L03P_0
P164
I/O
1
IO_L01P_1/A16
P106
DUAL
0
IO_L04N_0/VREF_0
P168
VREF
1
IO_L02N_1/A13
P109
DUAL
0
IO_L04P_0
P167
I/O
1
IO_L02P_1/A14
P108
DUAL
0
IO_L05N_0
P172
I/O
1
IO_L03N_1/VREF_1
P113
VREF
0
IO_L05P_0
P171
I/O
1
IO_L03P_1
P112
I/O
0
IO_L07N_0/GCLK5
P178
GCLK
1
IO_L04N_1
P116
I/O
0
IO_L07P_0/GCLK4
P177
GCLK
1
IO_L04P_1
P115
I/O
0
IO_L08N_0/GCLK7
P181
GCLK
1
IO_L05N_1/A11
P120
DUAL
0
IO_L08P_0/GCLK6
P180
GCLK
1
IO_L05P_1/A12
P119
DUAL
0
IO_L10N_0/GCLK11
P186
GCLK
1
IO_L06N_1/VREF_1
P123
VREF
0
IO_L10P_0/GCLK10
P185
GCLK
1
IO_L06P_1
P122
I/O
0
IO_L11N_0
P190
I/O
1
IO_L07N_1/A9/RHCLK1
P127
RHCLK/DUAL
0
IO_L11P_0
P189
I/O
1
IO_L07P_1/A10/RHCLK0
P126
RHCLK/DUAL
0
IO_L12N_0/VREF_0
P193
VREF
1
IO_L08N_1/A7/RHCLK3
P129
RHCLK/DUAL
0
IO_L12P_0
P192
I/O
1
IO_L08P_1/A8/RHCLK2
P128
RHCLK/DUAL
0
IO_L13N_0
P197
I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
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21
R
Pinout Descriptions
Table 17: PQ208 Package Pinout
22
Table 17: PQ208 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
Type
Bank
1
IO_L09N_1/A5/RHCLK5
P133
RHCLK/DUAL
2
1
IO_L09P_1/A6/RHCLK4
P132
RHCLK/DUAL
1
IO_L10N_1/A3/RHCLK7
P135
1
IO_L10P_1/A4/RHCLK6
1
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
Type
IO_L04N_2
P63
I/O
2
IO_L04P_2
P62
I/O
RHCLK/DUAL
2
IO_L05N_2
P65
I/O
P134
RHCLK/DUAL
2
IO_L05P_2
P64
I/O
IO_L11N_1/A1
P138
DUAL
2
IO_L06N_2
P69
I/O
1
IO_L11P_1/A2
P137
DUAL
2
IO_L06P_2
P68
I/O
1
IO_L12N_1/A0
P140
DUAL
2
IO_L08N_2/D6/GCLK13
P75
DUAL/GCLK
1
IO_L12P_1
P139
I/O
2
IO_L08P_2/D7/GCLK12
P74
DUAL/GCLK
1
IO_L13N_1
P145
I/O
2
IO_L09N_2/D3/GCLK15
P78
DUAL/GCLK
1
IO_L13P_1
P144
I/O
2
IO_L09P_2/D4/GCLK14
P77
DUAL/GCLK
1
IO_L14N_1
P147
I/O
2
IO_L11N_2/D1/GCLK3
P83
DUAL/GCLK
1
IO_L14P_1
P146
I/O
2
IO_L11P_2/D2/GCLK2
P82
DUAL/GCLK
1
IO_L15N_1/LDC0
P151
DUAL
2
IO_L12N_2/DIN/D0
P87
DUAL
1
IO_L15P_1/HDC
P150
DUAL
2
IO_L12P_2/M0
P86
DUAL
1
IO_L16N_1/LDC2
P153
DUAL
2
IO_L13N_2
P90
I/O
1
IO_L16P_1/LDC1
P152
DUAL
2
IO_L13P_2
P89
I/O
1
IP
P110
INPUT
2
IO_L14N_2/A22
P94
DUAL
1
IP
P118
INPUT
2
IO_L14P_2/A23
P93
DUAL
1
IP
P124
INPUT
2
IO_L15N_2/A20
P97
DUAL
1
IP
P130
INPUT
2
IO_L15P_2/A21
P96
DUAL
1
IP
P142
INPUT
2
IO_L16N_2/VS1/A18
P100
DUAL
1
IP
P148
INPUT
2
IO_L16P_2/VS2/A19
P99
DUAL
1
IP
P154
INPUT
2
IO_L17N_2/CCLK
P103
DUAL
1
IP/VREF_1
P136
VREF
2
IO_L17P_2/VS0/A17
P102
DUAL
1
VCCO_1
P114
VCCO
2
IP
P54
INPUT
1
VCCO_1
P125
VCCO
2
IP
P91
INPUT
1
VCCO_1
P143
VCCO
2
IP
P101
INPUT
2
IO/D5
P76
DUAL
2
IP_L02N_2
P58
INPUT
2
IO/M1
P84
DUAL
2
IP_L02P_2
P57
INPUT
2
IO/VREF_2
P98
VREF
2
IP_L07N_2/VREF_2
P72
VREF
2
IO_L01N_2/INIT_B
P56
DUAL
2
IP_L07P_2
P71
INPUT
2
IO_L01P_2/CSO_B
P55
DUAL
2
IP_L10N_2/M2/GCLK1
P81
DUAL/GCLK
2
IO_L03N_2/MOSI/CSI_B
P61
DUAL
2
P80
DUAL/GCLK
2
IO_L03P_2/DOUT/BUSY
P60
DUAL
IP_L10P_2/RDWR_B/
GCLK0
2
VCCO_2
P59
VCCO
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 17: PQ208 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
Table 17: PQ208 Package Pinout
PQ208
Pin
Type
Bank
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
Type
2
VCCO_2
P73
VCCO
3
IO_L16P_3
P49
I/O
2
VCCO_2
P88
VCCO
3
IP
P6
INPUT
3
IO/VREF_3
P45
VREF
3
IP
P14
INPUT
3
IO_L01N_3
P3
I/O
3
IP
P26
INPUT
3
IO_L01P_3
P2
I/O
3
IP
P32
INPUT
3
IO_L02N_3/VREF_3
P5
VREF
3
IP
P43
INPUT
3
IO_L02P_3
P4
I/O
3
IP
P51
INPUT
3
IO_L03N_3
P9
I/O
3
IP/VREF_3
P20
VREF
3
IO_L03P_3
P8
I/O
3
VCCO_3
P21
VCCO
3
IO_L04N_3
P12
I/O
3
VCCO_3
P38
VCCO
3
IO_L04P_3
P11
I/O
3
VCCO_3
P46
VCCO
3
IO_L05N_3
P16
I/O
GND
GND
P10
GND
3
IO_L05P_3
P15
I/O
GND
GND
P17
GND
3
IO_L06N_3
P19
I/O
GND
GND
P27
GND
3
IO_L06P_3
P18
I/O
GND
GND
P37
GND
3
IO_L07N_3/LHCLK1
P23
LHCLK
GND
GND
P52
GND
3
IO_L07P_3/LHCLK0
P22
LHCLK
GND
GND
P53
GND
3
IO_L08N_3/LHCLK3
P25
LHCLK
GND
GND
P70
GND
3
IO_L08P_3/LHCLK2
P24
LHCLK
GND
GND
P79
GND
3
IO_L09N_3/LHCLK5
P29
LHCLK
GND
GND
P85
GND
3
IO_L09P_3/LHCLK4
P28
LHCLK
GND
GND
P95
GND
3
IO_L10N_3/LHCLK7
P31
LHCLK
GND
GND
P105
GND
3
IO_L10P_3/LHCLK6
P30
LHCLK
GND
GND
P121
GND
3
IO_L11N_3
P34
I/O
GND
GND
P131
GND
3
IO_L11P_3
P33
I/O
GND
GND
P141
GND
3
IO_L12N_3
P36
I/O
GND
GND
P156
GND
3
IO_L12P_3
P35
I/O
GND
GND
P173
GND
3
IO_L13N_3
P40
I/O
GND
GND
P182
GND
3
IO_L13P_3
P39
I/O
GND
GND
P188
GND
3
IO_L14N_3
P42
I/O
GND
GND
P198
GND
3
IO_L14P_3
P41
I/O
GND
GND
P208
GND
3
IO_L15N_3
P48
I/O
VCCAUX
DONE
P104
CONFIG
3
IO_L15P_3
P47
I/O
VCCAUX
PROG_B
P1
CONFIG
3
IO_L16N_3
P50
I/O
VCCAUX
TCK
P158
JTAG
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
23
R
Pinout Descriptions
Table 17: PQ208 Package Pinout
XC3S250E
XC3S500E
Pin Name
Bank
Table 17: PQ208 Package Pinout
PQ208
Pin
Type
Bank
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
Type
VCCAUX
TDI
P207
JTAG
VCCINT
VCCINT
P67
VCCINT
VCCAUX
TDO
P157
JTAG
VCCINT
VCCINT
P117
VCCINT
VCCAUX
TMS
P155
JTAG
VCCINT
VCCINT
P170
VCCINT
VCCAUX
VCCAUX
P7
VCCAUX
VCCAUX
VCCAUX
P44
VCCAUX
VCCAUX
VCCAUX
P66
VCCAUX
VCCAUX
VCCAUX
P92
VCCAUX
Table 18 indicates how the 158 available user-I/O pins are
distributed between the four I/O banks on the PQ208 package.
VCCAUX
VCCAUX
P111
VCCAUX
Footprint Migration Differences
VCCAUX
VCCAUX
P149
VCCAUX
VCCAUX
VCCAUX
P166
VCCAUX
VCCAUX
VCCAUX
P195
VCCAUX
The XC3S250E and XC3S500E FPGAs have identical footprints in the PQ208 package. Designs can migrate between
the XC3S250E and XC3S500E without further consideration.
VCCINT
VCCINT
P13
VCCINT
User I/Os by Bank
Table 18: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
38
18
6
1
5
8
Right
1
40
9
7
21
3
0
Bottom
2
40
8
6
24
2
0
Left
3
40
23
6
0
3
8
158
58
25
46
13
16
TOTAL
24
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
183 IP_L09P_0/GCLK8
182 GND
187 IO
186 IO_L10N_0/GCLK11
185 IO_L10P_0/GCLK10
184 IP_L09N_0/GCLK9
190 IO_L11N_0
189 IO_L11P_0
188 GND
193 IO_L12N_0/VREF_0
192 IO_L12P_0
191 VCCO_0
198 GND
197 IO_L13N_0
196 IO_L13P_0
195 VCCAUX
194 IP
Bank 0
78
79
GND
74
75
76
77
73
VCCO_2
IO_L08P_2/D7/GCLK12
IO_L08N_2/D6/GCLK13
IO_L09N_2/D3/GCLK15
71
72
IP_L07P_2
IP_L07N_2/VREF_2
IO/D5
IO_L09P_2/D4/GCLK14
69
70
66
67
VCCAUX
VCCINT
68
63
64
65
IO_L04N_2
IO_L05P_2
IO_L05N_2
IO_L06P_2
61
62
IO_L03N_2/MOSI/CSI_B
IO_L04P_2
DS312-4_03_030705
IO_L06N_2
GND
58
59
60
Bank 2
IP_L02N_2
VCCO_2
IO_L03P_2/DOUT/BUSY
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Bank 3
IO_L01N_3
IO_L02P_3
IO_L02N_3/VREF_3
IP
VCCAUX
IO_L03P_3
IO_L03N_3
GND
IO_L04P_3
IO_L04N_3
VCCINT
IP
IO_L05P_3
IO_L05N_3
GND
IO_L06P_3
IO_L06N_3
IP/VREF_3
VCCO_3
IO_L07P_3/LHCLK0
IO_L07N_3/LHCLK1
IO_L08P_3/LHCLK2
IO_L08N_3/LHCLK3
IP
GND
IO_L09P_3/LHCLK4
IO_L09N_3/LHCLK5
IO_L10P_3/LHCLK6
IO_L10N_3/LHCLK7
IP
IO_L11P_3
IO_L11N_3
IO_L12P_3
IO_L12N_3
GND
VCCO_3
IO_L13P_3
IO_L13N_3
IO_L14P_3
IO_L14N_3
IP
VCCAUX
IO/VREF_3
VCCO_3
IO_L15P_3
IO_L15N_3
IO_L16P_3
IO_L16N_3
IP
GND
53
54
55
56
57
1
2
GND
IP
IO_L01P_2/CSO_B
IO_L01N_2/INIT_B
IP_L02P_2
PROG_B
IO_L01P_3
203 IO_L15N_0
202 IO_L15P_0
201 VCCO_0
200 IO_L14N_0/VREF_0
199 IO_L14P_0
208
207
206
205
204
GND
TDI
IO_L16N_0/HSWAP
IO_L16P_0
IP
PQ208 Footprint (Left)
Figure 5: PQ208 Footprint (Left)
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
25
R
Pinout Descriptions
157 TDO
161 IO_L01N_0
160 IO_L01P_0
159 IP
158 TCK
IO_L05P_0
VCCINT
IP
IO_L04N_0/VREF_0
IO_L04P_0
VCCAUX
IO_L03N_0
IO_L03P_0
IO_L02N_0/VREF_0
IO_L02P_0
171
170
169
168
167
166
165
164
163
162
181 IO_L08N_0/GCLK7
180 IO_L08P_0/GCLK6
179 IO/VREF_0
178 IO_L07N_0/GCLK5
177 IO_L07P_0/GCLK4
176 VCCO_0
175 IP_L06N_0
174 IP_L06P_0
173 GND
172 IO_L05N_0
PQ208 Footprint (Right)
156 GND
155 TMS
Bank 1
Bank 0
99
IO_L16N_2/VS1/A18 100
IP 101
IO_L17P_2/VS0/A17 102
IO_L17N_2/CCLK 103
DONE 104
93
94
95
96
97
98
IP
IO_L16N_1/LDC2
IO_L16P_1/LDC1
IO_L15N_1/LDC0
IO_L15P_1/HDC
VCCAUX
IP
IO_L14N_1
IO_L14P_1
IO_L13N_1
IO_L13P_1
VCCO_1
IP
GND
IO_L12N_1/A0
IO_L12P_1
IO_L11N_1/A1
IO_L11P_1/A2
IP/VREF_1
IO_L10N_1/A3/RHCLK7
IO_L10P_1/A4/RHCLK6
IO_L09N_1/A5/RHCLK5
IO_L09P_1/A6/RHCLK4
GND
IP
IO_L08N_1/A7/RHCLK3
IO_L08P_1/A8/RHCLK2
IO_L07N_1/A9/RHCLK1
IO_L07P_1/A10/RHCLK
VCCO_1
IP
IO_L06N_1/VREF_1
IO_L06P_1
GND
IO_L05N_1/A11
IO_L05P_1/A12
IP
VCCINT
IO_L04N_1
IO_L04P_1
VCCO_1
IO_L03N_1/VREF_1
IO_L03P_1
VCCAUX
IP
IO_L02N_1/A13
IO_L02P_1/A14
IO_L01N_1/A15
IO_L01P_1/A16
GND
IO_L14N_2/A22
GND
IO_L15P_2/A21
IO_L15N_2/A20
IO/VREF_2
IO_L16P_2/VS2/A19
IP
VCCAUX
IO_L14P_2/A23
IO_L13N_2
82
83
IO_L11P_2/D2/GCLK2
IO_L11N_2/D1/GCLK3
IO/M1
GND
IO_L12P_2/M0
IO_L12N_2/DIN/D0
VCCO_2
IO_L13P_2
84
85
86
87
88
89
90
91
92
80
81
IP_L10P_2/RDWR_B/GCLK0
IP_L10N_2/M2/GCLK1
Bank 2
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DS312-4_04_030705
Figure 6: PQ208 Footprint (Right)
26
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
FT256: 256-ball Fine-pitch, Thin Ball
Grid Array
The 256-lead fine-pitch, thin ball grid array package, FT256,
supports three different Spartan-3E FPGAs, including the
XC3S250E, the XC3S500E, and the XC3S1200E.
Table 19 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The highlighted rows indicate pinout differences between
the XC3S250E, the XC3S500E, and the XC3S1200E
FPGAs. The XC3S250E has 18 unconnected balls, indicated as N.C. (No Connection) in Table 19 and with the
black diamond character ( ) in both Table 19 and in
Figure 7.
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S250E FPGA maps
to a VREF pin on the XC3S500E and XC3S1200E FPGA. If
the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S250E FPGA. This VREF connection on
the board allows future migration to the larger devices without modifying the printed-circuit board.
All other balls have nearly identical functionality on all three
devices. Table 23 summarizes the Spartan-3E footprint
migration differences for the FT256 package.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 19: FT256 Package Pinout
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
FT256
Ball
Type
0
IO
IO
IO
A7
I/O
0
IO
IO
IO
A12
I/O
0
IO
IO
IO
B4
I/O
0
IP
IP
IO
B6
250E: INPUT
500E: INPUT
1200E: I/O
0
IP
IP
IO
B10
250E: INPUT
500E: INPUT
1200E: I/O
0
IO/VREF_0
IO/VREF_0
IO/VREF_0
D9
VREF
0
IO_L01N_0
IO_L01N_0
IO_L01N_0
A14
I/O
0
IO_L01P_0
IO_L01P_0
IO_L01P_0
B14
I/O
0
IO_L03N_0/VREF_0
IO_L03N_0/VREF_0
IO_L03N_0/VREF_0
A13
VREF
0
IO_L03P_0
IO_L03P_0
IO_L03P_0
B13
I/O
0
IO_L04N_0
IO_L04N_0
IO_L04N_0
E11
I/O
0
IO_L04P_0
IO_L04P_0
IO_L04P_0
D11
I/O
0
IO_L05N_0/VREF_0
IO_L05N_0/VREF_0
IO_L05N_0/VREF_0
B11
VREF
0
IO_L05P_0
IO_L05P_0
IO_L05P_0
C11
I/O
0
IO_L06N_0
IO_L06N_0
IO_L06N_0
E10
I/O
0
IO_L06P_0
IO_L06P_0
IO_L06P_0
D10
I/O
0
IO_L08N_0/GCLK5
IO_L08N_0/GCLK5
IO_L08N_0/GCLK5
F9
GCLK
0
IO_L08P_0/GCLK4
IO_L08P_0/GCLK4
IO_L08P_0/GCLK4
E9
GCLK
0
IO_L09N_0/GCLK7
IO_L09N_0/GCLK7
IO_L09N_0/GCLK7
A9
GCLK
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
27
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
FT256
Ball
Type
0
IO_L09P_0/GCLK6
IO_L09P_0/GCLK6
IO_L09P_0/GCLK6
A10
GCLK
0
IO_L11N_0/GCLK11
IO_L11N_0/GCLK11
IO_L11N_0/GCLK11
D8
GCLK
0
IO_L11P_0/GCLK10
IO_L11P_0/GCLK10
IO_L11P_0/GCLK10
C8
GCLK
0
IO_L12N_0
IO_L12N_0
IO_L12N_0
F8
I/O
0
IO_L12P_0
IO_L12P_0
IO_L12P_0
E8
I/O
0
N.C. ( )
IO_L13N_0
IO_L13N_0
C7
250E: N.C.
500E: I/O
1200E: I/O
0
N.C. ( )
IO_L13P_0
IO_L13P_0
B7
250E: N.C.
500E: I/O
1200E: I/O
28
0
IO_L14N_0/VREF_0
IO_L14N_0/VREF_0
IO_L14N_0/VREF_0
D7
VREF
0
IO_L14P_0
IO_L14P_0
IO_L14P_0
E7
I/O
0
IO_L15N_0
IO_L15N_0
IO_L15N_0
D6
I/O
0
IO_L15P_0
IO_L15P_0
IO_L15P_0
C6
I/O
0
IO_L17N_0/VREF_0
IO_L17N_0/VREF_0
IO_L17N_0/VREF_0
A4
VREF
0
IO_L17P_0
IO_L17P_0
IO_L17P_0
A5
I/O
0
IO_L18N_0
IO_L18N_0
IO_L18N_0
C4
I/O
0
IO_L18P_0
IO_L18P_0
IO_L18P_0
C5
I/O
0
IO_L19N_0/HSWAP
IO_L19N_0/HSWAP
IO_L19N_0/HSWAP
B3
DUAL
0
IO_L19P_0
IO_L19P_0
IO_L19P_0
C3
I/O
0
IP
IP
IP
A3
INPUT
0
IP
IP
IP
C13
INPUT
0
IP_L02N_0
IP_L02N_0
IP_L02N_0
C12
INPUT
0
IP_L02P_0
IP_L02P_0
IP_L02P_0
D12
INPUT
0
IP_L07N_0
IP_L07N_0
IP_L07N_0
C9
INPUT
0
IP_L07P_0
IP_L07P_0
IP_L07P_0
C10
INPUT
0
IP_L10N_0/GCLK9
IP_L10N_0/GCLK9
IP_L10N_0/GCLK9
B8
GCLK
0
IP_L10P_0/GCLK8
IP_L10P_0/GCLK8
IP_L10P_0/GCLK8
A8
GCLK
0
IP_L16N_0
IP_L16N_0
IP_L16N_0
E6
INPUT
0
IP_L16P_0
IP_L16P_0
IP_L16P_0
D5
INPUT
0
VCCO_0
VCCO_0
VCCO_0
B5
VCCO
0
VCCO_0
VCCO_0
VCCO_0
B12
VCCO
0
VCCO_0
VCCO_0
VCCO_0
F7
VCCO
0
VCCO_0
VCCO_0
VCCO_0
F10
VCCO
1
IO_L01N_1/A15
IO_L01N_1/A15
IO_L01N_1/A15
R15
DUAL
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
FT256
Ball
Type
1
IO_L01P_1/A16
IO_L01P_1/A16
IO_L01P_1/A16
R16
DUAL
1
IO_L02N_1/A13
IO_L02N_1/A13
IO_L02N_1/A13
P15
DUAL
1
IO_L02P_1/A14
IO_L02P_1/A14
IO_L02P_1/A14
P16
DUAL
1
N.C. ( )
IO_L03N_1/VREF_1
IO_L03N_1/VREF_1
N15
250E: N.C.
500E: VREF
1200E: VREF
1
N.C. ( )
IO_L03P_1
IO_L03P_1
N14
250E: N.C.
500E: I/O
1200E: I/O
1
IO_L04N_1/VREF_1
IO_L04N_1/VREF_1
IO_L04N_1/VREF_1
M16
VREF
1
IO_L04P_1
IO_L04P_1
IO_L04P_1
N16
I/O
1
N.C. ( )
IO_L05N_1
IO_L05N_1
L13
250E: N.C.
500E: I/O
1200E: I/O
1
N.C. ( )
IO_L05P_1
IO_L05P_1
L12
250E: N.C.
500E: I/O
1200E: I/O
1
IO_L06N_1
IO_L06N_1
IO_L06N_1
L15
I/O
1
IO_L06P_1
IO_L06P_1
IO_L06P_1
L14
I/O
1
IO_L07N_1/A11
IO_L07N_1/A11
IO_L07N_1/A11
K12
DUAL
1
IO_L07P_1/A12
IO_L07P_1/A12
IO_L07P_1/A12
K13
DUAL
1
IO_L08N_1/VREF_1
IO_L08N_1/VREF_1
IO_L08N_1/VREF_1
K14
VREF
1
IO_L08P_1
IO_L08P_1
IO_L08P_1
K15
I/O
1
IO_L09N_1/A9/RHCLK1
IO_L09N_1/A9/RHCLK1
IO_L09N_1/A9/RHCLK1
J16
RHCLK/DUAL
1
IO_L09P_1/A10/RHCLK0
IO_L09P_1/A10/RHCLK0
IO_L09P_1/A10/RHCLK0
K16
RHCLK/DUAL
1
IO_L10N_1/A7/RHCLK3/
TRDY1
IO_L10N_1/A7/RHCLK3/
TRDY1
IO_L10N_1/A7/RHCLK3/
TRDY1
J13
RHCLK/DUAL
1
IO_L10P_1/A8/RHCLK2
IO_L10P_1/A8/RHCLK2
IO_L10P_1/A8/RHCLK2
J14
RHCLK/DUAL
1
IO_L11N_1/A5/RHCLK5
IO_L11N_1/A5/RHCLK5
IO_L11N_1/A5/RHCLK5
H14
RHCLK/DUAL
1
IO_L11P_1/A6/RHCLK4/
IRDY1
IO_L11P_1/A6/RHCLK4/
IRDY1
IO_L11P_1/A6/RHCLK4/
IRDY1
H15
RHCLK/DUAL
1
IO_L12N_1/A3/RHCLK7
IO_L12N_1/A3/RHCLK7
IO_L12N_1/A3/RHCLK7
H11
RHCLK/DUAL
1
IO_L12P_1/A4/RHCLK6
IO_L12P_1/A4/RHCLK6
IO_L12P_1/A4/RHCLK6
H12
RHCLK/DUAL
1
IO_L13N_1/A1
IO_L13N_1/A1
IO_L13N_1/A1
G16
DUAL
1
IO_L13P_1/A2
IO_L13P_1/A2
IO_L13P_1/A2
G15
DUAL
1
IO_L14N_1/A0
IO_L14N_1/A0
IO_L14N_1/A0
G14
DUAL
1
IO_L14P_1
IO_L14P_1
IO_L14P_1
G13
I/O
1
IO_L15N_1
IO_L15N_1
IO_L15N_1
F15
I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
29
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
FT256
Ball
Type
1
IO_L15P_1
IO_L15P_1
IO_L15P_1
F14
I/O
1
IO_L16N_1
IO_L16N_1
IO_L16N_1
F12
I/O
1
IO_L16P_1
IO_L16P_1
IO_L16P_1
F13
I/O
1
N.C. ( )
IO_L17N_1
IO_L17N_1
E16
250E: N.C.
500E: I/O
1200E: I/O
1
N.C. ( ).
IO_L17P_1
IO_L17P_1
E13
250E: N.C.
500E: I/O
1200E: I/O
1
IO_L18N_1/LDC0
IO_L18N_1/LDC0
IO_L18N_1/LDC0
D14
DUAL
1
IO_L18P_1/HDC
IO_L18P_1/HDC
IO_L18P_1/HDC
D15
DUAL
1
IO_L19N_1/LDC2
IO_L19N_1/LDC2
IO_L19N_1/LDC2
C15
DUAL
1
IO_L19P_1/LDC1
IO_L19P_1/LDC1
IO_L19P_1/LDC1
C16
DUAL
1
IP
IP
IP
B16
INPUT
1
IP
IP
IP
E14
INPUT
1
IP
IP
IP
G12
INPUT
1
IP
IP
IP
H16
INPUT
1
IP
IP
IP
J11
INPUT
1
IP
IP
IP
J12
INPUT
1
IP
IP
IP
M13
INPUT
1
IO
IO
IP
M14
250E: I/O
500E: I/O
1200E: INPUT
1
IO/VREF_1
IP/VREF_1
IP/VREF_1
D16
250E: VREF(I/O)
500E:
VREF(INPUT)
1200E:
VREF(INPUT)
1
IP/VREF_1
IP/VREF_1
IP/VREF_1
H13
VREF
1
VCCO_1
VCCO_1
VCCO_1
E15
VCCO
1
VCCO_1
VCCO_1
VCCO_1
G11
VCCO
1
VCCO_1
VCCO_1
VCCO_1
K11
VCCO
1
VCCO_1
VCCO_1
VCCO_1
M15
VCCO
2
IP
IP
IO
M7
250E: INPUT
500E: INPUT
1200E: I/O
2
IP
IP
IO
T12
250E: INPUT
500E: INPUT
1200E: I/O
30
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
FT256
Ball
Type
2
IO/D5
IO/D5
IO/D5
T8
DUAL
2
IO/M1
IO/M1
IO/M1
T10
DUAL
2
IO/VREF_2
IO/VREF_2
IO/VREF_2
P13
VREF
2
IO/VREF_2
IO/VREF_2
IO/VREF_2
R4
VREF
2
IO_L01N_2/INIT_B
IO_L01N_2/INIT_B
IO_L01N_2/INIT_B
P4
DUAL
2
IO_L01P_2/CSO_B
IO_L01P_2/CSO_B
IO_L01P_2/CSO_B
P3
DUAL
2
IO_L03N_2/MOSI/CSI_B
IO_L03N_2/MOSI/CSI_B
IO_L03N_2/MOSI/CSI_B
N5
DUAL
2
IO_L03P_2/DOUT/BUSY
IO_L03P_2/DOUT/BUSY
IO_L03P_2/DOUT/BUSY
P5
DUAL
2
IO_L04N_2
IO_L04N_2
IO_L04N_2
T5
I/O
2
IO_L04P_2
IO_L04P_2
IO_L04P_2
T4
I/O
2
IO_L05N_2
IO_L05N_2
IO_L05N_2
N6
I/O
2
IO_L05P_2
IO_L05P_2
IO_L05P_2
M6
I/O
2
IO_L06N_2
IO_L06N_2
IO_L06N_2
P6
I/O
2
IO_L06P_2
IO_L06P_2
IO_L06P_2
R6
I/O
2
N.C. ( )
IO_L07N_2
IO_L07N_2
P7
250E: N.C.
500E: I/O
1200E: I/O
2
N.C. ( )
IO_L07P_2
IO_L07P_2
N7
250E: N.C.
500E: I/O
1200E: I/O
2
IO_L09N_2/D6/GCLK13
IO_L09N_2/D6/GCLK13
IO_L09N_2/D6/GCLK13
L8
DUAL/GCLK
2
IO_L09P_2/D7/GCLK12
IO_L09P_2/D7/GCLK12
IO_L09P_2/D7/GCLK12
M8
DUAL/GCLK
2
IO_L10N_2/D3/GCLK15
IO_L10N_2/D3/GCLK15
IO_L10N_2/D3/GCLK15
P8
DUAL/GCLK
2
IO_L10P_2/D4/GCLK14
IO_L10P_2/D4/GCLK14
IO_L10P_2/D4/GCLK14
N8
DUAL/GCLK
2
IO_L12N_2/D1/GCLK3
IO_L12N_2/D1/GCLK3
IO_L12N_2/D1/GCLK3
N9
DUAL/GCLK
2
IO_L12P_2/D2/GCLK2
IO_L12P_2/D2/GCLK2
IO_L12P_2/D2/GCLK2
P9
DUAL/GCLK
2
IO_L13N_2/DIN/D0
IO_L13N_2/DIN/D0
IO_L13N_2/DIN/D0
M9
DUAL
2
IO_L13P_2/M0
IO_L13P_2/M0
IO_L13P_2/M0
L9
DUAL
2
N.C. ( )
IO_L14N_2/VREF_2
IO_L14N_2/VREF_2
R10
250E: N.C.
500E: VREF
1200E: VREF
2
N.C. ( )
IO_L14P_2
IO_L14P_2
P10
250E: N.C.
500E: I/O
1200E: I/O
2
IO_L15N_2
IO_L15N_2
IO_L15N_2
M10
I/O
2
IO_L15P_2
IO_L15P_2
IO_L15P_2
N10
I/O
2
IO_L16N_2/A22
IO_L16N_2/A22
IO_L16N_2/A22
P11
DUAL
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
31
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
FT256
Ball
Type
2
IO_L16P_2/A23
IO_L16P_2/A23
IO_L16P_2/A23
R11
DUAL
2
IO_L18N_2/A20
IO_L18N_2/A20
IO_L18N_2/A20
N12
DUAL
2
IO_L18P_2/A21
IO_L18P_2/A21
IO_L18P_2/A21
P12
DUAL
2
IO_L19N_2/VS1/A18
IO_L19N_2/VS1/A18
IO_L19N_2/VS1/A18
R13
DUAL
2
IO_L19P_2/VS2/A19
IO_L19P_2/VS2/A19
IO_L19P_2/VS2/A19
T13
DUAL
2
IO_L20N_2/CCLK
IO_L20N_2/CCLK
IO_L20N_2/CCLK
R14
DUAL
2
IO_L20P_2/VS0/A17
IO_L20P_2/VS0/A17
IO_L20P_2/VS0/A17
P14
DUAL
2
IP
IP
IP
T2
INPUT
2
IP
IP
IP
T14
INPUT
2
IP_L02N_2
IP_L02N_2
IP_L02N_2
R3
INPUT
2
IP_L02P_2
IP_L02P_2
IP_L02P_2
T3
INPUT
2
IP_L08N_2/VREF_2
IP_L08N_2/VREF_2
IP_L08N_2/VREF_2
T7
VREF
2
IP_L08P_2
IP_L08P_2
IP_L08P_2
R7
INPUT
2
IP_L11N_2/M2/GCLK1
IP_L11N_2/M2/GCLK1
IP_L11N_2/M2/GCLK1
R9
DUAL/GCLK
2
IP_L11P_2/RDWR_B/
GCLK0
IP_L11P_2/RDWR_B/
GCLK0
IP_L11P_2/RDWR_B/
GCLK0
T9
DUAL/GCLK
2
IP_L17N_2
IP_L17N_2
IP_L17N_2
M11
INPUT
2
IP_L17P_2
IP_L17P_2
IP_L17P_2
N11
INPUT
2
VCCO_2
VCCO_2
VCCO_2
L7
VCCO
2
VCCO_2
VCCO_2
VCCO_2
L10
VCCO
2
VCCO_2
VCCO_2
VCCO_2
R5
VCCO
2
VCCO_2
VCCO_2
VCCO_2
R12
VCCO
3
IO_L01N_3
IO_L01N_3
IO_L01N_3
B2
I/O
3
IO_L01P_3
IO_L01P_3
IO_L01P_3
B1
I/O
3
IO_L02N_3/VREF_3
IO_L02N_3/VREF_3
IO_L02N_3/VREF_3
C2
VREF
3
IO_L02P_3
IO_L02P_3
IO_L02P_3
C1
I/O
3
IO_L03N_3
IO_L03N_3
IO_L03N_3
E4
I/O
3
IO_L03P_3
IO_L03P_3
IO_L03P_3
E3
I/O
3
N.C. ( )
IO_L04N_3/VREF_3
IO_L04N_3/VREF_3
F4
250E: N.C.
500E: VREF
1200E: VREF
3
N.C. ( )
IO_L04P_3
IO_L04P_3
F3
250E: N.C.
500E: I/O
1200E: I/O
32
3
IO_L05N_3
IO_L05N_3
IO_L05N_3
E1
I/O
3
IO_L05P_3
IO_L05P_3
IO_L05P_3
D1
I/O
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
FT256
Ball
Type
3
IO_L06N_3
IO_L06N_3
IO_L06N_3
G4
I/O
3
IO_L06P_3
IO_L06P_3
IO_L06P_3
G5
I/O
3
IO_L07N_3
IO_L07N_3
IO_L07N_3
G2
I/O
3
IO_L07P_3
IO_L07P_3
IO_L07P_3
G3
I/O
3
IO_L08N_3/LHCLK1
IO_L08N_3/LHCLK1
IO_L08N_3/LHCLK1
H6
LHCLK
3
IO_L08P_3/LHCLK0
IO_L08P_3/LHCLK0
IO_L08P_3/LHCLK0
H5
LHCLK
3
IO_L09N_3/LHCLK3/
IRDY2
IO_L09N_3/LHCLK3/
IRDY2
IO_L09N_3/LHCLK3/
IRDY2
H4
LHCLK
3
IO_L09P_3/LHCLK2
IO_L09P_3/LHCLK2
IO_L09P_3/LHCLK2
H3
LHCLK
3
IO_L10N_3/LHCLK5
IO_L10N_3/LHCLK5
IO_L10N_3/LHCLK5
J3
LHCLK
3
IO_L10P_3/LHCLK4/
TRDY2
IO_L10P_3/LHCLK4/
TRDY2
IO_L10P_3/LHCLK4/
TRDY2
J2
LHCLK
3
IO_L11N_3/LHCLK7
IO_L11N_3/LHCLK7
IO_L11N_3/LHCLK7
J4
LHCLK
3
IO_L11P_3/LHCLK6
IO_L11P_3/LHCLK6
IO_L11P_3/LHCLK6
J5
LHCLK
3
IO_L12N_3
IO_L12N_3
IO_L12N_3
K1
I/O
3
IO_L12P_3
IO_L12P_3
IO_L12P_3
J1
I/O
3
IO_L13N_3
IO_L13N_3
IO_L13N_3
K3
I/O
3
IO_L13P_3
IO_L13P_3
IO_L13P_3
K2
I/O
3
N.C. ( )
IO_L14N_3/VREF_3
IO_L14N_3/VREF_3
L2
250E: N.C.
500E: VREF
1200E: VREF
3
N.C. ( )
IO_L14P_3
IO_L14P_3
L3
250E: N.C.
500E: I/O
1200E: I/O
3
IO_L15N_3
IO_L15N_3
IO_L15N_3
L5
I/O
3
IO_L15P_3
IO_L15P_3
IO_L15P_3
K5
I/O
3
IO_L16N_3
IO_L16N_3
IO_L16N_3
N1
I/O
3
IO_L16P_3
IO_L16P_3
IO_L16P_3
M1
I/O
3
N.C. ( )
IO_L17N_3
IO_L17N_3
L4
250E: N.C.
500E: I/O
1200E: I/O
3
N.C. ( )
IO_L17P_3
IO_L17P_3
M4
250E: N.C.
500E: I/O
1200E: I/O
3
IO_L18N_3
IO_L18N_3
IO_L18N_3
P1
I/O
3
IO_L18P_3
IO_L18P_3
IO_L18P_3
P2
I/O
3
IO_L19N_3
IO_L19N_3
IO_L19N_3
R1
I/O
3
IO_L19P_3
IO_L19P_3
IO_L19P_3
R2
I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
33
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
FT256
Ball
Type
3
IP
IP
IP
D2
INPUT
3
IP
IP
IP
F2
INPUT
3
IO
IO
IP
F5
250E: I/O
500E: I/O
1200E: INPUT
3
IP
IP
IP
H1
INPUT
3
IP
IP
IP
J6
INPUT
3
IP
IP
IP
K4
INPUT
3
IP
IP
IP
M3
INPUT
3
IP
IP
IP
N3
INPUT
3
IP/VREF_3
IP/VREF_3
IP/VREF_3
G1
VREF
3
IO/VREF_3
IO/VREF_3
IP/VREF_3
N2
250E: VREF(I/O)
500E: VREF(I/O)
1200E:
VREF(INPUT)
34
3
VCCO_3
VCCO_3
VCCO_3
E2
VCCO
3
VCCO_3
VCCO_3
VCCO_3
G6
VCCO
3
VCCO_3
VCCO_3
VCCO_3
K6
VCCO
3
VCCO_3
VCCO_3
VCCO_3
M2
VCCO
GND
GND
GND
GND
A1
GND
GND
GND
GND
GND
A16
GND
GND
GND
GND
GND
B9
GND
GND
GND
GND
GND
F6
GND
GND
GND
GND
GND
F11
GND
GND
GND
GND
GND
G7
GND
GND
GND
GND
GND
G8
GND
GND
GND
GND
GND
G9
GND
GND
GND
GND
GND
G10
GND
GND
GND
GND
GND
H2
GND
GND
GND
GND
GND
H7
GND
GND
GND
GND
GND
H8
GND
GND
GND
GND
GND
H9
GND
GND
GND
GND
GND
H10
GND
GND
GND
GND
GND
J7
GND
GND
GND
GND
GND
J8
GND
GND
GND
GND
GND
J9
GND
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 19: FT256 Package Pinout (Continued)
Bank
XC3S250E Pin Name
XC3S500E Pin Name
XC3S1200E Pin Name
FT256
Ball
Type
GND
GND
GND
GND
J10
GND
GND
GND
GND
GND
J15
GND
GND
GND
GND
GND
K7
GND
GND
GND
GND
GND
K8
GND
GND
GND
GND
GND
K9
GND
GND
GND
GND
GND
K10
GND
GND
GND
GND
GND
L6
GND
GND
GND
GND
GND
L11
GND
GND
GND
GND
GND
R8
GND
GND
GND
GND
GND
T1
GND
GND
GND
GND
GND
T16
GND
VCCAUX
DONE
DONE
DONE
T15
CONFIG
VCCAUX
PROG_B
PROG_B
PROG_B
D3
CONFIG
VCCAUX
TCK
TCK
TCK
A15
JTAG
VCCAUX
TDI
TDI
TDI
A2
JTAG
VCCAUX
TDO
TDO
TDO
C14
JTAG
VCCAUX
TMS
TMS
TMS
B15
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
A6
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
A11
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
F1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
F16
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
L1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
L16
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
T6
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
T11
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
D4
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
D13
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E5
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E12
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
M5
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
M12
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
N4
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
N13
VCCINT
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
35
R
Pinout Descriptions
User I/Os by Bank
Table 20, Table 21, and Table 22 indicate how the available
user-I/O pins are distributed between the four I/O banks on
the FT256 package.
The XC3S250E FPGA in the FT256 package has 18 unconnected balls, labeled with an “N.C.” type. These pins are
also indicated with the black diamond ( ) symbol in
Figure 7.
Table 20: User I/Os Per Bank on XC3S250E in the FT256 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
44
20
10
1
5
8
Right
1
42
10
7
21
4
0
Bottom
2
44
8
9
24
3
0
Left
3
42
24
7
0
3
8
172
62
33
46
15
16
TOTAL
Table 21: User I/Os Per Bank on XC3S500E in the FT256 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
46
22
10
1
5
8
Right
1
48
15
7
21
5
0
Bottom
2
48
11
9
24
4
0
Left
3
48
28
7
0
5
8
190
76
33
46
19
16
TOTAL
Table 22: User I/Os Per Bank on XC3S1200E in the FT256 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
46
24
8
1
5
8
Right
1
48
14
8
21
5
0
Bottom
2
48
13
7
24
4
0
Left
3
48
27
8
0
5
8
190
78
31
46
19
16
TOTAL
36
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Footprint Migration Differences
Table 23 summarizes any footprint and functionality differences between the XC3S250E, the XC3S500E, and the
XC3S1200E FPGAs that may affect easy migration
between devices in the FG256 package. There are 26 such
balls. All other pins not listed in Table 23 unconditionally
migrate between Spartan-3E devices available in the FT256
package.
and the XC3S1200E. The arrows indicate the direction for
easy migration. A double-ended arrow (
) indicates that
the two pins have identical functionality. A left-facing arrow
( ) indicates that the pin on the device on the right unconditionally migrates to the pin on the device on the left. It may
be possible to migrate the opposite direction depending on
the I/O configuration. For example, an I/O pin (Type = I/O)
can migrate to an input-only pin (Type = INPUT) if the I/O
pin is configured as an input.
The XC3S250E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S500E
Table 23: FT256 Footprint Migration Differences
FT256
Ball
Bank
XC3S250E
Type
B6
0
INPUT
INPUT
I/O
INPUT
B7
0
N.C.
I/O
I/O
N.C.
B10
0
INPUT
INPUT
I/O
INPUT
Migration
XC3S500E
Type
Migration
XC3S1200E
Type
Migration
XC3S250E
Type
C7
0
N.C.
I/O
I/O
N.C.
D16
1
VREF(I/O)
VREF(INPUT)
VREF(INPUT)
VREF(I/O)
E13
1
N.C.
I/O
I/O
N.C.
E16
1
N.C.
I/O
I/O
N.C.
F3
3
N.C.
I/O
I/O
N.C.
F4
3
N.C.
VREF
VREF
N.C.
F5
3
I/O
I/O
INPUT
I/O
L2
3
N.C.
VREF
VREF
N.C.
L3
3
N.C.
I/O
I/O
N.C.
L4
3
N.C.
I/O
I/O
N.C.
L12
1
N.C.
I/O
I/O
N.C.
L13
1
N.C.
I/O
I/O
N.C.
M4
3
N.C.
I/O
I/O
N.C.
M7
2
INPUT
INPUT
I/O
INPUT
M14
1
I/O
I/O
INPUT
I/O
N2
3
VREF(I/O)
VREF(I/O)
VREF(INPUT)
VREF(I/O)
N7
2
N.C.
I/O
I/O
N.C.
N14
1
N.C.
I/O
I/O
N.C.
N15
1
N.C.
VREF
VREF
N.C.
P7
2
N.C.
I/O
I/O
N.C.
P10
2
N.C.
I/O
I/O
N.C.
R10
2
N.C.
VREF
VREF
N.C.
T12
2
INPUT
INPUT
I/O
INPUT
DIFFERENCES
19
7
26
Legend:
This pin is identical on both the device on the left and the right.
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible
depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible
depending on how the pin is configured for the device on the left.
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
37
R
Pinout Descriptions
FT256 Footprint
2
3
4
I/O
A
GND
B
I/O
I/O
L01P_3
L01N_3
C
D
E
F
Bank 3
G
I/O
L02P_3
I/O
L05P_3
I/O
L05N_3
VCCAUX
I/O
L02N_3
VREF_3
INPUT
I/O
L17N_0
VREF_0
L17P_0
I/O
VCCO_0
I/O
L19N_0
HSWAP
I/O
I/O
I/O
L18N_0
L18P_0
L15P_0
I/O
I/O
L03P_3
L03N_3
I/O
I/O
L04P_3
L04N_3
VREF_3
VCCINT
INPUT
I/O
L10P_0
GCLK8
L09N_0
GCLK7
L09P_0
GCLK6
I/O
INPUT
L13P_0
L10N_0
GCLK9
I/O
I/O
L13N_0
L11P_0
GCLK10
I/O
I/O
L14N_0
VREF_0
L11N_0
GCLK11
INPUT
I/O
I/O
L16N_0
L14P_0
L12P_0
GND
VCCO_0
VCCO_3
I/O
GND
INPUT
11
12
13
VCCAUX
I/O
L03N_0
VREF_0
I/O
L05N_0
VREF_0
VCCO_0
INPUT
INPUT
I/O
INPUT
L07N_0
L07P_0
L05P_0
L02N_0
I/O
I/O
I/O
INPUT
VREF_0
L06P_0
L04P_0
L02P_0
I/O
L08P_0
GCLK4
14
I/O
I/O
I/O
L06N_0
L04N_0
I/O
L12N_0
L08N_0
GCLK5
VCCO_0
GND
GND
GND
GND
GND
VCCO_1
I/O
L01N_0
I/O
I/O
L03P_0
L01P_0
INPUT
TDO
VCCO_1
L17N_1
I/O
I/O
I/O
I/O
L16N_1
L16P_1
L15P_1
L15N_1
I/O
I/O
I/O
I/O
L13P_1
A2
L13N_1
A1
I/O
I/O
I/O
I/O
I/O
L08P_3
LHCLK0
L08N_3
LHCLK1
GND
GND
GND
GND
L12N_1
A3
RHCLK7
L12P_1
A4
RHCLK6
INPUT
GND
GND
GND
GND
INPUT
INPUT
I/O
I/O
I/O
VCCO_3
GND
GND
GND
GND
VCCO_1
L07N_1
A11
L07P_1
A12
L08N_1
VREF_1
I/O
I/O
I/O
I/O
GND
VCCO_2
L09N_2
D6
GCLK13
L13P_2
M0
VCCO_2
GND
L05P_1
L05N_1
I/O
INPUT
I/O
L11P_3
LHCLK6
I/O
I/O
L13N_3
I/O
I/O
I/O
L
VCCAUX
L14N_3
VREF_3
L14P_3
L17N_3
VCCO_3
INPUT
L17P_3
INPUT
I/O
INPUT VCCINT L03N_2
I/O
L16P_3
I/O
L16N_3
INPUT
L15P_3
I/O
L15N_3
I/O
VREF_3
VCCINT
MOSI
CSI_B
I/O
I/O
I/O
I/O
I/O
L18N_3
L18P_3
L01P_2
CSO_B
L01N_2
INIT_B
L03P_2
DOUT
BUSY
I/O
I/O
INPUT
I/O
L19N_3
L19P_3
L02N_2
VREF_2
GND
INPUT
VCCO_2
INPUT
I/O
I/O
L02P_2
L04P_2
L04N_2
INPUT
L14P_1
INPUT
VREF_1
I/O
L05P_2
I/O
L05N_2
I/O
L06N_2
I/O
L13N_2
DIN
D0
I/O
I/O
I/O
L07P_2
L10P_2
D4
GCLK14
L12N_2
D1
GCLK3
I/O
INPUT
L15N_2
L17N_2
I/O
INPUT
L15P_2
L17P_2
VCCINT INPUT
I/O
L18N_2
A20
I/O
I/O
I/O
I/O
I/O
I/O
L07N_2
L10N_2
D3
GCLK15
L12P_2
D2
GCLK2
L14P_2
L16N_2
A22
L18P_2
A21
I/O
INPUT
L06P_2
L08P_2
INPUT
VCCAUX
I/O
L09P_2
D7
GCLK12
L08N_2
VREF_2
GND
I/O
D5
INPUT
I/O
L11N_2
M2
GCLK1
L14N_2
VREF_2
INPUT
L11P_2
RDWR_B
GCLK0
I/O
M1
I/O
L16P_2
A23
VCCAUX
L10N_1
A7
RHCLK3
TRDY1
VCCO_2
INPUT
I/O
L11N_1
A5
RHCLK5
I/O
I/O
L11P_1
A6
RHCLK4
IRDY1
I/O
L10P_1
A8
RHCLK2
I/O
L08P_1
I/O
I/O
L06N_1
INPUT
INPUT
I/O
GND
L06P_1
I/O
VCCINT L03P_1
VREF_2
VCCAUX
L14N_1
A0
L09N_3
LHCLK3
IRDY2
I/O
I/O
L19P_1
LDC1
INPUT
I/O
L11N_3
LHCLK7
I/O
L19N_1
LDC2
I/O
VCCINT L17P_1
L09P_3
LHCLK2
I/O
INPUT
LDC0
GND
L10N_3
LHCLK5
TMS
I/O
I/O
I/O
GND
INPUT
L06P_3
L10P_3
LHCLK4
TRDY2
TCK
VREF_1
I/O
I/O
16
I/O
L06N_3
L12P_3
15
L18P_1
HDC
I/O
VCCINT L18N_1
I/O
I/O
T
I/O
L07P_3
L13P_3
R
I/O
I/O
I/O
P
10
INPUT
L07N_3
L12N_3
N
I/O
L15N_0
Bank 0
8
9
7
INPUT
K
M
INPUT
I/O
L16P_0
INPUT
VCCAUX
L19P_0
INPUT
INPUT PROG_B VCCINT
VCCO_3
6
VREF_3
H INPUT
J
TDI
5
L09N_1
A9
RHCLK1
Bank 1
1
I/O
L09P_1
A10
RHCLK0
VCCAUX
I/O
VCCO_1
I/O
L03N_1
VREF_1
L04N_1
VREF_1
I/O
L04P_1
I/O
I/O
I/O
L20P_2
VS0
A17
L02N_1
A13
L02P_1
A14
I/O
I/O
I/O
I/O
L19N_2
VS1
A18
L20N_2
CCLK
L01N_1
A15
L01P_1
A16
INPUT
DONE
GND
I/O
L19P_2
VS2
A19
Bank 2
DS312-4_05_021705
Figure 7: FT256 Package Footprint (top view)
2
28
6
38
CONFIG: Dedicated
configuration pins
4
JTAG: Dedicated JTAG port
pins
8
VCCINT: Internal core supply
voltage (+1.2V)
8
VCCAUX: Auxiliary supply
voltage (+2.5V)
GND: Ground
16
VCCO: Output voltage supply
for bank
Migration Difference: For
flexible package migration,
use these pins as inputs.
18
Unconnected pins on
XC3S250E
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
FG320: 320-ball Fine-pitch Ball Grid
Array
The 320-lead fine-pitch ball grid array package, FG320,
supports three different Spartan-3E FPGAs, including the
XC3S500E, the XC3S1200E, and the XC3S1600E, as
shown in Table 24 and Figure 8.
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
Table 24 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The highlighted rows indicate pinout differences between
the XC3S500E, the XC3S1200E, and the XC3S1600E
FPGAs. The XC3S500E has 18 unconnected balls, indicated as N.C. (No Connection) in Table 24 and with the
black diamond character ( ) in both Table 24 and in
Figure 8.
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S500E FPGA maps
to a VREF pin on the XC3S1200E and XC3S1600E FPGA.
If the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S500E FPGA. This VREF connection on
the board allows future migration to the larger devices without modifying the printed-circuit board.
All other balls have nearly identical functionality on all three
devices. Table 23 summarizes the Spartan-3E footprint
migration differences for the FG320 package.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 24: FG320 Package Pinout
Bank
0
XC3S500E Pin Name
IP
XC3S1200E Pin Name
IO
XC3S1600E Pin Name
IO
FG320
Ball
Type
A7
500E: INPUT
1200E: I/O
1600E: I/O
0
IO
IO
IO
A8
I/O
0
IO
IO
IO
A11
I/O
0
IO
IO
IO
C4
I/O
0
IP
IO
IO
D13
500E: INPUT
1200E: I/O
1600E: I/O
0
IO
IO
IO
E13
I/O
0
IO
IO
IO
G9
I/O
0
IO/VREF_0
IO/VREF_0
IO/VREF_0
B11
VREF
0
IO_L01N_0
IO_L01N_0
IO_L01N_0
A16
I/O
0
IO_L01P_0
IO_L01P_0
IO_L01P_0
B16
I/O
0
IO_L03N_0/VREF_0
IO_L03N_0/VREF_0
IO_L03N_0/VREF_0
C14
VREF
0
IO_L03P_0
IO_L03P_0
IO_L03P_0
D14
I/O
0
IO_L04N_0
IO_L04N_0
IO_L04N_0
A14
I/O
0
IO_L04P_0
IO_L04P_0
IO_L04P_0
B14
I/O
0
IO_L05N_0/VREF_0
IO_L05N_0/VREF_0
IO_L05N_0/VREF_0
B13
VREF
0
IO_L05P_0
IO_L05P_0
IO_L05P_0
A13
I/O
0
IO_L06N_0
IO_L06N_0
IO_L06N_0
E12
I/O
0
IO_L06P_0
IO_L06P_0
IO_L06P_0
F12
I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
39
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
FG320
Ball
Type
0
IO_L08N_0
IO_L08N_0
IO_L08N_0
F11
I/O
0
IO_L08P_0
IO_L08P_0
IO_L08P_0
E11
I/O
0
IO_L09N_0
IO_L09N_0
IO_L09N_0
D11
I/O
0
IO_L09P_0
IO_L09P_0
IO_L09P_0
C11
I/O
0
IO_L11N_0/GCLK5
IO_L11N_0/GCLK5
IO_L11N_0/GCLK5
E10
GCLK
0
IO_L11P_0/GCLK4
IO_L11P_0/GCLK4
IO_L11P_0/GCLK4
D10
GCLK
0
IO_L12N_0/GCLK7
IO_L12N_0/GCLK7
IO_L12N_0/GCLK7
A10
GCLK
0
IO_L12P_0/GCLK6
IO_L12P_0/GCLK6
IO_L12P_0/GCLK6
B10
GCLK
0
IO_L14N_0/GCLK11
IO_L14N_0/GCLK11
IO_L14N_0/GCLK11
D9
GCLK
0
IO_L14P_0/GCLK10
IO_L14P_0/GCLK10
IO_L14P_0/GCLK10
C9
GCLK
0
IO_L15N_0
IO_L15N_0
IO_L15N_0
F9
I/O
0
IO_L15P_0
IO_L15P_0
IO_L15P_0
E9
I/O
0
IO_L17N_0
IO_L17N_0
IO_L17N_0
F8
I/O
0
IO_L17P_0
IO_L17P_0
IO_L17P_0
E8
I/O
0
IO_L18N_0/VREF_0
IO_L18N_0/VREF_0
IO_L18N_0/VREF_0
D7
VREF
0
IO_L18P_0
IO_L18P_0
IO_L18P_0
C7
I/O
0
IO_L19N_0/VREF_0
IO_L19N_0/VREF_0
IO_L19N_0/VREF_0
E7
VREF
0
IO_L19P_0
IO_L19P_0
IO_L19P_0
F7
I/O
0
IO_L20N_0
IO_L20N_0
IO_L20N_0
A6
I/O
0
IO_L20P_0
IO_L20P_0
IO_L20P_0
B6
I/O
0
N.C. ( )
IO_L21N_0
IO_L21N_0
E6
500E: N.C.
1200E: I/O
1600E: I/O
0
N.C. ( )
IO_L21P_0
IO_L21P_0
D6
500E: N.C.
1200E: I/O
1600E: I/O
0
IO_L23N_0/VREF_0
IO_L23N_0/VREF_0
IO_L23N_0/VREF_0
D5
VREF
0
IO_L23P_0
IO_L23P_0
IO_L23P_0
C5
I/O
0
IO_L24N_0
IO_L24N_0
IO_L24N_0
B4
I/O
0
IO_L24P_0
IO_L24P_0
IO_L24P_0
A4
I/O
0
IO_L25N_0/HSWAP
IO_L25N_0/HSWAP
IO_L25N_0/HSWAP
B3
DUAL
0
IO_L25P_0
IO_L25P_0
IO_L25P_0
C3
I/O
0
IP
IP
IP
A3
INPUT
0
N.C. ( )
IO
IP
A12
500E: N.C.
1200E: I/O
1600E: INPUT
40
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
FG320
Ball
Type
0
IP
IP
IP
C15
INPUT
0
IP_L02N_0
IP_L02N_0
IP_L02N_0
A15
INPUT
0
IP_L02P_0
IP_L02P_0
IP_L02P_0
B15
INPUT
0
IP_L07N_0
IP_L07N_0
IP_L07N_0
D12
INPUT
0
IP_L07P_0
IP_L07P_0
IP_L07P_0
C12
INPUT
0
IP_L10N_0
IP_L10N_0
IP_L10N_0
G10
INPUT
0
IP_L10P_0
IP_L10P_0
IP_L10P_0
F10
INPUT
0
IP_L13N_0/GCLK9
IP_L13N_0/GCLK9
IP_L13N_0/GCLK9
B9
GCLK
0
IP_L13P_0/GCLK8
IP_L13P_0/GCLK8
IP_L13P_0/GCLK8
B8
GCLK
0
IP_L16N_0
IP_L16N_0
IP_L16N_0
D8
INPUT
0
IP_L16P_0
IP_L16P_0
IP_L16P_0
C8
INPUT
0
IP_L22N_0
IP_L22N_0
IP_L22N_0
B5
INPUT
0
IP_L22P_0
IP_L22P_0
IP_L22P_0
A5
INPUT
0
VCCO_0
VCCO_0
VCCO_0
A9
VCCO
0
VCCO_0
VCCO_0
VCCO_0
C6
VCCO
0
VCCO_0
VCCO_0
VCCO_0
C13
VCCO
0
VCCO_0
VCCO_0
VCCO_0
G8
VCCO
0
VCCO_0
VCCO_0
VCCO_0
G11
VCCO
1
N.C. ( )
IO
IO
P16
500E: N.C.
1200E: I/O
1600E: I/O
1
IO_L01N_1/A15
IO_L01N_1/A15
IO_L01N_1/A15
T17
DUAL
1
IO_L01P_1/A16
IO_L01P_1/A16
IO_L01P_1/A16
U18
DUAL
1
IO_L02N_1/A13
IO_L02N_1/A13
IO_L02N_1/A13
T18
DUAL
1
IO_L02P_1/A14
IO_L02P_1/A14
IO_L02P_1/A14
R18
DUAL
1
IO_L03N_1/VREF_1
IO_L03N_1/VREF_1
IO_L03N_1/VREF_1
R16
VREF
1
IO_L03P_1
IO_L03P_1
IO_L03P_1
R15
I/O
1
N.C. ( )
IO_L04N_1
IO_L04N_1
N14
500E: N.C.
1200E: I/O
1600E: INPUT
1
N.C. ( )
IO_L04P_1
IO_L04P_1
N15
500E: N.C.
1200E: I/O
1600E: INPUT
1
IO_L05N_1/VREF_1
IO_L05N_1/VREF_1
IO_L05N_1/VREF_1
M13
VREF
1
IO_L05P_1
IO_L05P_1
IO_L05P_1
M14
I/O
1
IO_L06N_1
IO_L06N_1
IO_L06N_1
P18
I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
41
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
FG320
Ball
Type
1
IO_L06P_1
IO_L06P_1
IO_L06P_1
P17
I/O
1
IO_L07N_1
IO_L07N_1
IO_L07N_1
M16
I/O
1
IO_L07P_1
IO_L07P_1
IO_L07P_1
M15
I/O
1
IO_L08N_1
IO_L08N_1
IO_L08N_1
M18
I/O
1
IO_L08P_1
IO_L08P_1
IO_L08P_1
N18
I/O
1
IO_L09N_1/A11
IO_L09N_1/A11
IO_L09N_1/A11
L15
DUAL
1
IO_L09P_1/A12
IO_L09P_1/A12
IO_L09P_1/A12
L16
DUAL
1
IO_L10N_1/VREF_1
IO_L10N_1/VREF_1
IO_L10N_1/VREF_1
L17
VREF
1
IO_L10P_1
IO_L10P_1
IO_L10P_1
L18
I/O
1
IO_L11N_1/A9/RHCLK1
IO_L11N_1/A9/RHCLK1
IO_L11N_1/A9/RHCLK1
K12
RHCLK/DUAL
1
IO_L11P_1/A10/RHCLK0
IO_L11P_1/A10/RHCLK0
IO_L11P_1/A10/RHCLK0
K13
RHCLK/DUAL
1
IO_L12N_1/A7/RHCLK3/
TRDY1
IO_L12N_1/A7/RHCLK3/
TRDY1
IO_L12N_1/A7/RHCLK3/
TRDY1
K14
RHCLK/DUAL
1
IO_L12P_1/A8/RHCLK2
IO_L12P_1/A8/RHCLK2
IO_L12P_1/A8/RHCLK2
K15
RHCLK/DUAL
1
IO_L13N_1/A5/RHCLK5
IO_L13N_1/A5/RHCLK5
IO_L13N_1/A5/RHCLK5
J16
RHCLK/DUAL
1
IO_L13P_1/A6/RHCLK4/
IRDY1
IO_L13P_1/A6/RHCLK4/
IRDY1
IO_L13P_1/A6/RHCLK4/
IRDY1
J17
RHCLK/DUAL
1
IO_L14N_1/A3/RHCLK7
IO_L14N_1/A3/RHCLK7
IO_L14N_1/A3/RHCLK7
J14
RHCLK/DUAL
1
IO_L14P_1/A4/RHCLK6
IO_L14P_1/A4/RHCLK6
IO_L14P_1/A4/RHCLK6
J15
RHCLK/DUAL
1
IO_L15N_1/A1
IO_L15N_1/A1
IO_L15N_1/A1
J13
DUAL
1
IO_L15P_1/A2
IO_L15P_1/A2
IO_L15P_1/A2
J12
DUAL
1
IO_L16N_1/A0
IO_L16N_1/A0
IO_L16N_1/A0
H17
DUAL
1
IO_L16P_1
IO_L16P_1
IO_L16P_1
H16
I/O
1
IO_L17N_1
IO_L17N_1
IO_L17N_1
H15
I/O
1
IO_L17P_1
IO_L17P_1
IO_L17P_1
H14
I/O
1
IO_L18N_1
IO_L18N_1
IO_L18N_1
G16
I/O
1
IO_L18P_1
IO_L18P_1
IO_L18P_1
G15
I/O
1
IO_L19N_1
IO_L19N_1
IO_L19N_1
F17
I/O
1
IO_L19P_1
IO_L19P_1
IO_L19P_1
F18
I/O
1
IO_L20N_1
IO_L20N_1
IO_L20N_1
G13
I/O
1
IO_L20P_1
IO_L20P_1
IO_L20P_1
G14
I/O
1
IO_L21N_1
IO_L21N_1
IO_L21N_1
F14
I/O
1
IO_L21P_1
IO_L21P_1
IO_L21P_1
F15
I/O
1
N.C. ( )
IO_L22N_1
IO_L22N_1
E16
500E: N.C.
1200E: I/O
1600E: I/O
42
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank
1
XC3S500E Pin Name
N.C. ( )
XC3S1200E Pin Name
IO_L22P_1
XC3S1600E Pin Name
IO_L22P_1
FG320
Ball
Type
E15
500E: N.C.
1200E: I/O
1600E: I/O
1
IO_L23N_1/LDC0
IO_L23N_1/LDC0
IO_L23N_1/LDC0
D16
DUAL
1
IO_L23P_1/HDC
IO_L23P_1/HDC
IO_L23P_1/HDC
D17
DUAL
1
IO_L24N_1/LDC2
IO_L24N_1/LDC2
IO_L24N_1/LDC2
C17
DUAL
1
IO_L24P_1/LDC1
IO_L24P_1/LDC1
IO_L24P_1/LDC1
C18
DUAL
1
IP
IP
IP
B18
INPUT
1
IO
IP
IP
E17
500E: I/O
1200E: INPUT
1600E: INPUT
1
IP
IP
IP
E18
INPUT
1
IP
IP
IP
G18
INPUT
1
IP
IP
IP
H13
INPUT
1
IP
IP
IP
K17
INPUT
1
IP
IP
IP
K18
INPUT
1
IP
IP
IP
L13
INPUT
1
IP
IP
IP
L14
INPUT
1
IP
IP
IP
N17
INPUT
1
IO
IP
IP
P15
500E: I/O
1200E: INPUT
1600E: INPUT
1
IP
IP
IP
R17
INPUT
1
IP/VREF_1
IP/VREF_1
IP/VREF_1
D18
VREF
1
IP/VREF_1
IP/VREF_1
IP/VREF_1
H18
VREF
1
VCCO_1
VCCO_1
VCCO_1
F16
VCCO
1
VCCO_1
VCCO_1
VCCO_1
H12
VCCO
1
VCCO_1
VCCO_1
VCCO_1
J18
VCCO
1
VCCO_1
VCCO_1
VCCO_1
L12
VCCO
1
VCCO_1
VCCO_1
VCCO_1
N16
VCCO
2
IO
IO
IO
P9
I/O
2
IO
IO
IO
R11
I/O
2
IP
IO
IO
U6
500E: INPUT
1200E: I/O
1600E: I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
43
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank
2
XC3S500E Pin Name
IP
XC3S1200E Pin Name
IO
XC3S1600E Pin Name
IO
FG320
Ball
Type
U13
500E: INPUT
1200E: I/O
1600E: I/O
2
N.C. ( )
IO
IO
V7
500E: N.C.
1200E: I/O
1600E: I/O
2
IO/D5
IO/D5
IO/D5
R9
DUAL
2
IO/M1
IO/M1
IO/M1
V11
DUAL
2
IO/VREF_2
IO/VREF_2
IO/VREF_2
T15
VREF
2
IO/VREF_2
IO/VREF_2
IO/VREF_2
U5
VREF
2
IO_L01N_2/INIT_B
IO_L01N_2/INIT_B
IO_L01N_2/INIT_B
T3
DUAL
2
IO_L01P_2/CSO_B
IO_L01P_2/CSO_B
IO_L01P_2/CSO_B
U3
DUAL
2
IO_L03N_2/MOSI/CSI_B
IO_L03N_2/MOSI/CSI_B
IO_L03N_2/MOSI/CSI_B
T4
DUAL
2
IO_L03P_2/DOUT/BUSY
IO_L03P_2/DOUT/BUSY
IO_L03P_2/DOUT/BUSY
U4
DUAL
2
IO_L04N_2
IO_L04N_2
IO_L04N_2
T5
I/O
2
IO_L04P_2
IO_L04P_2
IO_L04P_2
R5
I/O
2
IO_L05N_2
IO_L05N_2
IO_L05N_2
P6
I/O
2
IO_L05P_2
IO_L05P_2
IO_L05P_2
R6
I/O
2
N.C. ( )
IO_L06N_2/VREF_2
IO_L06N_2/VREF_2
V6
500E: N.C.
1200E: VREF
1600E: VREF
2
N.C. ( )
IO_L06P_2
IO_L06P_2
V5
500E: N.C.
1200E: I/O
1600E: I/O
44
2
IO_L07N_2
IO_L07N_2
IO_L07N_2
P7
I/O
2
IO_L07P_2
IO_L07P_2
IO_L07P_2
N7
I/O
2
IO_L09N_2
IO_L09N_2
IO_L09N_2
N8
I/O
2
IO_L09P_2
IO_L09P_2
IO_L09P_2
P8
I/O
2
IO_L10N_2
IO_L10N_2
IO_L10N_2
T8
I/O
2
IO_L10P_2
IO_L10P_2
IO_L10P_2
R8
I/O
2
IO_L12N_2/D6/GCLK13
IO_L12N_2/D6/GCLK13
IO_L12N_2/D6/GCLK13
M9
DUAL/GCLK
2
IO_L12P_2/D7/GCLK12
IO_L12P_2/D7/GCLK12
IO_L12P_2/D7/GCLK12
N9
DUAL/GCLK
2
IO_L13N_2/D3/GCLK15
IO_L13N_2/D3/GCLK15
IO_L13N_2/D3/GCLK15
V9
DUAL/GCLK
2
IO_L13P_2/D4/GCLK14
IO_L13P_2/D4/GCLK14
IO_L13P_2/D4/GCLK14
U9
DUAL/GCLK
2
IO_L15N_2/D1/GCLK3
IO_L15N_2/D1/GCLK3
IO_L15N_2/D1/GCLK3
P10
DUAL/GCLK
2
IO_L15P_2/D2/GCLK2
IO_L15P_2/D2/GCLK2
IO_L15P_2/D2/GCLK2
R10
DUAL/GCLK
2
IO_L16N_2/DIN/D0
IO_L16N_2/DIN/D0
IO_L16N_2/DIN/D0
N10
DUAL
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
FG320
Ball
Type
2
IO_L16P_2/M0
IO_L16P_2/M0
IO_L16P_2/M0
M10
DUAL
2
IO_L18N_2
IO_L18N_2
IO_L18N_2
N11
I/O
2
IO_L18P_2
IO_L18P_2
IO_L18P_2
P11
I/O
2
IO_L19N_2/VREF_2
IO_L19N_2/VREF_2
IO_L19N_2/VREF_2
V13
VREF
2
IO_L19P_2
IO_L19P_2
IO_L19P_2
V12
I/O
2
IO_L20N_2
IO_L20N_2
IO_L20N_2
R12
I/O
2
IO_L20P_2
IO_L20P_2
IO_L20P_2
T12
I/O
2
N.C. ( )
IO_L21N_2
IO_L21N_2
P12
500E: N.C.
1200E: I/O
1600E: I/O
2
N.C. ( )
IO_L21P_2
IO_L21P_2
N12
500E: N.C.
1200E: I/O
1600E: I/O
2
IO_L22N_2/A22
IO_L22N_2/A22
IO_L22N_2/A22
R13
DUAL
2
IO_L22P_2/A23
IO_L22P_2/A23
IO_L22P_2/A23
P13
DUAL
2
IO_L24N_2/A20
IO_L24N_2/A20
IO_L24N_2/A20
R14
DUAL
2
IO_L24P_2/A21
IO_L24P_2/A21
IO_L24P_2/A21
T14
DUAL
2
IO_L25N_2/VS1/A18
IO_L25N_2/VS1/A18
IO_L25N_2/VS1/A18
U15
DUAL
2
IO_L25P_2/VS2/A19
IO_L25P_2/VS2/A19
IO_L25P_2/VS2/A19
V15
DUAL
2
IO_L26N_2/CCLK
IO_L26N_2/CCLK
IO_L26N_2/CCLK
U16
DUAL
2
IO_L26P_2/VS0/A17
IO_L26P_2/VS0/A17
IO_L26P_2/VS0/A17
T16
DUAL
2
IP
IP
IP
V2
INPUT
2
IP
IP
IP
V16
INPUT
2
IP_L02N_2
IP_L02N_2
IP_L02N_2
V3
INPUT
2
IP_L02P_2
IP_L02P_2
IP_L02P_2
V4
INPUT
2
IP_L08N_2
IP_L08N_2
IP_L08N_2
R7
INPUT
2
IP_L08P_2
IP_L08P_2
IP_L08P_2
T7
INPUT
2
IP_L11N_2/VREF_2
IP_L11N_2/VREF_2
IP_L11N_2/VREF_2
V8
VREF
2
IP_L11P_2
IP_L11P_2
IP_L11P_2
U8
INPUT
2
IP_L14N_2/M2/GCLK1
IP_L14N_2/M2/GCLK1
IP_L14N_2/M2/GCLK1
T10
DUAL/GCLK
2
IP_L14P_2/RDWR_B/
GCLK0
IP_L14P_2/RDWR_B/
GCLK0
IP_L14P_2/RDWR_B/
GCLK0
U10
DUAL/GCLK
2
IP_L17N_2
IP_L17N_2
IP_L17N_2
U11
INPUT
2
IP_L17P_2
IP_L17P_2
IP_L17P_2
T11
INPUT
2
IP_L23N_2
IP_L23N_2
IP_L23N_2
U14
INPUT
2
IP_L23P_2
IP_L23P_2
IP_L23P_2
V14
INPUT
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
45
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
FG320
Ball
Type
2
VCCO_2
VCCO_2
VCCO_2
M8
VCCO
2
VCCO_2
VCCO_2
VCCO_2
M11
VCCO
2
VCCO_2
VCCO_2
VCCO_2
T6
VCCO
2
VCCO_2
VCCO_2
VCCO_2
T13
VCCO
2
VCCO_2
VCCO_2
VCCO_2
V10
VCCO
3
N.C. ( )
IO
IO
D4
500E: N.C.
1200E: I/O
1600E: I/O
3
IO_L01N_3
IO_L01N_3
IO_L01N_3
C2
I/O
3
IO_L01P_3
IO_L01P_3
IO_L01P_3
C1
I/O
3
IO_L02N_3/VREF_3
IO_L02N_3/VREF_3
IO_L02N_3/VREF_3
D2
VREF
3
IO_L02P_3
IO_L02P_3
IO_L02P_3
D1
I/O
3
IO_L03N_3
IO_L03N_3
IO_L03N_3
E1
I/O
3
IO_L03P_3
IO_L03P_3
IO_L03P_3
E2
I/O
3
N.C. ( )
IO_L04N_3
IO_L04N_3
E3
500E: N.C.
1200E: I/O
1600E: I/O
3
N.C. ( )
IO_L04P_3
IO_L04P_3
E4
500E: N.C.
1200E: I/O
1600E: I/O
46
3
IO_L05N_3
IO_L05N_3
IO_L05N_3
F2
I/O
3
IO_L05P_3
IO_L05P_3
IO_L05P_3
F1
I/O
3
IO_L06N_3/VREF_3
IO_L06N_3/VREF_3
IO_L06N_3/VREF_3
G4
VREF
3
IO_L06P_3
IO_L06P_3
IO_L06P_3
G3
I/O
3
IO_L07N_3
IO_L07N_3
IO_L07N_3
G5
I/O
3
IO_L07P_3
IO_L07P_3
IO_L07P_3
G6
I/O
3
IO_L08N_3
IO_L08N_3
IO_L08N_3
H5
I/O
3
IO_L08P_3
IO_L08P_3
IO_L08P_3
H6
I/O
3
IO_L09N_3
IO_L09N_3
IO_L09N_3
H3
I/O
3
IO_L09P_3
IO_L09P_3
IO_L09P_3
H4
I/O
3
IO_L10N_3
IO_L10N_3
IO_L10N_3
H1
I/O
3
IO_L10P_3
IO_L10P_3
IO_L10P_3
H2
I/O
3
IO_L11N_3/LHCLK1
IO_L11N_3/LHCLK1
IO_L11N_3/LHCLK1
J4
LHCLK
3
IO_L11P_3/LHCLK0
IO_L11P_3/LHCLK0
IO_L11P_3/LHCLK0
J5
LHCLK
3
IO_L12N_3/LHCLK3/
IRDY2
IO_L12N_3/LHCLK3/
IRDY2
IO_L12N_3/LHCLK3/
IRDY2
J2
LHCLK
3
IO_L12P_3/LHCLK2
IO_L12P_3/LHCLK2
IO_L12P_3/LHCLK2
J1
LHCLK
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Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
FG320
Ball
Type
3
IO_L13N_3/LHCLK5
IO_L13N_3/LHCLK5
IO_L13N_3/LHCLK5
K4
LHCLK
3
IO_L13P_3/LHCLK4/
TRDY2
IO_L13P_3/LHCLK4/
TRDY2
IO_L13P_3/LHCLK4/
TRDY2
K3
LHCLK
3
IO_L14N_3/LHCLK7
IO_L14N_3/LHCLK7
IO_L14N_3/LHCLK7
K5
LHCLK
3
IO_L14P_3/LHCLK6
IO_L14P_3/LHCLK6
IO_L14P_3/LHCLK6
K6
LHCLK
3
IO_L15N_3
IO_L15N_3
IO_L15N_3
L2
I/O
3
IO_L15P_3
IO_L15P_3
IO_L15P_3
L1
I/O
3
IO_L16N_3
IO_L16N_3
IO_L16N_3
L4
I/O
3
IO_L16P_3
IO_L16P_3
IO_L16P_3
L3
I/O
3
IO_L17N_3/VREF_3
IO_L17N_3/VREF_3
IO_L17N_3/VREF_3
L5
VREF
3
IO_L17P_3
IO_L17P_3
IO_L17P_3
L6
I/O
3
IO_L18N_3
IO_L18N_3
IO_L18N_3
M3
I/O
3
IO_L18P_3
IO_L18P_3
IO_L18P_3
M4
I/O
3
IO_L19N_3
IO_L19N_3
IO_L19N_3
M6
I/O
3
IO_L19P_3
IO_L19P_3
IO_L19P_3
M5
I/O
3
IO_L20N_3
IO_L20N_3
IO_L20N_3
N5
I/O
3
IO_L20P_3
IO_L20P_3
IO_L20P_3
N4
I/O
3
IO_L21N_3
IO_L21N_3
IO_L21N_3
P1
I/O
3
IO_L21P_3
IO_L21P_3
IO_L21P_3
P2
I/O
3
N.C. ( )
IO_L22N_3
IO_L22N_3
P4
500E: N.C.
1200E: I/O
1600E: I/O
3
N.C. ( )
IO_L22P_3
IO_L22P_3
P3
500E: N.C.
1200E: I/O
1600E: I/O
3
IO_L23N_3
IO_L23N_3
IO_L23N_3
R2
I/O
3
IO_L23P_3
IO_L23P_3
IO_L23P_3
R3
I/O
3
IO_L24N_3
IO_L24N_3
IO_L24N_3
T1
I/O
3
IO_L24P_3
IO_L24P_3
IO_L24P_3
T2
I/O
3
IP
IP
IP
D3
INPUT
3
IO
IP
IP
F4
500E: I/O
1200E: INPUT
1600E: INPUT
3
IP
IP
IP
F5
INPUT
3
IP
IP
IP
G1
INPUT
3
IP
IP
IP
J7
INPUT
3
IP
IP
IP
K2
INPUT
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
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47
R
Pinout Descriptions
Table 24: FG320 Package Pinout (Continued)
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
FG320
Ball
Type
3
IP
IP
IP
K7
INPUT
3
IP
IP
IP
M1
INPUT
3
IP
IP
IP
N1
INPUT
3
IP
IP
IP
N2
INPUT
3
IP
IP
IP
R1
INPUT
3
IP
IP
IP
U1
INPUT
3
IP/VREF_3
IP/VREF_3
IP/VREF_3
J6
VREF
3
IO/VREF_3
IP/VREF_3
IP/VREF_3
R4
500E: VREF(I/O)
1200E:
VREF(INPUT)
1600E:
VREF(INPUT)
48
3
VCCO_3
VCCO_3
VCCO_3
F3
VCCO
3
VCCO_3
VCCO_3
VCCO_3
H7
VCCO
3
VCCO_3
VCCO_3
VCCO_3
K1
VCCO
3
VCCO_3
VCCO_3
VCCO_3
L7
VCCO
3
VCCO_3
VCCO_3
VCCO_3
N3
VCCO
GND
GND
GND
GND
A1
GND
GND
GND
GND
GND
A18
GND
GND
GND
GND
GND
B2
GND
GND
GND
GND
GND
B17
GND
GND
GND
GND
GND
C10
GND
GND
GND
GND
GND
G7
GND
GND
GND
GND
GND
G12
GND
GND
GND
GND
GND
H8
GND
GND
GND
GND
GND
H9
GND
GND
GND
GND
GND
H10
GND
GND
GND
GND
GND
H11
GND
GND
GND
GND
GND
J3
GND
GND
GND
GND
GND
J8
GND
GND
GND
GND
GND
J11
GND
GND
GND
GND
GND
K8
GND
GND
GND
GND
GND
K11
GND
GND
GND
GND
GND
K16
GND
GND
GND
GND
GND
L8
GND
GND
GND
GND
GND
L9
GND
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DS312-4 (v1.1) March 21, 2005
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Table 24: FG320 Package Pinout (Continued)
Bank
XC3S500E Pin Name
XC3S1200E Pin Name
XC3S1600E Pin Name
FG320
Ball
Type
GND
GND
GND
GND
L10
GND
GND
GND
GND
GND
L11
GND
GND
GND
GND
GND
M7
GND
GND
GND
GND
GND
M12
GND
GND
GND
GND
GND
T9
GND
GND
GND
GND
GND
U2
GND
GND
GND
GND
GND
U17
GND
GND
GND
GND
GND
V1
GND
GND
GND
GND
GND
V18
GND
VCCAUX
DONE
DONE
DONE
V17
CONFIG
VCCAUX
PROG_B
PROG_B
PROG_B
B1
CONFIG
VCCAUX
TCK
TCK
TCK
A17
JTAG
VCCAUX
TDI
TDI
TDI
A2
JTAG
VCCAUX
TDO
TDO
TDO
C16
JTAG
VCCAUX
TMS
TMS
TMS
D15
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
B7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
B12
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
G2
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
G17
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
M2
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
M17
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
U7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
U12
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
E5
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
E14
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
F6
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
F13
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
N6
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
N13
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
P5
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
P14
VCCINT
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
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49
R
Pinout Descriptions
User I/Os by Bank
Table 25, Table 26, and Table 27 indicate how the available
user-I/O pins are distributed between the four I/O banks on
the FG320 package.
Table 25: User I/Os Per Bank for XC3S500E in the FG320 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
58
29
14
1
6
8
Right
1
58
22
10
21
5
0
Bottom
2
58
17
13
24
4
0
Left
3
58
34
11
0
5
8
232
102
48
46
20
16
TOTAL
Table 26: User I/Os Per Bank for XC3S1200E in the FG320 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
61
34
12
1
6
8
Right
1
63
25
12
21
5
0
Bottom
2
63
23
11
24
5
0
Left
3
63
38
12
0
5
8
250
120
47
46
21
16
TOTAL
Table 27: User I/Os Per Bank for XC3S1600E in the FG320 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
61
33
13
1
6
8
Right
1
63
25
12
21
5
0
Bottom
2
63
23
11
24
5
0
Left
3
63
38
12
0
5
8
250
119
48
46
21
16
TOTAL
Footprint Migration Differences
Table 28 summarizes any footprint and functionality differences between the XC3S500E, the XC3S1200E, and the
XC3S1600E FPGAs that may affect easy migration
between devices available in the FG320 package. There are
26 such balls. All other pins not listed in Table 28 unconditionally migrate between Spartan-3E devices available in
the FG320 package.
50
The XC3S500E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S1200E
and the XC3S1600E. The arrows indicate the direction for
easy migration. A double-ended arrow (
) indicates that
the two pins have identical functionality. A left-facing arrow
( ) indicates that the pin on the device on the right unconditionally migrates to the pin on the device on the left. It may
be possible to migrate the opposite direction depending on
the I/O configuration. For example, an I/O pin (Type = I/O)
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Pinout Descriptions
can migrate to an input-only pin (Type = INPUT) if the I/O
pin is configured as an input.
Table 28: FG320 Footprint Migration Differences
Pin
Bank
XC3S500E
A7
0
INPUT
I/O
I/O
INPUT
A12
0
N.C.
I/O
INPUT
N.C.
D4
3
N.C.
I/O
I/O
N.C.
D6
0
N.C.
I/O
I/O
N.C.
D13
0
INPUT
I/O
I/O
INPUT
E3
3
N.C.
I/O
I/O
N.C.
E4
3
N.C.
I/O
I/O
N.C.
E6
0
N.C.
I/O
I/O
N.C.
E15
1
N.C.
I/O
I/O
N.C.
E16
1
N.C.
I/O
I/O
N.C.
E17
1
I/O
INPUT
INPUT
I/O
F4
3
I/O
INPUT
INPUT
I/O
N12
2
N.C.
I/O
I/O
N.C.
N14
1
N.C.
I/O
I/O
N.C.
N15
1
N.C.
I/O
I/O
N.C.
P3
3
N.C.
I/O
I/O
N.C.
P4
3
N.C.
I/O
I/O
N.C.
P12
2
N.C.
I/O
I/O
N.C.
P15
1
I/O
INPUT
INPUT
I/O
P16
1
N.C.
I/O
I/O
N.C.
R4
3
VREF(I/O)
VREF(INPUT)
VREF(INPUT)
VREF(I/O)
U6
2
INPUT
I/O
I/O
INPUT
U13
2
INPUT
I/O
I/O
INPUT
V5
2
N.C.
I/O
I/O
N.C.
V6
2
N.C.
VREF
VREF
N.C.
V7
2
N.C.
I/O
I/O
N.C.
DIFFERENCES
Migration
XC3S1200E
26
Migration
1
XC3S1600E
Migration
XC3S500E
26
Legend:
This pin is identical on both the device on the left and the right.
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible
depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible
depending on how the pin is configured for the device on the left.
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51
R
Pinout Descriptions
FG320 Footprint
Bank 0
2
3
A
GND
TDI
INPUT
B
PROG_B
GND
L25N_0
HSWAP
4
D
E
F
G
H
Bank 3
J
K
L
I/O
I/O
I/O
L01P_3
L01N_3
L25P_0
I/O
L02P_3
I/O
I/O
L03N_3
L03P_3
I/O
I/O
L05P_3
L05N_3
INPUT
VCCAUX
I/O
L22P_0
L20N_0
I/O
INPUT
I/O
L24N_0
L22N_0
L20P_0
I/O
I/O
I/O
L04P_3
I/O
I/O
L07P_3
I/O
I/O
I/O
I/O
I/O
I/O
L10N_3
L10P_3
L09N_3
L09P_3
L08N_3
L08P_3
I/O
I/O
GND
L11N_3
LHCLK1
L11P_3
LHCLK0
I/O
I/O
L12P_3
LHCLK2
L12N_3
LHCLK3
IRDY2
VCCO_3
INPUT
I/O
I/O
I/O
L13N_3
LHCLK5
L14N_3
LHCLK7
L14P_3
LHCLK6
I/O
I/O
I/O
L15N_3
L16P_3
L16N_3
I/O
I/O
I/O
L18P_3
L19P_3
L19N_3
I/O
I/O
I/O
I/O
L21N_3
L21P_3
L22P_3
L22N_3
I/O
I/O
L23N_3
L23P_3
VREF_3
I/O
I/O
L24N_3
L24P_3
U
INPUT
GND
V
GND
INPUT
I/O
L17P_3
I/O
VCCO_3
INPUT
I/O
L17N_3
VREF_3
L18N_3
INPUT
INPUT
INPUT
VREF_3
I/O
I/O
I/O
I/O
L20P_3
L20N_3
I/O
I/O
L03N_2
MOSI
CSI_B
I/O
I/O
L01P_2
CSO_B
L03P_2
DOUT
BUSY
INPUT
INPUT
L02N_2
L02P_2
INPUT
L16P_0
VCCINT
INPUT
L16N_0
I/O
I/O
L14N_0
GCLK11
L11P_0
GCLK4
I/O
L15P_0
L11N_0
GCLK5
L01N_0
I/O
INPUT
L09P_0
L07P_0
I/O
INPUT
I/O
L04P_0
L02P_0
L01P_0
INPUT
TDO
I/O
INPUT
L09N_0
L07N_0
I/O
I/O
TMS
L23N_1
LDC0
L23P_1
HDC
I/O
I/O
L08P_0
L06N_0
I/O
VCCO_0
L03N_0
VREF_0
INPUT
I/O
L03P_0
I/O
I/O
VCCINT L22P_1
INPUT
I/O
I/O
L24N_1
LDC2
L24P_1
LDC1
INPUT
I/O
GND
VCCO_0
I/O
VCCO_0
GND
VCCO_3
GND
GND
GND
VCCO_1
I/O
I/O
I/O
I/O
I/O
INPUT
GND
GND
L15P_1
A2
L15N_1
A1
L14N_1
A3
RHCLK7
L14P_1
A4
4
RHCLK6
L13N_1
A5
RHCLK5
L13P_1
A6
RHCLK4
IRDY1
I/O
GND
INPUT
L10N_0
GND
INPUT
GND
VCCO_3
GND
GND
I/O
I/O
GND
VCCO_2
L12N_2
D6
GCLK13
L16P_2
M0
I/O
I/O
L07P_2
L09N_2
I/O
I/O
L12P_2
D7
GCLK12
L16N_2
DIN
D0
I/O
L15N_2
D1
GCLK3
I/O
I/O
L10P_2
D5
I/O
L08P_2
L10N_2
VCCAUX
I/O
INPUT
L11P_2
I/O
INPUT
L13P_2
D4
GCLK14
L14P_2
RDWR_B
GCLK0
INPUT
I/O
L11N_2
VREF_2
L13N_2
D3
GCLK15
I/O
I/O
L18P_1
L18N_1
INPUT
I/O
I/O
I/O
L17P_1
L17N_1
L16P_1
I/O
L11P_1
A10
RHCLK0
L12N_1
A7
RHCLK3
TRDY1
GND
VCCO_1
INPUT
INPUT
VCCO_2
GND
L05N_1
VREF_1
I/O
L21P_2
I/O
I/O
L18P_2
I/O
L14N_2
M2
GCLK1
I/O
L20P_1
I/O
L15P_2
D2
GCLK2
INPUT
GND
I/O
L11N_1
A9
RHCLK1
L18N_2
I/O
I/O
I/O
INPUT
I/O
L17P_2
L20P_2
INPUT
L17N_2
VCCO_2
L04P_1
VCCO_1
INPUT
I/O
VCCAUX
I/O
I/O
M1
L19P_2
I/O
L24N_2
A20
VCCO_2
L24P_2
A21
INPUT
INPUT
I/O
L23N_2
I/O
L19N_2
VREF_2
INPUT
L23P_2
I/O
L16N_1
A0
INPUT
VREF_1
I/O
I/O
I/O
VCCINT L04N_1
I/O
INPUT
L10N_1
VREF_1
I/O
L22N_2
A22
VCCAUX
I/O
L07N_1
VCCINT
I/O
L19P_1
L09P_1
A12
I/O
I/O
I/O
I/O
L07P_1
L22P_2
A23
INPUT
L19N_1
L09N_1
A11
I/O
I/O
INPUT
VREF_1
VCCO_1
I/O
L12P_1
A8
RHCLK2
L05P_1
L21N_2
L20N_2
VCCO_1
L20N_1
GND
I/O
L08N_2
INPUT
GND
I/O
L21P_1
GND
L06P_0
INPUT
I/O
GND
I/O
VCCINT
L21N_1
I/O
L22N_1
TCK
L08N_0
INPUT
I/O
I/O
L02N_0
L10P_0
I/O
L06N_2
VREF_2
INPUT
INPUT
L05P_2
I/O
I/O
L04N_0
L05N_0
VREF_0
18
I/O
I/O
L06P_2
I/O
L05P_0
I/O
VCCAUX
17
L15N_0
L04P_2
INPUT
I/O
VREF_0
16
I/O
I/O
I/O
15
L17N_0
L09P_2
VREF_2
14
I/O
I/O
VCCO_2
13
L19P_0
L07N_2
I/O
I/O
I/O
I/O
L17P_0
I/O
L04N_2
GND
12
INPUT
I/O
L14P_0
GCLK10
L05N_2
VCCINT
INPUT
L01N_2
INIT_B
I/O
L18P_0
I/O
L13P_3
LHCLK4
TRDY2
L15P_3
I/O
L19N_0
VREF_0
11
L12N_0
GCLK7
L12P_0
GCLK6
I/O
I/O
VCCO_0
L13N_0
GCLK9
L18N_0
VREF_0
L07N_3
I/O
INPUT
I/O
INPUT VCCINT
10
I/O
L13P_0
GCLK8
L21P_0
I/O
VCCINT L21N_0
9
INPUT
I/O
I/O
N
T
VCCO_0
8
VCCAUX
L23N_0
VREF_0
L06N_3
VREF_3
VCCAUX
R
L23P_0
INPUT
M INPUT
P
I/O
I/O
L04N_3
L06P_3
INPUT
INPUT
INPUT
VCCO_3
7
I/O
I/O
L02N_3
VREF_3
6
L24P_0
I/O
C
5
VCCAUX
I/O
I/O
L03P_1
I/O
VREF_2
INPUT
I/O
L10P_1
I/O
L08N_1
I/O
L08P_1
I/O
I/O
L06P_1
L06N_1
INPUT
L02P_1
A14
I/O
L03N_1
VREF_1
INPUT
Bank 1
1
I/O
I/O
I/O
I/O
L26P_2
VS0
A17
L01N_1
A15
L02N_1
A13
I/O
I/O
L25N_2
VS1
A18
L26N_2
CCLK
GND
L01P_1
A16
INPUT
DONE
GND
I/O
I/O
L25P_2
VS2
A19
Bank 2
DS312-4_06_021605
Figure 8: FG320 Package Footprint (top view)
52
I/O: Unrestricted,
general-purpose user I/O
46
DUAL: Configuration pin, then
possible user-I/O
INPUT: Unrestricted,
general-purpose input pin
16
GCLK: User I/O, input, or
global buffer input
2
CONFIG: Dedicated
configuration pins
4
0
N.C.: Not connected
28
VREF: User I/O or input
voltage reference for bank
20
VCCO: Output voltage supply
for bank
JTAG: Dedicated JTAG port
pins
8
VCCINT: Internal core supply
voltage (+1.2V)
GND: Ground
8
VCCAUX: Auxiliary supply
voltage (+2.5V)
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
FG400: 400-ball Fine-pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FG400, supports two
different Spartan-3E FPGAs, including the XC3S1200E and
the XC3S1600E. Both devices share a common footprint for
this package as shown in Table 29 and Figure 9.
Table 29 lists all the FG400 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
Table 29: FG400 Package Pinout
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
0
IO_L09P_0
A14
I/O
0
IO_L10N_0
B13
I/O
0
IO_L10P_0
C13
I/O
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
0
IO_L11N_0
C12
I/O
0
IO_L11P_0
D12
I/O
0
IO_L12N_0
E12
I/O
Pinout Table
0
IO_L12P_0
F12
I/O
0
IO_L14N_0/GCLK5
G11
GCLK
0
IO_L14P_0/GCLK4
F11
GCLK
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
Bank
FG400
Ball
0
IO_L15N_0/GCLK7
E10
GCLK
Type
0
IO_L15P_0/GCLK6
E11
GCLK
0
IO
A3
I/O
0
IO_L17N_0/GCLK11
A9
GCLK
0
IO
A8
I/O
0
IO_L17P_0/GCLK10
A10
GCLK
0
IO
A12
I/O
0
IO_L18N_0
F9
I/O
0
IO
C7
I/O
0
IO_L18P_0
E9
I/O
0
IO
C10
I/O
0
IO_L20N_0
C9
I/O
0
IO
E8
I/O
0
IO_L20P_0
D9
I/O
0
IO
E13
I/O
0
IO_L21N_0/VREF_0
B8
VREF
0
IO
E16
I/O
0
IO_L21P_0
B9
I/O
0
IO
F13
I/O
0
IO_L23N_0/VREF_0
F7
VREF
0
IO
F14
I/O
0
IO_L23P_0
F8
I/O
0
IO
G7
I/O
0
IO_L24N_0
A6
I/O
0
IO/VREF_0
C11
VREF
0
IO_L24P_0
A7
I/O
0
IO_L01N_0
B17
I/O
0
IO_L26N_0
B5
I/O
0
IO_L01P_0
C17
I/O
0
IO_L26P_0
B6
I/O
0
IO_L03N_0/VREF_0
A18
VREF
0
IO_L27N_0
D6
I/O
0
IO_L03P_0
A19
I/O
0
IO_L27P_0
C6
I/O
0
IO_L04N_0
A17
I/O
0
IO_L29N_0/VREF_0
C5
VREF
0
IO_L04P_0
A16
I/O
0
IO_L29P_0
D5
I/O
0
IO_L06N_0
A15
I/O
0
IO_L30N_0
A2
I/O
0
IO_L06P_0
B15
I/O
0
IO_L30P_0
B2
I/O
0
IO_L07N_0
C14
I/O
0
IO_L31N_0/HSWAP
D4
DUAL
0
IO_L07P_0
D14
I/O
0
IO_L31P_0
C4
I/O
0
IO_L09N_0/VREF_0
A13
VREF
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
53
R
Pinout Descriptions
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
Bank
54
Table 29: FG400 Package Pinout
FG400
Ball
Type
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
0
IP
B18
INPUT
1
IO_L04N_1
W20
I/O
0
IP
E5
INPUT
1
IO_L04P_1
V20
I/O
0
IP_L02N_0
C16
INPUT
1
IO_L05N_1
R18
I/O
0
IP_L02P_0
D16
INPUT
1
IO_L05P_1
R17
I/O
0
IP_L05N_0
D15
INPUT
1
IO_L06N_1
T20
I/O
0
IP_L05P_0
C15
INPUT
1
IO_L06P_1
U20
I/O
0
IP_L08N_0
E14
INPUT
1
IO_L07N_1
P18
I/O
0
IP_L08P_0
E15
INPUT
1
IO_L07P_1
P17
I/O
0
IP_L10N_0
G14
INPUT
1
IO_L08N_1/VREF_1
P20
VREF
0
IP_L10P_0
G13
INPUT
1
IO_L08P_1
R20
I/O
0
IP_L13N_0
B11
INPUT
1
IO_L09N_1
P16
I/O
0
IP_L13P_0
B12
INPUT
1
IO_L09P_1
N16
I/O
0
IP_L16N_0/GCLK9
G10
GCLK
1
IO_L10N_1
N19
I/O
0
IP_L16P_0/GCLK8
H10
GCLK
1
IO_L10P_1
N18
I/O
0
IP_L19N_0
G9
INPUT
1
IO_L11N_1
N15
I/O
0
IP_L19P_0
G8
INPUT
1
IO_L11P_1
M15
I/O
0
IP_L22N_0
C8
INPUT
1
IO_L12N_1/A11
M18
DUAL
0
IP_L22P_0
D8
INPUT
1
IO_L12P_1/A12
M17
DUAL
0
IP_L25N_0
E6
INPUT
1
IO_L13N_1/VREF_1
L19
VREF
0
IP_L25P_0
E7
INPUT
1
IO_L13P_1
M19
I/O
0
IP_L28N_0
A4
INPUT
1
IO_L14N_1/A9/RHCLK1
L16
0
IP_L28P_0
A5
INPUT
RHCLK/
DUAL
0
VCCO_0
B4
VCCO
1
IO_L14P_1/A10/RHCLK0
M16
RHCLK/
DUAL
0
VCCO_0
B10
VCCO
1
VCCO_0
B16
VCCO
IO_L15N_1/A7/RHCLK3/
TRDY1
L14
0
RHCLK/
DUAL
0
VCCO_0
D7
VCCO
1
IO_L15P_1/A8/RHCLK2
L15
RHCLK/
DUAL
0
VCCO_0
D13
VCCO
1
IO_L16N_1/A5/RHCLK5
K14
0
VCCO_0
F10
VCCO
RHCLK/
DUAL
1
IO_L01N_1/A15
U18
DUAL
1
K13
1
IO_L01P_1/A16
U17
DUAL
IO_L16P_1/A6/RHCLK4/
IRDY1
RHCLK/
DUAL
1
IO_L02N_1/A13
T18
DUAL
1
IO_L17N_1/A3/RHCLK7
J20
RHCLK/
DUAL
1
IO_L02P_1/A14
T17
DUAL
1
IO_L17P_1/A4/RHCLK6
K20
1
IO_L03N_1/VREF_1
V19
VREF
RHCLK/
DUAL
1
IO_L03P_1
U19
I/O
1
IO_L18N_1/A1
K16
DUAL
1
IO_L18P_1/A2
J16
DUAL
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
Bank
Table 29: FG400 Package Pinout
FG400
Ball
Type
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
1
IO_L19N_1/A0
J13
DUAL
1
IP
R16
INPUT
1
IO_L19P_1
J14
I/O
1
IP
R19
INPUT
1
IO_L20N_1
J17
I/O
1
IP/VREF_1
E19
VREF
1
IO_L20P_1
J18
I/O
1
IP/VREF_1
K18
VREF
1
IO_L21N_1
H19
I/O
1
VCCO_1
D19
VCCO
1
IO_L21P_1
J19
I/O
1
VCCO_1
G17
VCCO
1
IO_L22N_1
H15
I/O
1
VCCO_1
K15
VCCO
1
IO_L22P_1
H16
I/O
1
VCCO_1
K19
VCCO
1
IO_L23N_1
H18
I/O
1
VCCO_1
N17
VCCO
1
IO_L23P_1
H17
I/O
1
VCCO_1
T19
VCCO
1
IO_L24N_1/VREF_1
H20
VREF
2
IO
P8
I/O
1
IO_L24P_1
G20
I/O
2
IO
P13
I/O
1
IO_L25N_1
G16
I/O
2
IO
R9
I/O
1
IO_L25P_1
F16
I/O
2
IO
R13
I/O
1
IO_L26N_1
F19
I/O
2
IO
W15
I/O
1
IO_L26P_1
F20
I/O
2
IO
Y5
I/O
1
IO_L27N_1
F18
I/O
2
IO
Y7
I/O
1
IO_L27P_1
F17
I/O
2
IO
Y13
I/O
1
IO_L28N_1
D20
I/O
2
IO/D5
N11
DUAL
1
IO_L28P_1
E20
I/O
2
IO/M1
T11
DUAL
1
IO_L29N_1/LDC0
D18
DUAL
2
IO/VREF_2
Y3
VREF
1
IO_L29P_1/HDC
E18
DUAL
2
IO/VREF_2
Y17
VREF
1
IO_L30N_1/LDC2
C19
DUAL
2
IO_L01N_2/INIT_B
V4
DUAL
1
IO_L30P_1/LDC1
C20
DUAL
2
IO_L01P_2/CSO_B
U4
DUAL
1
IP
B20
INPUT
2
IO_L03N_2/MOSI/CSI_B
V5
DUAL
1
IP
G15
INPUT
2
IO_L03P_2/DOUT/BUSY
U5
DUAL
1
IP
G18
INPUT
2
IO_L04N_2
Y4
I/O
1
IP
H14
INPUT
2
IO_L04P_2
W4
I/O
1
IP
J15
INPUT
2
IO_L06N_2
T6
I/O
1
IP
L18
INPUT
2
IO_L06P_2
T5
I/O
1
IP
M20
INPUT
2
IO_L07N_2
U7
I/O
1
IP
N14
INPUT
2
IO_L07P_2
V7
I/O
1
IP
N20
INPUT
2
IO_L09N_2/VREF_2
R7
VREF
1
IP
P15
INPUT
2
IO_L09P_2
T7
I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
55
R
Pinout Descriptions
Table 29: FG400 Package Pinout
Bank
FG400
Ball
Type
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
2
IO_L10N_2
V8
I/O
2
IO_L32P_2/VS0/A17
Y19
DUAL
2
IO_L10P_2
W8
I/O
2
IP
T16
INPUT
2
IO_L12N_2
U9
I/O
2
IP
W3
INPUT
2
IO_L12P_2
V9
I/O
2
IP_L02N_2
Y2
INPUT
2
IO_L13N_2
Y8
I/O
2
IP_L02P_2
W2
INPUT
2
IO_L13P_2
Y9
I/O
2
IP_L05N_2
V6
INPUT
2
IO_L15N_2/D6/GCLK13
W10
DUAL/
GCLK
2
IP_L05P_2
U6
INPUT
2
IP_L08N_2
Y6
INPUT
2
IO_L15P_2/D7/GCLK12
W9
DUAL/
GCLK
2
IP_L08P_2
W6
INPUT
2
IO_L16N_2/D3/GCLK15
P10
DUAL/
GCLK
2
IP_L11N_2
R8
INPUT
2
IP_L11P_2
T8
INPUT
2
IP_L14N_2/VREF_2
T10
VREF
2
IP_L14P_2
T9
INPUT
2
IP_L17N_2/M2/GCLK1
P12
DUAL/
GCLK
2
IP_L17P_2/RDWR_B/
GCLK0
P11
DUAL/
GCLK
2
IP_L20N_2
T12
INPUT
2
IP_L20P_2
R12
INPUT
2
IP_L23N_2/VREF_2
T13
VREF
2
IP_L23P_2
T14
INPUT
2
IP_L26N_2
V14
INPUT
2
IP_L26P_2
V15
INPUT
2
IP_L29N_2
W16
INPUT
2
IP_L29P_2
Y16
INPUT
2
VCCO_2
R11
VCCO
2
VCCO_2
U8
VCCO
2
VCCO_2
U14
VCCO
2
VCCO_2
W5
VCCO
2
VCCO_2
W11
VCCO
2
VCCO_2
W17
VCCO
3
IO_L01N_3
D2
I/O
3
IO_L01P_3
D3
I/O
3
IO_L02N_3/VREF_3
E3
VREF
3
IO_L02P_3
E4
I/O
2
IO_L16P_2/D4/GCLK14
R10
DUAL/
GCLK
2
IO_L18N_2/D1/GCLK3
V11
DUAL/
GCLK
2
56
XC3S1200E
XC3S1600E
Pin Name
Table 29: FG400 Package Pinout
IO_L18P_2/D2/GCLK2
V10
DUAL/
GCLK
2
IO_L19N_2/DIN/D0
Y12
DUAL
2
IO_L19P_2/M0
Y11
DUAL
2
IO_L21N_2
U12
I/O
2
IO_L21P_2
V12
I/O
2
IO_L22N_2/VREF_2
W12
VREF
2
IO_L22P_2
W13
I/O
2
IO_L24N_2
U13
I/O
2
IO_L24P_2
V13
I/O
2
IO_L25N_2
P14
I/O
2
IO_L25P_2
R14
I/O
2
IO_L27N_2/A22
Y14
DUAL
2
IO_L27P_2/A23
Y15
DUAL
2
IO_L28N_2
T15
I/O
2
IO_L28P_2
U15
I/O
2
IO_L30N_2/A20
V16
DUAL
2
IO_L30P_2/A21
U16
DUAL
2
IO_L31N_2/VS1/A18
Y18
DUAL
2
IO_L31P_2/VS2/A19
W18
DUAL
2
IO_L32N_2/CCLK
W19
DUAL
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 29: FG400 Package Pinout
Bank
XC3S1200E
XC3S1600E
Pin Name
Table 29: FG400 Package Pinout
FG400
Ball
Type
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
3
IO_L03N_3
C1
I/O
3
IO_L20N_3/VREF_3
N6
VREF
3
IO_L03P_3
B1
I/O
3
IO_L20P_3
M6
I/O
3
IO_L04N_3
E1
I/O
3
IO_L21N_3
N2
I/O
3
IO_L04P_3
D1
I/O
3
IO_L21P_3
N1
I/O
3
IO_L05N_3
F3
I/O
3
IO_L22N_3
P7
I/O
3
IO_L05P_3
F4
I/O
3
IO_L22P_3
N7
I/O
3
IO_L06N_3
F1
I/O
3
IO_L23N_3
N4
I/O
3
IO_L06P_3
F2
I/O
3
IO_L23P_3
N3
I/O
3
IO_L07N_3
G4
I/O
3
IO_L24N_3
R1
I/O
3
IO_L07P_3
G3
I/O
3
IO_L24P_3
P1
I/O
3
IO_L08N_3
G5
I/O
3
IO_L25N_3
R5
I/O
3
IO_L08P_3
H5
I/O
3
IO_L25P_3
P5
I/O
3
IO_L09N_3/VREF_3
H3
VREF
3
IO_L26N_3
T2
I/O
3
IO_L09P_3
H2
I/O
3
IO_L26P_3
R2
I/O
3
IO_L10N_3
H7
I/O
3
IO_L27N_3
R4
I/O
3
IO_L10P_3
H6
I/O
3
IO_L27P_3
R3
I/O
3
IO_L11N_3
J4
I/O
3
IO_L28N_3/VREF_3
T1
VREF
3
IO_L11P_3
J3
I/O
3
IO_L28P_3
U1
I/O
3
IO_L12N_3
J1
I/O
3
IO_L29N_3
T3
I/O
3
IO_L12P_3
J2
I/O
3
IO_L29P_3
U3
I/O
3
IO_L13N_3
J6
I/O
3
IO_L30N_3
V1
I/O
3
IO_L13P_3
K6
I/O
3
IO_L30P_3
V2
I/O
3
IO_L14N_3/LHCLK1
K2
LHCLK
3
IP
F5
INPUT
3
IO_L14P_3/LHCLK0
K3
LHCLK
3
IP
G1
INPUT
3
IO_L15N_3/LHCLK3/IRDY2
L7
LHCLK
3
IP
G6
INPUT
3
IO_L15P_3/LHCLK2
K7
LHCLK
3
IP
H1
INPUT
3
IO_L16N_3/LHCLK5
L1
LHCLK
3
IP
J5
INPUT
3
IO_L16P_3/LHCLK4/TRDY2
M1
LHCLK
3
IP
L5
INPUT
3
IO_L17N_3/LHCLK7
L3
LHCLK
3
IP
L8
INPUT
3
IO_L17P_3/LHCLK6
M3
LHCLK
3
IP
M2
INPUT
3
IO_L18N_3
M7
I/O
3
IP
N5
INPUT
3
IO_L18P_3
M8
I/O
3
IP
P3
INPUT
3
IO_L19N_3
M4
I/O
3
IP
T4
INPUT
3
IO_L19P_3
M5
I/O
3
IP
W1
INPUT
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
57
R
Pinout Descriptions
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
Bank
58
Table 29: FG400 Package Pinout
FG400
Ball
Type
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
3
IP/VREF_3
K5
VREF
GND
GND
M10
GND
3
IP/VREF_3
P6
VREF
GND
GND
M12
GND
3
VCCO_3
E2
VCCO
GND
GND
N13
GND
3
VCCO_3
H4
VCCO
GND
GND
P2
GND
3
VCCO_3
L2
VCCO
GND
GND
P9
GND
3
VCCO_3
L6
VCCO
GND
GND
P19
GND
3
VCCO_3
P4
VCCO
GND
GND
R6
GND
3
VCCO_3
U2
VCCO
GND
GND
R15
GND
GND
GND
A1
GND
GND
GND
U11
GND
GND
GND
A11
GND
GND
GND
V3
GND
GND
GND
A20
GND
GND
GND
V18
GND
GND
GND
B7
GND
GND
GND
W7
GND
GND
GND
B14
GND
GND
GND
W14
GND
GND
GND
C3
GND
GND
GND
Y1
GND
GND
GND
C18
GND
GND
GND
Y10
GND
GND
GND
D10
GND
GND
GND
Y20
GND
GND
GND
F6
GND
VCCAUX
DONE
V17
CONFIG
GND
GND
F15
GND
VCCAUX
PROG_B
C2
CONFIG
GND
GND
G2
GND
VCCAUX
TCK
D17
JTAG
GND
GND
G12
GND
VCCAUX
TDI
B3
JTAG
GND
GND
G19
GND
VCCAUX
TDO
B19
JTAG
GND
GND
H8
GND
VCCAUX
TMS
E17
JTAG
GND
GND
J9
GND
VCCAUX
VCCAUX
D11
VCCAUX
GND
GND
J11
GND
VCCAUX
VCCAUX
H12
VCCAUX
GND
GND
K1
GND
VCCAUX
VCCAUX
J7
VCCAUX
GND
GND
K8
GND
VCCAUX
VCCAUX
K4
VCCAUX
GND
GND
K10
GND
VCCAUX
VCCAUX
L17
VCCAUX
GND
GND
K12
GND
VCCAUX
VCCAUX
M14
VCCAUX
GND
GND
K17
GND
VCCAUX
VCCAUX
N9
VCCAUX
GND
GND
L4
GND
VCCAUX
VCCAUX
U10
VCCAUX
GND
GND
L9
GND
VCCINT
VCCINT
H9
VCCINT
GND
GND
L11
GND
VCCINT
VCCINT
H11
VCCINT
GND
GND
L13
GND
VCCINT
VCCINT
H13
VCCINT
GND
GND
L20
GND
VCCINT
VCCINT
J8
VCCINT
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 29: FG400 Package Pinout
Table 29: FG400 Package Pinout
XC3S1200E
XC3S1600E
Pin Name
Bank
FG400
Ball
Type
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
VCCINT
VCCINT
J10
VCCINT
VCCINT
VCCINT
M13
VCCINT
VCCINT
VCCINT
J12
VCCINT
VCCINT
VCCINT
N8
VCCINT
VCCINT
VCCINT
K9
VCCINT
VCCINT
VCCINT
N10
VCCINT
VCCINT
VCCINT
K11
VCCINT
VCCINT
VCCINT
N12
VCCINT
VCCINT
VCCINT
L10
VCCINT
VCCINT
VCCINT
L12
VCCINT
VCCINT
VCCINT
M9
VCCINT
VCCINT
VCCINT
M11
VCCINT
User I/Os by Bank
Table 30 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG400 package.
Table 30: User I/Os Per Bank for the XC3S250E and XC3S500E in the FG400 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
78
43
20
1
6
8
Right
1
74
35
12
21
6
0
Bottom
2
78
30
18
24
6
0
Left
3
74
48
12
0
6
8
304
156
62
46
24
16
TOTAL
Footprint Migration Differences
The XC3S1200E and XC3S1600E FPGAs have identical
footprints in the FG400 package. Designs can migrate
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
between the XC3S1200E and XC3S1600E FPGAs without
further consideration.
www.xilinx.com
59
R
Pinout Descriptions
FG400 Footprint
Bank 0
1
Left Half of Package
(top view)
62
46
24
16
2
4
42
I/O
3
4
I/O
I/O
L28P_0
L24N_0
L24P_0
I/O
I/O
L03P_3
L30P_0
C
L03N_3
D
I/O
I/O
I/O
L04P_3
L01N_3
L01P_3
E
L04N_3
VCCO_3
L02N_3
VREF_3
F
I/O
I/O
I/O
I/O
L06N_3
L06P_3
L05N_3
L05P_3
G
INPUT
GND
CONFIG: Dedicated
configuration pins
H
INPUT
JTAG: Dedicated JTAG
port pins
J
I/O
I/O
I/O
I/O
L12N_3
L12P_3
L11P_3
L11N_3
I/O
I/O
K
GND
L14N_3
LHCLK1
L14P_3
LHCLK0
L
L16N_3
LHCLK5
VCCO_3
L17N_3
LHCLK7
L16P_3
LHCLK4
TRDY2
INPUT
L17P_3
LHCLK6
INPUT: User I/O or
reference resistor input for
bank
DUAL: Configuration pin,
then possible user I/O
VREF: User I/O or input
voltage reference for bank
GCLK: User I/O, input, or
clock buffer input
I/O
PROG_B
TDI
GND
I/O
I/O
GND: Ground
I/O
L09P_3
VCCO_0
I/O
L31P_0
I/O
L31N_0
HSWAP
I/O
L02P_3
I/O
I/O
L26N_0
L26P_0
I/O
I/O
I/O
L27N_0
INPUT
I/O
I/O
L08N_3
VCCAUX
L23N_0
VREF_0
INPUT
I/O
I/O
L13N_3
INPUT
I/O
VREF_3
L13P_3
INPUT
VCCO_3
VCCAUX: Auxiliary supply
voltage (+2.5V)
N
I/O
I/O
I/O
I/O
L21P_3
L21N_3
L23P_3
L23N_3
P
L24P_3
GND
INPUT
VCCO_3
R
I/O
I/O
I/O
I/O
I/O
L24N_3
L26P_3
L27P_3
L27N_3
L25N_3
I/O
I/O
L28N_3
VREF_3
I/O
I/O
I/O
L26N_3
L29N_3
U
L28P_3
V
I/O
I/O
L30N_3
L30P_3
W
INPUT
Y
GND
VCCO_3
INPUT
L02P_2
I/O
L29P_3
GND
INPUT
I/O
VCCAUX
L21N_0
VREF_0
9
10
I/O
I/O
L17N_0
GCLK11
L17P_0
GCLK10
I/O
L21P_0
INPUT
I/O
L22N_0
L20N_0
INPUT
I/O
L22P_0
L20P_0
I/O
I/O
L18P_0
VCCO_0
I/O
GND
I/O
L15N_0
GCLK7
I/O
I/O
L23P_0
L18N_0
INPUT
INPUT
L19P_0
L19N_0
GND
VCCINT
L16P_0
GCLK8
VCCINT
GND
VCCINT
GND
VCCINT
GND
INPUT
GND
VCCINT
VCCINT
GND
VCCO_0
INPUT
L16N_0
GCLK9
INPUT
I/O
L15P_3
LHCLK2
I/O
I/O
I/O
T
GND
I/O
M
N.C.: Not connected
L25P_0
L10N_3
VCCINT: Internal core
supply voltage (+1.2V)
0
INPUT
L25N_0
I/O
16
8
INPUT
L10P_3
VCCO: Output voltage
supply for bank
I/O
VCCO_0
I/O
24
I/O
I/O
L08P_3
INPUT
8
I/O
GND
I/O
INPUT
L07N_3
VCCO_3
L27P_0
L29P_0
I/O
I/O
I/O
L29N_0
VREF_0
L07P_3
L09N_3
VREF_3
7
INPUT
B
I/O: Unrestricted,
general-purpose user I/O
I/O
6
L28N_0
GND
L30N_0
5
INPUT
A
Bank 3
156
2
GND
L15N_3
LHCLK3
IRDY2
I/O
I/O
I/O
I/O
I/O
L19N_3
L19P_3
L20P_3
L18N_3
L18P_3
INPUT
L20N_3
VREF_3
INPUT
I/O
I/O
INPUT
I/O
L25P_3
VREF_3
L22N_3
GND
L09N_2
VREF_2
INPUT
L11P_2
L14P_2
I/O
I/O
I/O
INPUT
L03N_2
MOSI
CSI_B
L04N_2
L16P_2
D4
GCLK14
I/O
I/O
I/O
I/O
L09P_2
L01N_2
INIT_B
VREF_2
L11N_2
L16N_2
D3
GCLK15
I/O
I/O
L02N_2
INPUT
GND
L06N_2
L03P_2
DOUT
BUSY
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT VCCAUX VCCINT
L06P_2
L01P_2
CSO_B
L04P_2
I/O
L22P_3
INPUT
I/O
L05P_2
L07N_2
I/O
I/O
I/O
L05N_2
L07P_2
L10N_2
L12P_2
L08P_2
INPUT
I/O
I/O
L12N_2
INPUT
INPUT
VCCO_2
VCCO_2
L08N_2
Bank 2
GND
I/O
I/O
L10P_2
INPUT
L14N_2
VREF_2
VCCAUX
I/O
L18P_2
D2
GCLK2
I/O
I/O
L15P_2
D7
GCLK12
L15N_2
D6
GCLK13
I/O
I/O
L13N_2
L13P_2
GND
DS312-4_08_031105
Figure 9: FG400 Package Footprint (top view)
60
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Bank 0
12
13
I/O
GND
I/O
INPUT
INPUT
I/O
L13N_0
L13P_0
L10N_0
L09N_0
VREF_0
14
15
16
17
I/O
I/O
I/O
I/O
L09P_0
L06N_0
L04P_0
L04N_0
GND
I/O
L06P_0
VCCO_0
I/O
L01N_0
I/O
I/O
I/O
I/O
INPUT
INPUT
I/O
VREF_0
L11N_0
L10P_0
L07N_0
L05P_0
L02N_0
L01P_0
VCCAUX
I/O
L15P_0
GCLK6
I/O
L14P_0
GCLK4
I/O
L11P_0
I/O
L12N_0
I/O
L12P_0
I/O
L14N_0
GCLK5
GND
I/O
INPUT
INPUT
L07P_0
L05N_0
L02P_0
INPUT
INPUT
L08N_0
L08P_0
I/O
I/O
GND
INPUT
INPUT
L10P_0
L10N_0
VCCO_0
I/O
VCCINT VCCAUX VCCINT
I/O
GND
VCCINT
VCCINT
GND
GND
VCCINT
VCCINT
GND
L19N_1
A0
I/O
L16P_1
A6
RHCLK4
IRDY1
INPUT
I/O
L19P_1
I/O
D5
VCCINT
INPUT
INPUT
L17P_2
RDWR_B
GCLK0
L17N_2
M2
GCLK1
VCCO_2
INPUT
L20P_2
I/O
INPUT
M1
L20N_2
GND
I/O
L18N_2
D1
GCLK3
VCCINT VCCAUX
GND
I/O
I/O
INPUT
L23N_2
VREF_2
I/O
I/O
L21N_2
L24N_2
INPUT
I/O
L25N_2
I/O
L25P_2
I/O
I/O
I/O
I/O
I/O
L27P_1
L27N_1
L26N_1
L26P_1
VCCO_1
INPUT
GND
I/O
L25N_1
I/O
I/O
I/O
L20N_1
L20P_1
L21P_1
I/O
I/O
I/O
L15P_1
A8
RHCLK2
L14N_1
A9
RHCLK1
I/O
L28P_2
I/O
I/O
I/O
L27N_2
A22
L27P_2
A23
INPUT
I/O
I/O
L12N_1
A11
I/O
VCCO_1
I/O
L13P_1
I/O
L10N_1
I/O
I/O
L07P_1
L07N_1
I/O
I/O
L05P_1
L05N_1
I/O
I/O
L02P_1
A14
L02N_1
A13
INPUT
VCCO_1
I/O
I/O
I/O
L01P_1
A16
L01N_1
A15
DONE
GND
I/O
I/O
VCCO_2
L31P_2
VS2
A19
L32N_2
CCLK
I/O
INPUT
L29N_2
G
H
I/O
L17N_1
A3
RHCLK7
J
L17P_1
A4
RHCLK6
K
GND
L
INPUT
M
INPUT
N
L08N_1
VREF_1
I/O
L08P_1
I/O
L06N_1
I/O
I/O
L03P_1
L06P_1
I/O
INPUT
I/O
L29P_2
VREF_2
L03N_1
VREF_1
I/O
I/O
L31N_2
VS1
A18
L32P_2
VS0
A17
I/O
L04P_1
I/O
P
R
T
U
V
L04N_1
W
GND
Y
Bank 2
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
F
I/O
GND
L30P_2
A21
L30N_2
A20
E
I/O
L24N_1
VREF_1
L13N_1
VREF_1
I/O
I/O
INPUT
D
I/O
VCCO_1
L10P_1
L09N_1
INPUT
I/O
L24P_1
Right Half of Package
(top view)
C
I/O
VCCAUX
L12P_1
A12
L09P_1
I/O
INPUT
VREF_1
I/O
I/O
L28N_2
GND
L14P_1
A10
RHCLK0
L11N_1
GND
I/O
I/O
L28P_1
L18N_1
A1
L26P_2
I/O
INPUT
VREF_1
VCCO_1
INPUT
L19N_2
DIN
D0
L29P_1
HDC
I/O
L28N_1
L25P_1
I/O
L26N_2
I/O
TMS
VCCO_1
L18P_1
A2
INPUT
L19P_2
M0
L29N_1
LDC0
INPUT
I/O
I/O
I/O
TCK
I/O
L24P_2
L22P_2
I/O
L30P_1
LDC1
L21N_1
I/O
L22N_2
VREF_2
I/O
L30N_1
LDC2
I/O
L23P_2
B
GND
L23N_1
GND
INPUT
TDO
I/O
INPUT
A
INPUT
L23P_1
L11P_1
GND
L03P_0
I/O
INPUT
VCCO_2
I/O
L22P_1
I/O
20
L03N_0
VREF_0
I/O
I/O
19
I/O
L21P_2
I/O
VCCO_2
L15N_1
A7
RHCLK3
TRDY1
I/O
L22N_1
I/O
L16N_1
A5
RHCLK5
I/O
GND
INPUT
18
Bank 1
11
DS312-4_09_031105
www.xilinx.com
61
R
Pinout Descriptions
FG484: 484-ball Fine-pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FG484, supports the
XC3S1600E FPGA.
Table 31 lists all the FG484 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
Table 31: FG484 Package Pinout
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
0
IO_L10P_0
F15
I/O
0
IO_L11N_0
D14
I/O
0
IO_L11P_0
E14
I/O
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
0
IO_L12N_0/VREF_0
A14
VREF
0
IO_L12P_0
A15
I/O
Pinout Table
0
IO_L13N_0
H14
I/O
0
IO_L13P_0
G14
I/O
0
IO_L15N_0
G13
I/O
0
IO_L15P_0
F13
I/O
0
IO_L16N_0
J13
I/O
0
IO_L16P_0
H13
I/O
0
IO_L18N_0/GCLK5
E12
GCLK
0
IO_L18P_0/GCLK4
F12
GCLK
0
IO_L19N_0/GCLK7
C12
GCLK
0
IO_L19P_0/GCLK6
B12
GCLK
0
IO_L21N_0/GCLK11
B11
GCLK
0
IO_L21P_0/GCLK10
C11
GCLK
0
IO_L22N_0
D11
I/O
0
IO_L22P_0
E11
I/O
0
IO_L24N_0
A9
I/O
0
IO_L24P_0
A10
I/O
0
IO_L25N_0/VREF_0
D10
VREF
0
IO_L25P_0
C10
I/O
0
IO_L27N_0
H8
I/O
0
IO_L27P_0
H9
I/O
0
IO_L28N_0
C9
I/O
0
IO_L28P_0
B9
I/O
0
IO_L29N_0
E9
I/O
0
IO_L29P_0
D9
I/O
0
IO_L30N_0
B8
I/O
0
IO_L30P_0
A8
I/O
0
IO_L32N_0/VREF_0
F7
VREF
0
IO_L32P_0
F8
I/O
0
IO_L33N_0
A6
I/O
Table 31: FG484 Package Pinout
XC3S1600E
Pin Name
Bank
62
FG484
Ball
Type
0
IO
B6
I/O
0
IO
B13
I/O
0
IO
C5
I/O
0
IO
C14
I/O
0
IO
E16
I/O
0
IO
F9
I/O
0
IO
F16
I/O
0
IO
G8
I/O
0
IO
H10
I/O
0
IO
H15
I/O
0
IO
J11
I/O
0
IO/VREF_0
G12
VREF
0
IO_L01N_0
C18
I/O
0
IO_L01P_0
C19
I/O
0
IO_L03N_0/VREF_0
A20
VREF
0
IO_L03P_0
A21
I/O
0
IO_L04N_0
A19
I/O
0
IO_L04P_0
A18
I/O
0
IO_L06N_0
C16
I/O
0
IO_L06P_0
D16
I/O
0
IO_L07N_0
A16
I/O
0
IO_L07P_0
A17
I/O
0
IO_L09N_0/VREF_0
B15
VREF
0
IO_L09P_0
C15
I/O
0
IO_L10N_0
G15
I/O
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 31: FG484 Package Pinout
XC3S1600E
Pin Name
Bank
Table 31: FG484 Package Pinout
FG484
Ball
Type
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
0
IO_L33P_0
A7
I/O
0
VCCO_0
B5
VCCO
0
IO_L35N_0
A4
I/O
0
VCCO_0
B10
VCCO
0
IO_L35P_0
A5
I/O
0
VCCO_0
B14
VCCO
0
IO_L36N_0
E7
I/O
0
VCCO_0
B18
VCCO
0
IO_L36P_0
D7
I/O
0
VCCO_0
E8
VCCO
0
IO_L38N_0/VREF_0
D6
VREF
0
VCCO_0
F14
VCCO
0
IO_L38P_0
D5
I/O
0
VCCO_0
G11
VCCO
0
IO_L39N_0
B4
I/O
1
IO_L01N_1/A15
Y22
DUAL
0
IO_L39P_0
B3
I/O
1
IO_L01P_1/A16
AA22
DUAL
0
IO_L40N_0/HSWAP
D4
DUAL
1
IO_L02N_1/A13
W21
DUAL
0
IO_L40P_0
C4
I/O
1
IO_L02P_1/A14
Y21
DUAL
0
IP
B19
INPUT
1
IO_L03N_1/VREF_1
W20
VREF
0
IP
E6
INPUT
1
IO_L03P_1
V20
I/O
0
IP_L02N_0
D17
INPUT
1
IO_L04N_1
U19
I/O
0
IP_L02P_0
D18
INPUT
1
IO_L04P_1
V19
I/O
0
IP_L05N_0
C17
INPUT
1
IO_L05N_1
V22
I/O
0
IP_L05P_0
B17
INPUT
1
IO_L05P_1
W22
I/O
0
IP_L08N_0
E15
INPUT
1
IO_L06N_1
T19
I/O
0
IP_L08P_0
D15
INPUT
1
IO_L06P_1
T18
I/O
0
IP_L14N_0
D13
INPUT
1
IO_L07N_1/VREF_1
U20
VREF
0
IP_L14P_0
C13
INPUT
1
IO_L07P_1
U21
I/O
0
IP_L17N_0
A12
INPUT
1
IO_L08N_1
T22
I/O
0
IP_L17P_0
A13
INPUT
1
IO_L08P_1
U22
I/O
0
IP_L20N_0/GCLK9
H11
GCLK
1
IO_L09N_1
R19
I/O
0
IP_L20P_0/GCLK8
H12
GCLK
1
IO_L09P_1
R18
I/O
0
IP_L23N_0
F10
INPUT
1
IO_L10N_1
R16
I/O
0
IP_L23P_0
F11
INPUT
1
IO_L10P_1
T16
I/O
0
IP_L26N_0
G9
INPUT
1
IO_L11N_1
R21
I/O
0
IP_L26P_0
G10
INPUT
1
IO_L11P_1
R20
I/O
0
IP_L31N_0
C8
INPUT
1
IO_L12N_1/VREF_1
P18
VREF
0
IP_L31P_0
D8
INPUT
1
IO_L12P_1
P17
I/O
0
IP_L34N_0
C7
INPUT
1
IO_L13N_1
P22
I/O
0
IP_L34P_0
C6
INPUT
1
IO_L13P_1
R22
I/O
0
IP_L37N_0
A3
INPUT
1
IO_L14N_1
P15
I/O
0
IP_L37P_0
A2
INPUT
1
IO_L14P_1
P16
I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
63
R
Pinout Descriptions
Table 31: FG484 Package Pinout
Bank
64
XC3S1600E
Pin Name
Table 31: FG484 Package Pinout
FG484
Ball
Type
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
1
IO_L15N_1
N18
I/O
1
IO_L30N_1
H17
I/O
1
IO_L15P_1
N19
I/O
1
IO_L30P_1
G17
I/O
1
IO_L16N_1/A11
N16
DUAL
1
IO_L31N_1
F22
I/O
1
IO_L16P_1/A12
N17
DUAL
1
IO_L31P_1
G22
I/O
1
IO_L17N_1/VREF_1
M20
VREF
1
IO_L32N_1
F20
I/O
1
IO_L17P_1
N20
I/O
1
IO_L32P_1
G20
I/O
1
IO_L18N_1/A9/RHCLK1
M22
RHCLK/
DUAL
1
IO_L33N_1
G18
I/O
1
IO_L33P_1
G19
I/O
1
IO_L18P_1/A10/RHCLK0
N22
RHCLK/
DUAL
1
IO_L34N_1
D22
I/O
1
IO_L19N_1/A7/RHCLK3/
TRDY1
M16
RHCLK/
DUAL
1
IO_L34P_1
E22
I/O
1
IO_L35N_1
F19
I/O
1
IO_L19P_1/A8/RHCLK2
M15
RHCLK/
DUAL
1
IO_L35P_1
F18
I/O
1
IO_L20N_1/A5/RHCLK5
L21
RHCLK/
DUAL
1
IO_L36N_1
E20
I/O
1
IO_L36P_1
E19
I/O
1
IO_L37N_1/LDC0
C21
DUAL
1
IO_L37P_1/HDC
C22
DUAL
1
IO_L38N_1/LDC2
B21
DUAL
1
IO_L38P_1/LDC1
B22
DUAL
1
IP
D20
INPUT
1
IO_L20P_1/A6/RHCLK4/
IRDY1
L20
RHCLK/
DUAL
1
IO_L21N_1/A3/RHCLK7
L19
RHCLK/
DUAL
1
IO_L21P_1/A4/RHCLK6
L18
RHCLK/
DUAL
1
IO_L22N_1/A1
K22
DUAL
1
IP
F21
INPUT
1
IO_L22P_1/A2
L22
DUAL
1
IP
G16
INPUT
1
IO_L23N_1/A0
K17
DUAL
1
IP
H16
INPUT
1
IO_L23P_1
K16
I/O
1
IP
J16
INPUT
1
IO_L24N_1
K19
I/O
1
IP
J22
INPUT
1
IO_L24P_1
K18
I/O
1
IP
K20
INPUT
1
IO_L25N_1
K15
I/O
1
IP
L15
INPUT
1
IO_L25P_1
J15
I/O
1
IP
M18
INPUT
1
IO_L26N_1
J20
I/O
1
IP
N15
INPUT
1
IO_L26P_1
J21
I/O
1
IP
N21
INPUT
1
IO_L27N_1
J17
I/O
1
IP
P20
INPUT
1
IO_L27P_1
J18
I/O
1
IP
R15
INPUT
1
IO_L28N_1/VREF_1
H21
VREF
1
IP
T17
INPUT
1
IO_L28P_1
H22
I/O
1
IP
T20
INPUT
1
IO_L29N_1
H20
I/O
1
IP
U18
INPUT
1
IO_L29P_1
H19
I/O
1
IP/VREF_1
D21
VREF
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 31: FG484 Package Pinout
XC3S1600E
Pin Name
Bank
Table 31: FG484 Package Pinout
FG484
Ball
Type
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
1
IP/VREF_1
L17
VREF
2
IO_L11P_2
AA8
I/O
1
VCCO_1
E21
VCCO
2
IO_L12N_2
W9
I/O
1
VCCO_1
H18
VCCO
2
IO_L12P_2
V9
I/O
1
VCCO_1
K21
VCCO
2
IO_L13N_2/VREF_2
R9
VREF
1
VCCO_1
L16
VCCO
2
IO_L13P_2
T9
I/O
1
VCCO_1
P21
VCCO
2
IO_L14N_2
AB9
I/O
1
VCCO_1
R17
VCCO
2
IO_L14P_2
AB10
I/O
1
VCCO_1
V21
VCCO
2
IO_L16N_2
U10
I/O
2
IO
Y8
I/O
2
IO_L16P_2
T10
I/O
2
IO
Y9
I/O
2
IO_L17N_2
R10
I/O
2
IO
AA10
I/O
2
IO_L17P_2
P10
I/O
2
IO
AB5
I/O
2
IO_L19N_2/D6/GCLK13
U11
2
IO
AB13
I/O
DUAL/
GCLK
2
IO
AB14
I/O
2
IO_L19P_2/D7/GCLK12
V11
DUAL/
GCLK
2
IO
AB16
I/O
2
IO_L20N_2/D3/GCLK15
T11
2
IO
AB18
I/O
DUAL/
GCLK
2
IO/D5
AB11
DUAL
2
IO_L20P_2/D4/GCLK14
R11
DUAL/
GCLK
2
IO/M1
AA12
DUAL
2
IO_L22N_2/D1/GCLK3
W12
2
IO/VREF_2
AB4
VREF
DUAL/
GCLK
2
IO/VREF_2
AB21
VREF
2
IO_L22P_2/D2/GCLK2
Y12
2
IO_L01N_2/INIT_B
AB3
DUAL
DUAL/
GCLK
2
IO_L01P_2/CSO_B
AA3
DUAL
2
IO_L23N_2/DIN/D0
U12
DUAL
2
IO_L03N_2/MOSI/CSI_B
Y5
DUAL
2
IO_L23P_2/M0
V12
DUAL
2
IO_L03P_2/DOUT/BUSY
W5
DUAL
2
IO_L25N_2
Y13
I/O
2
IO_L04N_2
W6
I/O
2
IO_L25P_2
W13
I/O
2
IO_L04P_2
V6
I/O
2
IO_L26N_2/VREF_2
U14
VREF
2
IO_L06N_2
W7
I/O
2
IO_L26P_2
U13
I/O
2
IO_L06P_2
Y7
I/O
2
IO_L27N_2
T14
I/O
2
IO_L07N_2
U7
I/O
2
IO_L27P_2
R14
I/O
2
IO_L07P_2
V7
I/O
2
IO_L28N_2
Y14
I/O
2
IO_L09N_2/VREF_2
V8
VREF
2
IO_L28P_2
AA14
I/O
2
IO_L09P_2
W8
I/O
2
IO_L29N_2
W14
I/O
2
IO_L10N_2
T8
I/O
2
IO_L29P_2
V14
I/O
2
IO_L10P_2
U8
I/O
2
IO_L30N_2
AB15
I/O
2
IO_L11N_2
AB8
I/O
2
IO_L30P_2
AA15
I/O
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
65
R
Pinout Descriptions
Table 31: FG484 Package Pinout
XC3S1600E
Pin Name
Bank
66
Table 31: FG484 Package Pinout
FG484
Ball
Type
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
2
IO_L32N_2
W15
I/O
2
IP_L37N_2
AA19
INPUT
2
IO_L32P_2
Y15
I/O
2
IP_L37P_2
AB19
INPUT
2
IO_L33N_2
U16
I/O
2
VCCO_2
T12
VCCO
2
IO_L33P_2
V16
I/O
2
VCCO_2
U9
VCCO
2
IO_L35N_2/A22
AB17
DUAL
2
VCCO_2
V15
VCCO
2
IO_L35P_2/A23
AA17
DUAL
2
VCCO_2
AA5
VCCO
2
IO_L36N_2
W17
I/O
2
VCCO_2
AA9
VCCO
2
IO_L36P_2
Y17
I/O
2
VCCO_2
AA13
VCCO
2
IO_L38N_2/A20
Y18
DUAL
2
VCCO_2
AA18
VCCO
2
IO_L38P_2/A21
W18
DUAL
3
IO_L01N_3
C1
I/O
2
IO_L39N_2/VS1/A18
AA20
DUAL
3
IO_L01P_3
C2
I/O
2
IO_L39P_2/VS2/A19
AB20
DUAL
3
IO_L02N_3/VREF_3
D2
VREF
2
IO_L40N_2/CCLK
W19
DUAL
3
IO_L02P_3
D3
I/O
2
IO_L40P_2/VS0/A17
Y19
DUAL
3
IO_L03N_3
E3
I/O
2
IP
V17
INPUT
3
IO_L03P_3
E4
I/O
2
IP
AB2
INPUT
3
IO_L04N_3
E1
I/O
2
IP_L02N_2
AA4
INPUT
3
IO_L04P_3
D1
I/O
2
IP_L02P_2
Y4
INPUT
3
IO_L05N_3
F4
I/O
2
IP_L05N_2
Y6
INPUT
3
IO_L05P_3
F3
I/O
2
IP_L05P_2
AA6
INPUT
3
IO_L06N_3
G5
I/O
2
IP_L08N_2
AB7
INPUT
3
IO_L06P_3
G4
I/O
2
IP_L08P_2
AB6
INPUT
3
IO_L07N_3
F1
I/O
2
IP_L15N_2
Y10
INPUT
3
IO_L07P_3
G1
I/O
2
IP_L15P_2
W10
INPUT
3
IO_L08N_3/VREF_3
G6
VREF
2
IP_L18N_2/VREF_2
AA11
VREF
3
IO_L08P_3
G7
I/O
2
IP_L18P_2
Y11
INPUT
3
IO_L09N_3
H4
I/O
2
IP_L21N_2/M2/GCLK1
P12
DUAL/
GCLK
3
IO_L09P_3
H5
I/O
3
IO_L10N_3
H2
I/O
2
IP_L21P_2/RDWR_B/
GCLK0
R12
DUAL/
GCLK
3
IO_L10P_3
H3
I/O
2
IP_L24N_2
R13
INPUT
3
IO_L11N_3
H1
I/O
2
IP_L24P_2
T13
INPUT
3
IO_L11P_3
J1
I/O
2
IP_L31N_2/VREF_2
T15
VREF
3
IO_L12N_3
J6
I/O
2
IP_L31P_2
U15
INPUT
3
IO_L12P_3
J5
I/O
2
IP_L34N_2
Y16
INPUT
3
IO_L13N_3/VREF_3
J3
VREF
2
IP_L34P_2
W16
INPUT
3
IO_L13P_3
K3
I/O
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 31: FG484 Package Pinout
Bank
XC3S1600E
Pin Name
Table 31: FG484 Package Pinout
FG484
Ball
Type
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
3
IO_L14N_3
J8
I/O
3
IO_L31P_3
U1
I/O
3
IO_L14P_3
K8
I/O
3
IO_L32N_3
T4
I/O
3
IO_L15N_3
K4
I/O
3
IO_L32P_3
T5
I/O
3
IO_L15P_3
K5
I/O
3
IO_L33N_3
W1
I/O
3
IO_L16N_3
K1
I/O
3
IO_L33P_3
V1
I/O
3
IO_L16P_3
L1
I/O
3
IO_L34N_3
U4
I/O
3
IO_L17N_3
L7
I/O
3
IO_L34P_3
U3
I/O
3
IO_L17P_3
K7
I/O
3
IO_L35N_3
V4
I/O
3
IO_L18N_3/LHCLK1
L5
LHCLK
3
IO_L35P_3
V3
I/O
3
IO_L18P_3/LHCLK0
M5
LHCLK
3
IO_L36N_3/VREF_3
W3
VREF
3
IO_L19N_3/LHCLK3/IRDY2
M8
LHCLK
3
IO_L36P_3
W2
I/O
3
IO_L19P_3/LHCLK2
L8
LHCLK
3
IO_L37N_3
Y2
I/O
3
IO_L20N_3/LHCLK5
N1
LHCLK
3
IO_L37P_3
Y1
I/O
3
IO_L20P_3/LHCLK4/TRDY2
M1
LHCLK
3
IO_L38N_3
AA1
I/O
3
IO_L21N_3/LHCLK7
M4
LHCLK
3
IO_L38P_3
AA2
I/O
3
IO_L21P_3/LHCLK6
M3
LHCLK
3
IP
F2
INPUT
3
IO_L22N_3
N6
I/O
3
IP
F5
INPUT
3
IO_L22P_3
N7
I/O
3
IP
G3
INPUT
3
IO_L23N_3
P8
I/O
3
IP
H7
INPUT
3
IO_L23P_3
N8
I/O
3
IP
J7
INPUT
3
IO_L24N_3/VREF_3
N4
VREF
3
IP
K2
INPUT
3
IO_L24P_3
N5
I/O
3
IP
K6
INPUT
3
IO_L25N_3
P2
I/O
3
IP
M2
INPUT
3
IO_L25P_3
P1
I/O
3
IP
M6
INPUT
3
IO_L26N_3
R7
I/O
3
IP
N3
INPUT
3
IO_L26P_3
P7
I/O
3
IP
P3
INPUT
3
IO_L27N_3
P6
I/O
3
IP
R8
INPUT
3
IO_L27P_3
P5
I/O
3
IP
T1
INPUT
3
IO_L28N_3
R2
I/O
3
IP
T7
INPUT
3
IO_L28P_3
R1
I/O
3
IP
U5
INPUT
3
IO_L29N_3
R3
I/O
3
IP
W4
INPUT
3
IO_L29P_3
R4
I/O
3
IP/VREF_3
L3
VREF
3
IO_L30N_3
T6
I/O
3
IP/VREF_3
T3
VREF
3
IO_L30P_3
R6
I/O
3
VCCO_3
E2
VCCO
3
IO_L31N_3
U2
I/O
3
VCCO_3
H6
VCCO
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
67
R
Pinout Descriptions
Table 31: FG484 Package Pinout
XC3S1600E
Pin Name
Bank
68
Table 31: FG484 Package Pinout
FG484
Ball
Type
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
3
VCCO_3
J2
VCCO
GND
GND
P4
GND
3
VCCO_3
M7
VCCO
GND
GND
P9
GND
3
VCCO_3
N2
VCCO
GND
GND
P11
GND
3
VCCO_3
R5
VCCO
GND
GND
P14
GND
3
VCCO_3
V2
VCCO
GND
GND
P19
GND
GND
GND
A1
GND
GND
GND
T2
GND
GND
GND
A11
GND
GND
GND
T21
GND
GND
GND
A22
GND
GND
GND
U6
GND
GND
GND
B7
GND
GND
GND
U17
GND
GND
GND
B16
GND
GND
GND
V10
GND
GND
GND
C3
GND
GND
GND
V13
GND
GND
GND
C20
GND
GND
GND
Y3
GND
GND
GND
E10
GND
GND
GND
Y20
GND
GND
GND
E13
GND
GND
GND
AA7
GND
GND
GND
F6
GND
GND
GND
AA16
GND
GND
GND
F17
GND
GND
GND
AB1
GND
GND
GND
G2
GND
GND
GND
AB12
GND
GND
GND
G21
GND
GND
GND
AB22
GND
GND
GND
J4
GND
VCCAUX DONE
AA21
CONFIG
GND
GND
J9
GND
VCCAUX PROG_B
B1
CONFIG
GND
GND
J12
GND
VCCAUX TCK
E17
JTAG
GND
GND
J14
GND
VCCAUX TDI
B2
JTAG
GND
GND
J19
GND
VCCAUX TDO
B20
JTAG
GND
GND
K10
GND
VCCAUX TMS
D19
JTAG
GND
GND
K12
GND
VCCAUX VCCAUX
D12
VCCAUX
GND
GND
L2
GND
VCCAUX VCCAUX
E5
VCCAUX
GND
GND
L6
GND
VCCAUX VCCAUX
E18
VCCAUX
GND
GND
L9
GND
VCCAUX VCCAUX
K14
VCCAUX
GND
GND
L13
GND
VCCAUX VCCAUX
L4
VCCAUX
GND
GND
M10
GND
VCCAUX VCCAUX
M19
VCCAUX
GND
GND
M14
GND
VCCAUX VCCAUX
N9
VCCAUX
GND
GND
M17
GND
VCCAUX VCCAUX
V5
VCCAUX
GND
GND
M21
GND
VCCAUX VCCAUX
V18
VCCAUX
GND
GND
N11
GND
VCCAUX VCCAUX
W11
VCCAUX
GND
GND
N13
GND
VCCINT
J10
VCCINT
www.xilinx.com
VCCINT
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Table 31: FG484 Package Pinout
Table 31: FG484 Package Pinout
XC3S1600E
Pin Name
Bank
FG484
Ball
Type
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
VCCINT
VCCINT
K9
VCCINT
VCCINT
VCCINT
M13
VCCINT
VCCINT
VCCINT
K11
VCCINT
VCCINT
VCCINT
N10
VCCINT
VCCINT
VCCINT
K13
VCCINT
VCCINT
VCCINT
N12
VCCINT
VCCINT
VCCINT
L10
VCCINT
VCCINT
VCCINT
N14
VCCINT
VCCINT
VCCINT
L11
VCCINT
VCCINT
VCCINT
P13
VCCINT
VCCINT
VCCINT
L12
VCCINT
VCCINT
VCCINT
L14
VCCINT
VCCINT
VCCINT
M9
VCCINT
VCCINT
VCCINT
M11
VCCINT
VCCINT
VCCINT
M12
VCCINT
User I/Os by Bank
Table 32 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG484 package.
Table 32: User I/Os Per Bank for the XC3S1600E in the FG484 Package
Package
Edge
All Possible I/O Pins by Type
I/O Bank
Maximum
I/O
I/O
INPUT
DUAL
VREF
GCLK
Top
0
94
56
22
1
7
8
Right
1
94
50
16
21
7
0
Bottom
2
94
45
18
24
7
0
Left
3
94
63
16
0
7
8
376
214
72
46
28
16
TOTAL
Footprint Migration Differences
The XC3S1600E FPGA is the only Spartan-3E device
offered in the FG484 package.
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
69
R
Pinout Descriptions
FG484 Footprint
Bank 0
1
Left Half of Package
(top view)
214
I/O: Unrestricted,
general-purpose user I/O
72
INPUT: User I/O or
reference resistor input for
bank
46
DUAL: Configuration pin,
then possible user I/O
28
VREF: User I/O or input
voltage reference for bank
A
GND
B
PROG_B
C
D
E
F
G
16
GCLK: User I/O, input, or
clock buffer input
H
4
48
JTAG: Dedicated JTAG
port pins
K
GND: Ground
28
VCCO: Output voltage
supply for bank
16
10
0
J
Bank 3
2
CONFIG: Dedicated
configuration pins
L
2
3
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L37P_0
L37N_0
L35N_0
L35P_0
L33N_0
L33P_0
L30P_0
L24N_0
L24P_0
VCCO_0
I/O
GND
INPUT
INPUT
INPUT
I/O
I/O
L34P_0
L34N_0
L31N_0
L28N_0
L25P_0
I/O
INPUT
I/O
L36P_0
L31P_0
L29P_0
TDI
I/O
I/O
L01N_3
L01P_3
I/O
L04P_3
I/O
L04N_3
I/O
L07N_3
I/O
L07P_3
I/O
L02N_3
VREF_3
VCCO_3
INPUT
GND
I/O
I/O
L39P_0
L39N_0
GND
I/O
L02P_3
I/O
I/O
L03N_3
L03P_3
I/O
I/O
L05P_3
L05N_3
INPUT
GND
I/O
I/O
L06P_3
L06N_3
I/O
L09P_3
VCCO_3
L13N_3
VREF_3
I/O
I/O
L16N_3
I/O
L16P_3
I/O
INPUT
GND
VCCAUX: Auxiliary supply
voltage (+2.5V)
P
N.C.: Not connected
R
GND
I/O
I/O
L15P_3
VCCAUX
L18N_3
LHCLK1
I/O
I/O
I/O
L21N_3
LHCLK7
L18P_3
LHCLK0
VCCO_3
INPUT
L24N_3
VREF_3
INPUT
GND
I/O
I/O
I/O
L25N_3
I/O
I/O
I/O
I/O
L28P_3
L28N_3
L29N_3
L29P_3
INPUT
GND
I/O
I/O
L33N_3
L36P_3
I/O
I/O
L37P_3
L37N_3
I/O
I/O
L38N_3
L38P_3
GND
INPUT
I/O
L35N_3
GND
I/O
L01P_2
CSO_B
I/O
L01N_2
INIT_B
INPUT
INPUT
L02P_2
INPUT
L02N_2
I/O
VREF_2
VCCO_3
L19N_3
LHCLK3
IRDY2
I/O
I/O
I/O
I/O
L27N_3
L26P_3
L23N_3
VCCAUX
L03P_2
DOUT
BUSY
I/O
L03N_2
MOSI
CSI_B
VCCO_2
I/O
GND
I/O
L25N_0
VREF_0
GND
L21N_0
GCLK11
I/O
L21P_0
GCLK10
I/O
L22N_0
I/O
L22P_0
INPUT
INPUT
L23N_0
L23P_0
INPUT
L26P_0
VCCO_0
INPUT
I/O
L20N_0
GCLK9
GND
VCCINT
I/O
VCCINT
GND
VCCINT
I/O
L19P_3
LHCLK2
L27P_3
I/O
I/O
L36N_3
VREF_3
I/O
L14P_3
I/O
I/O
I/O
L30P_3
L26N_3
GND
I/O
I/O
11
I/O
VCCO_0
L26N_0
I/O
L14N_3
10
INPUT
L27P_0
L23P_3
VCCO_3
I/O
I/O
I/O
I/O
I/O
L29N_0
L27N_0
I/O
INPUT
L35P_3
I/O
L22P_3
I/O
I/O
I/O
L32P_0
I/O
L30N_3
L34N_3
VCCO_0
L22N_3
I/O
I/O
I/O
L28P_0
I/O
L32P_3
L34P_3
I/O
L17P_3
L17N_3
9
L30N_0
L24P_3
I/O
I/O
INPUT
8
GND
VCCINT VCCINT
I/O
INPUT
L32N_3
L31N_3
VCCO_3
GND
INPUT
I/O
I/O
INPUT
VREF_3
L31P_3
L33P_3
INPUT
I/O
L21P_3
LHCLK6
I/O
VCCO_3
I/O
L15N_3
L32N_0
VREF_0
L08P_3
L12N_3
INPUT
L25P_3
I/O
I/O
I/O
INPUT
I/O
L36N_0
L08N_3
VREF_3
L12P_3
L13P_3
VREF_3
7
I/O
I/O
I/O
A
B
INPUT
L09N_3
L20N_3
LHCLK5
A
A
INPUT
I/O
N
Y
VCCAUX
L10P_3
L11P_3
I/O
L38N_0
VREF_0
I/O
VCCINT: Internal core
supply voltage (+1.2V)
W
I/O
6
L38P_0
L10N_3
I/O
V
I/O
L40N_0
HSWAP
I/O
I/O
L20P_3
LHCLK4
TRDY2
U
I/O
L40P_0
5
L11N_3
M
T
4
INPUT
VCCINT
GND
GND
L13N_2
VREF_2
I/O
L17P_2
I/O
L17N_2
I/O
I/O
L13P_2
L16P_2
I/O
I/O
VCCAUX
I/O
L10P_2
L07P_2
VCCINT
L10N_2
I/O
I/O
GND
I/O
INPUT
L07N_2
L04P_2
VCCINT
I/O
L09N_2
VREF_2
VCCO_2
I/O
L12P_2
I/O
L16N_2
I/O
I/O
I/O
I/O
INPUT
L06N_2
L09P_2
L12N_2
L15P_2
I/O
I/O
I/O
L05N_2
L06P_2
INPUT
L05P_2
GND
I/O
L11P_2
I/O
L20P_2
D4
GCLK14
I/O
L20N_2
D3
GCLK15
I/O
L19N_2
D6
GCLK13
I/O
GND
L04N_2
INPUT
GND
L19P_2
D7
GCLK12
VCCAUX
INPUT
INPUT
L15N_2
L18P_2
I/O
L18N_2
VREF_2
INPUT
VCCO_2
INPUT
INPUT
I/O
I/O
I/O
I/O
L08P_2
L08N_2
L11N_2
L14N_2
L14P_2
D5
Bank 2
DS312_10_031105
Figure 10: FG484 Package Footprint (top view)
70
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
R
Pinout Descriptions
Bank 0
13
14
INPUT
INPUT
L17N_0
L17P_0
L12N_0
VREF_0
I/O
VCCO_0
I/O
I/O
L19P_0
GCLK6
I/O
L19N_0
GCLK7
VCCAUX
I/O
L18P_0
GCLK4
16
17
18
19
I/O
I/O
I/O
I/O
I/O
L12P_0
L07N_0
L07P_0
L04P_0
L04N_0
L03N_0
VREF_0
I/O
I/O
VCCO_0
INPUT
TDO
L38N_1
LDC2
L38P_1
LDC1
I/O
I/O
GND
L37N_1
LDC0
L37P_1
HDC
I/O
INPUT
L14P_0
I/O
L09N_0
VREF_0
I/O
INPUT
I/O
I/O
L06N_0
L05N_0
L01N_0
L01P_0
I/O
INPUT
I/O
INPUT
INPUT
L14N_0
L11N_0
L08P_0
L06P_0
L02N_0
L02P_0
I/O
INPUT
L11P_0
L08N_0
I/O
TCK
VCCAUX
I/O
GND
GND
I/O
L15P_0
VCCO_0
I/O
L10P_0
I/O
I/O
I/O
L15N_0
L13P_0
L10N_0
GND
GND
VCCINT
I/O
I/O
L16P_0
L13N_0
I/O
L16N_0
GND
GND
I/O
I/O
L25P_1
INPUT
L21P_2
RDWR_B
GCLK0
VCCO_2
I/O
L23N_2
DIN
D0
VCCINT
I/O
VCCINT INPUT
VCCO_1
GND
I/O
L27P_2
INPUT
I/O
L24P_2
L27N_2
I/O
L23P_2
M0
I/O
L22N_2
D1
GCLK3
I/O
L22P_2
D2
GCLK2
I/O
M1
GND
GND
L24N_2
I/O
GND
L19P_1
A8
RHCLK2
VCCINT INPUT
INPUT
L26P_2
INPUT
L23P_1
INPUT
L21N_2
M2
GCLK1
INPUT
I/O
I/O
GND
INPUT
L25N_1
VCCINT VCCAUX
VCCINT VCCINT
VCCINT
L05P_0
I/O
I/O
L20P_0
GCLK8
INPUT
L09P_0
VREF_0
INPUT
GND
INPUT
I/O
L18N_0
GCLK5
15
I/O
L26N_2
VREF_2
I/O
L29P_2
I/O
I/O
L32P_1
I/O
L30N_1
I/O
I/O
L27P_1
I/O
L23N_1
A0
GND
INPUT
VCCAUX
I/O
I/O
L10N_1
I/O
L10P_1
I/O
I/O
L33P_2
VCCO_1
INPUT
I/O
L34N_1
VCCO_1
INPUT
GND
I/O
L28N_1
VREF_1
I/O
INPUT
VCCO_1
I/O
L20P_1
A6
RHCLK4
IRDY1
I/O
L34P_2
L36N_2
I/O
I/O
I/O
INPUT
I/O
L25N_2
L28N_2
L32P_2
L34N_2
L36P_2
GND
L35P_2
A23
I/O
L35N_2
A22
I/O
I/O
L31N_1
I/O
L31P_1
I/O
L28P_1
INPUT
GND
INPUT
L22N_1
A1
I/O
I/O
L20N_1
A5
RHCLK5
L22P_1
A2
GND
L18N_1
A9
RHCLK1
INPUT
L18P_1
A10
RHCLK0
VCCO_1
I/O
L13N_1
I/O
I/O
I/O
I/O
I/O
L09N_1
L11P_1
L11N_1
L13P_1
INPUT
GND
I/O
I/O
L06N_1
I/O
L04N_1
C
D
E
F
G
H
J
I/O
L07N_1
VREF_1
I/O
I/O
L04P_1
L03P_1
K
L
M
I/O
L09P_1
L06P_1
B
I/O
I/O
I/O
L08N_1
I/O
I/O
L07P_1
L08P_1
VCCO_1
I/O
L05N_1
N
P
R
T
U
V
I/O
I/O
I/O
I/O
L38P_2
A21
L40N_2
CCLK
L03N_1
VREF_1
L02N_1
A13
I/O
I/O
GND
L02P_1
A14
L01N_1
A15
Y
I/O
DONE
L01P_1
A16
A
A
I/O
I/O
L38N_2
A20
L40P_2
VS0
A17
I/O
VCCO_2
I/O
Bank 2
L17N_1
VREF_1
L17P_1
VCCAUX
INPUT
I/O
L34P_1
I/O
INPUT
L37N_2
INPUT
L37P_2
Right Half of Package
(top view)
A
I/O
I/O
INPUT
I/O
GND
INPUT
L26P_1
L15P_1
L12N_1
VREF_1
22
VREF_1
I/O
I/O
INPUT
L32N_2
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
L03P_0
L26N_1
L15N_1
GND
I/O
I/O
21
I/O
I/O
L16P_1
A12
L33N_2
L30N_2
I/O
L24N_1
I/O
L29N_2
I/O
I/O
L24P_1
L21N_1
A3
RHCLK7
I/O
I/O
GND
I/O
I/O
L31P_2
I/O
I/O
L29N_1
L21P_1
A4
RHCLK6
INPUT
L16N_1
A11
INPUT
L30P_2
I/O
L29P_1
VREF_1
I/O
I/O
VCCO_1
L27N_1
L12P_1
L28P_2
I/O
L32N_1
L33P_1
L25P_2
VCCO_2
I/O
L35N_1
I/O
I/O
VCCO_2
I/O
L35P_1
L33N_1
L14P_1
L31N_2
VREF_2
I/O
L36N_1
I/O
I/O
INPUT
I/O
L36P_1
I/O
L19N_1
A7
RHCLK3
TRDY1
INPUT
L30P_1
L14N_1
INPUT
TMS
20
I/O
I/O
L39N_2
VS1
A18
I/O
L39P_2
VS2
A19
Bank 1
12
I/O
VREF_2
I/O
L05P_1
GND
W
A
B
DS312_11_031105
www.xilinx.com
71
R
Pinout Descriptions
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
03/01/05
1.0
Initial Xilinx release.
03/21/05
1.1
Added XC3S250E in the CP132 package to Table 6. Corrected number of differential I/O
pairs on CP132. Added pinout and footprint information for the CP132, FG400, and FG484
packages. Removed IRDY and TRDY pins from the VQ100, TQ144, and PQ208 packages.
The Spartan-3E Family Data Sheet
DS312-1, Spartan-3E FPGA Family: Introduction and Ordering Information (Module 1)
DS312-2, Spartan-3E FPGA Family: Functional Description (Module 2)
DS312-3, Spartan-3E FPGA Family: DC and Switching Characteristics (Module 3)
DS312-4, Spartan-3E FPGA Family: Pinout Descriptions (Module 4)
72
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Advance Product Specification