INFINEON XC866_05

User’s Manual, V 0 .2, Jan 2005
XC866
8-Bit Single Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2005-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
User’s Manual, V 0 .2, Jan 2005
XC866
8-Bit Single Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
XC866
Revision History:
2005-01
V 0.2
Previous Version:
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XC866
Table of Contents
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.4
Textual Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.5
Reserved, Undefined and Unimplemented Terminology . . . . . . . . . . . . 1-13
1.6
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.3
Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Operation Register (EO) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Control Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.4.1
3.3.5
3.3.5.1
3.3.5.2
3.3.5.3
3.3.5.4
3.3.5.5
3.3.5.6
3.3.5.7
3.3.5.8
3.3.5.9
3.4
3.4.1
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Bit-Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
XC866 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Boot ROM Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
User’s Manual
I-1
2-1
2-2
2-4
2-4
2-4
2-4
2-4
2-5
2-6
2-7
2-8
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3.4.2
BootStrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.4.3
OCDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.7.1
4.7.2
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Wordline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
D-Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
D-Flash Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.5
5.6
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Non-maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Internal Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Extended Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Interrupt Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Interrupt Request Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Interrupt Request Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
6
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.1.3
6.1.1.4
6.1.1.5
6.1.1.6
6.2
6.3
6.3.1
6.3.2
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
General Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
General Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Open Drain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Pull-Up/Pull-Down Device Register . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Alternate Input Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Alternate Output Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
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6.4
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.1
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.2
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.1
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.2
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
6-19
6-19
6-21
6-24
6-24
6-26
6-28
6-28
6-31
7
7.1
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.1.4
7.2.1.5
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.1.1
7.3.2
7.3.3
7.3.4
Power Supply, Reset and Clock Management . . . . . . . . . . . . . . . . . . 7-1
Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . 7-1
Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Types of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Power-Down Wake-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Register Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Clock Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slow-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description
......................................
8-1
8-2
8-2
8-2
8-3
8-4
8-6
9
9.1
9.2
9.3
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-1
9-2
9-5
9-5
10
10.1
Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
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10.1.1
UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.1.1
Mode 1, 8-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 10-2
10.1.1.2
Mode 2, 9-Bit UART, Fixed Baud Rate . . . . . . . . . . . . . . . . . . . . . 10-5
10.1.1.3
Mode 3, 9-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 10-5
10.1.2
Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.1.3
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.1.4
Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.1.4.1
Baud-rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.1.5
Interfaces of UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.2
LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.2.1
LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.2.2
LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.2.3
Baud Rate Detection of LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.3
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . 10-19
10.3.1
General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.3.1.1
Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.3.1.2
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.3.1.3
Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.3.1.4
Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.3.1.5
Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.3.1.6
Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.3.1.7
Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.3.2
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10.3.3
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10.3.4
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.3.4.1
Port Input Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.3.4.2
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.3.4.3
Baud Rate Timer Reload Register . . . . . . . . . . . . . . . . . . . . . . . . 10-37
10.3.4.4
Transmit and Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . 10-38
11
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1
Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.1
Basic Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.2
Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.1.2.1
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.2.2
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.1.2.3
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.1.2.4
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.1.3
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.1.4
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.2
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.2.1
Auto-Reload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.2.1.1
Up/Down Count Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
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Table of Contents
11.2.1.2
Up/Down Count Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.2
Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.3
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.4
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
11-14
11-16
11-17
11-17
12
12.1
12.1.1
12.1.1.1
12.1.1.2
12.1.1.3
12.1.1.4
12.1.1.5
12.1.1.6
12.1.1.7
12.1.1.8
12.1.1.9
12.1.2
12.1.2.1
12.1.2.2
12.1.2.3
12.1.2.4
12.1.3
12.1.4
12.1.5
12.1.6
12.1.6.1
12.1.6.2
12.1.7
12.1.8
12.2
12.3
12.3.1
12.3.1.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.5.1
12.3.5.2
12.3.6
Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Timer T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Counting Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Switching Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Compare Mode of T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Duty Cycle of 0% and 100% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Dead-time Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
Hysteresis-Like Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
Timer T13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Synchronization of T13 to T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
Multi-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
Sampling of the Hall Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
Brushless-DC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
Port Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
Timer T12 – Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
Timer T13 – Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41
Capture/Compare Control Registers . . . . . . . . . . . . . . . . . . . . . . . 12-45
Modulation Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57
Global Module Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57
Multi-Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-77
13
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
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Table of Contents
Page
13.1
Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2
Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2.1
Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3
Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.1
Request Source Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.4.2
Conversion Start Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.4.3
Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.4.4
Sequential Request Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.4.4.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.4.4.2
Request Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.4.5
Parallel Request Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.4.5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.4.5.2
Request Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.4.5.3
External Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.4.5.4
Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.4.5.5
Autoscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13.4.6
Wait-for-Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13.4.7
Result Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.4.7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.4.7.2
Limit Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.4.7.3
Data Reduction Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.4.7.4
Result FIFO Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.4.7.5
Result Register View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.4.8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
13.4.8.1
Event Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
13.4.8.2
Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
13.4.9
External Trigger Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
13.5
ADC Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
13.6
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
13.7
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31
13.7.1
General Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31
13.7.2
Priority and Arbitration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33
13.7.3
External Trigger Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35
13.7.4
Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36
13.7.5
Input Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-37
13.7.6
Sequential Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-38
13.7.7
Parallel Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-44
13.7.8
Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-48
13.7.9
Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-52
14
14.1
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
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Table of Contents
14.2
Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.1
Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.1.1
Hardware Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.1.2
Software Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.1.3
External Breaks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2
Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2.1
Call the Monitor Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2.2
Activate the MBC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.1
JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15.1
15.2
Page
14-3
14-3
14-4
14-5
14-6
14-6
14-6
14-6
14-7
14-9
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
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V 0.2, 2005-01
XC866
Introduction
1
Introduction
The XC866 is a member of the high-performance XC800 family of 8-bit microcontrollers.
It is based on the XC800 Core that is compatible with the industry standard 8051
processor. The XC866 features a great number of enhancements to enable new
application technologies through its highly integrated on-chip components, such as
on-chip oscillator or an integrated voltage regulator, allowing a single voltage supply of
3.0 to 5.5 V. In addition, the XC866 is equipped with either embedded Flash memory to
offer high flexibility in development and ramp-up, or compatible ROM versions to provide
cost-saving potential in high-volume production.
The multi-bank Flash architecture supports In-Application Programming (IAP), allowing
user program to run from one bank, while programming or erasing another bank.
In-System Programming (ISP) is available through the Boot ROM-based BootStrap
Loader (BSL), enabling convenient programming and erasing of the embedded Flash via
an external host (e.g., personal computer).
Other key features of the XC866 include a Capture/Compare Unit 6 (CCU6) for the
generation of pulse width modulated signal with special modes for motor control, and a
10-bit Analog-to-Digital Converter (ADC) with extended functionalities like autoscan and
result accumulation for anti-aliasing filtering or for averaging. Local Interconnect Network
(LIN) applications are also supported through extended UART features and the provision
of LIN low level drivers for most devices. For low power applications, various power
saving modes are available for selection by the user. Control of the numerous on-chip
peripheral functionalities is achieved by extending the Special Function Register (SFR)
address range with an intelligent paging mechanism optimized for interrupt handling.
Figure 1-1 shows the functional units of the XC866.
Flash or ROM 1)
8K/16K x 8
On-Chip Debug Support
Boot ROM
8K x 8
UART
SSC
Port 0
6-bit Digital I/O
Capture/Compare Unit
16-bit
Port 1
5-bit Digital I/O
Compare Unit
16-bit
Port 2
8-bit Digital/Analog Input
Port 3
8-bit Digital I/O
XC800 Core
XRAM
512 x 8
RAM
256 x 8
Timer 0
16-bit
Timer 1
16-bit
Timer 2
16-bit
Watchdog
Timer
ADC
10-bit
8-channel
1) All ROM devices include 4K x 8 Flash
Figure 1-1
User’s Manual
Intro, V 0.3
XC866 Functional Units
1-1
V 0.2, 2005-01
XC866
Introduction
The XC866 product family features eight devices with different configurations and
program memory sizes, offering cost-effective solution for different application
requirements. In general, each device contains a non-volatile 8K × 8 read-only program
memory, a volatile 768 × 8 read/write data memory, four ports, three 16-bit timers, a
16-bit capture/compare unit, a 16-bit compare timer, 14 interrupt vectors (and an NMI),
four priority-level interrupt structure, two serial ports, versatile fail-safe mechanisms,
on-chip debugging support logic and a 10-bit ADC.
The list of XC866 devices and their differences are summarized in Table 1-1.
Table 1-1
Device Summary
Device Type
Device Name
Flash Size
ROM Size
LIN Support
Flash
XC866L-4FR
16 Kbytes
–
Yes
XC866-4FR
16 Kbytes
–
No
XC866L-2FR
8 Kbytes
–
Yes
XC866-2FR
8 Kbytes
–
No
XC866L-4RR
4 Kbytes
16 Kbytes
Yes
XC866-4RR
4 Kbytes
16 Kbytes
No
XC866L-2RR
4 Kbytes
8 Kbytes
Yes
XC866-2RR
4 Kbytes
8 Kbytes
No
ROM
The term “XC866” in this document refers to all devices of the XC866 family unless
otherwise stated.
User’s Manual
Intro, V 0.3
1-2
V 0.2, 2005-01
XC866
Introduction
1.1
Feature Summary
The following list summarizes the main features of the XC866:
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 8 Kbytes of Boot ROM
– 256 bytes of RAM
– 512 bytes of XRAM
– 8/16 Kbytes of Flash; or
8/16 Kbytes of ROM, with additional 4 Kbytes of Flash
• I/O port supply at 3.0 to 5.5 V and core logic supply at 2.5 V (generated by embedded
voltage regulator)
• Power-on reset generation
• Brownout detection for core logic supply
• On-chip OSC and PLL for clock generation
– PLL loss-of-lock detection
• Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Four ports
– 19 pins as digital I/O
– 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Three 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2
• Capture/compare unit for PWM signal generation (CCU6)
• Full-duplex serial interface (UART)
• Synchronous serial channel (SSC)
• On-chip debug support
– 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM)
– 64 bytes of monitor RAM
• PG-TSSOP-38 pin package
• Temperature range TA:
– SAF (-40 to 85 °C)
– SAK (-40 to 125 °C)
User’s Manual
Intro, V 0.3
1-3
V 0.2, 2005-01
XC866
Introduction
The block diagram of the XC866 is shown in Figure 1-2.
XC866
XTAL1
XTAL2
UART
Port 0
T0 & T1
P1.0 - P1.1
P1.5-P1.7
P2.0 - P2.7
CCU6
512-byte XRAM
SSC
8/16-Kbyte
Flash or ROM 2)
Timer 2
ADC
Clock Generator
WDT
10 MHz
On-chip OSC
OCDS
PLL
Port 3
TMS
MBC
RESET
VDDP
VSSP
VDDC
VSSC
256-byte RAM
+
64-byte monitor
RAM
P0.0 - P0.5
Port 1
XC800 Core
Port 2
Internal Bus
8-Kbyte
Boot ROM 1)
VAREF
VAGND
P3.0 - P3.7
1) Includes 1-Kbyte monitor ROM
2) Includes additional 4-Kbyte Flash
Figure 1-2
User’s Manual
Intro, V 0.3
XC866 Block Diagram
1-4
V 0.2, 2005-01
XC866
Introduction
1.2
Pin Configuration
The pin configuration of the XC866, based on the PG-TSSOP-38 package, is shown in
Figure 1-3.
MBC
1
38
RESET
P0.3/SCLK_1/COUT63_1
2
37
P3.5/COUT62_0
P0.4/MTSR_1/CC62_1
3
36
P3.4/CC62_0
P0.5/MRST_1/EXINT0_0/COUT62_1
4
35
P3.3/COUT61_0
XTAL2
5
34
P3.2/CC61_0
XTAL1
6
33
P3.1/COUT60_0
VSSC
7
32
P3.0/CC60_0
VDDC
8
31
P3.7/EXINT4/COUT63_0
P1.6/CCPOS1_1/T12HR_0/EXINT6
9
30
P3.6/CTRAP_0/RSTOUT
29
P1.5/CCPOS0_1/EXINT5
P1.7/CCPOS2_1/T13HR_0
10
TMS
11
28
P1.1/EXINT3/TDO_1/TXD_0
P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT
12
27
P1.0/RXD_0/T2EX
P0.2/CTRAP_2/TDO_0/TXD_1
13
26
P2.7/AN7
P0.1/TDI_0/T13HR_1/RXD_1/COUT61_1
14
25
VAREF
P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/AN0
15
24
VAGND
P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/AN1
16
23
P2.6/AN6
P2.2/CCPOS2_0/CTRAP_1/AN2
17
22
P2.5/AN5
VDDP
18
21
P2.4/AN4
VSSP
19
20
P2.3/AN3
Figure 1-3
User’s Manual
Intro, V 0.3
XC866
XC866 Pin Configuration, PG-TSSOP-38 Package (top view)
1-5
V 0.2, 2005-01
XC866
Introduction
1.3
Pin Definitions and Functions
After reset, all pins are configured as input with one of the following:
• Pull-up device enabled (PU)
• Pull-down device enabled (PD)
• High impedance with both pull-up and pull-down devices disabled (Hi-Z)
The functions and default states of the XC866 external pins are provided in Table 1-2.
Table 1-2
Pin Definitions and Functions
Symbol Pin
Type Reset Function
Number
State
P0
P0.0
I/O
12
Port 0
Port 0 is a 6-bit bidirectional general purpose I/O
port. It can be used as alternate functions for the
JTAG, CCU6, UART, and the SSC.
Hi-Z
TCK_0
T12HR_1
CC61_1
CLKOUT
JTAG Clock Input
CCU6 Timer 12 Hardware Run
Input
Input/Output of Capture/Compare
channel 1
10 MHz On-Chip OSC Clock
Output
P0.1
14
Hi-Z
TDI_0
T13HR_1
JTAG Serial Data Input
CCU6 Timer 13 Hardware Run
Input
RXD_1
UART Receive Input
COUT61_1 Output of Capture/Compare
channel 1
P0.2
13
PU
CTRAP_2
TDO_0
TXD_1
P0.3
2
Hi-Z
SCK_1
SSC Clock Input/Output
COUT63_1 Output of Capture/Compare
channel 3
P0.4
3
Hi-Z
MTSR_1
CC62_1
User’s Manual
Intro, V 0.3
1-6
CCU6 Trap Input
JTAG Serial Data Output
UART Transmit Output
SSC Master Transmit Output/
Slave Receive Input
Input/Output of Capture/Compare
channel 2
V 0.2, 2005-01
XC866
Introduction
Table 1-2
Pin Definitions and Functions (cont’d)
Symbol Pin
Type Reset Function
Number
State
P0.5
4
User’s Manual
Intro, V 0.3
Hi-Z
MRST_1
SSC Master Receive Input/
Slave Transmit Output
EXINT0_0 External Interrupt Input 0
COUT62_1 Output of Capture/Compare
channel 2
1-7
V 0.2, 2005-01
XC866
Introduction
Table 1-2
Pin Definitions and Functions (cont’d)
Symbol Pin
Type Reset Function
Number
State
P1
I/O
Port 1
Port 1 is a 5-bit bidirectional general purpose I/O
port. It can be used as alternate functions for the
JTAG, CCU6, UART, and the SSC.
P1.0
27
PU
RXD_0
T2EX
UART Receive Input
Timer 2 External Trigger Input
P1.1
28
PU
EXINT3
TDO_1
TXD_0
External Interrupt Input 3
JTAG Serial Data Output
UART Transmit Output
P1.5
29
PU
CCPOS0_1 CCU6 Hall Input 0
EXINT5
External Interrupt Input 5
P1.6
9
PU
CCPOS1_1 CCU6 Hall Input 1
T12HR_0
CCU6 Timer 12 Hardware Run
Input
EXINT6
External Interrupt Input 6
P1.7
10
PU
CCPOS2_1 CCU6 Hall Input 2
T13HR_0
CCU6 Timer 13 Hardware Run
Input
P1.5 and P1.6 can be used as a software chip
select output for the SSC.
User’s Manual
Intro, V 0.3
1-8
V 0.2, 2005-01
XC866
Introduction
Table 1-2
Pin Definitions and Functions (cont’d)
Symbol Pin
Type Reset Function
Number
State
P2
I
Port 2
Port 2 is an 8-bit general purpose input-only port. It
can be used as alternate functions for the digital
inputs of the JTAG and CCU6. It is also used as the
analog inputs for the ADC.
P2.0
15
Hi-Z
CCPOS0_0 CCU6 Hall Input 0
EXINT1
External Interrupt Input 1
T12HR_2
CCU6 Timer 12 Hardware Run
Input
TCK_1
JTAG Clock Input
AN0
Analog Input 0
P2.1
16
Hi-Z
CCPOS1_0 CCU6 Hall Input 1
EXINT2
External Interrupt Input 2
T13HR_2
CCU6 Timer 13 Hardware Run
Input
TDI_1
JTAG Serial Data Input
AN1
Analog Input 1
P2.2
17
Hi-Z
CCPOS2_0 CCU6 Hall Input 2
CCU6 Trap Input
CTRAP_1
AN2
Analog Input 2
P2.3
20
Hi-Z
AN3
Analog Input 3
P2.4
21
Hi-Z
AN4
Analog Input 4
P2.5
22
Hi-Z
AN5
Analog Input 5
P2.6
23
Hi-Z
AN6
Analog Input 6
P2.7
26
Hi-Z
AN7
Analog Input 7
User’s Manual
Intro, V 0.3
1-9
V 0.2, 2005-01
XC866
Introduction
Table 1-2
Pin Definitions and Functions (cont’d)
Symbol Pin
Type Reset Function
Number
State
P3
I
Port 3
Port 3 is a bidirectional general purpose I/O port. It
can be used as alternate functions for the CCU6.
P3.0
32
Hi-Z
CC60_0
P3.1
33
Hi-Z
COUT60_0 Output of Capture/Compare
channel 0
P3.2
34
Hi-Z
CC61_0
P3.3
35
Hi-Z
COUT61_0 Output of Capture/Compare
channel 1
P3.4
36
Hi-Z
CC62_0
P3.5
37
Hi-Z
COUT62_0 Output of Capture/Compare
channel 2
P3.6
30
PD
CTRAP_0
RSTOUT
P3.7
31
Hi-Z
EXINT4
External Interrupt Input 4
COUT63_0 Output of Capture/Compare
channel 3
User’s Manual
Intro, V 0.3
1-10
Input/Output of Capture/Compare
channel 0
Input/Output of Capture/Compare
channel 1
Input/Output of Capture/Compare
channel 2
CCU6 Trap Input
Reset output indication for internal
reset condition in microcontroller
V 0.2, 2005-01
XC866
Introduction
Table 1-2
Pin Definitions and Functions (cont’d)
Symbol Pin
Type Reset Function
Number
State
VDDP
VSSP
VDDC
VSSC
VAREF
VAGND
18
–
–
I/O Port Supply (3.0 - 5.5 V)
19
–
–
I/O Port Ground
8
–
–
Core Supply Output (2.5 V)
7
–
–
Core Supply Ground
25
–
–
ADC Reference Voltage
24
–
–
ADC Reference Ground
XTAL1
6
I
Hi-Z
External Oscillator Input
(backup for on-chip OSC, normally NC)
XTAL2
5
O
Hi-Z
External Oscillator Output
(backup for on-chip OSC, normally NC)
TMS
11
I
PD
Test Mode Select
RESET
38
I
PU
Reset Input for PG-TSSOP-38 package
MBC
1
I
PU
Monitor & BootStrap Loader Control
User’s Manual
Intro, V 0.3
1-11
V 0.2, 2005-01
XC866
Introduction
1.4
Textual Convention
This document uses the following textual conventions for named components of the
XC866:
• Functional units of the XC866 are shown in upper case. For example: “The SSC can
be used to communicate with shift registers.”
• Pins using negative logic are indicated by an overbar. For example: “A reset input pin
RESET is provided for the hardware reset.”
• Bit fields and bits in registers are generally referenced as “Register name.Bit field” or
“Register name.Bit”. Most of the register names contain a module name prefix,
separated by an underscore character “_” from the actual register name. In the
example of “SSC_CON”, “SSC” is the module name prefix, and “CON” is the actual
register name).
• Variables that are used to represent sets of processing units or registers appear in
mixed-case type. For example, the register name “CC6xR” refers to multiple “CC6xR”
registers with the variable x (x = 0, 1, 2). The bounds of the variables are always
specified where the register expression is first used (e.g., “x = 0 - 2”), and is repeated
as needed.
• The default radix is decimal. Hexadecimal constants have a suffix with the subscript
letter “H” (e.g., C0H). Binary constants have a suffix with the subscript letter “B”
(e.g., 11B).
• When the extents of register fields, groups of signals, or groups of pins are collectively
named in the body of the document, they are represented as “NAME[A:B]”, which
defines a range, from B to A, for the named group. Individual bits, signals, or pins are
represented as “NAME[C]”, with the range of the variable C provided in the text
(e.g., CFG[2:0] and TOS[0]).
• Units are abbreviated as follows:
– MHz
= Megahertz
– µs
= Microseconds
– kBaud, kbit
= 1000 characters/bits per second
– MBaud, Mbit
= 1,000,000 characters/bits per second
– Kbyte
= 1024 bytes of memory
– Mbyte
= 1,048,576 bytes of memory
In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by
1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The kBaud
unit scales the expression preceding it by 1000. The M prefix scales by 1,000,000 or
1,048,576, and µ scales by 0.000001. For example, 1 Kbyte is 1024 bytes, 1 Mbyte is
1024 × 1024 bytes, 1 kBaud/kbit are 1000 characters/bits per second, 1 MBaud/Mbit
are 1,000,000 characters/bits per second, and 1 MHz is 1,000,000 Hz.
• Data format quantities are defined as follows:
– byte
= 8-bit quantity
User’s Manual
Intro, V 0.3
1-12
V 0.2, 2005-01
XC866
Introduction
1.5
Reserved, Undefined and Unimplemented Terminology
In tables where register bit fields are defined, the following conventions are used to
indicate undefined and unimplemented function. Further, types of bits and bit fields are
defined using the abbreviations shown in Table 1-3.
Table 1-3
Bit Function Terminology
Function of Bits
Description
Unimplemented
Register bit fields named “0” indicate unimplemented functions
with the following behavior.
– Reading these bit fields returns 0.
– Writing to these bit fields has no effect.
These bit fields are reserved. When writing, software should
always set such bit fields to 0 in order to preserve compatibility
with future products. Setting the bit fields to 1 may lead to
unpredictable results.
Undefined
Certain bit combinations in a bit field can be labeled “Reserved”,
indicating that the behavior of the XC866 is undefined for that
combination of bits. Setting the register to undefined bit
combinations may lead to unpredictable results. Such bit
combinations are reserved. When writing, software must always
set such bit fields to legal values as provided in the bit field
description tables.
rw
The bit or bit field can be read and written.
r
The bit or bit field can only be read (read-only).
w
The bit or bit field can only be written (write-only). Reading
always return 0.
h
The bit or bit field can also be modified by hardware (such as a
status bit). This attribute can be combined with ‘rw’ or ‘r’ bits to
‘rwh’ and ‘rh’ bits, respectively.
User’s Manual
Intro, V 0.3
1-13
V 0.2, 2005-01
XC866
Introduction
1.6
Acronyms
Table 1-4 lists the acronyms used in this document.
Table 1-4
Acronyms
ADC
Analog-to-Digital Converter
ALU
Arithmetic/Logic Unit
BSL
BootStrap Loader
CCU6
Capture/Compare Unit 6
CGU
Clock Generation Unit
CPU
Central Processing Unit
ECC
Error Correction Code
EVR
Embedded Voltage Regulator
FIFO
First-In First-Out
GPIO
General Purpose I/O
IAP
In-Application Programming
I/O
Input/Output
ISP
In-System Programming
JTAG
Joint Test Action Group
LIN
Local Interconnect Network
NMI
Non-Maskable Interrupt
OCDS
On-Chip Debug Support
PC
Program Counter
POR
Power-On Reset
PLL
Phase-Locked Loop
PSW
Program Status Word
PWM
Pulse Width Modulation
RAM
Random Access Memory
ROM
Read-Only Memory
SFR
Special Function Register
SPI
Serial Peripheral Interface
SSC
Synchronous Serial Controller
UART
Universal Asynchronous Receiver/Transmitter
WDT
Watchdog Timer
User’s Manual
Intro, V 0.3
1-14
V 0.2, 2005-01
XC866
Processor Architecture
2
Processor Architecture
The XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is
compatible with the standard 8051 processor. While the standard 8051 processor is
designed around a 12-clock machine cycle, the XC866 CPU uses a 2-clock machine
cycle. This allows fast access to ROM or RAM memories without wait state. Access to
the Flash memory, however, requires an additional wait state (one machine cycle).
See Section 2.3. The instruction set consists of 45% one-byte, 41% two-byte and 14%
three-byte instructions.
The XC866 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and SFRs.
Features:
•
•
•
•
•
•
•
•
•
Two clocks per machine cycle architecture (for memory access without wait state)
Wait state support for Flash memory
Program memory download option
15-source, 4-level interrupt controller
Two data pointers
Power saving modes
Dedicated debug mode and debug signals
Two 16-bit timers (Timer 0 and Timer 1)
Full-duplex serial port (UART)
User’s Manual
Processor Architecture, V 0.3
2-1
V 0.2, 2005-01
XC866
Processor Architecture
2.1
Functional Description
Figure 2-1 shows the CPU functional blocks. The CPU consists of the instruction
decoder, the arithmetic section, and the program control section. Each program
instruction is decoded by the instruction decoder. This instruction decoder generates
internal signals that control the functions of the individual units within the CPU. The
internal signals have an effect on the source and destination of data transfers and control
the arithmetic/logic unit (ALU) processing.
Internal Data
Memory
Core SFRs
Register Interface
External Data
Memory
Program Memory
fCCLK
Memory Wait
Reset
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Non-Maskable Interrupt
Figure 2-1
External SFRs
16-bit Registers &
Memory Interface
ALU
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
State Machine &
Power Saving
UART
Interrupt
Controller
CPU Block Diagram
User’s Manual
Processor Architecture, V 0.3
2-2
V 0.2, 2005-01
XC866
Processor Architecture
The arithmetic section of the processor performs extensive data manipulation and
consists of the ALU, ACC register, B register, and PSW register.
The ALU accepts 8-bit data words from one or two sources, and generates an 8-bit result
under the control of the instruction decoder. The ALU performs both arithmetic and logic
operations. Arithmetic operations include add, subtract, multiply, divide, increment,
decrement, BCD-decimal-add-adjust, and compare. Logic operations include AND, OR,
Exclusive OR, complement, and rotate (right, left, or swap nibble (left four)). Also
included is a Boolean processor performing the bit operations such as set, clear,
complement, jump-if-set, jump-if-not-set, jump-if-set-and-clear, and move to/from carry.
The ALU can perform the bit operations of logical AND or logical OR between any
addressable bit (or its complement) and the carry flag, and place the new result in the
carry flag.
The program control section controls the sequence in which the instructions stored in
program memory are executed. The 16-bit Program Counter (PC) holds the address of
the next instruction to be executed. The conditional branch logic enables internal and
external events to the processor to cause a change in the program execution sequence.
User’s Manual
Processor Architecture, V 0.3
2-3
V 0.2, 2005-01
XC866
Processor Architecture
2.2
CPU Register Description
The CPU registers occupy direct Internal Data Memory space locations in the range 80H
to FFH.
2.2.1
Stack Pointer (SP)
The SP register contains the Stack Pointer (SP). The SP is used to load the Program
Counter (PC) into Internal Data Memory during LCALL and ACALL instructions, and to
retrieve the PC from memory during RET and RETI instructions. Data may also be saved
on or retrieved from the stack using PUSH and POP instructions, respectively.
Instructions that use the stack automatically pre-increment or post-decrement the stack
pointer so that the stack pointer always points to the last byte written to the stack, i.e.,
the top of the stack. On reset, the SP is reset to 07H. This causes the stack to begin at
a location = 08H above register bank zero. The SP can be read or written under software
control.
2.2.2
Data Pointer (DPTR)
The Data Pointer (DPTR) is stored in registers DPL (Data Pointer Low byte) and DPH
(Data Pointer High byte) to form 16-bit addresses for External Data Memory accesses
(MOVX A,@DPTR
and
MOVX @DPTR,A),
for
program
byte
moves
(MOVC A,@A+DPTR), and for indirect program jumps (JMP @A+DPTR).
Two true 16-bit operations are allowed on the Data Pointer: load immediate
(MOV DPTR,#data) and increment (INC DPTR).
2.2.3
Accumulator (ACC)
This register provides one of the operands for most ALU operations. While ACC is the
symbol for the accumulator register, the mnemonics for accumulator-specific
instructions refer to the accumulator simply as “A”.
2.2.4
B Register
The B register is used during multiply and divide operations to provide the second
operand. For other instructions, it can be treated as another scratch pad register.
User’s Manual
Processor Architecture, V 0.3
2-4
V 0.2, 2005-01
XC866
Processor Architecture
2.2.5
Program Status Word
The Program Status Word (PSW) contains several status bits that reflect the current
state of the CPU.
PSW
Program Status Word Register
Reset Value: 00H
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
rw
rwh
rwh
rw
rw
rwh
rwh
rh
Field
Bits
Type Description
P
0
rh
Parity Flag
Set/cleared by hardware after each instruction to
indicate an odd/even number of “one” bits in the
accumulator, i.e., even parity.
F1
1
rwh
General Purpose Flag
OV
2
rwh
Overflow Flag
Used by arithmetic instructions
RS0
RS1
3
4
rw
Register Bank Select
These bits are used to select one of the four register
banks.
RS1 RS0 Function
0
0
Bank 0 selected, data address 00H-07H
0
1
Bank 1 selected, data address 08H-0FH
1
0
Bank 2 selected, data address 10H-17H
1
1
Bank 3 selected, data address 18H-1FH
F0
5
rwh
General Purpose Flag
AC
6
rwh
Auxiliary Carry Flag
Used by instructions that execute BCD operations
CY
7
rw
Carry Flag
Used by arithmetic instructions
User’s Manual
Processor Architecture, V 0.3
2-5
V 0.2, 2005-01
XC866
Processor Architecture
2.2.6
Extended Operation Register (EO)
The instruction set includes an additional instruction MOVC @(DPTR++),A which allows
program memory to be written. This instruction may be used to download code into the
program memory when the CPU is initialized and subsequently, also to provide software
updates. The instruction copies the contents of the accumulator to the code memory at
the location pointed to by the current data pointer, and then increments the data pointer.
The instruction uses the opcode A5H, which is the same as the software break instruction
TRAP (see Table 2-1). Register bit EO.TRAP_EN is used to select the instruction
executed by the opcode A5H. When TRAP_EN is 0 (default), the A5H opcode executes
the MOVC instruction. When TRAP_EN is 1, the A5H opcode executes the software
break instruction TRAP, which switches the CPU to debug mode for breakpoint
processing.
EO
Extended Operation Register
7
6
5
Reset Value: 00H
4
3
2
1
0
0
TRAP_EN
0
DPSEL0
r
rw
r
rw
Field
Bits
Type Description
DPSEL0
0
rw
Data Pointer Select
0
DPTR0 is selected.
1
DPTR1 is selected.
TRAP_EN
4
rw
TRAP Enable
0
Select MOVC @(DPTR++),A
1
Select software TRAP instruction
0
[3:1],
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Processor Architecture, V 0.3
2-6
V 0.2, 2005-01
XC866
Processor Architecture
2.2.7
Power Control Register (PCON)
The CPU has two power-saving modes: idle mode and power-down mode. The idle
mode can be entered via the PCON register. In idle mode, the clock to the CPU is
stopped while the timers, serial port and interrupt controller continue to run using a
half-speed clock. In power-down mode, the clock to the entire CPU is stopped.
PCON
Power Control Register
7
6
Reset Value: 00H
5
4
3
2
1
0
SMOD
0
GF1
GF0
0
IDLE
rw
r
rw
rw
r
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
IDLE
0
rw
Idle Mode Enable
0
Do not enter idle mode
1
Enter idle mode
GF0
2
rw
General Purpose Flag Bit 0
GF1
3
rw
General Purpose Flag Bit 1
User’s Manual
Processor Architecture, V 0.3
2-7
V 0.2, 2005-01
XC866
Processor Architecture
2.3
Instruction Timing
For memory access without wait state, a CPU machine cycle comprises two input clock
periods referred to as Phase 1 (P1) and Phase 2 (P2) that correspond to two different
CPU states. A CPU state within an instruction is denoted by reference to the machine
cycle and state number, e.g., C2P1 is the first clock period within machine cycle 2.
Memory accesses take place during one or both phases of the machine cycle. SFR
writes only occur at the end of P2. An instruction takes one, two or four machine cycles
to execute. Registers are generally updated and the next opcode read at the end of P2
of the last machine cycle for the instruction.
With each access to the Flash memory, instruction execution times are extended by one
machine cycle (one wait state), starting from either P1 or P2.
Figure 2-2 shows the fetch/execute timing related to the internal states and phases.
Execution of an instruction occurs at C1P1. For a 2-byte instruction, the second reading
starts at C1P1.
Figure 2-2 (a) shows two timing diagrams for a 1-byte, 1-cycle (1 × machine cycle)
instruction. The first diagram shows the instruction being executed within one machine
cycle since the opcode (C1P2) is fetched from a memory without wait state. The second
diagram shows the corresponding states of the same instruction being executed over
two machine cycles (instruction time extended), with one wait state inserted for opcode
fetching from the Flash memory.
Figure 2-2 (b) shows two timing diagrams for a 2-byte, 1-cycle (1 × machine cycle)
instruction. The first diagram shows the instruction being executed within one machine
cycle since the second byte (C1P1) and the opcode (C1P2) are fetched from a memory
without wait state. The second diagram shows the corresponding states of the same
instruction being executed over three machine cycles (instruction time extended), with
one wait state inserted for each access to the Flash memory (two wait states inserted in
total).
Figure 2-2 (c) shows two timing diagrams of a 1-byte, 2-cycle (2 × machine cycle)
instruction. The first diagram shows the instruction being executed over two machine
cycles with the opcode (C2P2) fetched from a memory without wait state. The second
diagram shows the corresponding states of the same instruction being executed over
three machine cycles (instruction time extended), with one wait state inserted for opcode
fetching from the Flash memory.
User’s Manual
Processor Architecture, V 0.3
2-8
V 0.2, 2005-01
XC866
Processor Architecture
fCCLK
Read next opcode
(without wait state)
C1P1
C1P2
next instruction
Read next opcode
(one wait state)
C1P1
C1P2
WAIT
WAIT
next instruction
(a) 1-byte, 1-cycle instruction, e.g. INC A
Read 2nd byte
(without wait state)
C1P1
Read next opcode
(without wait state)
C1P2
next instruction
Read 2nd byte
(one wait state)
C1P1
WAIT
Read next opcode
(one wait state)
WAIT
C1P2
WAIT
WAIT
next instruction
(b) 2-byte, 1-cycle instruction, e.g. ADD A, #data
Read next opcode
(without wait state)
C1P1
C1P2
C2P1
C2P2
next instruction
Read next opcode
(one wait state)
C1P1
C1P2
C2P1
C2P2
WAIT
WAIT
next instruction
(b) 1-byte, 2-cycle instruction, e.g. MOVX
Figure 2-2
CPU Instruction Timing
User’s Manual
Processor Architecture, V 0.3
2-9
V 0.2, 2005-01
XC866
Processor Architecture
Instructions are 1, 2 or 3 bytes long as indicated in the “Bytes” column of Table 2-1. For
the XC866, the time taken for each instruction includes:
• decoding/executing the fetched opcode
• fetching the operand/s (for instructions > 1 byte)
• fetching the first byte (opcode) of the next instruction (due to XC866 CPU pipeline)
Note: The XC866 CPU fetches the opcode of the next instruction while executing the
current instruction.
Table 2-1 provides a reference for the number of clock cycles required by each
instruction. The first value applies to fetching operand(s) and opcode from fast program
memory (e.g., Boot ROM and XRAM) without wait state. The second value applies to
fetching operand(s) and opcode from slow program memory (e.g., Flash) with one wait
state inserted. The instruction time for the standard 8051 processor is provided in the last
column for performance comparison with the XC866 CPU. Even with one wait state
inserted for each byte of operand/opcode fetched, the XC866 CPU executes instructions
faster than the standard 8051 processor by a factor of between two (e.g., 2-byte, 1-cycle
instructions) to six (e.g., 1-byte, 4-cycle instructions).
Table 2-1
CPU Instruction Timing
Mnemonic
Hex Code Bytes
Number of fCCLK Cycles
XC866
no ws
8051
1 ws
ARITHMETIC
ADD A,Rn
28-2F
1
2
4
12
ADD A,dir
25
2
2
6
12
ADD A,@Ri
26-27
1
2
4
12
ADD A,#data
24
2
2
6
12
ADDC A,Rn
38-3F
1
2
4
12
ADDC A,dir
35
2
2
6
12
ADDC A,@Ri
36-37
1
2
4
12
ADDC A,#data
34
2
2
6
12
SUBB A,Rn
98-9F
1
2
4
12
SUBB A,dir
95
2
2
6
12
SUBB A,@Ri
96-97
1
2
4
12
SUBB A,#data
94
2
2
6
12
INC A
04
1
2
4
12
08-0F
1
2
4
12
INC Rn
User’s Manual
Processor Architecture, V 0.3
2-10
V 0.2, 2005-01
XC866
Processor Architecture
Table 2-1
CPU Instruction Timing (cont’d)
Mnemonic
Hex Code Bytes
Number of fCCLK Cycles
XC866
no ws
INC dir
8051
1 ws
05
2
2
6
12
06-07
1
2
4
12
14
1
2
4
12
DEC Rn
18-1F
1
2
4
12
DEC dir
15
2
2
6
12
DEC @Ri
16-17
1
2
4
12
INC DPTR
A3
1
4
4
24
MUL AB
A4
1
8
8
48
DIV AB
84
1
8
8
48
DA A
D4
1
2
4
12
INC @Ri
DEC A
LOGICAL
ANL A,Rn
58-5F
1
2
4
12
ANL A,dir
55
2
2
6
12
ANL A,@Ri
56-57
1
2
4
12
ANL A,#data
54
2
2
6
12
ANL dir,A
52
2
2
6
12
ANL dir,#data
53
3
4
10
24
ORL A,Rn
48-4F
1
2
4
12
ORL A,dir
45
2
2
6
12
ORL A,@Ri
46-47
1
2
4
12
ORL A,#data
44
2
2
6
12
ORL dir,A
42
2
2
6
12
ORL dir,#data
43
3
4
10
24
XRL A,Rn
68-6F
1
2
4
12
XRL A,dir
65
2
2
6
12
XRL A,@Ri
66-67
1
2
4
12
XRL A,#data
64
2
2
6
12
XRL dir,A
62
2
2
6
12
User’s Manual
Processor Architecture, V 0.3
2-11
V 0.2, 2005-01
XC866
Processor Architecture
Table 2-1
CPU Instruction Timing (cont’d)
Mnemonic
Hex Code Bytes
Number of fCCLK Cycles
XC866
no ws
8051
1 ws
XRL dir,#data
63
3
4
10
24
CLR A
E4
1
2
4
12
CPL A
F4
1
2
4
12
SWAP A
C4
1
2
4
12
RL A
23
1
2
4
12
RLC A
33
1
2
4
12
RR A
03
1
2
4
12
RRC A
13
1
2
4
12
DATA TRANSFER
MOV A,Rn
E8-EF
1
2
4
12
MOV A,dir
E5
2
2
6
12
MOV A,@Ri
E6-E7
1
2
4
12
MOV A,#data
74
2
2
6
12
MOV Rn,A
F8-FF
1
2
4
12
MOV Rn,dir
A8-AF
2
4
8
24
MOV Rn,#data
78-7F
2
2
6
12
F5
2
2
6
12
MOV dir,Rn
88-8F
2
4
8
24
MOV dir,dir
85
3
4
10
24
MOV dir,@Ri
86-87
2
4
8
24
MOV dir,#data
75
3
4
10
24
MOV @Ri,A
F6-F7
1
2
4
12
MOV @Ri,dir
A6-A7
2
4
8
24
MOV @Ri,#data
76-77
2
2
6
12
MOV DPTR,#data
90
3
4
10
24
MOVC A,@A+DPTR
93
1
4
6
24
MOVC A,@A+PC
83
1
4
6
24
E2-E3
1
4
6
24
MOV dir,A
MOVX A,@Ri
User’s Manual
Processor Architecture, V 0.3
2-12
V 0.2, 2005-01
XC866
Processor Architecture
Table 2-1
CPU Instruction Timing (cont’d)
Mnemonic
Hex Code Bytes
Number of fCCLK Cycles
XC866
no ws
MOVX A,@DPTR
8051
1 ws
E0
1
4
6
24
F2-F3
1
4
6
24
MOVX @DPTR,A
F0
1
4
6
24
PUSH dir
C0
2
4
8
24
POP dir
D0
2
4
8
24
XCH A,Rn
C8-CF
1
2
4
12
XCH A,dir
C5
2
2
6
12
XCH A,@Ri
C6-C7
1
2
4
12
XCHD A,@Ri
D6-D7
1
2
4
12
MOVX @Ri,A
BOOLEAN
CLR C
C3
1
2
4
12
CLR bit
C2
2
2
6
12
SETB C
D3
1
2
4
12
SETB bit
D2
2
2
6
12
CPL C
B3
1
2
4
12
CPL bit
B2
2
2
6
12
ANL C,bit
82
2
4
8
24
ANL C,/bit
B0
2
4
8
24
ORL C,bit
72
2
4
8
24
ORL C,/bit
A0
2
4
8
24
MOV C,bit
A2
2
2
6
12
MOV bit,C
92
2
4
8
24
BRANCHING
ACALL addr11
11->F1
2
4
8
24
LCALL addr16
12
3
4
10
24
RET
22
1
4
4
24
RETI
32
1
4
4
24
01->E1
2
4
8
24
AJMP addr 11
User’s Manual
Processor Architecture, V 0.3
2-13
V 0.2, 2005-01
XC866
Processor Architecture
Table 2-1
CPU Instruction Timing (cont’d)
Mnemonic
Hex Code Bytes
Number of fCCLK Cycles
XC866
no ws
8051
1 ws
LJMP addr 16
02
3
4
10
24
SJMP rel
80
2
4
8
24
JC rel
40
2
4
8
24
JNC rel
50
2
4
8
24
JB bit,rel
20
3
4
10
24
JNB bit,rel
30
3
4
10
24
JBC bit,rel
10
3
4
10
24
JMP @A+DPTR
73
1
4
4
24
JZ rel
60
2
4
8
24
JNZ rel
70
2
4
8
24
CJNE A,dir,rel
B5
3
4
10
24
CJNE A,#d,rel
B4
3
4
10
24
CJNE Rn,#d,rel
B8-BF
3
4
10
24
CJNE @Ri,#d,rel
B6-B7
3
4
10
24
DJNZ Rn,rel
D8-DF
2
4
8
24
DJNZ dir,rel
D5
3
4
10
24
1
2
4
12
MISCELLANEOUS
NOP
00
ADDITIONAL INSTRUCTIONS
MOVC @(DPTR++),A
A5
1
4
4
–
TRAP
A5
1
2
tbd
–
User’s Manual
Processor Architecture, V 0.3
2-14
V 0.2, 2005-01
XC866
Memory Organization
3
Memory Organization
The XC866 CPU operates in the following five address spaces:
• 8 Kbytes of Boot ROM program memory
• 256 bytes of internal RAM data memory
• 512 bytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
• a 128-byte Special Function Register area
• 8/16 Kbytes of Flash program memory (Flash devices); or
8/16 Kbytes of ROM program memory, with additional 4 Kbytes of Flash
(ROM devices)
Figure 3-1 illustrates the memory address spaces of the 16-Kbyte Flash devices. For the
8-Kbyte Flash devices, the shaded banks are not available.
FFFF H
XRAM
512 bytes
F200H
F000H
FFFF H
XRAM
512 bytes
F200H
F000H
E000H
Boot ROM
8 Kbytes
C000H
B000H
D-Flash Bank
4 Kbytes
A000H
3000H
Indirect
Address
Direct
Address
2000H
Internal RAM
Special Function
Registers
P-Flash Bank 2
4 Kbytes
80H
P-Flash Bank 1
4 Kbytes
1000H
7FH
P-Flash Bank 0
4 Kbytes
Internal RAM
0000H
Program Space
Figure 3-1
FFH
0000H
External Data Space
00H
Internal Data Space
Memory Map of XC866 Flash Device
User’s Manual
Memory Organization, V 0.2
3-1
V 0.2, 2005-01
XC866
Memory Organization
Figure 3-2 illustrates the memory address spaces of the 16-Kbyte ROM devices. For the
8-Kbyte ROM devices, the shaded address regions are not available.
FFFF H
XRAM
512 bytes
F200H
F000H
FFFF H
XRAM
512 bytes
F200H
F000H
E000H
Boot ROM
8 Kbytes
C000H
B000H
D-Flash Bank
4 Kbytes
A000H
4000H
ROM
16 Kbytes
2000H
Indirect
Address
Direct
Address
Internal RAM
Special Function
Registers
FFH
80H
7FH
Internal RAM
0000H
Program Space
Figure 3-2
0000H
External Data Space
00H
Internal Data Space
Memory Map of XC866 ROM Device
User’s Manual
Memory Organization, V 0.2
3-2
V 0.2, 2005-01
XC866
Memory Organization
3.1
Program Memory
The performance of the CPU is optimized with a dedicated interface for direct interfacing
with the program memory without using any port pin. This means that a code fetch can
occur on every rising edge of the clock. Hence, there is no concept of ‘internal’ or
‘external’ program memory as all code is fetched from a single program memory
interface.
3.2
Data Memory
The data memory space consists of an internal and external memory space. The labels
‘internal’ and ‘external’ for data memory are used to distinguish between the register
memory and the 64-Kbyte data space accessed using ‘MOVX’ instructions. They do not
imply that the external data memory is located off-chip.
3.2.1
Internal Data Memory
The internal data memory is divided into two physically separate and distinct blocks: the
256-byte RAM and the 128-byte Special Function Register (SFR) area. While the upper
128 bytes of RAM and the SFR area share the same address locations, they are
accessed through different addressing modes. The lower 128 bytes of RAM can be
accessed through either direct or register indirect addressing, while the upper 128 bytes
of RAM can be accessed through register indirect addressing only. The SFRs are
accessible through direct addressing.
The 16 bytes of RAM that occupy addresses from 20H to 2FH are bitaddressable. RAM
occupying direct addresses from 30H to 7FH can be used as scratch pad registers or
used for the stack.
3.2.2
External Data Memory
The 512-byte XRAM is mapped to both the external data memory area and the program
memory area. It can be accessed using both ‘MOVX’ and ‘MOVC’ instructions.
User’s Manual
Memory Organization, V 0.2
3-3
V 0.2, 2005-01
XC866
Memory Organization
3.3
Special Function Registers
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80H to FFH. All registers, except the program counter, reside in the SFR area. The
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
• Mapping
• Paging
3.3.1
Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80H to FFH, bringing the number
of addressable SFRs to 256. The extended address range is not directly controlled by
the CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed
by clearing bit RMAP. The SFR area can be selected as shown in Figure 3-3.
SYSCON0
System Control Register 0
7
6
Reset Value: 00H
5
4
3
2
1
0
0
RMAP
r
rw
Field
Bits
Type Description
RMAP
0
rw
Special Function Register Map Control
0
The access to the standard SFR area is
enabled.
1
The access to the mapped SFR area is
enabled.
0
[7:1]
r
Reserved
Returns 0 if read; should be written with 0.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
User’s Manual
Memory Organization, V 0.2
3-4
V 0.2, 2005-01
XC866
Memory Organization
S ta n d a rd A re a (R M A P = 0 )
FF
H
80
H
FF
H
80
H
M o d u le 1 S F R s
S Y S C O N 0 .R M A P
M o d u le 2 S F R s
rw
… ...
M o d u le n S F R s
S F R D a ta
(to /fro m C P U )
M a p p e d A re a (R M A P = 1 )
M o d u le ( n + 1 ) S F R s
M o d u le ( n + 2 ) S F R s
… ...
M o d u le m S F R s
D ir e c t
In te rn a l D a ta
M e m o ry A d d re s s
Figure 3-3
Address Extension by Mapping
User’s Manual
Memory Organization, V 0.2
3-5
V 0.2, 2005-01
XC866
Memory Organization
3.3.2
Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC866 has a 256-SFR address range. However, this is still
less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFR of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFR. A page inside
the extended address range can be selected as shown in Figure 3-4.
S F R A d d re s s
(fro m C P U )
PAGE 0
M O D _ P A G E .P A G E
SFR0
rw
SFR1
… ...
SFRx
PAGE 1
SFR0
S F R D a ta
(to /fro m C P U )
SFR1
… ...
SFRy
… ...
PAGE q
SFR0
SFR1
… ...
SFRz
M o d u le
Figure 3-4
Address Extension by Paging
User’s Manual
Memory Organization, V 0.2
3-6
V 0.2, 2005-01
XC866
Memory Organization
In order to access a register located in a page different from the actual one, the current
page must be left. This is done by reprogramming the bit field PAGE in the page register.
Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed and finally, the old page
setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and
restore action of the current page setting. By indicating which storage bit field should be
used in parallel with the new page value, a single write operation can:
• Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to
the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
PAGE
value update
from CPU
Figure 3-5
Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC866 supports local address extension for:
•
•
•
•
Parallel Ports
Analog-to-Digital Converter (ADC)
Capture/Compare Unit 6 (CCU6)
System Control Registers
User’s Manual
Memory Organization, V 0.2
3-7
V 0.2, 2005-01
XC866
Memory Organization
The page register has the following definition:
MOD_PAGE
Page Register for module MOD
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
0
PAGE
w
w
r
rw
0
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
User’s Manual
Memory Organization, V 0.2
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
3-8
V 0.2, 2005-01
XC866
Memory Organization
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
3.3.3
Bit-Addressing
SFRs that have addresses in the form of 1XXXX000B (e.g., 80H, 88H, 90H, ..., F0H, F8H)
are bitaddressable. The addresses of these bitaddressable SFRs appear in bold
typeface in Table 3-1 to Table 3-9.
User’s Manual
Memory Organization, V 0.2
3-9
V 0.2, 2005-01
XC866
Memory Organization
3.3.4
System Control Registers
The system control SFRs are used to control the overall system functionalities, such as
interrupts, variable baud rate generation, clock management, bit protection scheme,
oscillator and PLL control. The SFRs are located in the standard memory area
(RMAP = 0) and organized into 2 pages. The SCU_PAGE register is located at B2H. It
contains the page value and page control information.
SCU_PAGE
Page Register for System Control
7
6
5
Reset Value: 00H
4
3
2
1
OP
STNR
0
PAGE
w
w
r
rw
0
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
User’s Manual
Memory Organization, V 0.2
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
3-10
V 0.2, 2005-01
XC866
Memory Organization
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Memory Organization, V 0.2
3-11
V 0.2, 2005-01
XC866
Memory Organization
3.3.4.1
Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the
bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit
field PASS closes access to writing of all protected bits. Note that access is opened for
maximum 32 CCLKs if the “close access” password is not written. If “open access”
password is written again before the end of 32 CCLK cycles, there will be a recount of
32 CCLK cycles. The protected bits include NDIV, WDTEN, PD, and SD.
PASSWD
Password Register
7
Reset Value: 07H
6
5
4
3
2
1
0
PASS
PROTECT
_S
MODE
wh
rh
rw
Field
Bits
Type Description
MODE
[1:0]
rw
Bit Protection Scheme Control bits
00
Scheme Disabled
11
Scheme Enabled (default)
Others: Scheme Enabled
These two bits cannot be written directly. To change
the value between 11B and 00B, the bit field PASS
must be written with 11000B; only then, will the
MODE[1:0] be registered.
PROTECT_S
2
rh
Bit Protection Signal Status bit
This bit shows the status of the protection.
0
Software is able to write to all protected bits.
1
Software is unable to write to any protected
bits.
PASS
[7:3]
wh
Password bits
The Bit Protection Scheme only recognizes three
patterns.
11000B Enables writing of the bit field MODE.
10011B Opens access to writing of all protected bits.
10101B Closes access to writing of all protected bits.
User’s Manual
Memory Organization, V 0.2
3-12
V 0.2, 2005-01
XC866
Memory Organization
3.3.5
XC866 Register Overview
The SFRs of the XC866 are organized into groups according to their functional units. The
contents (bits) of the SFRs are summarized in Section 3.3.5.1 to Section 3.3.5.9.
Note: The addresses of the bitaddressable SFRs appear in bold typeface in Table 3-1
to Table 3-9.
3.3.5.1
CPU Registers
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 3-1
Addr
CPU Register Overview
Register Name
Bit
7
6
5
4
3
2
1
0
DPL2
rw
DPH2
rw
GF0
rw
DPL1
rw
DPH1
rw
0
r
DPL0
rw
DPH0
rw
IDLE
rw
IT1
rw
0
r
IE0
rwh
IT0
rw
RMAP = 0 or 1
81H
82H
SP
Stack Pointer Register
Reset: 07H
DPL
Reset: 00H
Data Pointer Register Low
Bit Field
Type
Bit Field
Type
Bit Field
83H
DPH
Reset: 00H
Data Pointer Register High
87H
PCON
Power Control Register
Reset: 00H
Type
Bit Field
88H
TCON
Timer Control Register
Reset: 00H
Type
Bit Field
TMOD
Timer Mode Register
Reset: 00H
Type
Bit Field
TL0
Timer 0 Register Low
Reset: 00H
Type
Bit Field
8BH
TL1
Timer 1 Register Low
Reset: 00H
Type
Bit Field
8CH
TH0
Timer 0 Register High
Reset: 00H
Type
Bit Field
8DH
TH1
Timer 1 Register High
Reset: 00H
Type
Bit Field
98H
SCON
Reset: 00H
Serial Channel Control Register
89H
8AH
99H
SBUF
Reset: 00H
Serial Data Buffer Register
A2H
EO
Reset: 00H
Extended Operation Register
A8H
IEN0
Reset: 00H
Interrupt Enable Register 0
B8H
IP
Reset: 00H
Interrupt Priority Register
B9H
IPH
Reset: 00H
Interrupt Priority Register High
D0H
PSW
Reset: 00H
Program Status Word Register
User’s Manual
Memory Organization, V 0.2
Type
Bit Field
Type
Bit Field
DPL7 DPL6
rw
rw
DPH7 DPH6
rw
rw
SMOD
rw
TF1
rwh
GATE1
rw
TR1
rw
0
r
Type
Bit Field
TR0
rw
T1M
rw
IE1
rwh
GATE0
rw
T0M
rw
VAL
rwh
VAL
rwh
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
rw
rw
rw
rw
rw
rwh
rwh
rwh
VAL
rwh
0
ET2
TRAP_
EN
rw
ES
ET1
r
EX1
ET0
DPSEL
0
rw
EX0
0
r
rw
PT2
rw
rw
PS
rw
rw
PT1
rw
rw
PX1
rw
rw
PT0
rw
rw
PX0
rw
0
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
r
rw
F0
rwh
rw
RS1
rw
rw
RS0
rw
rw
OV
rwh
rw
F1
rwh
rw
P
rh
EA
r
0
rw
r
Type
Bit Field
Type
Bit Field
Type
TF0
rwh
VAL
rwh
VAL
rwh
Type
Bit Field
Type
Bit Field
DPL5
rw
DPH5
rw
0
r
SP
rw
DPL4 DPL3
rw
rw
DPH4 DPH3
rw
rw
GF1
rw
CY
rw
3-13
AC
rwh
0
V 0.2, 2005-01
XC866
Memory Organization
Table 3-1
CPU Register Overview (cont’d)
Addr
Register Name
E0H
ACC
Accumulator Register
Bit
E8H
IEN1
Reset: 00H
Interrupt Enable Register 1
F0H
B
B Register
Reset: 00H
Bit Field
Type
F8H
IP1
Reset: 00H
Interrupt Priority Register 1
Bit Field
F9H
IPH1
Reset: 00H
Interrupt Priority Register 1 High
Bit Field
Reset: 00H
Bit Field
Type
Bit Field
Type
Type
Type
3.3.5.2
7
6
5
4
3
ACC7 ACC6 ACC5 ACC4 ACC3
rw
rw
rw
rw
rw
ECCIP ECCIP ECCIP ECCIP EXM
3
2
1
0
rw
rw
rw
rw
rw
B7
B6
B5
B4
B3
rw
rw
rw
rw
rw
PCCIP PCCIP PCCIP PCCIP
3
2
1
0
rw
rw
rw
rw
PXM
rw
PCCIP PCCIP PCCIP PCCIP PXMH
3H
2H
1H
0H
rw
rw
rw
rw
rw
2
1
0
ACC2
rw
EX2
ACC1
rw
ESSC
ACC0
rw
EADC
rw
B2
rw
rw
B1
rw
rw
B0
rw
PX2
PSSC
PADC
rw
rw
rw
PX2H PSSCH PADC
H
rw
rw
rw
System Control Registers
The system control SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-2
Addr
System Control Register Overview
Register Name
Bit
7
6
RMAP = 0 or 1
SYSCON0
Reset: 00H
8FH
System Control Register 0
Bit Field
Type
RMAP = 0
SCU_PAGE
Reset: 00H
BFH
Page Register for System Control
Bit Field
Type
OP
w
Bit Field
0
5
4
3
2
1
0
0
r
RMAP
rw
STNR
w
0
r
PAGE
rw
RMAP = 0, Page 0
B3H
MODPISEL
Reset: 00H
Peripheral Input Select Register
B4H
IRCON0
Reset: 00H
Interrupt Request Register 0
B5H
IRCON1
Reset: 00H
Interrupt Request Register 1
Bit Field
B7H
EXICON0
Reset: 00H
External Interrupt Control Register 0
Bit Field
BAH
EXICON1
Reset: 00H
External Interrupt Control Register 1
BBH
NMICON
NMI Control Register
Reset: 00H
Type
Bit Field
0
BCH
NMISR
NMI Status Register
Reset: 00H
Type
Bit Field
BDH
BCON
Reset: 00H
Baud Rate Control Register
Type
Bit Field
BEH
BG
Reset: 00H
Baud Rate Timer/Reload Register
Type
Bit Field
0
Type
r
JTAG JTAG
0
EXINT URRIS
TDIS TCKS
0IS
r
rw
rw
r
rw
rw
EXINT EXINT EXINT EXINT EXINT EXINT EXINT
6
5
4
3
2
1
0
rwh
rwh
rwh
rwh
rwh
rwh
rwh
0
Type
User’s Manual
Memory Organization, V 0.2
Type
Bit Field
ADCS
RC1
rwh
r
ADCS
RC0
RIR
rwh
rwh
EXINT1
TIR
EIR
rwh
rwh
EXINT0
EXINT3
rw
EXINT2
rw
rw
rw
0
EXINT6
EXINT5
EXINT4
NMI
ECC
rw
NMI
NMI
VDDP VDD
r
0
rw
FNMI
ECC
rw
FNMI
VDDP
rw
FNMI
VDD
rw
NMI
NMI
OCDS FLASH
TIMER
rw
rw
r
rwh
rwh
rwh
r
BGSEL
Type
Bit Field
rw
Type
rw
FNMI FNMI FNMI
OCDS FLASH PLL
TIMER
rwh
T2EXIS BREN
rw
rw
NMI
PLL
rw
BR_VALUE
rwh
BRPRE
rw
rwh
NMI
WDT
rw
FNMI
WDT
rwh
R
rw
rw
3-14
V 0.2, 2005-01
XC866
Memory Organization
Table 3-2
Addr
System Control Register Overview (cont’d)
Register Name
RMAP = 0, Page 1
ID
B3H
Identity Register
Bit
Reset: 01H
7
6
5
Bit Field
PMCON0
Reset: 00H
Power Mode Control Register 0
B5H
PMCON1
Reset: 00H
Power Mode Control Register 1
B6H
OSC_CON
OSC Control Register
Reset: 08H
Type
Bit Field
B7H
PLL_CON
PLL Control Register
Reset: 20H
Type
Bit Field
BAH
CMCON
Clock Control Register
Reset: 00H
Type
Bit Field
BBH
PASSWD
Password Register
Reset: 07H
Type
Bit Field
BCH
FEAL
Reset: 00H
Flash Error Address Register Low
BDH
FEAH
Reset: 00H
Flash Error Address Register High
User’s Manual
Memory Organization, V 0.2
3
2
1
PRODID
r
Type
B4H
4
Bit Field
0
Type
r
WDT
RST
rwh
Bit Field
WKRS
rwh
VERID
r
WK
SEL
rw
0
SD
PD
rw
T2_DIS
rwh
CCU
_DIS
rw
rw
r
0
OSC
PD
rw
r
NDIV
rw
0
r
XPD
rw
VCO
BYP
rw
rw
SSC
_DIS
rw
ADC
_DIS
rw
CLKREL
rw
PROTE
CT_S
rh
wh
ECCERRADDR[7:0]
rh
Type
Bit Field
WS
OSC
ORD OSCR
SS
RES
rw
rwh
rw
OSC RESLD LOCK
DISC
rw
rwh
rh
PASS
Type
Bit Field
0
MODE
rw
ECCERRADDR[15:8]
rh
Type
3-15
V 0.2, 2005-01
XC866
Memory Organization
3.3.5.3
WDT Registers
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 3-3
Addr
WDT Register Overview
Register Name
Bit
RMAP = 1
WDTCON
Reset: 00H
BBH
Watchdog Timer Control Register
7
6
Bit Field
0
Type
Bit Field
r
5
4
WINB
EN
rw
3
WDT
0
PR
r
rh
WDTREL
rw
WDTWINB
BCH
WDTREL
Reset: 00H
Watchdog Timer Reload Register
BDH
WDTWINB
Reset: 00H
Watchdog Window-Boundary Count
Register
BEH
WDTL
Reset: 00H
Watchdog Timer Register Low
Bit Field
Type
rw
WDT[7:0]
rh
BFH
WDTH
Reset: 00H
Watchdog Timer Register High
Bit Field
Type
WDT[15:8]
rh
3.3.5.4
Type
Bit Field
Type
2
1
0
WDT
EN
rw
WDT
RS
rwh
WDT
IN
rw
1
0
Port Registers
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-4
Addr
Port Register Overview
Register Name
Bit
RMAP = 0
PORT_PAGE
Reset: 00H
B2H
Page Register for PORT
RMAP = 0, Page 0
P0_DATA
80H
P0 Data Register
Reset: 00H
Bit Field
4
STNR
w
P5
rw
P4
rw
0
P5
P4
rw
rw
Bit Field
Type
90H
P1_DATA
P1 Data Register
Reset: 00H
Bit Field
Type
91H
P1_DIR
P1 Direction Register
Reset: 00H
Bit Field
Type
A0H
P2_DATA
P2 Data Register
Reset: 00H
Bit Field
Type
B0H
P3_DATA
P3 Data Register
Reset: 00H
Bit Field
Type
B1H
P3_DIR
P3 Direction Register
Reset: 00H
Bit Field
Type
r
3
2
0
r
0
r
Reset: 00H
90H
5
Bit Field
Type
P0_DIR
P0 Direction Register
86H
6
OP
w
Type
86H
RMAP = 0, Page 1
P0_PUDSEL
Reset: FFH
80H
P0 Pull-Up/Pull-Down Select Register
7
PAGE
rw
P3
P2
P1
P0
rw
P3
rw
P2
rw
P1
rw
P0
rw
0
r
0
rw
rw
P1
rw
P1
rw
P0
rw
P0
P7
rw
P7
P6
rw
P6
P5
rw
P5
rw
P7
rw
P6
rw
P5
P4
r
P3
P2
rw
P1
rw
P0
rw
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
rw
rw
rw
rw
rw
rw
rw
P7
rw
P6
rw
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P0
Bit Field
Type
0
P5
P4
P3
P2
P1
r
rw
rw
rw
rw
rw
rw
P0_PUDEN
Reset: C4H Bit Field
P0 Pull-Up/Pull-Down Enable Register Type
P1_PUDSEL
Reset: FFH Bit Field
P1 Pull-Up/Pull-Down Select Register Type
0
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
User’s Manual
Memory Organization, V 0.2
r
P7
rw
3-16
P6
rw
P5
rw
0
r
rw
rw
P1
rw
P0
rw
V 0.2, 2005-01
XC866
Memory Organization
Table 3-4
Port Register Overview (cont’d)
Addr
Register Name
7
6
5
91H
P1_PUDEN
Reset: FFH Bit Field
P1 Pull-Up/Pull-Down Enable Register Type
P2_PUDSEL
Reset: FFH Bit Field
P2 Pull-Up/Pull-Down Select Register Type
P7
rw
P7
rw
P6
rw
P6
rw
P5
rw
P5
rw
P4
rw
P2_PUDEN
Reset: 00H Bit Field
P2 Pull-Up/Pull-Down Enable Register Type
P3_PUDSEL
Reset: BFH Bit Field
P3 Pull-Up/Pull-Down Select Register Type
P7
rw
P6
rw
P5
rw
P4
rw
P7
rw
P7
rw
P6
rw
P6
rw
P5
rw
P5
rw
A0H
A1H
B0H
B1H
Bit
P3_PUDEN
Reset: 40H Bit Field
P3 Pull-Up/Pull-Down Enable Register Type
4
3
1
0
P1
P0
P2
rw
P1
rw
P0
rw
P3
rw
rw
P2
rw
rw
P1
rw
rw
P0
rw
P4
rw
P4
rw
P3
P2
P1
P0
rw
P3
rw
P2
rw
P1
rw
P0
rw
rw
rw
rw
0
r
P3
2
RMAP = 0, Page 2
P0_ALTSEL0
Reset: 00H
80H
P0 Alternate Select 0 Register
Bit Field
Type
0
r
P5
rw
P4
rw
P3
rw
P2
rw
P1
rw
P0
rw
P0_ALTSEL1
Reset: 00H
P0 Alternate Select 1 Register
Bit Field
Type
0
r
P5
rw
P4
rw
P3
P2
P1
P0
rw
90H
P1_ALTSEL0
Reset: 00H
P1 Alternate Select 0 Register
Bit Field
Type
91H
P1_ALTSEL1
Reset: 00H
P1 Alternate Select 1 Register
Bit Field
Type
rw
P0
rw
P0
rw
P3_ALTSEL0
Reset: 00H
P3 Alternate Select 0 Register
Bit Field
Type
B1H
P3_ALTSEL1
Reset: 00H
P3 Alternate Select 1 Register
Bit Field
Type
P5
rw
P5
rw
P5
rw
P5
rw
rw
P1
rw
P1
rw
B0H
P6
rw
P6
rw
P6
rw
P6
rw
P4
rw
P4
rw
rw
0
r
0
r
P3
rw
P3
rw
P2
rw
P2
rw
P1
rw
P1
rw
P0
rw
P0
rw
RMAP = 0, Page 3
P0_OD
Reset: 00H
80H
P0 Open Drain Control Register
Bit Field
Type
P2
rw
90H
P1_OD
Reset: 00H
P1 Open Drain Control Register
Bit Field
Type
B0H
P3_OD
Reset: 00H
P3 Open Drain Control Register
Bit Field
Type
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
1
0
86H
3.3.5.5
P7
rw
P7
rw
P7
rw
P7
rw
0
r
P7
rw
P7
rw
P4
rw
P4
rw
P3
rw
0
r
P3
rw
P2
rw
ADC Registers
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-5
Addr
ADC Register Overview
Register Name
Bit
7
6
5
4
3
2
RMAP = 0
Bit Field
ADC_PAGE
Page Register for ADC
Reset: 00H
RMAP = 0, Page 0
ADC_GLOBCTR
Global Control Register
Reset: 00H
Bit Field
D1H
CAH
OP
w
Type
CBH
ADC_GLOBSTR
Global Status Register
Reset: 00H
Type
Bit Field
CCH
ADC_PRAR
Reset: 00H
Priority and Arbitration Register
Bit Field
Type
CDH
ADC_LCBR
Reset: B7H
Limit Check Boundary Register
Bit Field
Type
Type
User’s Manual
Memory Organization, V 0.2
ANON
rw
STNR
w
DW
rw
CTC
rw
CHNR
0
r
ASEN1 ASEN0
rw
rw
0
r
BOUND1
rw
3-17
0
r
PAGE
rw
0
r
0
SAM
PLE
rh
BUSY
r
rh
rh
ARBM CSM1 PRIO1 CSM0 PRIO0
rw
rw
rw
rw
rw
BOUND0
rw
V 0.2, 2005-01
XC866
Memory Organization
Table 3-5
ADC Register Overview (cont’d)
Addr
Register Name
CEH
ADC_INPCR0
Input Class Register 0
Bit
CFH
ADC_ETRCR
Reset: 00H
External Trigger Control Register
Reset: 00H
7
6
5
Bit Field
Type
Bit Field
Type
4
3
2
STC
rw
ETRSEL1
SYNEN SYNEN
1
0
rw
rw
1
0
ETRSEL0
rw
rw
RMAP = 0, Page 1
CAH
CBH
CCH
CDH
CEH
ADC_CHCTR0
Reset: 00H
Channel Control Register 0
ADC_CHCTR1
Reset: 00H
Channel Control Register 1
ADC_CHCTR2
Reset: 00H
Channel Control Register 2
ADC_CHCTR3
Reset: 00H
Channel Control Register 3
ADC_CHCTR4
Reset: 00H
Channel Control Register 4
CFH
ADC_CHCTR5
Reset: 00H
Channel Control Register 5
D2H
ADC_CHCTR6
Reset: 00H
Channel Control Register 6
D3H
ADC_CHCTR7
Reset: 00H
Channel Control Register 7
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
RMAP = 0, Page 2
ADC_RESR0L
CAH
Result Register 0 Low
Reset: 00H
Bit Field
CBH
ADC_RESR0H
Result Register 0 High
Reset: 00H
Type
Bit Field
CCH
ADC_RESR1L
Result Register 1 Low
Reset: 00H
Type
Bit Field
ADC_RESR1H
Result Register 1 High
Reset: 00H
Type
Bit Field
ADC_RESR2L
Result Register 2 Low
Reset: 00H
Type
Bit Field
ADC_RESR2H
Result Register 2 High
Reset: 00H
Type
Bit Field
ADC_RESR3L
Result Register 3 Low
Reset: 00H
Type
Bit Field
ADC_RESR3H
Result Register 3 High
Reset: 00H
Type
Bit Field
CDH
CEH
CFH
D2H
D3H
RMAP = 0, Page 3
ADC_RESRA0L
Reset: 00H
CAH
Result Register 0, View A Low
CBH
ADC_RESRA0H
Reset: 00H
Result Register 0, View A High
CCH
ADC_RESRA1L
Reset: 00H
Result Register 1, View A Low
CDH
ADC_RESRA1H
Reset: 00H
Result Register 1, View A High
CEH
ADC_RESRA2L
Reset: 00H
Result Register 2, View A Low
User’s Manual
Memory Organization, V 0.2
0
r
LCC
rw
0
RESRSEL
r
0
0
r
LCC
rw
rw
RESRSEL
r
rw
0
r
LCC
rw
0
r
RESRSEL
rw
0
r
LCC
rw
0
r
RESRSEL
rw
0
r
0
r
LCC
rw
LCC
rw
0
r
0
r
RESRSEL
rw
RESRSEL
rw
0
r
0
r
LCC
rw
LCC
rw
0
r
0
r
RESRSEL
rw
RESRSEL
rw
RESULT[1:0]
rh
0
r
RESULT[1:0]
rh
0
r
VF
DRC
rh
rh
RESULT[9:2]
rh
VF
DRC
rh
rh
0
r
RESULT[9:2]
rh
VF
DRC
rh
rh
CHNR
rh
RESULT[9:2]
rh
VF
DRC
rh
rh
CHNR
rh
RESULT[1:0]
rh
RESULT[1:0]
0
rh
r
CHNR
rh
CHNR
rh
RESULT[9:2]
Type
rh
Bit Field
RESULT[2:0]
Type
Bit Field
rh
Type
Bit Field
RESULT[2:0]
Type
Bit Field
rh
Type
Bit Field
RESULT[2:0]
rh
Type
3-18
VF
DRC
rh
rh
RESULT[10:3]
rh
VF
DRC
rh
rh
RESULT[10:3]
rh
VF
rh
DRC
rh
CHNR
rh
CHNR
rh
CHNR
rh
V 0.2, 2005-01
XC866
Memory Organization
Table 3-5
ADC Register Overview (cont’d)
Addr
Register Name
Bit
CFH
ADC_RESRA2H
Reset: 00H
Result Register 2, View A High
Bit Field
D2H
ADC_RESRA3L
Reset: 00H
Result Register 3, View A Low
D3H
ADC_RESRA3H
Reset: 00H
Result Register 3, View A High
RMAP = 0, Page 4
ADC_RCR0
Reset: 00H
CAH
Result Control Register 0
Type
Bit Field
Bit Field
ADC_EVINCR
Reset: 00H
Event Interrupt Clear Flag Register
D2H
ADC_EVINSR
Reset: 00H
Event Interrupt Set Flag Register
D3H
ADC_EVINPR
Reset: 00H
Event Interrupt Node Pointer Register
rw
r
rw
DRCT
R
rw
DRCT
R
rw
DRCT
R
rw
FEN
rw
IEN
r
0
rw
rw
rw
rw
0
r
Type
Bit Field
Type
Bit Field
Bit Field
Bit Field
Type
Bit Field
Type
EVINF EVINF EVINF EVINF
7
6
5
4
rh
rh
rh
rh
Type
Bit Field
w
w
w
w
EVINS EVINS EVINS EVINS
7
6
5
4
w
w
w
w
EVINP EVINP EVINP EVINP
7
6
5
4
rw
rw
rw
rw
Type
RMAP = 0, Page 6
ADC_CRCR1
Reset: 00H Bit Field
CAH
Conversion Request Control Register 1
Type
Bit Field
Type
VFC1
w
CHINF CHINF CHINF CHINF CHINF CHINF CHINF
7
6
5
4
3
2
1
rh
rh
rh
rh
rh
rh
rh
CHINC CHINC CHINC CHINC CHINC CHINC CHINC
7
6
5
4
3
2
1
w
w
w
w
w
w
w
CHINS CHINS CHINS CHINS CHINS CHINS CHINS
7
6
5
4
3
2
1
w
w
w
w
w
w
w
CHINP CHINP CHINP CHINP CHINP CHINP CHINP
7
6
5
4
3
2
1
rw
rw
rw
rw
rw
rw
rw
EVINC EVINC EVINC EVINC
7
6
5
4
Bit Field
r
VFC2
w
VFC3
w
Bit Field
Type
User’s Manual
Memory Organization, V 0.2
rw
rw
rw
VFCTR WFR
Type
ADC_CRPR1
Reset: 00H
Conversion Request Pending
Register 1
DRCT
R
Type
Type
CBH
0
r
0
Type
CFH
rw
IEN
rw
IEN
Bit Field
ADC_EVINFR
Reset: 00H
Event Interrupt Flag Register
rw
FEN
rw
FEN
ADC_VFCR
Reset: 00H
Valid Flag Clear Register
CEH
VFCTR WFR
rw
rw
VFCTR WFR
CEH
ADC_CHINPR
Reset: 00H
Channel Interrupt Node Pointer
Register
rh
Type
Bit Field
Bit Field
0
RESULT[10:3]
rh
0
ADC_RCR3
Reset: 00H
Result Control Register 3
1
CHNR
IEN
CDH
CDH
2
FEN
ADC_RCR2
Reset: 00H
Result Control Register 2
ADC_CHINSR
Reset: 00H
Channel Interrupt Set Register
3
VFCTR WFR
CCH
CCH
4
RESULT[10:3]
rh
VF
DRC
rh
rh
Bit Field
ADC_RCR1
Reset: 00H
Result Control Register 1
ADC_CHINCR
Reset: 00H
Channel Interrupt Clear Register
5
Type
CBH
CBH
6
RESULT[2:0]
rh
Type
Bit Field
Type
RMAP = 0, Page 5
ADC_CHINFR
Reset: 00H
CAH
Channel Interrupt Flag Register
7
CHINF
0
rh
CHINC
0
w
CHINS
0
w
CHINP
0
rw
0
EVINF EVINF
1
0
r
0
rh
rh
EVINC EVINC
1
0
w
w
r
0
EVINS EVINS
1
0
w
w
r
0
EVINP EVINP
1
0
r
rw
CH7
CH6
CH5
CH4
0
rwh
CHP7
rwh
CHP6
rwh
CHP5
rwh
CHP4
0
rwh
rwh
rwh
rwh
r
3-19
rw
VFC0
w
rw
r
V 0.2, 2005-01
XC866
Memory Organization
Table 3-5
ADC Register Overview (cont’d)
Addr
Register Name
Bit
7
6
CCH
ADC_CRMR1
Reset: 00H
Conversion Request Mode Register 1
Bit Field
0
LDEV
CDH
ADC_QMR0
Reset: 00H
Queue Mode Register 0
Bit Field
Type
CEH
ADC_QSR0
Reset: 20H
Queue Status Register 0
Bit Field
Type
CFH
ADC_Q0R0
Queue 0 Register 0
Reset: 00H
Bit Field
Type
CLR SCAN ENSI ENTR
ENGT
PND
rw
rw
rw
r
w
w
rw
CEV TREV FLUSH CLRV TRMD ENTR
ENGT
w
w
w
w
rw
rw
rw
0
EMPTY EV
0
r
rh
rh
r
EXTR ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
r
rh
D2H
ADC_QBUR0
Reset: 00H
Queue Backup Register 0
Bit Field
Type
EXTR
rh
ENSI
rh
RF
rh
D2H
ADC_QINR0
Queue Input Register 0
Bit Field
Type
EXTR
w
ENSI
w
RF
w
Type
3.3.5.6
Reset: 00H
5
4
3
V
rh
2
1
0
r
0
REQCHNR
rh
0
r
REQCHNR
w
Timer 2 Registers
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-6
Timer 2 Register Overview
Addr
Register Name
Bit
7
6
C0H
T2_T2CON
Reset: 00H
Timer 2 Control Register
Bit Field
TF2
EXF2
C1H
T2_T2MOD
Timer 2 Mode Register
Type
Bit Field
rwh
Reset: 00H
C2H
T2_RC2L
Reset: 00H
Timer 2 Reload/Capture Register Low
Bit Field
Type
C3H
T2_RC2H
Reset: 00H Bit Field
Timer 2 Reload/Capture Register High Type
T2_T2L
Reset: 00H Bit Field
Timer 2 Register Low
Type
T2_T2H
Reset: 00H Bit Field
Timer 2 Register High
Type
Type
C4H
C5H
3.3.5.7
rwh
0
r
5
4
0
3
2
1
0
EXEN2
TR2
C/T2
rwh
T2PRE
rw
CP/
RL2
rw
DCEN
r
rw
EDGE PREN
SEL
rw
rw
RC2[7:0]
rwh
RC2[15:8]
rwh
THL2[7:0]
rwh
THL2[15:8]
rw
rw
rwh
CCU6 Registers
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-7
Addr
CCU6 Register Overview
Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A3H
CCU6_PAGE
Reset: 00H
Page Register for CCU6
Bit Field
OP
w
Type
RMAP = 0, Page 0
CCU6_CC63SRL
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC63 Low
Type
0
r
PAGE
rw
CC63SL
9AH
User’s Manual
Memory Organization, V 0.2
STNR
w
rw
3-20
V 0.2, 2005-01
XC866
Memory Organization
Table 3-7
CCU6 Register Overview (cont’d)
Addr
Register Name
9BH
CCU6_CC63SRH
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC63 High
Type
CCU6_TCTR4L
Reset: 00H Bit Field
Timer Control Register 4 Low
Type
9CH
Bit
7
T12
STD
w
T12
STR
w
T13
STD
w
STRM
CM
w
STRHP
w
T13
STR
w
0
CCU6_TCTR4H
Reset: 00H
Timer Control Register 4 High
Bit Field
9EH
CCU6_MCMOUTSL
Reset: 00H
Multi-Channel Mode Output Shadow
Register Low
Bit Field
9FH
CCU6_MCMOUTSH
Reset: 00H
Multi-Channel Mode Output Shadow
Register High
CCU6_ISRL
Reset: 00H
Capture/Compare Interrupt Status
Reset Register Low
Bit Field
Type
A5H
CCU6_ISRH
Reset: 00H
Capture/Compare Interrupt Status
Reset Register High
Bit Field
A6H
CCU6_CMPMODIFL
Reset: 00H
Compare State Modification Register
Low
Bit Field
0
Type
A7H
CCU6_CMPMODIFH
Reset: 00H
Compare State Modification Register
High
Bit Field
r
0
Type
r
FAH
CCU6_CC60SRL
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC60 Low
Type
CCU6_CC60SRH
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC60 High
Type
A4H
FBH
Type
Bit Field
Type
Type
FCH
CCU6_CC61SRL
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC61 Low
Type
FDH
CCU6_CC61SRH
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC61 High
Type
CCU6_CC62SRL
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC62 Low
Type
FEH
FFH
5
4
3
2
1
0
CC63SH
9DH
Type
6
r
0
r
rw
DTRES
0
r
T12
RES
w
0
w
w
T13
RES
w
MCMPS
r
T12RS T12RR
w
T13RS T13RR
w
w
rw
CURHS
rw
EXPHS
rw
RT12P RT12O RCC62 RCC62 RCC61 RCC61 RCC60 RCC60
M
M
F
R
F
R
F
R
w
w
w
w
w
w
w
w
RSTR RIDLE RWHE RCHE
0
RTRPF RT13 RT13
PM
CM
w
w
w
w
r
w
w
w
MCC63
S
w
MCC63
R
w
0
MCC62 MCC61 MCC60
S
S
S
w
w
w
MCC62 MCC61 MCC60
R
R
R
r
0
r
w
w
w
CC60SL
rwh
CC60SH
rwh
CC61SL
rwh
CC61SH
rwh
CC62SL
rwh
CC62SH
CCU6_CC62SRH
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC62 High
Type
rwh
RMAP = 0, Page 1
9AH
9BH
9CH
CCU6_CC63RL
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC63 Low
Type
CCU6_CC63RH
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC63 High
Type
CCU6_T12PRL
Reset: 00H
Timer T12 Period Register Low
User’s Manual
Memory Organization, V 0.2
CC63VL
rh
CC63VH
rh
Bit Field
T12PVL
rwh
Type
3-21
V 0.2, 2005-01
XC866
Memory Organization
Table 3-7
CCU6 Register Overview (cont’d)
Addr
Register Name
Bit
9DH
CCU6_T12PRH
Reset: 00H
Timer T12 Period Register High
Bit Field
9EH
CCU6_T13PRL
Reset: 00H
Timer T13 Period Register Low
9FH
CCU6_T13PRH
Reset: 00H
Timer T13 Period Register High
A4H
CCU6_T12DTCL
Reset: 00H
Dead-Time Control Register for Timer
T12 Low
4
0
DTR2
DTR1
DTR0
Type
Bit Field
r
CTM
rh
CDIR
rh
STE12
rh
T12R
rh
CCU6_TCTR0H
Reset: 00H
Timer Control Register 0 High
FAH
CCU6_CC60RL
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC60 Low
Type
CCU6_CC60RH
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC60 High
Type
Type
Bit Field
0
rh
STE13
rh
T13R
Type
r
rh
rh
rw
CCU6_CC62RL
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC62 Low
Type
FFH
CCU6_CC62RH
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC62 High
Type
Bit Field
9CH
CCU6_IENL
Reset: 00H
Capture/Compare Interrupt Enable
Register Low
Bit Field
9DH
CCU6_IENH
Reset: 00H
Capture/Compare Interrupt Enable
Register High
9EH
CCU6_INPL
Reset: 40H
Capture/Compare Interrupt Node
Pointer Register Low
User’s Manual
Memory Organization, V 0.2
Type
Type
Bit Field
Type
Bit Field
DTE2
DTE1
DTE0
r
rw
rw
rw
T12
PRE
rw
T12CLK
T13
PRE
T13CLK
rw
rw
rw
rh
CC61VL
rh
CC61VH
rh
CC62VL
rh
CC62VH
rh
MSEL61
Type
CCU6_T12MSELH
Reset: 00H
T12 Capture/Compare Mode Select
Register High
0
rh
CC60VH
Bit Field
9BH
0
CC60VL
CCU6_CC61RL
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC61 Low
Type
CCU6_CC61RH
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC61 High
Type
FEH
1
DTM
rw
Bit Field
A7H
2
T13PVH
rwh
Type
CCU6_TCTR0L
Reset: 00H
Timer Control Register 0 Low
RMAP = 0, Page 2
CCU6_T12MSELL
Reset: 00H
9AH
T12 Capture/Compare Mode Select
Register Low
3
T12PVH
rwh
T13PVL
rwh
Type
Bit Field
A6H
FDH
5
Type
Bit Field
CCU6_T12DTCH
Reset: 00H
Dead-Time Control Register for Timer
T12 High
FCH
6
Type
Bit Field
A5H
FBH
7
MSEL60
rw
MSEL62
rw
HSYNC
DBYP
rw
rw
rw
ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC
PM
OM
62F
62R
61F
61R
60F
60R
rw
rw
rw
rw
rw
rw
rw
rw
ENSTR EN
EN
EN
0
EN
ENT13 ENT13
IDLE
WHE
CHE
TRPF
PM
CM
r
rw
rw
rw
rw
rw
rw
rw
INPCHE
INPCC62
INPCC61
INPCC60
Type
rw
3-22
rw
rw
rw
V 0.2, 2005-01
XC866
Memory Organization
Table 3-7
CCU6 Register Overview (cont’d)
Addr
Register Name
Bit
9FH
CCU6_INPH
Reset: 39H
Capture/Compare Interrupt Node
Pointer Register High
Bit Field
A4H
A5H
A6H
7
6
0
5
4
3
INPT13
2
1
INPT12
0
INPERR
Type
CCU6_ISSL
Reset: 00H Bit Field
Capture/Compare Interrupt Status Set
Register Low
Type
rw
rw
r
rw
ST12P ST12O SCC62 SCC62 SCC61 SCC61 SCC60 SCC60
M
M
F
R
F
R
F
R
w
w
w
w
w
w
w
w
CCU6_ISSH
Reset: 00H Bit Field
Capture/Compare Interrupt Status Set
Register High
Type
CCU6_PSLR
Reset: 00H Bit Field
Passive State Level Register
Type
SSTR SIDLE SWHE SCHE SWHC STRPF ST13 ST13
PM
CM
w
w
w
w
w
w
w
w
PSL63
0
PSL
rwh
r
rwh
0
SWSYN
0
SWSEL
r
rw
r
rw
0
T13TED
T13TEC
T13
T12
SSC
SSC
rw
rw
r
rw
rw
0
T13RSEL
T12RSEL
r
rw
rw
Bit Field
A7H
CCU6_MCMCTR
Reset: 00H
Multi-Channel Mode Control Register
FAH
CCU6_TCTR2L
Reset: 00H
Timer Control Register 2 Low
FBH
CCU6_TCTR2H
Reset: 00H
Timer Control Register 2 High
Bit Field
Type
FCH
CCU6_MODCTRL
Reset: 00H
Modulation Control Register Low
Bit Field
FDH
CCU6_MODCTRH
Reset: 00H
Modulation Control Register High
FEH
CCU6_TRPCTRL
Reset: 00H
Trap Control Register Low
Bit Field
Type
FFH
CCU6_TRPCTRH
Reset: 00H
Trap Control Register High
Bit Field
Type
Bit Field
Type
Type
Bit Field
Type
Type
MC
MEN
rw
ECT13
O
rw
0
T12MODEN
r
0
rw
T13MODEN
r
rw
TRPM2 TRPM1 TRPM0
rw
rw
rw
TRPEN
0
r
TRPPE TRPEN
N
13
rw
rw
rw
RMAP = 0, Page 3
Bit Field
0
Type
Bit Field
r
9AH
CCU6_MCMOUTL
Reset: 00H
Multi-Channel Mode Output Register
Low
9BH
CCU6_MCMOUTH
Reset: 00H
Multi-Channel Mode Output Register
High
9CH
CCU6_ISL
Reset: 00H
Capture/Compare Interrupt Status
Register Low
9DH
CCU6_ISH
Reset: 00H
Capture/Compare Interrupt Status
Register High
9EH
CCU6_PISEL0L
Reset: 00H
Port Input Select Register 0 Low
9FH
CCU6_PISEL0H
Reset: 00H
Port Input Select Register 0 High
A4H
CCU6_PISEL2
Reset: 00H
Port Input Select Register 2
Bit Field
Type
FAH
CCU6_T12L
Reset: 00H
Timer T12 Counter Register Low
Bit Field
Type
Bit Field
Type
Bit Field
MCMP
rh
rh
0
CURH
EXPH
rh
r
rh
T12PM T12OM ICC62F ICC62 ICC61F ICC61 ICC60F ICC60
R
R
R
rh
rh
rh
rh
STR
IDLE
WHE
CHE
rh
TRPS
rh
rh
rh
TRPF T13PM T13CM
rh
rh
ISCC61
rh
rh
ISCC62
rh
rh
ISCC60
Type
Bit Field
rh
rh
ISTRP
Type
Bit Field
rw
rw
rw
rw
IST12HR
ISPOS2
ISPOS1
ISPOS0
rw
rw
0
rw
Type
User’s Manual
Memory Organization, V 0.2
R
rw
IST13HR
r
rw
T12CVL
Type
rwh
3-23
V 0.2, 2005-01
XC866
Memory Organization
Table 3-7
CCU6 Register Overview (cont’d)
Addr
Register Name
Bit
FBH
CCU6_T12H
Reset: 00H
Timer T12 Counter Register High
Bit Field
FCH
CCU6_T13L
Reset: 00H
Timer T13 Counter Register Low
FDH
CCU6_T13H
Reset: 00H
Timer T13 Counter Register High
FEH
CCU6_CMPSTATL
Reset: 00H
Compare State Register Low
FFH
CCU6_CMPSTATH
Reset: 00H
Compare State Register High
6
5
Type
Bit Field
Type
Bit Field
Bit Field
Type
4
3
2
1
0
CC62
ST
rh
CC61
ST
rh
CC60
ST
rh
CC61
PS
COUT
60PS
CC60
PS
rwh
rwh
rwh
2
1
0
CIS
SIS
MIS
rw
rw
rw
REN
TEN
T12CVH
rwh
T13CVL
rwh
Type
Bit Field
Type
3.3.5.8
7
T13CVH
rwh
0
CC63 CCPO CCPO CCPO
ST
S2
S1
S0
rh
r
rh
rh
rh
T13IM COUT COUT CC62 COUT
63PS 62PS
PS
61PS
rwh
rwh
rwh
rwh
rwh
SSC Registers
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-8
Addr
SSC Register Overview
Register Name
Bit
RMAP = 0
SSC_PISEL
Reset: 00H
A9H
Port Input Select Register
AAH
SSC_CONL
Control Register Low
Programming Mode
Reset: 00H
ABH
SSC_CONH
Control Register High
Programming Mode
6
Type
Bit Field
Operating Mode
ACH
SSC_TBL
Reset: 00H
Transmitter Buffer Register Low
ADH
SSC_RBL
Reset: 00H
Receiver Buffer Register Low
AEH
SSC_BRL
Reset: 00H
Baudrate Timer Reload Register Low
AFH
SSC_BRH
Reset: 00H
Baudrate Timer Reload Register High
User’s Manual
Memory Organization, V 0.2
Type
Bit Field
Type
Bit Field
Type
Bit Field
4
3
0
r
LB
rw
PO
rw
Bit Field
Reset: 00H
5
Bit Field
Type
Operating Mode
7
PH
rw
HB
rw
BM
rw
0
r
BC
rh
EN
MS
0
rw
EN
rw
rw
MS
rw
r
0
r
Type
Bit Field
AREN
BEN
rw
rw
BSY
BE
rh
rwh
TB_VALUE
rw
PEN
rw
rw
rw
PE
rwh
RE
rwh
TE
rwh
RB_VALUE
Type
Bit Field
BR_VALUE[7:0]
rh
Type
Bit Field
rw
BR_VALUE[15:8]
Type
rw
3-24
V 0.2, 2005-01
XC866
Memory Organization
3.3.5.9
OCDS Registers
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 3-9
Addr
OCDS Register Overview
Register Name
RMAP = 1
MMCR2
Reset: 0UH
E9H
Monitor Mode Control Register 2
Bit
Bit Field
Type
Bit Field
F1H
MMCR
Reset: 00H
Monitor Mode Control Register
F2H
MMSR
Reset: 00H
Monitor Mode Status Register
Bit Field
F3H
MMBPCR
Reset: 00H
BreakPoints Control Register
Bit Field
F4H
Type
MMICR
Reset: 00H Bit Field
Monitor Mode Interrupt Control Register
Type
Type
Type
F5H
MMDR
Reset: 00H
Monitor Mode Data Register
Receive
Transmit
Bit Field
6
Type
HWBPSR
Reset: 00H Bit Field
Hardware Breakpoints Select Register
F7H
HWBPDR
Reset: 00H
Hardware Breakpoints Data Register
5
4
3
2
1
0
EXBC_ EXBC MBCO MBCO MMEP MMEP MMOD JENA
P
N_P
N
_P
E
w
rwh
rh
rh
w
rw
w
rwh
MEXIT MEXIT MSTEP MSTEP MRAM MRAM TRF
RRF
_P
_P
S_P
S
w
rwh
rh
rh
w
hw
w
rw
MBCA MBCIN EXBF SWBF HWB3 HWB2 HWB1 HWB0
M
F
F
F
F
rw
rh
rwh
rwh
rwh
rwh
rwh
rwh
SWBC
HWB3C
HWB2C
HWB1
HWB0C
C
rw
rw
rw
rw
rw
DVECT DRETR
0
MMUIE MMUIE RRIE_ RRIE
_P
P
w
rw
w
rw
rwh
rwh
r
MMRR
Type
Bit Field
F6H
User’s Manual
Memory Organization, V 0.2
7
rh
0
Type
Bit Field
r
Type
3-25
MMTR
w
BPSEL
_P
w
HWBPxx
rw
BPSEL
rw
V 0.2, 2005-01
XC866
Memory Organization
3.4
Boot ROM Operating Mode
After a reset, the CPU will always start by executing the Boot ROM code which occupies
the program memory address space 0000H – 1FFFH. The Boot ROM start-up procedure
will first switch the address space for the Boot ROM to C000H – DFFFH, as shown in
Figure 3-6. As a result, the program memory (Flash or ROM) previously occupying the
address range C000H – DFFFH will be mapped to 0000H – 1FFFH instead. After the
address space switch, the remaining Boot ROM start-up procedure will be executed from
C00XH. This includes checking the latched values of pins MBC, TMS and P0.0 to enter
the selected Boot ROM operating modes. Refer to Chapter 7.2.3 for the selection of
different Boot ROM operating modes. The memory organization of the XC866 shown in
this document is after the address space switch where the different operating modes are
executed.
FFFFH
FFFFH
E000H
Address
2 space E000H
switch
Memory Space
CPU starts
1
execution
Figure 3-6
3.4.1
C000H
C000H
2000H
2000H
Boot ROM
Boot ROM
Memory Space
0000H
0000H
Immediately
after reset
After address
space switch
Boot ROM Address Space Switch
User Mode
If (MBC, TMS, P0.0) = (1, x, x), the Boot ROM will jump to program memory address
0000H to execute the user code in the Flash or ROM memory. This is the normal
operating mode of the XC866.
User’s Manual
Memory Organization, V 0.2
3-26
V 0.2, 2005-01
XC866
Memory Organization
3.4.2
BootStrap Loader Mode
If (MBC, TMS, P0.0) = (0, 0, x), the software routines of the BootStrap Loader (BSL)
located in the Boot ROM will be executed, allowing the XRAM and Flash memory (if
available) to be programmed, erased and executed. Refer to Chapter 4.6 for the
different BSL working modes.
3.4.3
OCDS Mode
If (MBC, TMS, P0.0) = (0, 1, 1), the OCDS mode will be entered for debugging program
code. The OCDS hardware is initialized and a jump to program memory address 0000H
is next performed. The user code in the Flash or ROM memory is executed and the
debugging process may be started.
During the OCDS mode, the lowest 64 bytes (00H – 3FH) in the internal data memory
address range may be alternatively mapped to the 64-byte monitor RAM or the internal
data RAM.
User’s Manual
Memory Organization, V 0.2
3-27
V 0.2, 2005-01
XC866
Flash Memory
4
Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory,
allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V
supply from the Embedded Voltage Regulator (EVR) and does not require additional
programming or erasing voltage. The sectorization of the Flash memory allows each
sector to be erased independently.
Features:
•
•
•
•
•
•
•
In-System Programming (ISP) via UART
In-Application Programming (IAP)
Error Correction Code (ECC) for dynamic correction of single-bit errors
32-byte minimum program width
1-sector minimum erase width
1-byte read access
3 × CCLK period read access time (inclusive of one wait state)
User’s Manual
Flash Memory, V 0.3
4-1
V 0.2, 2005-01
XC866
Flash Memory
4.1
Flash Memory Map
The XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of
embedded Flash memory. These Flash memory sizes are made up of two or four
4-Kbyte Flash banks, respectively. Each Flash device consists of Program Flash
(P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization.
The program memory map for the two different Flash sizes is shown in Figure 4-1.
B000 H
D-Flash Bank
4 Kbytes
D-Flash Bank
4 Kbytes
A000 H
3000 H
P-Flash Bank 2
4 Kbytes
2000 H
P-Flash Bank 1
4 Kbytes
1000 H
P-Flash Bank 0
4 Kbytes
P-Flash Bank 0
4 Kbytes
8 Kbytes
16 Kbytes
0000 H
Figure 4-1
Flash Memory Map
For the 8-Kbyte Flash devices, P-Flash bank 0 is available and occupies the lower part
of the program memory address, starting from 0000H where the reset and interrupt
vectors are located. For the 16-Kbyte Flash devices, two additional P-Flash banks (1 and
2) are provided for storing user code:
• P-Flash bank 1 occupies the address range 1000H – 1FFFH
• P-Flash bank 2 occupies 2000H – 2FFFH
All devices in the XC866 product family (including ROM devices) offer a 4-Kbyte D-Flash
bank, occupying the address region A000H – AFFFH.
User’s Manual
Flash Memory, V 0.3
4-2
V 0.2, 2005-01
XC866
Flash Memory
4.2
Flash Bank Sectorization
The XC866 Flash devices consist of two types of 4-Kbyte banks, namely Program Flash
(P-Flash) bank and Data Flash (D-Flash) bank, with different sectorization as shown in
Figure 4-2. Both types can be used for code and data storage. The label “Data” neither
implies that the D-Flash is mapped to the data memory region, nor that it can only be
used for data storage. It is used to distinguish the different Flash bank sectorizations.
128-byte Sector 2
128-byte Sector 1
128-byte Sector 9
128-byte Sector 8
128-byte Sector 7
128-byte Sector 6
256-byte Sector 5
256-byte Sector 4
512-byte Sector 3
3.75-Kbyte Sector 0
512-byte Sector 2
1-Kbyte Sector 1
1-Kbyte Sector 0
P-Flash
Figure 4-2
D-Flash
Flash Bank Sectorization
Sector Partitioning in P-Flash:
• One 3.75-Kbyte sector
• Two 128-byte sectors
Sector Partitioning in D-Flash:
•
•
•
•
Two 1-Kbyte sectors
Two 512-byte sectors
Two 256-byte sectors
Four 128-byte sectors
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
be erased separately or in parallel. Contrary to standard EPROMs, erased Flash
memory cells contain 0s.
User’s Manual
Flash Memory, V 0.3
4-3
V 0.2, 2005-01
XC866
Flash Memory
The D-Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
For example, the user’s program can implement a buffer mechanism for each sector.
Double copies of each data set can be stored in separate sectors of similar size to ensure
that a backup copy of the data set is available in the event that the actual data set is
corrupted or erased.
Alternatively, the user can implement an algorithm for EEPROM emulation, which uses
the D-Flash bank like a circular stack memory; the latest data updates are always
programmed on top of the actual region. When the top of the sector is reached, all actual
data (representing the EEPROM data) is copied to the bottom area of the next sector
and the last sector is then erased. This round robin procedure, using multifold
replications of the emulated EEPROM size, significantly increases the endurance. To
speed up data search, the RAM can be used to contain the pointer to the valid data set.
User’s Manual
Flash Memory, V 0.3
4-4
V 0.2, 2005-01
XC866
Flash Memory
4.3
Wordline Address
The wordline (WL) addresses of the P-Flash and D-Flash banks are given in Figure 4-3.
1022H
1021H
1020H
101FH
……………………………..
1002H
1001H
1000H
0FFFH
……………………………..
0FE2H 0FE1H 0FE0H
……
……
……
……
0F61H
0F60H
0F1FH
……………………………..
0F02H
0EFFH
……………………………..
0EE2H 0EE1H 0EE0H
0F01H
0F00H
A83FH
……………………………..
A822H
A821H A820H
A81FH
……………………………..
A802H
A801H A800H
A7FFH
……………………………..
A7E2H A7E1H A7E0 H
A45FH
……………………………..
A442H
A441H A440H
A43FH
……………………………..
A422H
A421H A420H
A41FH
……………………………..
A402H
A401H A400H
A3FFH
……………………………..
A3E2H A3E1H A3E0 H
…...
…...
…...
D-Flash
007FH
……………………………..
0062H
0061H
0060H
005FH
……………………………..
0042H
0041H
0040H
A05FH
……………………………..
A042H
A041H A040H
003FH
……………………………..
0022H
0021H
0020H
A03FH
……………………………..
A022H
A021H A020H
001FH
……………………………..
0002H
0001H
0000H
A01FH
……………………………..
A002H
A001H A000H
WL
Address
Figure 4-3
Sector 9
W L 124 - 127
12 8-byte
Sector 8
W L 120 - 123
12 8-byte
Sector 7
W L 116 - 119
12 8-byte
Sector 6
W L 112 - 115
128 -byte
Secto r 5
W L 104 - 111
256 -byte
Secto r 4
WL 96 - 103
256 -byte
Sector 0
W L 0 - 119
3.75-K Byte
…...
……….
……….
……….
……….
A9E2H A9E1H A9E0 H
…...
0F62H
……………………………..
…...
……………………………..
AA02H AA01H AA00 H
A9FFH
…...
0F7FH
AA22H AA21H AA20 H
……………………………..
…...
0F80H
……
0F81H
……
0F82H
……
……………………………..
……
0F9FH
……………………………..
AA1FH
Secto r 3
W L 80 - 9 5
512- byte
……………………………..
AA3FH
…...
103FH
…...
1040H
…...
1060H
1041H
…...
1061H
1042H
AC02H AC01H AC00H
…...
1062H
……………………………..
…………………………….. ABE2 H ABE1H ABE0H
…...
……………………………..
105FH
……………………………..
ABFFH
…...
107FH
AD02H AD01H AD00H
AC1FH
…...
……….
……….
……….
……….
P-Flash 1
1F00H
…………………………….. ACE2H ACE1H ACE0H
……..
1EE2H 1EE1H 1EE0H
……………………………..
ACFFH
……..
1F02H
……………………………..
AD1FH
……..
……………………………..
AE02H AE01H AE00 H
…………………………….. ADE2H ADE1H ADE0H
……..
……
……
……
……
P-Flash 0
……
……
……
……
1F1FH
1EFFH
Secto r 2
W L 124 - 127
128 -byte
1F60H
Secto r 1
W L 120 - 123
128 -byte
1F80H
1F61H
Sector 0
W L 0 - 11 9
3.75-KB yte
1F81H
1F62H
S ector 2
W L 1 24 - 1 27
128-b yte
1F82H
……………………………..
S ector 1
W L 1 20 - 12 3
128-b yte
P-Flash 2
……………………………..
1F7FH
……………………………..
ADFFH
……..
1F9FH
AE1FH
……
1FE2H 1FE1H 1FE0H
……
……………………………..
……
1FFFH
……
2000H
AE62H AE61H AE60 H
……..
2020H
2001H
AE82H AE81H AE80 H
……………………………..
……
2021H
2002H
……
2022H
……………………………..
……
……………………………..
201FH
……
203FH
……………………………..
AE7FH
……..
2040H
AE9FH
……
2041H
……
2042H
……
……………………………..
AF02H AF01H AF00H
…………………………….. AEE2 H AEE1H AEE0H
……
205FH
……………………………..
AEFFH
……..
2060H
AF1FH
……
2061H
AF62H AF61H AF60H
……
2062H
1F01H
2F00H
……….
……………………………..
……….
207FH
……….
2EE2H 2EE1H 2EE0H
……….
2F02H
……………………………..
AF82H AF81H AF80H
……………………………..
……
2F01H
……
……
……
……
……………………………..
……………………………..
AF7FH
……
……
2F1FH
2EFFH
AF9FH
Sector 2
W L 64 - 7 9
512-b yte
2F60H
AFE2H AFE1H AFE0H
S ector 1
W L 32 - 63
1- KByte
2F80H
2F61H
……………………………..
S ector 0
W L 0 - 31
1-K Byte
2F81H
2F62H
Sector 2
W L 124 - 127
12 8-byte
2F82H
……………………………..
Byte 2 Byte 1 Byte 0
AFFFH
Sector 1
W L 120 - 123
12 8-byte
……………………………..
2F7FH
……
2F9FH
……
Byte 31
2FE2H 2FE1H 2FE0H
……
Byte 2 Byte 1 Byte 0
……………………………..
2FFFH
S ector 0
W L 0 - 119
3.7 5-KByte
Byte 31
WL
Address
Flash Wordline Addresses
User’s Manual
Flash Memory, V 0.3
4-5
V 0.2, 2005-01
XC866
Flash Memory
A WL address can be calculated as follow:
0000H + 20H × n, with 0 < n < 127 for P-Flash 0
[4.1]
1000H + 20H × n, with 0 < n < 127 for P-Flash 1
[4.2]
2000H + 20H × n, with 0 < n < 127 for P-Flash 2
[4.3]
A000H + 20H × n, with 0 < n < 127 for D-Flash
[4.4]
Only one out of all the wordlines in the Flash banks can be programmed at a time. The
width of each WL is 32 bytes (minimum/maximum program width). Before programming
can be done, the user must first write 32 bytes of data into the IRAM using MOV
instructions. Then, the BootStrap Loader (BSL) routine (see Section 4.6) or D-Flash
program subroutine (see Section 4.7.1) will transfer these IRAM data to the
corresponding write buffer of the targeted Flash bank. After 32 bytes of data are
assembled in the write buffers, the programming sequence will start the charge pumps,
storing the data content into the Flash cells along the selected WL. The WL is selected
via the WL addresses shown in Figure 4-3. It is necessary to fill the IRAM with 32 bytes
of data, otherwise the previous values stored in the write buffers will remain and be
programmed into the WL.
For the P-Flash banks, a programmed WL must be erased before it can be
reprogrammed again as the Flash cells can only withstand one gate disturb. This means
that the entire sector containing the WL must be erased since it is impossible to erase a
single WL.
For the D-Flash bank, the same WL can be programmed twice before erasing is required
as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to
program the same WL, for example, with 16 bytes of data in two times (see Figure 4-4).
32 bytes (1 WL)
0000 ….. 0000 H
0000 ….. 0000 H
Program 1
0000 ….. 0000 H
1111 ….. 1111 H
Program 2
1111 ….. 0000 H
1111 ….. 1111 H
16 bytes
0000 ….. 0000 H
1111 ….. 1111 H
1111 ….. 0000 H
0000 ….. 0000 H
Note: A Flash memory cell can be programmed
from 0 to 1, but not from 1 to 0.
Flash memory cells
Figure 4-4
16 bytes
32-byte write buffers
D-Flash Program
User’s Manual
Flash Memory, V 0.3
4-6
V 0.2, 2005-01
XC866
Flash Memory
4.4
Operating Modes
The Flash operating modes for each bank are shown in Figure 4-5.
Sector(s) Erase
Ready-to-Read
Call of
DFLASH_ERASE routine
or by BSL
Program
Call of
DFLASH_PROG routine
or by BSL
Power-Down
System Power-Down
Figure 4-5
Flash Operating Modes
In general, the Flash operating modes are controlled by the BSL and D-Flash program/
erase subroutines (see Section 4.7).
Each Flash bank must be in ready-to-read mode before the program mode or sector(s)
erase mode can be entered. In the ready-to-read mode, the 32-byte write buffers for
each Flash bank can be written, and the memory cell contents can be read via CPU
access. In the program mode, data in the 32-byte write buffers is programmed into the
Flash memory cells of the targeted wordline.
The operating modes for each Flash bank are enforced by its state machine to ensure
the correct sequence of Flash mode transition. This avoids inadvertent destruction of the
Flash contents with a reasonably low software overhead. The state machine also
ensures that a Flash bank is blocked (no read access possible) while it is being
programmed or erased. However, it is possible to program/erase one Flash bank while
reading from another.
When the user sets bit PMCON0.PD = 1 to enter the system power-down mode, the
Flash banks will automatically be brought to its power-down state by hardware. Upon
wake-up from system power-down, the Flash banks are brought to ready-to-read mode
to allow access by the CPU.
User’s Manual
Flash Memory, V 0.3
4-7
V 0.2, 2005-01
XC866
Flash Memory
4.5
Error Detection and Correction
The 8-bit data from the CPU is encoded with an Error Correction Code (ECC) before
being stored in the Flash memory. During a read access, data is retrieved from the Flash
memory and decoded for dynamic error detection and correction.
The correction algorithm (hamming code) has the capability to:
• Detect and correct all 1-bit errors
• Detect all 2-bit errors, but cannot correct
A corrected 1-bit error (result is valid) and an uncorrected 2-bit error (result is invalid) are
not distinguished, with an ECC non-maskable interrupt (NMI) generated for both cases.
The 16-bit Flash address at which the ECC error occurs is stored in the system control
SFRs FEAL and FEAH, and can be accessed by the interrupt service routine to
determine the Flash bank/sector in which the error occurred.
FEAL
Flash Error Address Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
ECCERRADDR[7:0]
rh
FEAH
Flash Error Address Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
ECCERRADDR[15:8]
rh
Field
Bits
ECCERRADDR
[7:0] of rh
FEAL,
[7:0] of
FEAH
User’s Manual
Flash Memory, V 0.3
Type Description
ECC Error Address Value
4-8
V 0.2, 2005-01
XC866
Flash Memory
4.6
In-System Programming
In-System Programming (ISP) of the Flash memory is supported via the Boot ROMbased BootStrap Loader (BSL), allowing a blank microcontroller device mounted onto an
application board to be programmed with the user-code, and also a previously
programmed device to be erased then reprogrammed without removal from the board.
This feature offers ease-of-use and versatility for the embedded design.
ISP is supported through the microcontroller’s serial interface (UART) which is
connected to the personal computer host via the commonly available RS-232 serial
cable. The BSL mode is selected if the latched values of the MBC and TMS pins are 0
after power-on or hardware reset. The BSL routine will first perform an automatic
synchronization with the transfer speed (baud rate) of the serial communication partner
(personal computer host). Communication between the BSL routine and the host is done
via a simple transfer protocol; information is sent from the host to the microcontroller in
blocks with specified block structure, and the BSL routine acknowledges the received
data by returning a single acknowledge or error byte. User can program, erase or
execute the P-Flash and/or D-Flash bank(s).
The available working modes are:
•
•
•
•
Transfer user program from host to XRAM and/or Flash
Execute user program in XRAM
Execute user program in Flash
Erase Flash sector(s) from the same or different bank(s)
User’s Manual
Flash Memory, V 0.3
4-9
V 0.2, 2005-01
XC866
Flash Memory
4.7
In-Application Programming
In most applications, data in the D-Flash needs to be modified during program execution.
In-Application Programming (IAP) is supported so that users can program or erase the
D-Flash data from their Flash user program by calling some special subroutines that
utilize the Flash Timer NMI. Hence, it is necessary to incorporate a Flash Timer NMI
service routine code as part of the Flash user program. The Flash Timer NMI service
routine is required as part of the D-Flash program and erase sequences.
Boot ROM
special D-Flash
program/erase
subroutines
user program
user NMI routine
Flash Timer NMI
service routine
Flash Timer
NMI
0073H
RETI instruction
Figure 4-6
D-Flash Program/Erase Flow
User’s Manual
Flash Memory, V 0.3
4-10
V 0.2, 2005-01
XC866
Flash Memory
4.7.1
D-Flash Programming
The Flash program subroutine can be called by the user to program 32 bytes of data into
a single D-Flash wordline (WL). At the beginning of this subroutine, the Flash Timer NMI
is enabled to enter the Flash Timer NMI service routine at each of the several timer
underflows throughout the programming sequence.
Before calling this subroutine, the user must ensure that the 32-byte WL contents are
stored incrementally in the IRAM, starting from the address specified in R0 of Register
Bank 3. In addition, the input DPTR0 (EO.DPSEL0 = 0) must contain the D-Flash WL
address. Otherwise, bit PSW.CY will be set and no programming will occur. If valid inputs
are available before calling the subroutine, the microcontroller will continue to initialize
the programming sequence (includes transferring the 32-byte IRAM data to the D-Flash
write buffers), exit the subroutine and then return to the user program code.
User program code will continue execution, from where it last stopped, until the next
Flash Timer NMI is triggered and the Flash Timer NMI service routine entered (see
Figure 4-6). The Flash Timer NMI service routine will first check the Flash Timer NMI
status bit (NMISR.FNMIFLASHTIMER = 1) to ensure that the NMI source is from the
Flash Timer before executing the remaining service routine instructions.
Table 4-1
D-Flash Program Subroutine
Subroutine
DFF6H: DFLASH_PROG
Input
DPTR0: D-Flash WL address
R0 of Register Bank 3 (IRAM address 18H):
IRAM start address for 32-byte D-Flash data
32-byte D-Flash data
Output
PSW.CY:
0 = D-Flash programming is in progress
1 = DPTR0 is not pointing to valid D-Flash WL address
DPTR0 is incremented by 20H
Flash Timer NMI is enabled (NMICON.NMIFLASHTIMER = 1)
Stack size
required
8
Resources
used/destroyed
PSW.CY, A, SCU_PAGE, DPTR1
Resources
reserved1)
R0 – R7 of Register Bank 3 (IRAM address 18H – 1FH)
Machine cycles
taken 2)
904
User’s Manual
Flash Memory, V 0.3
IRAM address 36H – 3DH
4-11
V 0.2, 2005-01
XC866
Flash Memory
1)
The data in the reserved resources must not be altered throughout the programming period (including Flash
Timer NMI servicing) to ensure correct programming flow.
2)
Estimated value without wait state.
Upon completing the D-Flash programming sequence, the Flash Timer NMI will be
disabled (NMICON.NMIFLASHTIMER = 0) by the program subroutine.
For ‘end of D-Flash programming’ indication, the user can check one of the following:
• Bit NMICON.NMIFLASHTIMER is cleared
• R3 of Register Bank 3 (IRAM address 1BH) is 03H
A manual check on the D-Flash data is necessary to determine the success of the
programming via using the MOVC instruction to read out the D-Flash data.
User’s Manual
Flash Memory, V 0.3
4-12
V 0.2, 2005-01
XC866
Flash Memory
4.7.2
D-Flash Erasing
The Flash erase subroutine can be called by the user to erase the sector(s) of the
D-Flash bank. For each erasing sequence, it is possible to select one sector, a
combination of several sectors or all 10 sectors to be erased. At the beginning of this
subroutine, the Flash Timer NMI is enabled to enter the Flash Timer NMI service routine
at each of the several timer underflows throughout the erasing sequence.
Before calling this subroutine, the user must ensure that R3 and R4 of Register Bank 3
are set accordingly. The microcontroller will first initialize the erasing sequence, exit the
subroutine, then return to the user program code. User program code will continue
execution, from where it last stopped, until the next Flash Timer NMI is triggered and the
Flash Timer NMI service routine is entered (see Figure 4-6). The Flash Timer NMI
service routine will first perform a check on the Flash Timer NMI status bit
(NMISR.FNMIFLASHTIMER = 1) to ensure that the NMI source is from the Flash Timer
before executing the remaining service routine instructions.
Table 4-2
D-Flash Erase Subroutine
Subroutine
DFF9H: DFLASH_ERASE
Input
R3 of Register Bank 3 (IRAM address 1BH):
Select sector(s) to be erased for D-Flash bank.
LSB represents sector 0, MSB represents sector 7.
R4 of Register Bank 3 (IRAM address 1CH):
Select sector(s) to be erased for D-Flash bank.
LSB represents sector 8, bit 1 represents sector 9.
Output
Flash Timer NMI is enabled (NMICON.NMIFLASHTIMER = 1)
Stack size
required
8
Resources
used/destroyed
PSW.CY, A, SCU_PAGE, DPTR1
Resources
reserved1)
R0 – R7 of Register Bank 3 (IRAM address 18H – 1FH)
Machine cycles
taken 2)
358
IRAM address 36H – 3DH
1)
The data in the reserved resources must not be altered throughout the erasing period (including Flash Timer
NMI servicing) to ensure correct erasing flow.
2) Estimated value without wait state.
User’s Manual
Flash Memory, V 0.3
4-13
V 0.2, 2005-01
XC866
Flash Memory
Upon completing the D-Flash erasing sequence, the Flash Timer NMI will be disabled
(NMICON.NMIFLASHTIMER = 0) by the erase subroutine.
For ‘end of D-Flash erasing’ indication, the user can check for one of the following:
• Bit NMICON.NMIFLASHTIMER is cleared
• R3 of Register Bank 3 (IRAM address 1BH) is 03H
A manual check on the D-Flash data is necessary to determine the success of the
erasing via a MOVC instruction.
User’s Manual
Flash Memory, V 0.3
4-14
V 0.2, 2005-01
XC866
Interrupt System
5
Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC866 interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and determining the interrupt
source.
5.1
Non-maskable Interrupt
The Non-Maskable Interrupt (NMI) is similar to regular interrupts, except it has the
highest priority (over other regular interrupts) when addressing important system events.
In the XC866, any one of the following seven events can generate an NMI:
•
•
•
•
•
•
WDT prewarning has occurred
The PLL has lost the lock to the external crystal
Flash Timer has overflowed
JTAG-receiving or user interrupt is requested in monitor mode
VDD is below the prewarning voltage level (2.3 V)
VDDP is below the prewarning voltage level (4.0 V if the external power supply is
5.0 V)
• Flash ECC error has occurred
The NMISR register is used to hold the NMI request flags for these events.
Corresponding bits in the NMICON register determine whether the NMI requests will be
accepted or ignored. When any enabled NMI request is serviced, the software routine
may clear the NMI request flags in the NMISR register.
5.2
Maskable Interrupts
All regular interrupts are called maskable interrupts. A maskable interrupt can be
masked or temporarily ignored by the processor while it completes its task. These
interrupts can be classified into three types: internal interrupts, external interrupts, and
extended interrupts.
5.2.1
Internal Interrupts
There are three internal interrupts that proceed from Timer 0, Timer 1, and UART. These
interrupt request signals go directly to the XC800 Core and their interrupt status is
maintained by the core.
Two interrupt flags TF0 and TF1 in the TCON register are set whenever Timer 0 or
Timer 1, respectively, overflows. TF0 and TF1 are automatically cleared by hardware on
entry to the corresponding interrupt service routine.
User’s Manual
Interrupt System, V 0.5
5-1
V 0.2, 2005-01
XC866
Interrupt System
The UART interrupt source comprises the logical OR of the two serial interface
interrupts. The interrupt flags RI and TI in register SCON are set automatically upon
receipt or transmission of a data frame. These two bits must be cleared by software.
5.2.2
External Interrupts
Seven external interrupts, EXT_INT[6:0], are driven into the XC866 from the ports.
External interrupts can be positive, negative or double edge triggered. Registers
EXICON0 and EXICON1 specify the active edge for the triggering of the external
interrupt.
Among the external interrupts, external interrupt 0 and external interrupt 1 can also be
selected without edge detection. The interrupt request signal (caused with/without the
edge triggered) to the core can further be programmed to either level activated or
negative transition activated by setting or clearing bit ITx (x = 0 or 1), respectively, in the
TCON register.
If the external interrupt is positive (negative) edge triggered, the external source must
hold the request pin low (high) for at least one CCLK cycle, and then hold it high (low)
for at least one CCLK cycle to ensure that the transition is recognized. If edge detection
is bypassed for external interrupt 0 and external interrupt 1, the external source must
hold the request pin “high” or “low” for at least two CCLK cycles.
5.2.3
Extended Interrupts
The extended interrupts are mainly for on-chip peripherals, which send interrupt
requests to the core. There are nine interrupt request signals, XINTR_SRC[13:5], that
are driven to the core, and each in turn receives an acknowledge signal
XINTR_ACK[13:5] from the core.
Some interrupt sources have their own request flag(s) located in a special function
register (e.g., TCON, T2CON, SCON). Registers IRCON0 and IRCON1 are used to hold
other interrupt request flags for extended and external interrupts.
As the peripherals/devices have more interrupts lines than the core supports, some
interrupts can be multiplexed and use the same interrupt input to the core. A few critical
peripheral (e.g., timers, CCU6) interrupts are connected directly to the interrupt inputs of
the core.
Each interrupt input requested by the corresponding flag can be individually enabled or
disabled by the enable/disabled bit in the SFR IEN0 or IEN1. In addition, there is a global
enable bit EA (contained in Register IEN0) for all interrupts, which when cleared,
disables all interrupts independent of their individual enable bits.
Figure 5-1 to Figure 5-5 give a general overview of the interrupt sources and illustrate
the request and control flags.
User’s Manual
Interrupt System, V 0.5
5-2
V 0.2, 2005-01
XC866
Interrupt System
WDT Overflow
FNMIWDT
NMIISR.0
NMIWDT
NMICON.0
PLL Loss of Lock
FNMIPLL
NMIISR.1
NMIPLL
NMICON.1
FNMIFLASH
TIMER
Flash Timer Overflow
NMIISR.2
Int 0
Int 1
Int 2
Int 3
Int 4
Int 5
Int 6
Int 7
Int 8
Int 9
Int 10
Int 11
Int 12
Int 13
VDD Pre-Warning
NMIFLASHTIMER
NMICON.2
>=1
OCDS
interrupt
>=1
FNMIOCDS
NMISR.3
NMIOCDS
NMICON.3
0073
H
Non
Maskable
Interrupt
FNMIVDD
NMIISR.4
NMIVDD
NMICON.4
VDDP Pre-Warning
FNMIVDDP
NMIISR.5
NMIVDDP
NMICON.5
Flash ECC Error
FNMIECC
NMIISR.6
NMIECC
NMICON.6
Figure 5-1
Non-Maskable Interrupt Request Source
User’s Manual
Interrupt System, V 0.5
5-3
V 0.2, 2005-01
XC866
Interrupt System
Highest
Timer 0
Overflow
TF0
TCON.5
ET0
000B
H
IEN0.1
Timer 1
Overflow
Lowest
Priority Level
IP.1/
IPH.1
TF1
TCON.7
ET1
001B
H
IEN0.3
IP.3/
IPH.3
RI
SCON.0
UART
EINT0
>=1
TI
ES
SCON.1
IEN0.4
TCON.1
IRCON0.0
IT0
EXINT0
0023
H
IP.4/
IPH.4
IE0
EXINT0
P
o
l
l
i
n
g
EX0
0003
H
IEN0.0
TCON.0
S
e
q
u
e
n
c
e
IP.0/
IPH.0
EXICON0.0/1
EINT1
EXINT1
IE1
IRCON0.1
TCON.3
IT1
EXINT1
TCON.2
EX1
0013
H
IEN0.2
IP.2/
IPH.2
EXICON0.2/3
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 5-2
Interrupt Request Sources (Part 1)
User’s Manual
Interrupt System, V 0.5
5-4
V 0.2, 2005-01
XC866
Interrupt System
Highest
Timer 2
Overflow
TF2
T2CON.7
T2EX
EXEN2
EDGES
EL
T2MOD.5
Lowest
Priority Level
>=1
EXF2
ET2
T2CON.6
IEN0.5
002B
H
IP.5/
IPH.5
T2CON.3
EINT2
EXINT2
IRCON0.2
EX2
0043
H
IEN1.2
EXINT2
IP1.2/
IPH1.2
EXICON0.4/5
EXINT3
EINT3
S
e
q
u
e
n
c
e
IRCON0.3
EXINT3
EXICON0.6/7
EXINT4
EINT4
P
o
l
l
i
n
g
IRCON0.4
EXM
EXINT3
>=1
EXICON1.0/1
004B
H
IEN1.3
IP1.3/
IPH1.3
EXINT5
EINT5
IRCON0.5
EXINT5
EXICON1.2/3
EA
IEN0.7
EXINT6
EINT6
IRCON0.6
EXINT6
EXICON1.4/5
Bit-addressable
Request flag is cleared by hardware
Figure 5-3
Interrupt Request Sources (Part 2)
User’s Manual
Interrupt System, V 0.5
5-5
V 0.2, 2005-01
XC866
Interrupt System
Highest
ADC_SRC0
ADCSRC0
IRCON1.3
ADC_SRC1
EADC
ADCSRC1
0033
H
IEN1.0
IRCON1.4
SSC_EIR
Lowest
Priority Level
>=1
IP1.0/
IPH1.0
EIR
IRCON1.0
SSC_TIR
TIR
>=1
ESSC
IRCON1.1
SSC_RIR
003B
H
IEN1.1
RIR
IP1.1/
IPH1.1
IRCON1.2
Capture/Compare
interrupt node 0
ECCIP0
0053
H
IEN1.4
IP1.4/
IPH1.4
Capture/Compare
interrupt node 1
ECCIP1
005B
H
IEN1.5
IP1.5/
IPH1.5
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
Capture/Compare
interrupt node 2
ECCIP2
0063
H
IEN1.6
IP1.6/
IPH1.6
Capture/Compare
interrupt node 3
ECCIP3
006B
H
IEN1.7
IP1.7/
IPH1.7
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 5-4
Interrupt Request Sources (Part 3)
User’s Manual
Interrupt System, V 0.5
5-6
V 0.2, 2005-01
XC866
Interrupt System
ICC60R
CC60
ISL.0
ICC60F
ISL.1
ICC61R
CC61
ISL.2
ICC61F
ISL.3
ICC62R
CC62
ISL.4
ICC62F
ISL.5
T12
One match
T12OM
T12
Period match
T12PM
T13
Compare match
T13
Period match
CTRAP
ISL.6
ISL.7
T13CM
ISH.0
T13PM
ISH.1
TRPF
ISH.2
Wrong Hall
Event
Correct Hall
Event
WHE
ISH.5
CHE
ISH.4
Multi-Channel
Shadow
Transfer
STR
ISH.7
ENCC60R
IENL.0
>=1
ENCC60F
IENL.1
ENCC61R
IENL.2
ENSTR
IENH.7
INPL.4
INPH.3
INPH.2
INPH.5
INPH.4
INPH.1
INPH.0
INPL.7
INPL.6
>=1
ENWHE
IENH.5
ENCHE
IENH.4
INPL.5
>=1
ENT13PM
IENH.1
ENTRPF
IENH.2
INPL.2
>=1
ENT12PM
IENL.7
ENT13CM
IENH.0
INPL.3
>=1
ENCC62F
IENL.5
ENT12OM
IENL.6
INPL.0
>=1
ENCC61F
IENL.3
ENCC62R
IENL.4
INPL.1
>=1
CCU6 Interrupt node 0
CCU6 Interrupt node 1
CCU6 Interrupt node 2
CCU6 Interrupt node 3
Figure 5-5
Interrupt Request Sources (Part 4)
User’s Manual
Interrupt System, V 0.5
5-7
V 0.2, 2005-01
XC866
Interrupt System
5.3
Interrupt Source and Vector
Each interrupt input has an associated interrupt vector address. This vector is accessed
in order to service the corresponding interrupt source. The assignment of the XC866
interrupt sources is summarized in Table 5-1.
Table 5-1
Interrupt
Input
Interrupt Vector Addresses
Vector Address
Interrupt Sources
NMI
0073H
Watchdog Timer, PLL, Flash Interface Timer, OCDS,
VDD and VDDP prewarning, Flash ECC
XINTR0
0003H
External Interrupt 0
XINTR1
000BH
Timer 0
XINTR2
0013H
External Interrupt 1
XINTR3
001BH
Timer 1
XINTR4
0023H
UART
XINTR5
002BH
Timer 2
XINTR6
0033H
ADC_SRC[1:0]
XINTR7
003BH
SSC
XINTR8
0043H
External Interrupt 2
XINTR9
004BH
External Interrupt [6:3]
XINTR10
0053H
CCU6 INP0
XINTR11
005BH
CCU6 INP1
XINTR12
0063H
CCU6 INP2
XINTR13
006BH
CCU6 INP3
User’s Manual
Interrupt System, V 0.5
5-8
V 0.2, 2005-01
XC866
Interrupt System
5.4
Interrupt Register Description
5.4.1
Interrupt Enable Registers
Each interrupt input can be individually enabled or disabled by setting or clearing the
corresponding bit in the interrupt enable registers IEN0 or IEN1. Register IEN0 also
contains the global enable/disable bit (EA), which can be cleared to disable all interrupts.
The NMI interrupt is shared by a number of sources, each of which can be enabled or
disabled individually via register NMICON.
After reset, the enable bits of IEN0, IEN1 and NMICON are cleared to 0. This implies that
the corresponding interrupts are disabled.
IEN0
Interrupt Enable Register 0
Reset Value: 00H
7
6
5
4
3
2
1
0
EA
0
ET2
ES
ET1
EX1
ET0
EX0
rw
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
EX0
0
rw
Enable External Interrupt 0
0
External Interrupt 0 is disabled.
1
External Interrupt 0 is enabled.
ET0
1
rw
Enable Timer 0 Overflow Interrupt
0
Timer 0 Overflow interrupt is disabled.
1
Timer 0 Overflow interrupt is enabled.
EX1
2
rw
Enable External Interrupt 1
0
External interrupt 1 is disabled.
1
External interrupt 1 is enabled.
ET1
3
rw
Enable Timer 1 Overflow Interrupt
0
Timer 1 Overflow interrupt is disabled.
1
Timer 1 Overflow interrupt is enabled.
ES
4
rw
Enable Serial Port Interrupt
0
Serial Port interrupt is disabled.
1
Serial Port interrupt is enabled.
ET2
5
rw
Enable Timer 2 Interrupt
0
Timer 2 interrupt is disabled.
1
Timer 2 interrupt is enabled.
User’s Manual
Interrupt System, V 0.5
5-9
V 0.2, 2005-01
XC866
Interrupt System
Field
Bits
Type Description
EA
7
rw
Enable/Disable All Interrupts
0
No interrupt will be acknowledged
1
Each interrupt source is individually enabled
or disabled by setting or clearing its enable
bit.
0
6
r
Reserved
Returns 0 if read; should be written with 0.
IEN1
Interrupt Enable Register 1
Reset Value: 00H
7
6
5
4
3
2
1
0
ECCIP3
ECCIP2
ECCIP1
ECCIP0
EXM
EX2
ESSC
EADC
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
EADC
0
rw
ADC Interrupt Enable
0
ADC interrupts are disabled.
1
ADC interrupts are enabled.
ESSC
1
rw
SSC Interrupt Enable
0
SSC interrupts are disabled.
1
SSC interrupts are enabled.
EX2
2
rw
External Interrupt 2 Enable
0
External interrupt 2 is disabled.
1
External interrupt 2 is enabled.
EXM
3
rw
External Interrupts [6:3] Enable
0
External interrupts [6:3] are disabled.
1
External interrupt [6:3] are enabled.
ECCIP0
4
rw
CCU6 Interrupt Node Pointer 0 Enable
0
CCU6 Interrupt Node Pointer 0 is disabled.
1
CCU6 Interrupt Node Pointer 0 is enabled.
ECCIP1
5
rw
CCU6 Interrupt Node Pointer 1 Enable
0
CCU6 Interrupt Node Pointer 1 is disabled.
1
CCU6 Interrupt Node Pointer 1 is enabled.
User’s Manual
Interrupt System, V 0.5
5-10
V 0.2, 2005-01
XC866
Interrupt System
Field
Bits
Type Description
ECCIP2
6
rw
CCU6 Interrupt Node Pointer 2 Enable
0
CCU6 Interrupt Node Pointer 2 is disabled.
1
CCU6 Interrupt Node Pointer 2 is enabled.
ECCIP3
7
rw
CCU6 Interrupt Node Pointer 3 Enable
0
CCU6 Interrupt Node Pointer 3 is disabled.
1
CCU6 Interrupt Node Pointer 3 is enabled.
NMICON
NMI Control Register
Reset Value: 00H
7
6
5
4
3
0
NMIECC
NMIVDDP
NMIVDD
NMIOCDS
r
rw
rw
rw
rw
2
NMIFLASHTIMER
rw
1
0
NMIPLL
NMIWDT
rw
rw
Field
Bits
Type Description
NMIWDT
0
rw
Watchdog Timer NMI Enable
0
WDT NMI is disabled.
1
WDT NMI is enabled.
NMIPLL
1
rw
PLL Loss of Lock NMI Enable
0
PLL Loss of Lock NMI is disabled.
1
PLL Loss of Lock NMI is enabled.
NMIFLASHTIMER
2
rw
Flash Timer NMI Enable
0
Flash Timer NMI is disabled.
1
Flash Timer NMI is enabled.
NMIOCDS
3
rw
OCDS NMI Enable
0
OCDS NMI is disabled.
1
OCDS NMI is enabled.
NMIVDD
4
rw
VDD Prewarning NMI Enable
0
VDD NMI is disabled.
1
VDD NMI is enabled.
NMIVDDP
5
rw
VDDP Prewarning NMI Enable
0
VDDP NMI is disabled.
1
VDDP NMI is enabled.
Note: When the external power supply is 3.3 V,
the user must disable NMIVDDP.
User’s Manual
Interrupt System, V 0.5
5-11
V 0.2, 2005-01
XC866
Interrupt System
Field
Bits
Type Description
NMIECC
6
rw
ECC NMI Enable
0
ECC NMI is disabled.
1
ECC NMI is enabled.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
EXICON0
External Interrupt Control Register 0
7
6
5
Reset Value: 00H
4
3
2
1
0
EXINT3
EXINT2
EXINT1
EXINT0
rw
rw
rw
rw
Field
Bits
Type Description
EXINT0
[1:0]
rw
External Interrupt 0 Trigger Select
00
Interrupt on falling edge
01
Interrupt on rising edge
10
Interrupt on both rising and falling edge
11
Bypass the edge detection
EXINT1
[3:2]
rw
External Interrupt 1 Trigger Select
00
Interrupt on falling edge
01
Interrupt on rising edge
10
Interrupt on both rising and falling edge
11
Bypass the edge detection
EXINT2
[5:4]
rw
External Interrupt 2 Trigger Select
00
Interrupt on falling edge
01
Interrupt on rising edge
10
Interrupt on both rising and falling edge
11
Reserved
EXINT3
[7:6]
rw
External Interrupt 3 Trigger Select
00
Interrupt on falling edge
01
Interrupt on rising edge
10
Interrupt on both rising and falling edge
11
Reserved
User’s Manual
Interrupt System, V 0.5
5-12
V 0.2, 2005-01
XC866
Interrupt System
EXICON1
External Interrupt Control Register 1
7
6
5
Reset Value: 00H
4
3
2
1
0
0
EXINT6
EXINT5
EXINT4
r
rw
rw
rw
Field
Bits
Type Description
EXINT4
[1:0]
rw
External Interrupt 4 Trigger Select
00
Interrupt on falling edge
01
Interrupt on rising edge
10
Interrupt on both rising and falling edge
11
Reserved
EXINT5
[3:2]
rw
External Interrupt 5 Trigger Select
00
Interrupt on falling edge
01
Interrupt on rising edge
10
Interrupt on both rising and falling edge
11
Reserved
EXINT6
[5:4]
rw
External Interrupt 6 Trigger Select
00
Interrupt on falling edge
01
Interrupt on rising edge
10
Interrupt on both rising and falling edge
11
Reserved
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Interrupt System, V 0.5
5-13
V 0.2, 2005-01
XC866
Interrupt System
5.4.2
Interrupt Request Flags
The interrupt request flags for the different sources are located in several Special
Function Registers (SFRs). This section details the locations and meanings of these
interrupt request flags.
IRCON0
Interrupt Request Register 0
Reset Value: 00H
7
6
5
4
3
2
1
0
0
EXINT6
EXINT5
EXINT4
EXINT3
EXINT2
EXINT1
EXINT0
r
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
EXINTx
(x = 0 - 6)
[6:0]
rwh
Interrupt Request Flag for External Interrupts
This bit is set by hardware and can only be cleared
by software.
0
Interrupt request is not active.
1
Interrupt request is active.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Interrupt System, V 0.5
5-14
V 0.2, 2005-01
XC866
Interrupt System
IRCON1
Interrupt Request Register 1
7
6
5
Reset Value: 00H
4
0
3
ADCSRC1 ADCSRC0
r
rwh
rwh
2
1
0
RIR
TIR
EIR
rwh
rwh
rwh
Field
Bits
Type Description
EIR
0
rwh
Error Interrupt Request Flag for SSC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt request is not active.
1
Interrupt request is active.
TIR
1
rwh
Transmit Interrupt Request Flag for SSC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt request is not active.
1
Interrupt request is active.
RIR
2
rwh
Receive Interrupt Request Flag for SSC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt request is not active.
1
Interrupt request is active.
ADCSRC0
3
rwh
Interrupt Request 0 Flag for ADC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt request is not active.
1
Interrupt request is active.
ADCSRC1
4
rwh
Interrupt Request 1 Flag for ADC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt request is not active.
1
Interrupt request is active.
0
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Interrupt System, V 0.5
5-15
V 0.2, 2005-01
XC866
Interrupt System
TCON
Timer Control Register
Reset Value: 00H
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
rwh
rw
rwh
rw
rwh
rw
rwh
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
IT0
0
rw
External Interrupt 0 Level/Edge Trigger Control
Flag
0
Low level triggered external interrupt 0 is
selected.
1
Falling edge triggered external interrupt 0 is
selected.
IE0
1
rwh
External Interrupt 0 Request Flag
Set by hardware when external interrupt 0 edge is
detected.
Cleared by hardware when the processor vectors
to interrupt routine.
IT1
2
rw
External Interrupt 1 Level/Edge Trigger Control
Flag
0
Low level triggered external interrupt 1 is
selected.
1
Falling edge triggered external interrupt 1 is
selected.
IE1
3
rwh
External Interrupt 1 Request Flag
Set by hardware when external interrupt 1 edge is
detected.
Cleared by hardware when the processor vectors
to interrupt routine.
TF0
5
rwh
Timer 0 Overflow Flag
Set by hardware on Timer/Counter 0 overflow.
Cleared by hardware when processor vectors to
interrupt routine.
User’s Manual
Interrupt System, V 0.5
5-16
V 0.2, 2005-01
XC866
Interrupt System
Field
Bits
Type Description
TF1
7
rwh
Timer 1 Overflow Flag
Set by hardware on Timer/Counter 1 overflow.
Cleared by hardware when processor vectors to
interrupt routine.
SCON
Serial Channel Control Register
Reset Value: 00H
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
rw
rw
rw
rw
rw
rwh
rwh
rwh
The functions of the shaded bits are not described here
Field
Bits
Type Description
RI
0
rwh
Serial Interface Receiver Interrupt Flag
Set by hardware if a serial data byte has been
received. Must be cleared by software.
TI
1
rwh
Serial Interface Transmitter Interrupt Flag
Set by hardware at the end of a serial data
transmission. Must be cleared by software.
NMISR
NMI Status Register
Reset Value: 00H
7
6
5
4
3
2
0
FNMIECC
FNMI
VDDP
FNMI
VDD
FNMI
OCDS
r
rwh
rwh
rwh
rwh
FNMIFLASHTIMER
rwh
Field
Bits
Type Description
FNMIWDT
0
rwh
User’s Manual
Interrupt System, V 0.5
1
0
FNMIPLL FNMIWDT
rwh
rwh
Watchdog Timer NMI Flag
0
No Watchdog NMI occurred.
1
WDT prewarning has occurred.
5-17
V 0.2, 2005-01
XC866
Interrupt System
Field
Bits
Type Description
FNMIPLL
1
rwh
PLL NMI Flag
0
No PLL NMI occurred.
1
The PLL has lost the lock to the external
crystal.
FNMIFLASHTIMER
2
rwh
Flash Timer NMI Flag
0
No Flash NMI occurred.
1
Flash Timer has overflowed.
FNMIOCDS
3
rwh
OCDS NMI Flag
0
No OCDS NMI occurred.
1
JTAG-receiving or user interrupt requested in
monitor mode.
FNMIVDD
4
rwh
VDD Prewarning NMI Flag
0
No VDD NMI occurred.
1
VDD is below the prewarning voltage level
(2.3 V).
FNMIVDDP
5
rwh
VDDP Prewarning NMI Flag
0
No VDDP NMI occurred.
1
VDDP is below the prewarning voltage level
(4.0 V if the external power supply is 5.0 V).
FNMIECC
6
rwh
ECC NMI Flag
0
No ECC error occurred.
1
ECC error has occurred.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
Register NMISR can only be cleared by software or reset to the default value after the
power-on reset/hardware reset/brownout reset. The register value is retained on any
other reset such as watchdog timer reset or power-down wake-up reset. This allows the
system to detect what caused the previous NMI.
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XC866
Interrupt System
5.4.3
Interrupt Priority Registers
Each interrupt source can be individually programmed to one of the four possible priority
levels. Two pairs of interrupt priority registers are available to program the priority level
of each interrupt vector. The first pair of registers is SFRs IP and IPH.
IP
Interrupt Priority Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
PT2
PS
PT1
PX1
PT0
PX0
r
rw
rw
rw
rw
rw
rw
IPH
Interrupt Priority Register High
7
6
Reset Value: 00H
5
4
3
2
1
0
0
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
PX0,
PX0H
0
rw
Priority Level for External Interrupt 0
PT0,
PT0H
1
rw
Priority Level for Timer 0 Overflow Interrupt
PX1,
PX1H
2
rw
Priority Level for External Interrupt 1
PT1,
PT1H
3
rw
Priority Level for Timer 1 Overflow Interrupt
PS,
PSH
4
rw
Priority Level for Serial Port Interrupt
PT2,
PT2H
5
rw
Priority Level for Timer 2 Interrupt
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
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XC866
Interrupt System
The second pair of interrupt priority registers is SFRs IP1 and IPH1.
IP1
Interrupt Priority Register 1
Reset Value: 00H
7
6
5
4
3
2
1
0
PCCIP3
PCCIP2
PCCIP1
PCCIP0
PXM
PX2
PSSC
PADC
rw
rw
rw
rw
rw
rw
rw
rw
IPH1
Interrupt Priority Register 1 High
Reset Value: 00H
7
6
5
4
3
2
1
0
PCCIP3H
PCCIP2H
PCCIP1H
PCCIP0H
PXMH
PX2H
PSSCH
PADCH
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
PADC,
PADCH
0
rw
Priority Level for ADC Interrupt
PSSC,
PSSCH
1
rw
Priority Level for SSC Interrupt
PX2,
PX2H
2
rw
Priority Level for External Interrupt 2
PXM,
PXMH
3
rw
Priority Level for External Interrupt 3 to 6
PCCIP0,
PCCIP0H
4
rw
Priority Level for CCU6 Interrupt Node Pointer 0
PCCIP1,
PCCIP1H
5
rw
Priority Level for CCU6 Interrupt Node Pointer 1
PCCIP2,
PCCIP2H
6
rw
Priority Level for CCU6 Interrupt Node Pointer 2
PCCIP3,
PCCIP3H
7
rw
Priority Level for CCU6 Interrupt Node Pointer 3
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5-20
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XC866
Interrupt System
5.4.4
Interrupt Priority
The respective bit fields of the interrupt priority registers together select one of the four
priority levels as shown in Table 5-2.
Table 5-2
Interrupt Priority Level Selection
IPH.x / IPH1.x
IP.x / IP1.x
Priority Level
0
0
Level 0 (lowest)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest)
Note: As the NMI has the highest priority, it does not use the level selection shown in
Table 5-2.
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another
interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot
be interrupted by any other interrupt source.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence as shown in Table 5-3.
Table 5-3
Priority Structure within Interrupt Level
Source
Level
Non-Maskable Interrupt (NMI)
(highest)
External Interrupt 0
1
Timer 0 Interrupt
2
External Interrupt 1
3
Timer 1 Interrupt
4
UART Interrupt
5
Timer 2 Interrupt
6
ADC Interrupt
7
SSC Interrupt
8
External Interrupt 2
9
External Interrupt [6:3]
10
CCU6 Interrupt Node Pointer 0
11
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5-21
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XC866
Interrupt System
Table 5-3
Priority Structure within Interrupt Level (cont’d)
Source
Level
CCU6 Interrupt Node Pointer 1
12
CCU6 Interrupt Node Pointer 2
13
CCU6 Interrupt Node Pointer 3
14
5.4.5
Interrupt Request Flags
The interrupt request flags are located in different SFRs. Table 5-4 shows the bit
locations of the interrupt request flags. Detailed information about the interrupt request
flags is provided in the respective peripheral chapters.
Table 5-4
Locations of the Interrupt Request Flags
Interrupt Source
Request Flags
SFR
Timer 0 Interrupt
TF0
TCON
Timer 1 Interrupt
TF1
TCON
Timer 2 Interrupt
TF2
T2CON
EXF2
T2CON
RI
SCON
TI
SCON
External Interrupt 0
IE0
TCON
External Interrupt 1
IE1
TCON
External Interrupt 2
EXINT2
IRCON0
External Interrupt 3
EXINT3
IRCON0
External Interrupt 4
EXINT4
IRCON0
External Interrupt 5
EXINT5
IRCON0
External Interrupt 6
EXINT6
IRCON0
ADC Interrupt
ADCSRC0
IRCON1
ADCSRC1
IRCON1
EIR
IRCON1
TIR
IRCON1
RIR
IRCON1
UART
SSC Interrupt
CCU6 Node 0 Interrupt
See note 1)
INPL/INPH
CCU6 Node 1 Interrupt
See note1)
INPL/INPH
CCU6 Node 2 Interrupt
note1)
INPL/INPH
User’s Manual
Interrupt System, V 0.5
See
5-22
V 0.2, 2005-01
XC866
Interrupt System
Table 5-4
Locations of the Interrupt Request Flags (cont’d)
Interrupt Source
Request Flags
1)
CCU6 Node 3 Interrupt
See note
SFR
INPL/INPH
Watchdog Timer NMI
FNMIWDT
NMISR
PLL NMI
FNMIPLL
NMISR
Flash Timer NMI
FNMI
FLASHTIMER
NMISR
OCDS NMI
FNMIOCDS
NMISR
VDD NMI
FNMIVDD
NMISR
VDDP NMI
FNMIVDDP
NMISR
ECC NMI
FNMIECC
NMISR
1)
Different CCU6 interrupts can be assigned to different CCU6 interrupt nodes[3:0], which are selected via
registers INPL/INPH.
5.5
Interrupt Handling
The interrupt flags are sampled at phase 2 in each machine cycle. The sampled flags
are then polled during the following machine cycle. If one of the flags was in a set
condition at phase 2 of the preceding cycle, the polling cycle will find it and the interrupt
system will generate an LCALL to the appropriate service routine, provided this
hardware-generated LCALL is not blocked by any of the following conditions:
• An interrupt of equal or higher priority is already in progress.
• The current (polling) cycle is not in the final cycle of the instruction in progress.
• The instruction in progress is RETI or any write access to registers IEN0/IEN1 or
IP,IPH/IP1,IP1H.
Any of these three conditions will block the generation of the LCALL to the interrupt
service routine. Condition 2 ensures that the instruction in progress is completed before
vectoring to any service routine. Condition 3 ensures that if the instruction in progress is
RETI or any write access to registers IEN0/IEN1 or IP,IPH/IP1,IP1H, then at least one
more instruction will be executed before any interrupt is vectored to; this delay
guarantees that changes of the interrupt status can be observed by the CPU.
The polling cycle is repeated with each machine cycle, and the values polled are the
values that were present at phase 2 of the previous machine cycle. Note that if any
interrupt flag is active but was not responded to for one of the conditions already
mentioned, or if the flag was no longer active at the time of removal of the blocking
condition, the denied interrupt will not be serviced. In other words, the fact that the
interrupt flag was once active but not serviced is not remembered. Every polling cycle
interrogates only the pending interrupt requests.
Figure 5-6 shows the timing example for extended interrupts.
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Interrupt System, V 0.5
5-23
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XC866
Interrupt System
| C..P2
| C L P1
| C L P2
| C 1P1
| C 1P2
| C 2P1
| C 2P2
PCLK
XINTR_SCR[1]
XINTR_ACK[1]
Interrupts
sampled here
Figure 5-6
Timing for Extended Interrupt
The processor acknowledges an interrupt request by executing a hardware generated
LCALL to the appropriate servicing routine. In some cases, hardware also clears the flag
that generated the interrupt, while in other cases, the flag must be cleared by the user’s
software. The hardware-generated LCALL pushes the contents of the Program Counter
(PC) onto the stack (but it does not save the PSW) and reloads the PC with an address
that depends on the source of the interrupt being vectored to, as shown in the Table 5-1.
Program execution returns to the next instruction after calling the interrupt when the
RETI instruction is encountered. The RETI instruction informs the processor that the
interrupt routine is no longer in progress, then pops the two top bytes from the stack and
reloads the PC. Execution of the interrupted program continues from the point where it
was stopped. Note that the RETI instruction is important because it informs the
processor that the program has left the current interrupt priority level. A simple RET
instruction would also have returned execution to the interrupted program, but it would
have left the interrupt control system on the assumption that an interrupt was still in
progress. In this case, no interrupt of the same or lower priority level would be
acknowledged.
5.6
Interrupt Response Time
If an interrupt is recognized, its corresponding request flag is set at phase 2 in every
machine cycle. The value is not polled by the circuitry until the next machine cycle. If the
request is active and conditions are right for it to be acknowledged, a hardware
subroutine call to the requested service routine will be the next instruction to be
executed. The call itself takes two machine cycles. Thus, a minimum of three complete
machine cycles will elapse from activation of the interrupt request to the beginning of
execution of the first instruction of the service routine. A longer response time would be
obtained if the request is blocked by one of the three previously listed conditions. If an
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Interrupt System
interrupt of equal or higher priority is already in progress, the additional wait time will
depend on the nature of the other interrupt's service routine. If the instruction in progress
is not in its final cycle, the additional wait time cannot be more than three machine cycles.
The longest instructions (MUL and DIV) are only four machine cycles long. If the
instruction in progress is RETI or a write access to registers IEN0, IEN1 or IP(H), IP1(H),
the additional wait time cannot be more than five cycles (a maximum of one more
machine cycle to complete the instruction in progress, plus four machine cycles to
complete the next instruction, if the instruction is MUL or DIV). Thus, in a single interrupt
system, if the wait states are not considered, the response time is between three and
nine machine cycles.
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XC866
Parallel Ports
6
Parallel Ports
The XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3).
Each pin has a pair of internal pull-up and pull-down devices that can be individually
enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general
purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip
peripherals. When configured as an output, the open drain mode can be selected. Port
P2 is an input-only port, providing general purpose input functions, alternate input
functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital
Converter (ADC).
Bidirectional Port Features:
•
•
•
•
•
Configurable pin direction
Configurable pull-up/pull-down devices
Configurable open drain mode
Transfer of data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Input Port Features:
•
•
•
•
Configurable pull-up/pull-down devices
Receive of data through digital input (general purpose input)
Alternate input for on-chip peripherals
Analog input for ADC module
User’s Manual
Parallel Ports, V 0.3
6-1
V 0.2, 2005-01
XC866
Parallel Ports
6.1
General Port Operation
Figure 6-1 shows the block diagram of an XC866 bidirectional port pin. Each port pin is
equipped with a number of control and data bits, thus enabling very flexible usage of the
pin. By defining the contents of the control register, each individual pin can be configured
as an input or an output. The user can also configure each pin as an open drain pin with
or without internal pull-up/pull-down device.
Each bidirectional port pin can be configured for input or output operation. Switching
between input and output mode is accomplished through the register Px_DIR
(x = 0, 1 or 3), which enables or disables the output and input drivers. A port pin can only
be configured as either input or output mode at any one time.
In input mode (default after reset), the output driver is switched off (high-impedance).
The actual voltage level present at the port pin is translated into a logic 0 or 1 via a
Schmitt-Trigger device and can be read via the register Px_DATA.
In output mode, the output driver is activated and drives the value supplied through the
multiplexer to the port pin. In the output driver, each port line can be switched to open
drain mode or normal mode (push-pull mode) via the register Px_OD.
The output multiplexer in front of the output driver enables the port output function to be
used for different purposes. If the pin is used for general purpose output, the multiplexer
is switched by software to the data register Px_DATA. Software can set or clear the bit
in Px_DATA and therefore directly influence the state of the port pin. If an on-chip
peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be
switched via the multiplexer to the output driver circuitry. Selection of the alternate
function is defined in registers Px_ALTSEL0 and Px_ALTSEL1. When a port pin is used
as an alternate function, its direction must be set accordingly in the register Px_DIR.
Each pin can also be programmed to activate an internal weak pull-up or pull-down
device. Register Px_PUDSEL selects whether a pull-up or the pull-down device is
activated while register Px_PUDEN enables or disables the pull device.
To achieve high speed I/O data transfer, each I/O pin can be switched for direct
connection to the various inputs of the peripheral units (AltDataIn). The function of the
input line from the pin to the data register Px_DATA and to AltDataIn is independent of
whether the port pin operates as input or output. This means that when the pin is in
output mode, the level of the pin can be read by software via Px_DATA or a peripheral
can use the pin level as an input. This offers additional advantages in an application:
• When the pin is configured as general purpose output, the data written to the data
register Px_DATA by software can be used as input data to an on-chip peripheral.
This enables, for example, peripheral tests via software without external circuitry.
Examples for this can be the triggering of a timer count input, generating an external
interrupt, or simulating the incoming serial data stream to a serial port receive input
via software.
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XC866
Parallel Ports
• When the pin is configured for alternate output function, the output data that is driven
to the pin by a peripheral can be read through software via Px_DATA or used by the
same or another peripheral as input data. This enables testing of peripheral functions
or provides additional connections between on-chip peripherals via the same pin
without external wires.
Internal Bus
Px_PUDSEL
Pull-up/Pull-down
Select Register
Pull-up/Pull-down
Control Logic
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_OD
Open Drain
Control Register
Px_DIR
Direction Register
Px_ALTSEL0
Alternate Select Register 0
Px_ALTSEL1
Pull
Device
Alternate Select Register 1
AltDataOut 2
Output
Driver
10
AltDataOut1
Pin
01
00
Px_Data
Data Register
Out
Input
Driver
In
Schmitt Trigger
AltDataIn
Pad
Figure 6-1
General Structure of Bidirectional Port
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6-3
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XC866
Parallel Ports
Figure 6-2 shows the structure of an input-only port pin. Each P2 pin can only function
in input mode. The actual voltage level present at the port pin is translated into a logic 0
or 1 via a Schmitt-Trigger device and can be read via the register P2_DATA. Each pin
can also be programmed to activate an internal weak pull-up or pull-down device.
Register P2_PUDSEL selects whether a pull-up or the pull-down device is activated
while register P2_PUDEN enables or disables the pull device. The analog input
(AnalogIn) bypasses the digital circuitry and Schmitt-Trigger device for direct feedthrough to the ADC input channel.
Internal Bus
P2_PUDSEL
Pull-up/Pull-down
Select Register
Pull-up/Pull-down
Control Logic
P2_PUDEN
Pull-up/Pull-down
Enable Register
Pull
Device
P2_Data
In
Input
Driver
Pin
Data Register
Schmitt Trigger
Pad
AltDataIn
AnalogIn
Figure 6-2
General Structure of Input Port
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Parallel Ports, V 0.3
6-4
V 0.2, 2005-01
XC866
Parallel Ports
6.1.1
General Register Description
The individual control and data bits of each parallel port are implemented in a number of
8-bit registers. Bits with the same meaning and function are assembled together in the
same register. The registers configure and use the port as general purpose I/O or
alternate function input/output.
For port P2, not all the registers in Table 6-1 are implemented. The availability and
definition of registers specific to each port is defined in Section 6.3 to Section 6.6. This
section provides only an overview of the different port registers.
Table 6-1
Port Registers
Register Short Name
Register Full Name
Description
see
Px_DATA
Port x Data Register
Page 6-6
Px_DIR
Port x Direction Register
Page 6-7
Px_OD
Port x Open Drain Control Register
Page 6-7
Px_PUDSEL
Port x Pull-Up/Pull-Down Select Register
Page 6-8
Px_PUDEN
Port x Pull-Up/Pull-Down Enable Register
Page 6-8
Px_ALTSEL0
Port x Alternate Select Register 0
Page 6-10
Px_ALTSEL1
Port x Alternate Select Register 1
Page 6-10
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Parallel Ports, V 0.3
6-5
V 0.2, 2005-01
XC866
Parallel Ports
6.1.1.1
Data Register
If a port pin is used as general purpose output, output data is written into the data register
Px_DATA. If a port pin is used as general purpose input, the latched value of the port pin
can be read through register Px_DATA.
Note: A port pin that has been assigned as input will latch in the active internal pull-up/
pull-down setting if it is not driven by an external source. This results in register
Px_DATA being updated with the active pull value.
Px_DATA
Port x Data Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 – 7)
n
rw
Port x Pin n Data Value
0
Port x pin n data value = 0
1
Port x pin n data value = 1
Bit Px_DATA.n can only be written if the corresponding pin is set to output
(Px_DIR.n = 1) and cannot be written if the corresponding pin is set to input
(Px_DIR.n = 0). The content of Px_DATA.n is output on the assigned pin if the pin is
assigned as GPIO pin and the direction is switched/set to output. A read operation of
Px_DATA returns the register value and not the state of the corresponding Px_DATA
pin.
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XC866
Parallel Ports
6.1.1.2
Direction Register
The direction of port pins is controlled by the respective direction register Px_DIR.
Px_DIR
Port x Direction Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
6.1.1.3
Port x Pin n Direction Control
0
Direction is set to input.
1
Direction is set to output.
Open Drain Control Register
Each pin in output mode can be switched to open drain mode. If driven with 1, no driver
will be activated and the pin output state depends on the internal pull-up/pull-down
device setting. If driven with 0, the driver’s pull-down transistor will be activated.
The open drain mode is controlled by the register Px_OD.
Px_OD
Port x Open Drain Control Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
User’s Manual
Parallel Ports, V 0.3
Port x Pin n Open Drain Mode
0
Normal mode; output is actively driven for 0 and
1 state
1
Open drain mode; output is actively driven only
for 0 state
6-7
V 0.2, 2005-01
XC866
Parallel Ports
6.1.1.4
Pull-Up/Pull-Down Device Register
Internal pull-up/pull-down devices can be optionally applied to a port pin. This offers the
possibility of configuring the following input characteristics:
• tristate
• high-impedance with a weak pull-up device
• high-impedance with a weak pull-down device
and the following output characteristics:
• push/pull (optional pull-up/pull-down)
• open drain with internal pull-up
• open drain with external pull-up
The pull-up/pull-down device can be fixed or controlled via the registers Px_PUDSEL
and Px_PUDEN. Register Px_PUDSEL selects the type of pull-up/pull-down device,
while register Px_PUDEN enables or disables it. The pull-up/pull-down device can be
selected pinwise.
Px_PUDSEL
Port x Pull-Up/Pull-Down Select Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
Pull-Up/Pull-Down Select Port x Bit n
0
Pull-down device is selected.
1
Pull-up device is selected.
Px_PUDEN
Port x Pull-Up/Pull-Down Enable Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
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XC866
Parallel Ports
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
User’s Manual
Parallel Ports, V 0.3
Pull-Up/Pull-Down Enable at Port x Bit n
0
Pull-up or Pull-down device is disabled.
1
Pull-up or Pull-down device is enabled.
6-9
V 0.2, 2005-01
XC866
Parallel Ports
6.1.1.5
Alternate Input Functions
The number of alternate functions that uses a pin for input is not limited. Each port control
logic of an I/O pin provides several input paths:
• Digital input value via register
• Direct digital input value
6.1.1.6
Alternate Output Functions
Alternate functions are selected via an output multiplexer. This multiplexer can be
controlled by the following registers:
• Register Px_ALTSEL0
• Register Px_ALTSEL1
Selection of alternate functions is defined in registers Px_ALTSEL0 and Px_ALTSEL1.
Px_ALTSELn (n = 0 - 1)
Port x Alternate Select Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Function of Bits Px_ALTSEL0.Pn and Px_ALTSEL1.Pn
Px_ALTSEL0.Pn
Px_ALTSEL1.Pn
Function
0
0
Normal GPIO
1
0
Alternate Output 1
0
1
Alternate Output 2
1
1
Reserved
Note: Set Px_ALTSEL0.Pn and Px_ALTSEL1.Pn to select only implemented alternate
output functions.
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XC866
Parallel Ports
6.2
Register Map
The Port SFRs are located in the standard memory area (RMAP = 0) and are organized
into 4 pages. The PORT_PAGE register is located at address B2H. It contains the page
value and page control information.
PORT_PAGE
Page Register for PORT
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
0
PAGE
w
w
r
rw
0
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
User’s Manual
Parallel Ports, V 0.3
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
6-11
V 0.2, 2005-01
XC866
Parallel Ports
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Parallel Ports, V 0.3
6-12
V 0.2, 2005-01
XC866
Parallel Ports
The addresses of the Port SFRs are listed in Table 6-2.
Table 6-2
SFR Address List for Pages 0-3
Address
Page 0
Page 1
Page 2
Page 3
80H
P0_DATA
P0_PUDSEL
P0_ALTSEL0
P0_OD
86H
P0_DIR
P0_PUDEN
P0_ALTSEL1
–
90H
P1_DATA
P1_PUDSEL
P1_ALTSEL0
P1_OD
91H
P1_DIR
P1_PUDEN
P1_ALTSEL1
–
A0H
P2_DATA
P2_PUDSEL
–
–
A1H
–
P2_PUDEN
–
–
B0H
P3_DATA
P3_PUDSEL
P3_ALTSEL0
P3_OD
B1H
P3_DIR
P3_PUDEN
P3_ALTSEL1
–
User’s Manual
Parallel Ports, V 0.3
6-13
V 0.2, 2005-01
XC866
Parallel Ports
6.3
Port 0
Port P0 is a 6-bit general purpose bidirectional port. The registers of P0 are summarized
in Table 6-3.
Table 6-3
Port 0 Registers
Register Short Name Register Full Name
P0_DATA
Port 0 Data Register
P0_DIR
Port 0 Direction Register
P0_OD
Port 0 Open Drain Control Register
P0_PUDSEL
Port 0 Pull-Up/Pull-Down Select Register
P0_PUDEN
Port 0 Pull-Up/Pull-Down Enable Register
P0_ALTSEL0
Port 0 Alternate Select Register 0
P0_ALTSEL1
Port 0 Alternate Select Register 1
6.3.1
Table 6-4
Functions
Port 0 Input/Output Functions
Port Pin
Input/Output Select
Connected Signal(s)
From/to Module
P0.0
Input
GPI
P0_DATA.P0
–
ALT1
TCK_0
JTAG
ALT2
T12HR_1
CCU6
ALT3
CC61_1
CCU6
GPO
P0_DATA.P0
–
ALT1
CLKOUT
On-chip OSC
ALT2
CC61_1
CCU6
GPI
P0_DATA.P1
–
ALT1
TDI_0
JTAG
ALT2
T13HR_1
CCU6
ALT3
RXD_1
UART
GPO
P0_DATA.P1
–
ALT1
–
–
ALT2
COUT61_1
CCU6
Output
P0.1
Input
Output
User’s Manual
Parallel Ports, V 0.3
6-14
V 0.2, 2005-01
XC866
Parallel Ports
Table 6-4
Port 0 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
From/to Module
P0.2
Input
GPI
P0_DATA.P2
–
ALT1
–
–
ALT2
CTRAP_2
CCU6
ALT3
–
–
GPO
P0_DATA.P2
–
ALT1
TDO_0
JTAG
ALT2
TXD_1
UART
GPI
P0_DATA.P3
–
ALT1
SCK_1
SSC
ALT2
–
–
ALT3
–
–
GPO
P0_DATA.P3
–
ALT1
SCK_1
SSC
ALT2
COUT63_1
CCU6
GPI
P0_DATA.P4
–
ALT1
MTSR_1
SSC
ALT2
–
–
ALT3
CC62_1
CCU6
GPO
P0_DATA.P4
–
ALT1
MTSR_1
SSC
ALT2
CC62_1
CCU6
GPI
P0_DATA.P5
–
ALT1
MRST_1
SSC
ALT2
EXINT0_0
External interrupt
0
ALT3
–
–
GPO
P0_DATA.P5
–
ALT1
MRST_1
SSC
ALT2
COUT62_1
CCU6
Output
P0.3
Input
Output
P0.4
Input
Output
P0.5
Input
Output
User’s Manual
Parallel Ports, V 0.3
6-15
V 0.2, 2005-01
XC866
Parallel Ports
6.3.2
Register Description
P0_DATA
Port 0 Data Register
7
Reset Value: 00H
6
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 – 5)
n
rw
Port 0 Pin n Data Value
0
Port 0 pin n data value = 0 (default)
1
Port 0 pin n data value = 1
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
P0_DIR
Port 0 Direction Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 5)
n
rw
Port 0 Pin n Direction Control
0
Direction is set to input (default).
1
Direction is set to output.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Parallel Ports, V 0.3
6-16
V 0.2, 2005-01
XC866
Parallel Ports
P0_OD
Port 0 Open Drain Control Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 5)
n
rw
Port 0 Pin n Open Drain Mode
0
Normal mode; output is actively driven for 0 and
1 state (default)
1
Open drain mode; output is actively driven only
for 0 state
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
P0_PUDSEL
Port 0 Pull-Up/Pull-Down Select Register
7
6
Reset Value: FFH
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 5)
n
rw
Pull-Up/Pull-Down Select Port 0 Bit n
0
Pull-down device is selected.
1
Pull-up device is selected (default).
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Parallel Ports, V 0.3
6-17
V 0.2, 2005-01
XC866
Parallel Ports
P0_PUDEN
Port 0 Pull-Up/Pull-Down Enable Register
7
6
Reset Value: C4H
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 5)
n
rw
Pull-Up/Pull-Down Enable at Port 0 Bit n
0
Pull-up or Pull-down device is disabled.
1
Pull-up or Pull-down device is enabled (default).
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
P0_ALTSELn (n = 0 – 1)
Port 0 Alternate Select Register
7
Table 6-5
6
Reset Value: 00H
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Function of Bits P0_ALTSEL0.Pn and P0_ALTSEL1.Pn
P0_ALTSEL0.Pn
P0_ALTSEL1.Pn
Function
0
0
Normal GPIO
1
0
Alternate Output 1
0
1
Alternate Output 2
1
1
Reserved
User’s Manual
Parallel Ports, V 0.3
6-18
V 0.2, 2005-01
XC866
Parallel Ports
6.4
Port 1
Port P1 is a 5-bit general purpose bidirectional port. The registers of P1 are summarized
in Table 6-6.
Table 6-6
Port 1 Registers
Register Short Name Register Full Name
P1_DATA
Port 1 Data Register
P1_DIR
Port 1 Direction Register
P1_OD
Port 1 Open Drain Control Register
P1_PUDSEL
Port 1 Pull-Up/Pull-Down Select Register
P1_PUDEN
Port 1 Pull-Up/Pull-Down Enable Register
P1_ALTSEL0
Port 1 Alternate Select Register 0
P1_ALTSEL1
Port 1 Alternate Select Register 1
6.4.1
Table 6-7
Functions
Port 1 Input/Output Functions
Port Pin
Input/Output Select
Connected Signal(s)
From/to Module
P1.0
Input
GPI
P1_DATA.P0
–
ALT 1
RXD_0
UART
ALT 2
T2EX
Timer 2
ALT 3
–
–
GPO
P1_DATA.P0
–
ALT1
–
–
ALT2
–
–
GPI
P1_DATA.P1
–
ALT 1
–
–
ALT 2
EXINT3
External interrupt 3
ALT 3
–
–
GPO
P1_DATA.P1
–
ALT1
TDO_1
JTAG
ALT2
TXD_0
UART
Output
P1.1
Input
Output
User’s Manual
Parallel Ports, V 0.3
6-19
V 0.2, 2005-01
XC866
Parallel Ports
Table 6-7
Port 1 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
From/to Module
P1.5
Input
GPI
P1_DATA.P5
–
ALT 1
CCPOS0_1
CCU6
ALT 2
EXINT5
External interrupt 5
ALT 3
–
–
GPO
P1_DATA.P5 1)
–
ALT1
–
–
ALT2
–
–
GPI
P1_DATA.P6
–
ALT 1
CCPOS1_1
CCU6
ALT 2
T12HR_0
CCU6
ALT 3
EXINT6
External interrupt 6
GPO
P1_DATA.P62)
–
ALT1
–
–
ALT2
–
–
GPI
P1_DATA.P7
–
ALT 1
CCPOS2_1
CCU6
ALT 2
T13HR_0
CCU6
ALT 3
–
–
GPO
P1_DATA.P7
–
ALT1
–
–
ALT2
–
–
Output
P1.6
Input
Output
P1.7
Input
Output
1)
P1.5 can be used as a software Chip Select function for the SSC.
2)
P1.6 can be used as a software Chip Select function for the SSC.
User’s Manual
Parallel Ports, V 0.3
6-20
V 0.2, 2005-01
XC866
Parallel Ports
6.4.2
Register Description
P1_DATA
Port 1 Data Register
Reset Value: 00H
7
6
5
P7
P6
P5
rw
rw
rw
Field
Bits
4
3
2
1
0
0
P1
P0
r
rw
rw
Type
Description
Pn
n
(n = 0 – 1, 5 – 7)
rw
Port 1 Pin n Data Value
0
Port 1 pin n data value = 0 (default)
1
Port 1 pin n data value = 1
0
r
Reserved
Returns 0 if read; should be written with 0.
[4:2]
P1_DIR
Port 1 Direction Register
7
6
5
P7
P6
P5
rw
rw
rw
Reset Value: 00H
4
3
2
1
0
0
P1
P0
r
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 1, 5 – 7)
n
rw
Port 1 Pin n Direction Control
0
Direction is set to input (default).
1
Direction is set to output.
0
[4:2]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Parallel Ports, V 0.3
6-21
V 0.2, 2005-01
XC866
Parallel Ports
P1_OD
Port 1 Open Drain Control Register
7
6
5
P7
P6
P5
rw
rw
rw
Field
Bits
Reset Value: 00H
4
3
2
1
0
0
P1
P0
r
rw
rw
Type Description
Pn
n
(n = 0 – 1, 5 – 7)
rw
Port 1 Pin n Open Drain Mode
0
Normal mode; output is actively driven for 0 and
1 state (default)
1
Open drain mode; output is actively driven only
for 0 state
0
r
Reserved
Returns 0 if read; should be written with 0.
[4:2]
P1_PUDSEL
Port 1 Pull-Up/Pull-Down Select Register
7
6
5
P7
P6
P5
rw
rw
rw
Field
Bits
4
Reset Value: FFH
3
2
1
0
0
P1
P0
r
rw
rw
Type Description
Pn
n
(n = 0 – 1, 5 – 7)
rw
Pull-Up/Pull-Down Select Port 1 Bit n
0
Pull-down device is selected.
1
Pull-up device is selected (default).
0
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Parallel Ports, V 0.3
[4:2]
6-22
V 0.2, 2005-01
XC866
Parallel Ports
P1_PUDEN
Port 1 Pull-Up/Pull-Down Enable Register
7
6
5
P7
P6
P5
rw
rw
rw
Field
Bits
4
Reset Value: FFH
3
2
1
0
0
P1
P0
r
rw
rw
Type Description
Pn
n
(n = 0 – 1, 5 – 7)
rw
Pull-Up/Pull-Down Enable at Port 1 Bit n
0
Pull-up or Pull-down device is disabled.
1
Pull-up or Pull-down device is enabled (default).
0
r
Reserved
Returns 0 if read; should be written with 0.
[4:2]
P1_ALTSELn (n = 0 – 1)
Port 1 Alternate Select Register
7
6
5
P7
P6
P5
rw
rw
rw
Table 6-8
Reset Value: 00H
4
3
2
1
0
0
P1
P0
r
rw
rw
Function of Bits P1_ALTSEL0.Pn and P1_ALTSEL1.Pn
P1_ALTSEL0.Pn
P1_ALTSEL1.Pn
Function
0
0
Normal GPIO
1
0
Alternate Output 1
0
1
Alternate Output 2
1
1
Reserved
User’s Manual
Parallel Ports, V 0.3
6-23
V 0.2, 2005-01
XC866
Parallel Ports
6.5
Port 2
Port P2 is an 8-bit general purpose input-only port. The registers of P2 are summarized
in Table 6-9.
Table 6-9
Port 2 Registers
Register Short Name Register Full Name
P2_DATA
Port 2 Data Register
P2_PUDSEL
Port 2 Pull-Up/Pull-Down Select Register
P2_PUDEN
Port 2 Pull-Up/Pull-Down Enable Register
6.5.1
Table 6-10
Functions
Port 2 Input Functions
Port Pin
Input/Output Select
Connected Signal(s)
From/to Module
P2.0
Input
GPI
P2_DATA.P0
–
ALT 1
CCPOS0_0
CCU6
ALT 2
EXINT1
External interrupt 1
ALT 3
T12HR_2
CCU6
ALT 4
TCK_1
JTAG
ANALOG
AN0
ADC
GPI
P2_DATA.P1
–
ALT 1
CCPOS1_0
CCU6
ALT 2
EXINT2
External interrupt 2
ALT 3
T13HR_2
CCU6
ALT 4
TDI_1
JTAG
ANALOG
AN1
ADC
GPI
P2_DATA.P2
–
ALT 1
CCPOS2_0
CCU6
ALT 2
–
–
ALT 3
CTRAP_1
CCU6
ALT 4
–
–
ANALOG
AN2
ADC
P2.1
P2.2
Input
Input
User’s Manual
Parallel Ports, V 0.3
6-24
V 0.2, 2005-01
XC866
Parallel Ports
Table 6-10
Port 2 Input Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
From/to Module
P2.3
Input
GPI
P2_DATA.P3
–
ALT 1
–
–
ALT 2
–
–
ALT 3
–
–
ANALOG
AN3
ADC
GPI
P2_DATA.P4
–
ALT 1
–
–
ALT 2
–
–
ALT 3
–
–
ANALOG
AN4
ADC
GPI
P2_DATA.P5
–
ALT 1
–
–
ALT 2
–
–
ALT 3
–
–
ANALOG
AN5
ADC
GPI
P2_DATA.P6
–
ALT 1
–
–
ALT 2
–
–
ALT 3
–
–
ANALOG
AN6
ADC
GPI
P2_DATA.P7
–
ALT 1
–
–
ALT 2
–
–
ALT 3
–
–
ANALOG
AN7
ADC
P2.4
P2.5
P2.6
P2.7
Input
Input
Input
Input
User’s Manual
Parallel Ports, V 0.3
6-25
V 0.2, 2005-01
XC866
Parallel Ports
6.5.2
Register Description
P2_DATA
Port 2 Data Register
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
Pn
(n = 0 – 7)
n
r
Port 2 Pin n Data Value
0
Port 2 pin n data value = 0 (default)
1
Port 2 pin n data value = 1
P2_PUDSEL
Port 2 Pull-Up/Pull-Down Select Register
Reset Value: FFH
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
User’s Manual
Parallel Ports, V 0.3
Pull-Up/Pull-Down Select Port 2 Bit n
0
Pull-down device is selected.
1
Pull-up device is selected.
6-26
V 0.2, 2005-01
XC866
Parallel Ports
P2_PUDEN
Port 2 Pull-Up/Pull-Down Enable Register
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
User’s Manual
Parallel Ports, V 0.3
Pull-Up/Pull-Down Enable at Port 2 Bit n
0
Pull-up or Pull-down device is disabled (default).
1
Pull-up or Pull-down device is enabled.
6-27
V 0.2, 2005-01
XC866
Parallel Ports
6.6
Port 3
Port P3 is an 8-bit general purpose bidirectional port. The registers of P3 are
summarized in Table 6-11.
Table 6-11
Port 3 Registers
Register Short Name Register Full Name
P3_DATA
Port 3 Data Register
P3_DIR
Port 3 Direction Register
P3_OD
Port 3 Open Drain Control Register
P3_PUDSEL
Port 3 Pull-Up/Pull-Down Select Register
P3_PUDEN
Port 3 Pull-Up/Pull-Down Enable Register
P3_ALTSEL0
Port 3 Alternate Select Register 0
P3_ALTSEL1
Port 3 Alternate Select Register 1
6.6.1
Table 6-12
Functions
Port 3 Input/Output Functions
Port Pin
Input/Output Select
Connected Signal(s)
From/to Module
P3.0
Input
GPI
P3_DATA.P0
–
ALT 1
CC60_0
CCU6
ALT 2
–
–
ALT 3
–
–
GPO
P3_DATA.P0
–
ALT1
CC60_0
CCU6
ALT2
–
–
GPI
P3_DATA.P1
–
ALT 1
–
–
ALT 2
–
–
ALT 3
–
–
GPO
P3_DATA.P1
–
ALT1
COUT60_0
CCU6
ALT2
–
–
Output
P3.1
Input
Output
User’s Manual
Parallel Ports, V 0.3
6-28
V 0.2, 2005-01
XC866
Parallel Ports
Table 6-12
Port 3 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
From/to Module
P3.2
Input
GPI
P3_DATA.P2
–
ALT 1
CC61_0
CCU6
ALT 2
–
–
ALT 3
–
–
GPO
P3_DATA.P3
–
ALT1
CC61_0
CCU6
ALT2
–
–
GPI
P3_DATA.P3
–
ALT 1
–
–
ALT 2
–
–
ALT 3
–
–
GPO
P3_DATA.P3
–
ALT1
COUT61_0
CCU6
ALT2
–
–
GPI
P3_DATA.P4
–
ALT 1
CC62_0
CCU6
ALT 2
–
–
ALT 3
–
–
GPO
P3_DATA.P4
–
ALT1
CC62_0
CCU6
ALT2
–
–
GPI
P3_DATA.P5
–
ALT 1
–
–
ALT 2
–
–
ALT 3
–
–
GPO
P3_DATA.P5
–
ALT1
COUT62_0
CCU6
ALT2
–
–
Output
P3.3
Input
Output
P3.4
Input
Output
P3.5
Input
Output
User’s Manual
Parallel Ports, V 0.3
6-29
V 0.2, 2005-01
XC866
Parallel Ports
Table 6-12
Port 3 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
From/to Module
P3.6
Input
GPI
P3_DATA.P6
–
ALT 1
CTRAP_0
CCU6
ALT 2
–
–
ALT 3
–
–
GPO
P3_DATA.P6
–
ALT1
–
–
ALT2
RSTOUT
Internal reset
GPI
P3_DATA.P7
–
ALT 1
–
–
ALT 2
EXINT4
External interrupt 4
ALT 3
–
–
GPO
P3_DATA.P7
–
ALT1
COUT63
CCU6
ALT2
–
–
Output
P3.7
Input
Output
User’s Manual
Parallel Ports, V 0.3
6-30
V 0.2, 2005-01
XC866
Parallel Ports
6.6.2
Register Description
P3_DATA
Port 3 Data Register
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
Pn
(n = 0 – 7)
n
rw
Port 3 Pin n Data Value
0
Port 3 pin n data value = 0 (default)
1
Port 3 pin n data value = 1
P3_DIR
Port 3 Direction Register
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
User’s Manual
Parallel Ports, V 0.3
Port 3 Pin n Direction Control
0
Direction is set to input (default).
1
Direction is set to output.
6-31
V 0.2, 2005-01
XC866
Parallel Ports
P3_OD
Port 3 Open Drain Control Register
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
Port 3 Pin n Open Drain Mode
0
Normal mode; output is actively driven for 0 and
1 state (default)
1
Open drain mode; output is actively driven only
for 0 state
P3_PUDSEL
Port 3 Pull-Up/Pull-Down Select Register
Reset Value: BFH
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
User’s Manual
Parallel Ports, V 0.3
Pull-Up/Pull-Down Select Port 3 Bit n
0
Pull-down device is selected.
1
Pull-up device is selected.
6-32
V 0.2, 2005-01
XC866
Parallel Ports
P3_PUDEN
Port 3 Pull-Up/Pull-Down Enable Register
Reset Value: 40H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 – 7)
n
rw
Pull-Up/Pull-Down Enable at Port 3 Bit n
0
Pull-up or Pull-down device is disabled.
1
Pull-up or Pull-down device is enabled.
P3_ALTSELn (n = 0 – 1)
Port 3 Alternate Select Register
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Table 6-13
Function of Bits P3_ALTSEL0.Pn and P3_ALTSEL1.Pn
P3_ALTSEL0.Pn
P3_ALTSEL1.Pn
Function
0
0
Normal GPIO
1
0
Alternate Output 1
0
1
Alternate Output 2
1
1
Reserved
User’s Manual
Parallel Ports, V 0.3
6-33
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
7
Power Supply, Reset and Clock Management
The XC866 provides a range of utility features for secure system performance under
critical conditions (e.g., brownout).
The power supply to the core, memories and the peripherals is regulated by the
Embedded Voltage Regulator (EVR), with detection circuitries to ensure that the
supplied voltages are within the specified operating range. The main voltage and low
power voltage regulators in the EVR may be independently switched off to reduce power
consumption for the different power saving modes.
At the center of the XC866 clock system is the Clock Generation Unit (CGU), which
generates a master clock frequency using the Phase-Locked Loop (PLL) and oscillator
units. In-phase synchronized clock signals are derived from the master clock and
distributed throughout the system. A programmable clock divider is available for scaling
the master clock into lower frequencies for power savings.
7.1
Power Supply System with Embedded Voltage Regulator
The XC866 microcontroller requires two different levels of power supply:
• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 7-1 shows the XC866 power supply system. A power supply of 3.3 V or 5.0 V
must be provided from the external power supply pin. The 2.5 V power supply for the
logic is generated by the EVR. The EVR helps reduce the power consumption of the
whole chip and the complexity of the application board design.
CPU &
Memory
On-chip
OSC
Peripheral
logic
ADC
VDD (2.5V)
FLASH
PLL
GPIO Ports
(P0-P3)
XTAL1&
XTAL2
EVR
VDDP (3.3V/5.0V)
VSSP
Figure 7-1
XC866 Power Supply System
User’s Manual
Power, Reset and Clock, V 0.4
7-1
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
EVR Features:
•
•
•
•
•
Input voltage (VDDP): 3.3 V/5.0 V
Output voltage (VDD): 2.5 V +/-7.5%
Low power voltage regulator provided in power-down mode
VDD and VDDP prewarning detection
VDD brownout detection
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode, the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
The EVR has the VDD and VDDP detectors. There are two threshold voltage levels for
VDD detection: prewarning (2.3 V) and brownout (2.1 V). When VDD is below 2.3 V, the
VDD NMI flag NMISR.FNMIVDD is set and an NMI request to the CPU is activated if VDD
NMI is enabled (NMICON.NMIVDD). If VDD is below 2.1 V, the brownout reset will be
activated, putting the microcontroller into a reset state.
For VDDP, there is only one prewarning threshold of 4.0 V if the external power supply is
5.0 V. When VDDP is below 4.0 V, the VDDP NMI flag NMISR.FNMIVDDP is set and an
NMI request to the CPU is activated if VDDP NMI is enabled (NMICON.NMIVDDP).
If an external power supply of 3.3 V is used, the user must disable VDDP detector by
clearing bit NMICON.NMIVDDP. In power-down mode, the VDD detector is switched off
and VDDP detector will continue to function.
The EVR also has a power-on reset (POR) detector for VDD to ensure correct power up.
The voltage level detection of POR is 1.6 V. The monitoring function is used in both
active mode and power-down mode. During power up, after VDD exceeds 1.6 V, the
reset of EVR is extended by a delay that is typically 300 µs. In active mode, VDD is
monitored mainly by the VDD detector, and a reset is generated when VDD drops below
2.1 V. In power-down mode, the VDD is monitored by the POR and a reset is generated
when VDD drops below 1.6 V.
User’s Manual
Power, Reset and Clock, V 0.4
7-2
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
7.2
Reset Control
The XC866 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC866 is first powered up, the status of certain pins (see Table 7-2) must be
defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
The hardware reset function can be used during normal operation or when the chip is in
power-down mode. A reset input pin RESET is provided for the hardware reset.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
A brownout reset is triggered if the VDD supply voltage dips below 2.1 V.
7.2.1
Types of Reset
7.2.1.1
Power-On Reset
The supply voltage VDDP is used to power up the chip. The EVR is the first module in the
chip to be reset, which includes:
1. Startup of the main voltage regulator and the low power voltage regulator.
2. When VDDP and VDD reach the threshold of the VDDP and VDD detectors, the reset of
EVR becomes inactive.
When the system starts up, the PLL is disconnected from the oscillator and will run at its
base frequency. Once the EVR is stable, provided the oscillator is running, the PLL is
connected and the continuous lock detection ensures that PLL starts functioning.
Following this, as soon as the system clock is stable, each 4-Kbyte Flash bank will enter
the ready-to-read mode.
The status of pins MBC, TMS and P0.0 is latched by the reset. The latched values are
used to select the boot options (see Section 7.2.3). A correctly executed reset leaves
the system in a defined state. The program execution starts from location 0000H.
Figure 7-2 shows the power-on reset sequence.
User’s Manual
Power, Reset and Clock, V 0.4
7-3
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
EVR is stable
Typ. 300 µs
Figure 7-2
7.2.1.2
PLL is locked
Max. 200 µs
Reset is
FLASH go to
released and
Ready-to-Read
start of program
Mode
Typ. 160 µs
Power-on Reset
Hardware Reset
An external hardware reset sequence is started when the reset input pin RESET is
asserted low. The RESET pin must be held low for at least 1ms. After the RESET pin is
deasserted, the reset sequence is the same as the power-on reset sequence, as shown
in Figure 7-2. A hardware reset through RESET pin will terminate the idle mode or the
power-down mode.
The status of pins MBC, TMS and P0.0 is latched by the reset. The latched value is used
to select the boot options (see Section 7.2.3).
7.2.1.3
Watchdog Timer Reset
The watchdog timer reset is an internal reset. The Watchdog Timer (WDT) maintains a
counter that must be refreshed or cleared periodically. If the WDT is not serviced
correctly and in time, it will generate an NMI request to the CPU and then reset the
device after a predefined time-out period. Bit PMCON0.WDTRST is used to indicate the
watchdog timer reset status.
For watchdog timer reset, as the EVR is already stable and PLL lock detection is not
needed, the timing for watchdog timer reset is approximately 200 µs, which is shorter as
compared to the other types of reset.
7.2.1.4
Power-Down Wake-Up Reset
Power is still applied to the XC866 during power-down mode, as the low power voltage
regulator is still operating. If power-down mode is entered appropriately, all important
system state will have been preserved in the Flash by software.
If the XC866 is in power-down mode, three options are available to awaken it:
• through RXD
• through EXINT0
• through RXD or EXINT0
User’s Manual
Power, Reset and Clock, V 0.4
7-4
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
Selection of these options is made via the control bit PMCON0.WS. The wake-up from
power-down can be with reset or without reset; this is chosen by the PMCON0.WKSET
bit. The wake-up status (with or without reset) is indicated by the PMCON0.WKRS bit.
Figure 7-3 shows the power-down wake-up reset sequence. The EVR takes
approximately 150 µs to become stable, which is a shorter time period as compared to
the power-on reset.
EVR is stable
PLL is locked
Typ. 150 µs
Max. 200 µs
Figure 7-3
Reset is
FLASH go to
released
and
Ready-to-Read
start of program
Mode
Typ. 160 µs
Power-down Wake-up Reset
In addition to the above-mentioned three options, the power-down mode can also be
exited by the hardware reset through RESET pin.
7.2.1.5
Brownout Reset
In active mode, the VDD detector in EVR detects brownout when the core supply voltage
VDD dips below the threshold voltage VDD_TH (2.1 V). The brownout will cause the device
to be reset. In power-down mode, the VDD is monitored by the POR in EVR and a reset
is generated when VDD drops below 1.6 V.
Once the brownout reset takes place, the reset sequence is the same as the power-on
reset sequence, as shown in Figure 7-2.
User’s Manual
Power, Reset and Clock, V 0.4
7-5
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
7.2.2
Module Reset Behavior
Table 7-1 shows how the functions of the XC866 are affected by the various reset types.
A “ ” means that this function is reset to its default state.
Table 7-1
Effect of Reset on Device Functions
Module/
Function
Wake-Up
Reset
Watchdog
Reset
Hardware
Reset
Power-On
Reset
Brownout
Reset
CPU Core
Peripherals
On-Chip
Static RAM
Not affected, Not affected, Not affected, Affected, un- Affected, unreliable
reliable
reliable
reliable
reliable
Oscillator,
PLL
Not affected
Port Pins
See Chapter 6, “Parallel Ports”
EVR
The voltage Not affected
regulator is
switched on
FLASH
NMI
Disabled
7.2.3
Disabled
Booting Scheme
When the XC866 is reset, it must identify the type of configuration with which to start the
different modes once the reset sequence is complete. Thus, boot configuration
information that is required for activation of special modes and conditions needs to be
applied by the external world through input pins. After power-on reset or hardware reset,
the pins MBC, TMS and P0.0 collectively select the different boot options. Table 7-2
shows the available boot options in the XC866.
Table 7-2
XC866 Boot Selections
MBC
TMS
P0.0
Type of Mode
PC Start Value
1
x
x
User Mode; OSC/PLL non-bypassed
0000H
0
0
x
BSL Mode; OSC/PLL non-bypassed
0000H
0
1
0
OCDS Mode; OSC/PLL non-bypassed
0000H
User’s Manual
Power, Reset and Clock, V 0.4
7-6
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
7.2.4
Register Description
PMCON0
Power Mode Control Register 0
Reset Value: See Table 7-3
7
6
5
4
3
2
1
0
0
WDTRST
WKRS
WKSEL
SD
PD
WS
r
rwh
rwh
rw
rw
rwh
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
WS
[1:0]
rw
Wake-Up Source Select
00
No wake-up is selected.
01
Wake-up source RXD is selected.
10
Wake-up source EXINT0 is selected.
11
Wake-up source RXD or EXINT0 is selected.
WKSEL
4
rw
Wake-Up Reset Select Bit
0
Wake-up without reset
1
Wake-up with reset
WKRS
5
rwh
Wake-Up Indication Bit
0
No wake-up occurred.
1
Wake-up has occurred.
This bit can only be set by hardware and reset by
software.
WDTRST
6
rwh
Watchdog Timer Reset Indication Bit
0
No watchdog timer reset occurred.
1
Watchdog timer reset has occurred.
This bit can only be set by hardware and reset by
software.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Power, Reset and Clock, V 0.4
7-7
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
Table 7-3
Reset Values of Register PMCON0
Reset Source
Reset Value
Power-on Reset/Hardware Reset/Brownout Reset
0000 0000B
Watchdog Timer Reset
0100 0000B
Power-down Wake-up Reset
0010 0000B
User’s Manual
Power, Reset and Clock, V 0.4
7-8
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
7.3
Clock System
The XC866 clock system performs the following functions:
• Acquires and buffers incoming clock signals to create a master clock frequency
• Distributes in-phase synchronized clock signals throughout the system
• Divides a system master clock frequency into lower frequencies for power saving
mode
7.3.1
Clock Generation Unit
The Clock Generation Unit (CGU) in the XC866 consists of an oscillator circuit and a
Phase-Locked Loop (PLL). In the XC866, the oscillator can be from either of these two
sources: the on-chip oscillator (10 MHz) or the external oscillator (3 MHz to 12 MHz).
The term “oscillator” is used to refer to both on-chip oscillator and external oscillator,
unless otherwise stated. After the reset, the on-chip oscillator will be used by default. The
external oscillator can be selected via software. The PLL can convert a low-frequency
external clock signal from the oscillator circuit to a high-speed internal clock for
maximum performance.
Figure 7-4 shows the block diagram of CGU.
OSC
fosc
P:1
fp
fn
osc fail
detect
OSCR
lock
detect
LOCK
PLL
core
N:1
OSCDISC
Figure 7-4
fsys
K:1
fvco
PLLBYP
VCOBYP
NDIV
CGU Block Diagram
User’s Manual
Power, Reset and Clock, V 0.4
7-9
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
7.3.1.1
Functional Description
When the XC866 is powered up, the PLL is disconnected from the oscillator and will run
at its VCO base frequency. After the EVR is stable, provided the oscillator is running, the
PLL will be connected and the continuous lock detection will ensure that the PLL starts
functioning. Once reset has been released, bit OSCR will be set to 1 if the oscillator is
running and bit LOCK will be set to 1 if the PLL is locked.
Loss-of-Lock Operation
If the PLL is not the system’s clock source (VCOBYP = 1) when the loss of lock is
detected, only the lock flag is reset (PLL_CON.LOCK = 0) and no further action is taken.
This allows the PLL parameters to be switched dynamically.
If PLL loses its lock to the oscillator, the PLL Loss-of-Lock NMI flag NMISR.FNMIPLL is
set and an NMI request to the CPU is activated if PLL NMI is enabled
(NMICON.NMIPLL). In addition, the LOCK flag in PLL_CON is reset. PLL VCO gradually
slows down to its base frequency. Emergency routines can be executed with the XC866
clocked with this base frequency.
The XC866 remains in this loss-of-lock state until the next power-on reset, hardware
reset or after a successful lock recovery has been performed.
Loss-of-Lock Recovery
If PLL has lost its lock to the oscillator, the PLL can be re-locked by software. The
following sequence must be performed:
1. Disconnect the oscillator from the PLL (OSCDISC = 1).
2. Set the N-divider of the PLL to the value 16 (PLL_CON.NDIV = 0010B).
3. Wait for 50 µs until the oscillator is stable.
4. Restart the Oscillator Run Detection by setting bit OSC_CON.ORDRES.
If bit OSC_CON.OSCR is set, then:
1. Select the VCO bypass mode (VCOBYP = 1).
2. Reconnect oscillator to the PLL (OSCDISC = 0).
3. Reprogram the NDIV factor to the original value.
4. The RESLD bit must be set and the LOCK flag checked. Only if the LOCK flag is set
again can the VCO bypass mode be deselected and normal operation resumed.
If neither OSCR nor LOCK is set, emergency measures must be executed. Emergency
measures such as a system shut down can be carried out by the user.
User’s Manual
Power, Reset and Clock, V 0.4
7-10
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
Changing PLL Parameters
To change the PLL parameters,
(OSC_CON.OSCR = 1). In this case:
first
check
if
the
oscillator
is
running
1. Select VCO bypass mode (VCOBYP = 1).
2. Connect oscillator to PLL (OSCDISC = 0).
3. Program desired NDIV value.
4. Wait till the LOCK bit has been set.
5. Disable VCO bypass mode.
Select the External Oscillator
To select the external oscillator, the following sequence must be performed:
1. Select the VCO bypass mode (VCOBYP = 1).
2. Disconnect the oscillator from the PLL (OSCDISC = 1).
3. External OSC is powered up by resetting bit XPD.
4. The source of external oscillator is selected by setting bit OSCSS.
5. Wait for 50 µs until the external oscillator is stable.
6. Restart the Oscillator Run Detection by setting bit OSC_CON.ORDRES.
If bit OSC_CON.OSCR is set, then:
1. Select the VCO bypass mode (VCOBYP = 1).
2. Reconnect oscillator to the PLL (OSCDISC = 0).
3. Reprogram the NDIV factor to the required value.
4. The RESLD bit must be set and the LOCK flag checked. Only if the LOCK flag is set
again, can the VCO bypass mode be deselected and normal operation resumed.
In order to minimize power consumption while the on-chip oscillator is used, XTAL is
powered down by setting bit XPD, but when the external oscillator is used, the on-chip
oscillator cannot be powered down by setting bit OSCPD.
7.3.2
Clock Source Control
The clock system provides four ways to generate CPU clock:
Direct Drive (PLL Bypass Operation)
In PLL bypass operation, the system clock has exactly the same frequency as the
external clock source. The PLL bypass is set inactive in the XC866.
f SYS = f OSC
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Power, Reset and Clock, V 0.4
7-11
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
PLL Base Mode
The system clock is derived from the VCO base frequency clock divided by the K factor.
Both VCO bypass and PLL bypass must be inactive for this PLL mode.
1
f SYS = f VCObase × ---K
Prescaler Mode (VCO Bypass Operation)
In VCO bypass operation, the system clock is derived from the oscillator clock, divided
by the P and K factors.
1
f SYS = f OSC × ------------P×K
PLL Mode
The system clock is derived from the oscillator clock, divided by the P factor, multiplied
by the N factor, and divided by the K factor. Both VCO bypass and PLL bypass must be
inactive for this PLL mode.
N
f SYS = f OSC × ------------P×K
In normal running mode, the system works in the PLL mode.
For different source oscillator, the selection of typical output frequency fsys = 80 MHz is
shown in Table 7-4.
Table 7-4
System frequency (fsys = 80 MHz)
Oscillator
fosc
N
P
K
fsys
On-chip
10 MHz
16
1
2
80 MHz
External
10 MHz
16
1
2
80 MHz
8 MHz
20
1
2
80 MHz
5 MHz
32
1
2
80 MHz
For the XC866, the values of P and K are fixed to “1” and “2”, respectively. In order to
obtain the required fsys, the value of N can be selected by bit NDIV for different oscillator
inputs. See Table 7-4. The output frequency needs to be within the range 75 MHz to
80 MHz.
User’s Manual
Power, Reset and Clock, V 0.4
7-12
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
Table 7-5 shows the VCO range in the XC866.
Table 7-5
VCO Ranges
fVCOmin
fVCOmax
fVCOFREEmin
fVCOFREEmax
Unit
150
200
40
130
MHz
7.3.3
Clock Management
The Clock Management sub-module generates all clock signals required within the
microcontroller from the basic clock. It consists of:
• Basic clock slow down circuitry
• Centralized enable/disable circuit for clock control
Figure 7-5 shows the clock generation from the system frequency fsys. In normal running
mode, the typical frequencies of different modules are as follows:
•
•
•
•
CPU clock: CCLK, SCLK = 26.7 MHz
CCU6 clock: FCLK = 26.7 MHz
Other peripherals: PCLK = 26.7 MHz
Flash Interface clock: CCLK3 = 80 MHz and CCLK = 26.7 MHz
Furthermore, the oscillator clock outputs to pin CLKOUT(P0.0). In idle mode, only the
CPU clock CCLK is disabled. In power-down mode, CCLK, SCLK, FCLK, CCLK3 and
PCLK are all disabled. If slow-down mode is enabled, the clock to the core and
peripherals will be divided by a programmable factor that is selected by the bit field
CMCON.CLKREL.
CLKREL
FCLK
OSC
fosc
PLL
PCLK
fsys=80MHz
/3
Figure 7-5
N,P,K
Peripherals
SCLK
CCLK
CLKOUT
CCU6
CCLK3
CORE
FLASH
Interface
Clock Generation from fsys
User’s Manual
Power, Reset and Clock, V 0.4
7-13
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
7.3.4
Register Description
OSC_CON
OSC Control Register
7
6
Reset Value: 0000 1000B
5
4
3
2
1
0
0
OSCPD
XPD
OSCSS
ORDRES
OSCR
r
rw
rw
rw
rwh
rh
Field
Bits
Type Description
OSCR
0
rh
Oscillator Run Status Bit
This bit shows the state of the oscillator run
detection.
0
The oscillator is not running.
1
The oscillator is running.
ORDRES
1
rwh
Oscillator Run Detection Reset
0
No operation
1
The oscillator run detection logic is reset and
restarted.
This bit will automatically be reset to 0.
OSCSS
2
rw
Oscillator Source Select
0 On-chip oscillator is selected.
1 External oscillator is selected.
XPD
3
rw
XTAL Power-down Control
0
XTAL is not powered down.
1
XTAL is powered down.
OSCPD
4
rw
On-chip OSC Power-down Control
0
The on-chip oscillator is not powered down.
1
The on-chip oscillator is powered down.
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
0
Note: The reset value of register OSC_CON is 0000 1000B. One clock cycle after reset,
bit OSCR will be set to 1 if the oscillator is running, then the value 0000 1001B will
be observed.
User’s Manual
Power, Reset and Clock, V 0.4
7-14
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
PLL_CON
PLL Control Register
7
6
Reset Value: 0010 0000B
5
4
3
2
1
0
NDIV
VCOBYP
OSCDISC
RESLD
LOCK
rw
rw
rw
rwh
rh
Field
Bits
Type Description
LOCK
0
rh
PLL Lock Status Flag
0
PLL is not locked.
1
PLL is locked.
RESLD
1
rwh
Restart Lock Detection
Setting this bit will reset the PLL lock status flag and
restart the lock detection. This bit will automatically
be reset to 0 and thus always be read back as 0.
0
No effect
1
Reset lock flag and restart lock detection
OSCDISC
2
rw
Oscillator Disconnect
0
Oscillator is connected to the PLL.
1
Oscillator is disconnected from the PLL.
VCOBYP
3
rw
PLL VCO Bypass Mode Select
0
Normal operation (default)
1
VCO bypass mode (PLL output clock is
derived from input clock divided by P- and
K-dividers).
User’s Manual
Power, Reset and Clock, V 0.4
7-15
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
Field
Bits
Type Description
NDIV
[7:4]
rw
PLL N-Divider
0000B N = 14
0001B N = 15
0010B N = 16
0011B N = 17
0100B N = 18
0101B N = 19
0110B N = 20
0111B N = 21
1000B N = 24
1001B N = 28
1010B N = 30
1011B N = 32
1100B N = 40
1101B N = 42
1110B N = 45
1111B N = 50
The NDIV bit is a protected bit. When the Protection
Scheme (see Chapter 3.3.4.1) is activated, this bit
cannot be written directly.
Note: The reset value of register PLL_CON is 0010 0000B. One clock cycle after reset,
bit LOCK will be set to 1 if the PLL is locked, then the value 0010 0001B will be
observed.
User’s Manual
Power, Reset and Clock, V 0.4
7-16
V 0.2, 2005-01
XC866
Power Supply, Reset and Clock Management
CMCON
Clock Control Register
7
6
Reset Value: 00H
5
4
3
2
1
0
CLKREL
r
rw
0
Field
Bits
Type Description
CLKREL
[3:0]
rw
Clock Divider
0000B fsys/1
0001B fsys/2
0010B fsys/4
0011B fsys/8
0100B fsys/16
0101B fsys/32
0110B fsys/64
0111B fsys/128
1000B fsys/256
1001B fsys/512
1010B fsys/1024
1011B fsys/2048
1100B Reserved
1101B Reserved
1110B Reserved
1111B Reserved
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
0
Note: Registers OSC_CON, PLL_CON and CMCON are not reset during the watchdog
timer reset.
User’s Manual
Power, Reset and Clock, V 0.4
7-17
V 0.2, 2005-01
XC866
Power Saving Modes
8
Power Saving Modes
The power saving modes in the XC866 provide flexible power consumption through a
combination of techniques, including:
•
•
•
•
Stopping the CPU clock
Stopping the clocks of individual system components
Reducing clock speed of some peripheral components
Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 8-1) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode
ACTIVE
any interrupt
& SD=0
set PD
bit
set IDLE
bit
set SD
bit
IDLE
EXINT0/RXD pin
& SD=0
clear SD
bit
set IDLE
bit
any interrupt
& SD=1
Figure 8-1
User’s Manual
SCU, V 0.4
POWER-DOWN
set PD
bit
SLOW-DOWN
EXINT0/RXD pin
& SD=1
Transition between Power Saving Modes
8-1
V 0.2, 2005-01
XC866
Power Saving Modes
8.1
Functional Description
This section describes the various power saving modes, their operations, and how they
are entered and exited.
8.1.1
Idle Mode
The idle mode is used to reduce power consumption by stopping the core’s clock.
In idle mode, the oscillator continues to run, but the core is stopped with its clock
disabled. Peripherals whose input clocks are not disabled are still functional. The user
should disable the Watchdog Timer (WDT) before the system enters the idle mode;
otherwise, it will generate an internal reset when an overflow occurs and thus will disrupt
the idle mode. The CPU status is preserved in its entirety: the stack pointer, program
counter, program status word, accumulator, and all other registers maintain their data
during idle mode. The port pins hold the logical state they had at the time the idle mode
was activated.
Software requests idle mode by setting the bit PCON.IDLE to 1.
The system will return to active mode on occurrence of any of the following conditions:
• The idle mode can be terminated by activating any enabled interrupt. The CPU
operation is resumed and the interrupt will be serviced. Upon RETI instruction, the
core will return to execute the next instruction after the instruction which sets the IDLE
bit to 1.
• An external hard reset signal (RESET) is asserted.
8.1.2
Slow-Down Mode
The slow-down mode is used to reduce power consumption by decreasing the internal
clock in the device.
The slow-down mode is activated by setting the bit SD in SFR PMCON0. The bit field
CMCON.CLKREL is used to select different slow-down frequency. The CPU and
peripherals are clocked at this lower frequency. The slow-down mode is terminated by
clearing bit SD.
The slow-down mode can be combined with the idle mode by performing the following
sequence:
1. The slow-down mode is activated by setting the bit PMCON0.SD.
2. The idle mode is activated by setting the bit PCON.IDLE.
There are two ways to terminate the combined idle and slow-down modes:
• The idle mode can be terminated by activation of any enabled interrupt. CPU
operation is resumed, and the interrupt will be serviced. The next instruction to be
executed after the RETI instruction will be the one following the instruction that had
set the bit IDLE. Nevertheless, the slow-down mode stays enabled and if required
User’s Manual
SCU, V 0.4
8-2
V 0.2, 2005-01
XC866
Power Saving Modes
termination must be done by clearing the bit SD in the corresponding interrupt service
routine or at any point in the program where the user no longer requires the slow-down
mode.
• The other way of terminating the combined idle and slow-down mode is through a
hardware reset.
8.1.3
Power-down Mode
In power-down mode, the oscillator and the PLL are turned off. The FLASH is put into
the power-down mode. The main voltage regulator is switched off, but the low power
voltage regulator continues to operate. Therefore, all functions of the microcontroller are
stopped and only the contents of the FLASH, on-chip RAM, XRAM and the SFRs are
maintained. The port pins hold the logical state they had when the power-down mode
was activated. For the digital ports, the user must take care from external side that the
ports are not floating in power-down mode. This can be done with external pull-up/pulldown or putting the port to output.
In power-down mode, the clock is turned off. Hence, it cannot be awakened by an
interrupt or by the WDT. It will be awakened only when it receives an external wake-up
signal or reset signal.
Entering Power-down Mode
Software requests power-down mode by setting the bit PMCON0.PD to 1.
If the external wake-up from power-down is used, software must prepare the external
environment of the XC866 to trigger one of these signals under the appropriate
conditions before entering power-down mode. A wake-up circuit is used to detect a
wake-up signal and activate the power-up. During power-down, this circuit remains
active. It does not depend on any clocks. Exit from power-down mode can be achieved
by applying a falling edge trigger into the:
• EXINT0 pin
• RXD pin
• RXD pin or EXINT0 pin
The wake-up source can be selected by the WS bit of the PMCON0 register. The
wake-up with reset or without reset is selected by bit PMCON0.WKSET. The wake-up
source and wake-up type must be selected before the system enters the power-down
mode.
Exiting Power-down Mode
If power-down mode is exited via a hardware reset, the device is put into the hardware
reset state.
When the wake-up source and wake-up type have been selected prior to entering
power-down mode, the power-down mode can be exited via EXINT0 pin/RXD pin.
User’s Manual
SCU, V 0.4
8-3
V 0.2, 2005-01
XC866
Power Saving Modes
Bit MODPISEL.URRIS is used to select one of the two RXD inputs and bit
MODPISEL.EXINT0IS is used to select one of the two EXINT0 inputs.
If bit WKSEL was set to 1 before entering power-down mode, the system will execute a
reset sequence similar to the power-on reset sequence. Therefore, all port pins are put
into their reset state and will remain in this state until they are affected by program
execution.
If bit WKSEL was cleared to 0 before entering power-down mode, a fast wake-up
sequence is used. The port pins continue to hold their state which was valid during
power-down mode until they are affected by program execution.
The wake-up from power-down without reset uses the following procedures:
1. In power-down mode, EXINT0 pin/RXD pin must be held at high level.
2. Power-down mode is exited when EXINT0 pin/RXD pin goes low for at least 100 ns.
3. The main voltage regulator is switched on and takes approximately 150 µs to become
stable.
4. The on-chip oscillator and the PLL are started. Typically, the on-chip oscillator takes
approximately 500 ns to stabilize. The PLL will be locked within 200 µs after the onchip oscillator clock is detected for stable nominal frequency.
5. Subsequently, the FLASH will enter ready-to-read mode. This does not require the
typical 160 µs as is the case for the normal reset. The timing for this part can be
ignored.
6. The CPU operation is resumed. If wake-up source is EXINT0 pin, the interrupt will be
serviced if EXINT0 is enabled before entering power-down mode. Upon RETI
instruction, the core will return to execute the next instruction after the instruction
which sets the PD bit. If wake-up source is RXD pin, the core will return to execute the
next instruction after the instruction which sets the PD bit.
8.1.4
Peripheral Clock Management
The degree of reduction in power consumption that can be achieved by this feature
depends on the number of peripherals running. Peripherals that are not required for a
particular functionality can be disabled by gating off the clock inputs. For example, in idle
mode, if all timers are stopped, and ADC, CCU6 and the serial interfaces are not running,
maximum power reduction can be achieved. However, the user must take care in
determining which peripherals should continue running and which must be stopped
during active and idle modes.
The ADC, SSC, CCU6 and Timer 2 can be disabled (clock is gated off) by setting the
corresponding bit in the PMCON1 register. Furthermore, the analog part of the ADC
module may be disabled by resetting the GLOBCTR.ANON bit. This feature causes the
generation of fADCI to be stopped and allows a reduction in power consumption when no
conversion is needed.
User’s Manual
SCU, V 0.4
8-4
V 0.2, 2005-01
XC866
Power Saving Modes
In order to save power consumption when the on-chip oscillator is used, XTAL should be
powered down by setting bit OSC_CON.XPD. However, when the external oscillator is
used, the on-chip oscillator cannot be powered down by setting bit OSC_CON.OSCPD.
User’s Manual
SCU, V 0.4
8-5
V 0.2, 2005-01
XC866
Power Saving Modes
8.2
Register Description
PMCON0
Power Mode Control Register 0
Reset Value: See Table 8-1
7
6
5
4
3
2
1
0
0
WDTRST
WKRS
WKSEL
SD
PD
WS
r
rwh
rwh
rw
rw
rwh
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
WS
[1:0]
rw
Wake-up Source Select
00
No wake-up is selected.
01
Wake-up source RXD is selected.
10
Wake-up source EXINT0 is selected.
11
Wake-up source RXD or EXINT0 is selected.
PD
2
rwh
Power-down Enable. Active High.
Setting this bit will cause the chip to enter
power-down mode. It is reset by wake-up circuit.
The PD bit is a protected bit. When the Protection
Scheme (see Chapter 3.3.4.1) is activated, this bit
cannot be written directly.
SD
3
rw
Slow-down Enable. Active High.
Setting this bit will cause the chip to enter slow-down
mode. It is reset by the user.
The SD bit is a protected bit. When the Protection
Scheme is activated, this bit cannot be written
directly.
WKSEL
4
rw
Wake-up Reset Select Bit
0
Wake-up without reset
1
Wake-up with reset
WKRS
5
rwh
Wake-up Indication Bit
0
No wake-up occurred.
1
Wake-up has occurred.
This bit can only be set by hardware and reset by
software.
User’s Manual
SCU, V 0.4
8-6
V 0.2, 2005-01
XC866
Power Saving Modes
Field
0
Table 8-1
Bits
Type Description
7
r
Reserved
Returns 0 if read; should be written with 0.
Reset Values of Register PMCON0
Reset Source
Reset Values
Power-on Reset/Hardware Reset/Brownout Reset 0000 0000B
Watchdog Timer Reset
0100 0000B
Power-down Wake-up Reset
0010 0000B
PCON
Power Control Register
7
6
Reset Value: 00H
5
4
3
2
1
0
SMOD
0
GF1
GF0
0
IDLE
rw
r
rw
rw
r
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
IDLE
0
rw
User’s Manual
SCU, V 0.4
Idle Mode Enable
0
Do not enter idle mode
1
Enter idle mode
8-7
V 0.2, 2005-01
XC866
Power Saving Modes
MODPISEL
Peripheral Input Select Register
7
6
5
Reset Value: 00H
4
3
JTAGTDIS JTAGTCK
S
0
r
rw
rw
2
1
0
0
EXINT0IS
URRIS
r
rw
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
URRIS
0
rw
UART Receive Input Select
0
UART Receiver Input RXD_0 is selected.
1
UART Receiver Input RXD_1 is selected.
EXINT0IS
1
rw
External Interrupt 0 Input Select
0
External Interrupt Input EXINT0_0 is selected.
1
External Interrupt Input EXINT0_1 is selected.
0
[3:2], r
[7:6]
Reserved
Returns 0 if read; should be written with 0.
PMCON1
Power Mode Control Register 1
7
6
5
Reset Value: 00H
4
3
2
1
0
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
r
rw
rw
rw
rw
Field
Bits
Type Description
ADC_DIS
0
rw
ADC Disable Request. Active high.
0
ADC is in normal operation (default).
1
ADC is disabled.
SSC_DIS
1
rw
SSC Disable Request. Active high.
0
SSC is in normal operation (default).
1
SSC is disabled.
User’s Manual
SCU, V 0.4
8-8
V 0.2, 2005-01
XC866
Power Saving Modes
Field
Bits
Type Description
CCU_DIS
2
rw
CCU6 Disable Request. Active High.
0
CCU6 is in normal operation (default).
1
CCU6 is disabled.
T2_DIS
3
rw
Timer 2 Disable Request. Active High.
0
Timer 2 is in normal operation (default).
1
Timer 2 is disabled.
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
ADC_GLOBCTR
Global Control Register
Reset Value: 00H
7
6
5
4
3
2
1
ANON
DW
CTC
0
rw
rw
rw
r
0
The functions of the shaded bits are not described here
Field
Bits
Type Description
ANON
7
rw
Analog Part Switched On
This bit enables the analog part of the ADC module
and defines its operation mode.
0
The analog part is switched off and
conversions are not possible.
To achieve minimal power consumption, the
internal analog circuitry is in its power-down
state and the generation of fADCI is stopped.
1
The analog part of the ADC module is
switched on and conversions are possible.
The automatic power-down capability of the
analog part is disabled.
0
[3:0]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
SCU, V 0.4
8-9
V 0.2, 2005-01
XC866
Power Saving Modes
OSC_CON
OSC Control Register
7
6
Reset Value: 0000 1000B
5
4
3
2
1
0
0
OSCPD
XPD
OSCSS
ORDRES
OSCR
r
rw
rw
rw
rwh
rh
The functions of the shaded bits are not described here
Field
Bits
Type Description
XPD
3
rw
XTAL Power-down Control
0
XTAL is not powered down.
1
XTAL is powered down.
OSCPD
4
rw
On-chip OSC Power-down Control
0
The on-chip oscillator is not powered down.
1
The on-chip oscillator is powered down.
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
0
User’s Manual
SCU, V 0.4
8-10
V 0.2, 2005-01
XC866
Watchdog Timer
9
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this time interval to
prevent the WDT from causing an XC866 system reset. Hence, routine service of the
WDT confirms that the system is functioning properly. This ensures that an accidental
malfunction of the XC866 will be aborted in a user-specified time period.
Features:
•
•
•
•
16-bit Watchdog Timer
Programmable reload value for upper 8 bits of timer
Programmable window boundary
Selectable input frequency of fPCLK/2 or fPCLK/128
User’s Manual
Watchdog Timer, V 0.4
9-1
V 0.2, 2005-01
XC866
Watchdog Timer
9.1
Functional Description
The Watchdog Timer (WDT) is a 16-bit timer, which is incremented by a count rate of
fPCLK/2 or fPCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The
upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog
service access in order to modify the watchdog expire time period. The lower 8 bits are
reset on each service access. Figure 9-1 shows the block diagram of the WDT unit.
WDT
Control
Clear
1:2
MUX
f PCLK
WDTREL
WDT Low Byte
WDT High Byte
1:128
Overflow/Time-out Control &
Window-boundary control
WDTIN
ENWDT
WDTTO
WDTRST
Logic
ENWDT_P
Figure 9-1
WDTWINB
WDT Block Diagram
If the WDT is enabled by setting bit WDTEN to 1, the timer is set to a user-defined start
value and begins counting up. It must be serviced before the counter overflows.
Servicing is performed through the refresh operation (setting WDTRS to 1). This reloads
the timer with the start value, and normal operation continues.
If the WDT is not serviced before the timer overflows, a system malfunction is assumed
and normal mode is terminated. A WDT NMI request (WDTTO) is then asserted and
prewarning is entered. The prewarning lasts for 30H count. During the prewarning
period, refreshing of the WDT is ignored and the WDT cannot be disabled. A reset
(WDTRST) of the XC866 is imminent and can no longer be stopped. The occurrence of
a WDT reset is indicated by the bit WDTRST, which is set to 1 once hardware detects
the assertion of the signal WDTRST. If refresh happens at the same time an overflow
occurs, WDT will not go into prewarning period.
The WDT must be serviced periodically so that its count value will not overflow. Servicing
the WDT clears the low byte and reloads the high byte with the preset value in bit field
WDTREL. Servicing the WDT also clears the bit WDTRS.
The WDT has a “programmable window boundary”, which disallows any refresh during
the WDT’s count-up. A refresh during this window-boundary constitutes an invalid
User’s Manual
Watchdog Timer, V 0.4
9-2
V 0.2, 2005-01
XC866
Watchdog Timer
access to the WDT and causes the WDT to activate WDTRST, although no NMI request
is generated in this instance. The window boundary is from 0000H to the value obtained
from the concatenation of WDTWINB and 00H. This feature can be enabled by WINBEN.
After being serviced, the WDT continues counting up from the value (<WDTREL> * 28).
The time period for an overflow of the WDT is programmable in two ways:
• the input frequency to the WDT can be selected via bit WDTIN in register WDTCON
to be either fPCLK/2 or fPCLK/128.
• the reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL.
The period PWDT between servicing the WDT and the next overflow can be determined
by the following formula:
( 1 + WDTIN × 6 ) × ( 2 16 – WDTREL × 2 8 )
----------------------------------------------------------------------------------------------------P WDT = 2
f PCLK
If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL. See also Figure 9-2. This period can be calculated by the same formula
by replacing WDTREL with WDTWINB. In order for this feature to be useful, WDTWINB
cannot be smaller than WDTREL.
Count
FFFF H
WDTWINB
WDTREL
time
No refresh
allowed
Figure 9-2
Refresh allowed
WDT Timing Diagram
User’s Manual
Watchdog Timer, V 0.4
9-3
V 0.2, 2005-01
XC866
Watchdog Timer
Table 9-1 lists the possible ranges for the watchdog time which can be achieved using
a certain module clock. Some numbers are rounded to 3 significant digits.
Table 9-1
Watchdog Time Ranges
Reload value
in WDTREL
Prescaler for fPCLK
2 (WDTIN = 0)
128 (WDTIN = 1)
20 MHz
16 MHz
12 MHz
20 MHz
16 MHz
12 MHz
FFH
25.6 µs
32.0 µs 42.67 µs
1.64 ms
2.05 ms
2.73 ms
7FH
3.3 ms
4.13 ms
5.5 ms
211 ms
264 ms
352 ms
00H
6.55 ms
8.19 ms 10.92 ms
419 ms
524 ms
699 ms
Note: For safety reasons, the user is advised to rewrite WDTCON each time before the
WDT is serviced.
User’s Manual
Watchdog Timer, V 0.4
9-4
V 0.2, 2005-01
XC866
Watchdog Timer
9.2
Register Map
The WDT SFRs are located in the mapped SFR area. Table 9-2 lists the addresses of
these SFRs.
Table 9-2
SFR Address list
Address
Name
BBH
WDTCON
BCH
WDTREL
BDH
WDTWINB
BEH
WDTL
BFH
WDTH
9.3
Register Description
The current count value of the WDT is contained in the Watchdog Timer Register WDT,
which is a non-bitaddressable read-only register. The operation of the WDT is controlled
by its bitaddressable WDT Control Register WDTCON. This register also selects the
input clock prescaling factor. The register WDTREL specifies the reload value for the
high byte of the timer.
WDTREL
Watchdog Timer Reload Register
7
6
5
Reset Value: 00H
4
3
2
1
0
WDTREL
rw
Field
Bits
Type Description
WDTREL
[7:0]
rw
User’s Manual
Watchdog Timer, V 0.4
Watchdog Timer Reload Value (for the high byte of
WDT)
A new reload value can be written to WDTREL and
this value is loaded to the upper 8 bits of the WDT
upon the enabling of the timer or the next service for
refresh.
9-5
V 0.2, 2005-01
XC866
Watchdog Timer
WDTCON
Watchdog Timer Control Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
WINBEN
WDTPR
0
WDTEN
WDTRS
WDTIN
r
rw
rh
r
rw
rwh
rw
Field
Bits
Type Description
WDTIN
0
rw
Watchdog Timer Input Frequency Selection
0
Input frequency is fWDT/2.
1
Input frequency is fWDT/128.
WDTRS
1
rwh
WDT Refresh Start
Active high. Set to start refresh operation on the
WDT. Cleared automatically by hardware.
WDTEN
2
rw
WDT Enable
0
WDT is disabled.
1
WDT is enabled.
WDTEN is a protected bit. If the Protection Scheme
(see Chapter 3.3.4.1) is activated, then this bit
cannot be written directly.
WDTPR
4
rh
Watchdog Prewarning Mode Flag
0
Normal mode (default after reset)
1
The Watchdog is operating in prewarning
mode.
This bit is set to 1 when a Watchdog error is
detected. The WDT has issued an NMI trap and is in
prewarning mode. A reset of the chip occurs after the
prewarning period has expired.
WINBEN
5
rw
Watchdog Window-Boundary Enable
0
Watchdog Window-Boundary feature is
disabled (default).
1
Watchdog Window-Boundary feature is
enabled.
0
3,
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Watchdog Timer, V 0.4
9-6
V 0.2, 2005-01
XC866
Watchdog Timer
WDTL
Watchdog Timer Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
WDT
rh
WDTH
Watchdog Timer Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
WDT
rh
Field
Bits
Type Description
WDT
[7:0] of
WDTL,
[7:0] of
WDTH
rh
Watchdog Timer Current Value
WDTWINB
Watchdog Window-Boundary Count
7
6
5
Reset Value: 00H
4
3
2
1
0
WDTWINB
rw
Field
Bits
Type Description
WDTWINB
[7:0]
rw
User’s Manual
Watchdog Timer, V 0.4
Watchdog Window-Boundary Count Value
This value is programmable. The WDT cannot do a
refresh within the Window Boundary range from
0000H to the value obtained from the concatenation
of WDTWINB and 00H, as it would cause WDTRST
to be asserted.
WDTWINB is matched to WDTH.
9-7
V 0.2, 2005-01
XC866
Watchdog Timer
PMCON0
Power Mode Control Register 0
Reset Value: See Table 8-1
7
6
5
4
3
2
1
0
0
WDTRST
WKRS
WKSEL
SD
PD
WS
r
rwh
rwh
rw
rw
rwh
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
WDTRST
6
rwh
Watchdog Timer Reset Indication Bit
0
No WDT reset has occurred.
1
WDT reset has occurred.
7
r
Reserved
Returns 0 if read; should be written with 0.
0
User’s Manual
Watchdog Timer, V 0.4
9-8
V 0.2, 2005-01
XC866
Serial Interfaces
10
Serial Interfaces
The XC866 contains two serial interfaces, the Universal Asynchronous Receiver/
Transmitter (UART) and the High-Speed Synchronous Serial Interface (SSC), for serial
communication with external devices. Additionally, the UART can be used to support the
Local Interconnect Network (LIN) protocol.
UART Features:
• Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception
LIN Features:
• Master and slave mode operation
SSC Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Transmit and receive buffered
• Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Variable baud rate
• Compatible with Serial Peripheral Interface (SPI)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
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10.1
UART
The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit
and receive simultaneously. It is also receive-buffered, i.e., it can commence reception
of a second byte before a previously received byte has been read from the receive
register. However, if the first byte still has not been read by the time reception of the
second byte is complete, one of the bytes will be lost.
10.1.1
UART Modes
The UART can be used in three asynchronous modes. In mode 1, it operates as an 8-bit
serial port, and in modes 2 and 3, it operates as a 9-bit serial port. The only difference
between mode 2 and mode 3 is the baud rate, which is fixed in mode 2 but variable in
mode 3. The variable baud rate is derived from the dedicated baud-rate generator.
The different modes are selected by setting bits SM0 and SM1 to their corresponding
values, as shown in Table 10-1. The selection where the value of both SM0 and SM1 is
zero, is reserved.
Table 10-1
UART Modes
SM0
SM1
Operating Mode
Baud Rate
0
0
Reserved
–
0
1
Mode 1: 8-bit shift UART
Variable
1
0
Mode 2: 9-bit shift UART
fPCLK/32 or fPCLK/64
1
1
Mode 3: 9-bit shift UART
Variable
10.1.1.1 Mode 1, 8-Bit UART, Variable Baud Rate
In mode 1, the UART behaves as an 8-bit serial port. A start bit (0), 8 data bits, and a
stop bit (1) are transmitted on TXD or received on RXD at the baud rate set by the
underflow rate on the dedicated baud-rate generator. This baud rate is variable.
The transmission cycle is activated by a write to SBUF. The data is transferred to the
transmit register and a 1 is loaded to the 9th bit position. At phase 1 of the machine cycle
after the next rollover in the divide-by-16 counter, the start bit is copied to TXD, and data
is activated one bit time later. One bit time after the data is activated, the data starts
getting shifted right with zeros shifted in from the left. When the MSB gets to the output
position, the control block executes one last shift and sets the TI bit.
Reception is started by a high to low transition on RXD (sampled at 16 times the baud
rate). The divide-by-16 counter is then reset and 1111 1111B is written to the receive
register. If a valid start bit (0) is then detected (based on two out of three samples), it is
shifted into the register followed by 8 data bits. If the transition is not followed by a valid
start bit, the controller goes back to looking for a high to low transition on RXD. When the
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start bit reaches the leftmost position, the control block executes one last shift, then
loads SBUF with the 8 data bits, loads RB8 (SCON.2) with the stop bit, and sets the
RI bit, provided RI = 0, and either SM2 = 0 (see Section 10.1.2) or the received stop
bit = 1. If none of these conditions is met, the received byte is lost.
The associated timings for transmit/receive in mode 1 are illustrated in Figure 10-1.
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Serial Interfaces
TI
TXD
Shift
Data
TX
Clock
RI
Shift
Bit Detector
Sample Times
RXD
RX
Clock
Start Bit
D0
reset
Start Bit
D1
D0
D2
D1
D3
D2
D4
D3
D5
D4
D6
D5
D7
D6
Stop Bit
D7
Stop Bit
Transmit
Receive
Figure 10-1 Serial Interface, Mode 1, Timing Diagram
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10.1.1.2 Mode 2, 9-Bit UART, Fixed Baud Rate
In mode 2, the UART behaves as a 9-bit serial port. A start bit (0), 8 data bits plus a
programmable 9th bit and a stop bit (1) are transmitted on TXD or received on RXD. The
9th bit for transmission is taken from TB8 (SCON.3) while for reception, the 9th bit
received is placed in RB8 (SCON.2).
The transmission cycle is activated by a write to SBUF. The data is transferred to the
transmit register and TB8 is copied into the 9th bit position. At phase 1 of the machine
cycle following the next rollover in the divide-by-16 counter, the start bit is copied to TXD
and data is activated one bit time later. One bit time after the data is activated, the data
starts shifting right. For the first shift, a stop bit (1) is shifted in from the left and for
subsequent shifts, zeros are shifted in. When the TB8 bit gets to the output position, the
control block executes one last shift and sets the TI bit.
Reception is started by a high to low transition on RXD (sampled at 16 times the baud
rate). The divide-by-16 counter is then reset and 1111 1111B is written to the receive
register. If a valid start bit (0) is then detected (based on two out of three samples), it is
shifted into the register followed by 8 data bits. If the transition is not followed by a valid
start bit, the controller goes back to looking for a high to low transition on RXD. When the
start bit reaches the leftmost position, the control block executes one last shift, then
loads SBUF with the 8 data bits, loads RB8 (SCON.2) with the 9th data bit, and sets the
RI bit, provided RI = 0, and either SM2 = 0 (see Section 10.1.2) or the 9th bit = 1. If none
of these conditions is met, the received byte is lost.
The baud rate for the transfer is either fPCLK/64 or fPCLK/32, depending on the setting of
the top bit (SMOD) of the PCON (Power Control) register, which acts as a Double Baud
Rate selector.
10.1.1.3 Mode 3, 9-Bit UART, Variable Baud Rate
Mode 3 is the same as mode 2 in all respects except that the baud rate is variable and
is set by the underflow rate on the dedicated baud-rate generator.
In all modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in the modes by the incoming start bit if REN = 1.
The serial interface also provides interrupt requests when transmission or reception of
the frames has been completed. The corresponding interrupt request flags are TI or RI,
respectively. If the serial interrupt is not used (i.e., serial interrupt not enabled), TI and
RI can also be used for polling the serial interface.
The associated timings for transmit/receive in modes 2 and 3 are illustrated
in Figure 10-2.
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Start Bit
RI
Shift
Bit Detector
Sample Times
RXD
RX
Clock
Stop Bit
Generation
TI
TXD
Shift
Data
TX
Clock
Start Bit
reset
D0
D1
D0
D2
D1
D3
D2
D4
D3
D5
D4
D6
D5
D7
D6
D7
TB8
RB8
Stop Bit
Stop Bit
XC866
Serial Interfaces
Transmit
Receive
Figure 10-2 Serial Interface, Modes 2 and 3, Timing Diagram
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10.1.2
Multiprocessor Communication
Modes 2 and 3 have a special provision for multiprocessor communication using a
system of address bytes with bit 9 = 1 and data bytes with bit 9 = 0. In these modes,
9 data bits are received. The 9th data bit goes into RB8. The communication always
ends with one stop bit. The port can be programmed such that when the stop bit is
received, the serial port interrupt will be activated only if RB8 = 1.
This feature is enabled by setting bit SM2 in SCON. One of the ways to use this feature
in multiprocessor systems is described in the following paragraph.
When the master processor wants to transmit a block of data to one of several slaves, it
first sends out an address byte that identifies the target slave. An address byte differs
from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With
SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will
interrupt all slaves, so that each slave can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit and prepare to receive the data
bytes that will be coming. The slaves that were not being addressed retain their SM2s
as set and ignore the incoming data bytes.
Bit SM2 can be used in mode 1 to check the validity of the stop bit. In a mode 1 reception,
if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
10.1.3
Register Description
The UART uses two Special Function Registers (SFRs), SCON and SBUF. SCON is the
control register and SBUF is the data register. On reset, both SCON and SBUF return
00H. The serial port control and status register is the SFR SCON. This register contains
not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8
and RB8) and the serial port interrupt bits (TI and RI).
SBUF is the receive and transmit buffer of the serial interface. Writing to SBUF loads the
transmit register and initiates transmission. This register is used for both transmit and
receive data. Transmit data is written to this location and receive data is read from this
location, but the two paths are independent.
Reading out SBUF accesses a physically separate receive register.
SBUF
Serial Data Buffer
7
6
Reset Value: 00H
5
4
3
2
1
0
VAL
rwh
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Serial Interfaces
Field
Bits
Type Description
VAL
[7:0]
rwh
Serial Interface Buffer Register
SCON
Serial Channel Control Register
Reset Value: 00H
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
rw
rw
rw
rw
rw
rwh
rwh
rwh
Field
Bits
Type Description
RI
0
rwh
Receive Interrupt Flag
This is set by hardware at the half point of the stop
bit in modes 1, 2, and 3. Must be cleared by software.
TI
1
rwh
Transmit Interrupt Flag
This is set by hardware at the beginning of the stop
bit in modes 1, 2, and 3. Must be cleared by software.
RB8
2
rwh
Serial Port Receiver Bit 9
In modes 2 and 3, this is the 9th data bit received.
In mode 1, this is the stop bit received.
TB8
3
rw
Serial Port Transmitter Bit 9
In modes 2 and 3, this is the 9th data bit sent.
REN
4
rw
Enable Receiver of Serial Port
0
Serial reception is disabled.
1
Serial reception is enabled.
SM2
5
rw
Enable Serial Port Multiprocessor
Communication in Modes 2 and 3
In mode 2 or 3, if SM2 is set to 1, RI will not be
activated if the received 9th data bit (RB8) is 0.
In mode 1, if SM2 is set to 1, RI will not be activated
if a valid stop bit (RB8) was not received.
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Field
Bits
Type Description
SM1
SM0
6
7
rw
Serial Port Operating Mode Selection
SM0 SM1 Selected operating mode
10.1.4
0
0
Mode 0: Reserved
0
1
Mode 1: 8-bit UART, variable baud
rate
1
0
Mode 2: 9-bit UART, fixed baud rate
(fPCLK/32 or fPCLK/64)
1
1
Mode 3: 9-bit UART, variable baud
rate
Baud Rate Generation
There are several ways to generate the baud rate clock for the serial port, depending on
the mode in which it is operating.
“Baud rate clock” and “baud rate” must be distinguished from each other. The serial
interface requires a clock rate that is 16 times the baud rate for internal synchronization.
Therefore, the baud-rate generators must provide a “baud rate clock” to the serial
interface where it is divided by 16 to obtain the actual “baud rate”. The abbreviation fPCLK
refers to the input clock frequency.
In mode 2, the baud rate is either fPCLK/64 or fPCLK/32 depending on the setting of
PCON.SMOD, which acts as a Double Baud Rate selector.
However, when the serial port is being used in either mode 1 or mode 3, it has a variable
baud rate principally set by the underflow rate of the dedicated baud-rate generator.
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The fixed baud rate of the serial port in mode 2 is controlled by bit SMOD in SFR PCON,
as shown below. The variable baud rate supplied by the dedicated baud-rate generator,
for modes 1 and 3, is unaffected by this bit.
PCON
Power Control Register
7
6
Reset Value: 00H
5
4
3
2
1
0
SMOD
0
GF1
GF0
0
IDLE
rw
r
rw
rw
r
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
SMOD
7
rw
Double Baud Rate Enable
0
Do not double the baud rate of serial interface
in mode 2.
1
Double baud rate of serial interface in mode 2.
Note: Depending on the programmed operating mode, different paths are selected for
the baud rate clock.
10.1.4.1 Baud-rate Generator
The XC866 provides a dedicated baud-rate generator to generate the baud rate for the
UART module. It has programmable 8-bit reload value and 3-bit prescaler.
The baud-rate generator is clocked with a clock (fDIV) derived via a prescaler from the
input clock fPCLK. The baud rate timer counts downwards and can be started or stopped
through the baud rate control run bit BCON.R. Each underflow of the timer provides one
clock pulse to the serial channel. The timer is reloaded with the value stored in its 8-bit
reload register each time it underflows. The prescaler is selected by the bit field
BCON.BRPRE.
Register BG is the dual-function Baud-rate Generator/Reload register. Reading BG
returns the contents of the timer, while writing to BG always updates the reload register.
An auto-reload of the timer with the contents of the reload register is performed each time
BG is written to. However, if BCON.R is cleared at the time a write operation to BG is
performed, the timer will not be reloaded until the first instruction cycle after BCON.R is
set.
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The baud rate of the baud-rate generator depends on the following bits and register
values:
• Input clock fPCLK
• Value of register BCON.BRPRE
• Value of the 8-bit reload register BG
8-Bit Baudrate Timer
fPCLK
fDIV
Prescaler
fBR
8-Bit Baudrate Timer
R
Figure 10-3 Baud-rate Generator Circuitry
The serial interface requires a clock rate which is 16 times the baud rate for internal
synchronization. Therefore, the baud-rate generators must provide a “baud rate clock”
to the serial interface, which is divided by 16 and results in the actual baud rate. The
following formula includes the factor and calculates the final baud rate.
baud rate =
fPCLK
16 x PRE x (BG+1)
The value of PRE (prescaler) is chosen by the bit BCON.BRPRE. BG represents the
contents of the reload register BG.BR_VALUE, which is taken as unsigned 8-bit integer.
The maximum baud rate that can be achieved for a module clock of 26.7 MHz is
1.67 MBaud. Table 10-2 lists various commonly used baud rates together with the
required reload values and the deviation errors compared to the intended baud rate.
Table 10-2
Typical Baud Rates of UART
Baud rate
(fPCLK = 26.7 MHz)
PRE
Reload Value
Deviation Error
19.2 kBaud
1 (BRPRE=000)
87 (57H)
-0.22 %
9600 Baud
1 (BRPRE=000)
174 (AEH)
-0.22 %
4800 Baud
2 (BRPRE=001)
174 (AEH)
-0.22 %
2400 Baud
4 (BRPRE=010)
174 (AEH)
-0.22 %
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Register BCON contains control bits for baud-rate generator and the prescaler bit field.
BCON
Baud Rate Control Register
7
6
Reset Value: 00H
5
4
3
BGSEL
T2EXIS
BRDIS
BRPRE
R
rw
rw
rw
rw
rw
Field
Bits
Type Description
R
0
rw
2
1
0
Baud-rate Generator Run Control Bit
0
Baud-rate generator is disabled.
1
Baud-rate generator is enabled.
Note: BR_VALUE should only be written if R = 0.
BRPRE
[3:1]
rw
Prescaler Bit
Selects the input clock for fDIV which is derived from
the peripheral clock.
000 fDIV= fPCLK
001 fDIV = fPCLK/2
010 fDIV = fPCLK/4
011 fDIV = fPCLK/8
100 fDIV = fPCLK/16
101 fDIV = fPCLK/32
Others: reserved
BRDIS
4
rw
Baud Rate Detection Disable
0
Baud rate detection is enabled.
1
Baud rate detection is disabled.
T2EXIS
5
rw
T2EX Function Select
0
T2EX is selected for baud rate detection.
1
T2EX is selected for Timer 2 function.
BGSEL
[7:6]
rw
Baud Rate Select for detection
00
10 kHz to 20 kHz
01
5 kHz to 10 kHz
10
2.5 kHz to 5 kHz
11
1.25 kHz to 2.5 kHz
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Register BG contains the 8-bit reload value for the baud rate timer.
BG
Baud Rate Timer/Reload Register
7
6
5
Reset Value: 00H
4
3
2
1
0
BR_VALUE
rw
Field
Bits
Type Description
BR_VALUE
[7:0]
rw
Baud Rate Timer/Reload Value
Reading returns the 8-bit content of the baud rate
timer; writing loads the baud rate timer/reload value.
Note: BG should only be written if R = 0.
10.1.5
Interfaces of UART
The UART has two input/output lines; TXD for data transmission and RXD for data
reception.
Data that is shifted into the UART module through RXD can be selected from two
different sources, RXD_0 and RXD_1. This selection is performed by the SFR bit
MODPISEL.URRIS.
MODPISEL
Peripheral Input Select Register
7
6
5
Reset Value: 00H
4
3
JTAGTDIS JTAGTCK
S
0
r
rw
rw
2
1
0
0
EXINT0IS
URRIS
r
rw
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
URRIS
0
rw
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Serial Interfaces, V 0.3
UART Receive Input Select
0
UART Receiver Input RXD_0 is selected.
1
UART Receiver Input RXD_1 is selected.
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10.2
LIN
The UART can be used to support the Local Interconnect Network (LIN) protocol for both
master and slave operations. The LIN baud rate detection feature provides the capability
to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be
synchronized to the LIN baud rate for data transmission and reception.
10.2.1
LIN Protocol
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 10-4. The frame consists of the:
•
•
•
•
header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field
response time
data bytes (according to UART protocol)
checksum
Frame slot
Frame
Header
Synch
Response
space
Protected
identifier
Interframe
space
Response
Data 1
Data 2
Data N
Checksum
Figure 10-4 The Structure of LIN Frame
Each byte field is transmitted as a serial byte, as shown in Figure 10-5. The LSB of the
data is sent first and the MSB is sent last. The start bit is encoded as a bit with value zero
(dominant) and the stop bit is encoded as a bit with value one (recessive).
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Byte field
Start
Bit
LSB
(bit 0)
MSB
(bit 7)
Stop
Bit
Figure 10-5 The Structure of Byte Field
The break is used to signal the beginning of a new frame. It is the only field that does not
comply with Figure 10-5. A break is always generated by the master task (in the master
mode) and it must be at least 13 bits of dominant value, including the start bit, followed
by a break delimiter, as shown in Figure 10-6. The break delimiter will be at least one
nominal bit time long.
A slave node will use a break detection threshold of 11 nominal bit times.
Start
Bit
Break
delimit
Figure 10-6 The Break Field
Synch Byte is a specific pattern for determination of time base. The byte field is with the
data value 55H, as shown in Figure 10-7.
A slave task is always able to detect the Break/Synch sequence, even if it expects a byte
field (assuming the byte fields are separated from each other). If this happens, detection
of the Break/Synch sequence will abort the transfer in progress and processing of the
new frame will commence.
Start
Bit
Stop
Bit
Figure 10-7 The Synch Byte Field
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The slave task will receive and transmit data when an appropriate ID is sent by the
master:
1. Slave waits for Synch Break
2. Slave synchronizes on Synch Byte
3. Slave snoops for ID
4. According to ID, slave determines whether to receive or transmit data, or do nothing
5. When transmitting, the slave sends 2, 4 or 8 data bytes, followed by check byte
10.2.2
LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
needed for the handshaking between the master and slave tasks is provided by the
master task through the header portion of the frame.
The header consists of a break and synch pattern followed by an identifier. Among these
three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
The break must contain a dominant value of 13 bits or more to ensure proper
synchronization of slave nodes.
The UART can be used to transmit a 20-bit break field by the following sequence:
Step 1: Set the UART to mode 1:
• This configures the UART as an 8-bit UART with a variable baud rate.
Step 2: Set the baud rate to two times of the desired baud rate
Step 3: Write 00H to the transmit buffer to begin transmission
By having two times of the desired baud rate, the 10-bit UART frame consisting of the
start, stop and 8 data bits will achieve the effect of a 20-bit break field on the LIN bus.
For subsequent synch and identifier fields, the baud rate must then be adjusted back to
the initial value.
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10.2.3
Baud Rate Detection of LIN
In the LIN communication, a slave task is required to be synchronized at the beginning
of the protected identifier field of frame. For this purpose, every frame starts with a
sequence consisting of a break field followed by a synch byte field. This sequence is
unique and provides enough information for any slave task to detect the beginning of a
new frame and be synchronized at the start of the identifier field.
In order to detect the baud rate of LIN, the bit timing Tbit is calculated by measuring the
time between the falling edges of pattern. In baud rate detection mode, the timing of the
two bits in Synch Byte field is captured, which is shown in Figure 10-8.
Synch Byte
2Tbit
START 0
BIT
1
2
3
4
5
6
7
STOP
BIT
Figure 10-8 The Bit Timing in Synch Byte
Register bits 4-7 of BCON register (see Page 10-12) are used for the LIN baud rate
detection. Register bit BRDIS is used to enable/disable the baud rate detection. Register
bit T2EXIS is used to choose the T2EX pin (P1.0) for the baud rate detection purpose or
for the normal Timer 2 function use. Users should specify the baud rate range via the
register bit BGSEL if they know the range of the LIN baud rate. The baud rate detection
unit will use different sampling rates for different baud rates according to this information.
This will result in accurate baud rate detection.
The following sequence is generally executed to start the baud rate detection:
Step1: With the first falling edge of RXD:
• If the system is in the power-down mode and PMCON0.WS = 01, a wake-up from the
power-down through the RXD pin will be activated.
• Once the system enters normal mode, the following settings must be done by
software:
– Bit PMCON1.T2_DIS is set to 0 (enable Timer 2)
– Bit BCON.BRDIS is set to 0 (enable baud rate detection)
– Bit BCON.T2EXIS is set to 0 (T2EX pin is used for baud rate detection)
– Provide the baud rate range via bit BCON.BGSEL
– Bits T2CON.CP/RL2 and T2CON. EXEN2 are set to 1. T2MOD.EDGESEL is set
to 0. (Timer 2 is set to the capture mode with falling edge trigger)
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• The UART is running with an estimated baud rate, which is generated by the
baud-rate generator. (See Section 10.1.4.1)
Step 2: With the second falling edge of Synch Byte:
• Start Timer 2 by hardware (Bit 1 of Synch Byte field).
Step 3: With the third falling edge of Synch Byte:
• The capture action of Timer 2 will be triggered and lead to a capture of the time of bit
1 and bit 2 in Synch Byte field. The contents of the timer register (THL2) are captured
into the RC2 register. The captured value is 2 LIN bit times long. If the capture signal
is detected while the counter is being incremented, the counter is first incremented
before the capture operation is performed. This ensures that the latest value of the
timer register is always captured.
• When the capture operation is completed, bit T2CON.EXF2 is set and can be used to
generate an interrupt request.
• The software will use the RC2 value of Timer 2 to retrieve the reload value BG_VALUE
and prescaler BRPRE of the baud-rate generator.
• The software updates the baud-rate generator with the new BG value and prescaler
value, and generates the new baud rate.
The reload register of Timer 2 (RC2) is reloaded with value 0000H by software.
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10.3
High-Speed Synchronous Serial Interface
The SSC supports full-duplex and half-duplex synchronous communication. The serial
clock signal can be generated by the SSC internally (master mode), using its own 16-bit
baud-rate generator, or can be received from an external master (slave mode). Data
width, shift direction, clock polarity and phase are programmable. This allows
communication with SPI-compatible devices or devices using other synchronous serial
interfaces.
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 10-9 shows the block diagram of the SSC.
PCLK
Baud-rate
Generator
SS_CLK
MS_CLK
Clock
Control
Shift
Clock
RIR
SSC Control Block
Register CON
Status
Receive Int. Request
TIR
Transmit Int. Request
EIR
Error Int. Request
Control
TXD(Master)
Pin
Control
16-Bit Shift
Register
RXD(Slave)
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 10-9 Synchronous Serial Channel SSC Block Diagram
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10.3.1
General Operation
10.3.1.1 Operating Mode Selection
The operating mode of the serial channel SSC is controlled by its control register CON.
This register has a double function:
• During programming (SSC disabled by CON.EN = 0), it provides access to a set of
control bits
• During operation (SSC enabled by CON.EN = 1), it provides access to a set of status
flags.
The shift register of the SSC is connected to both the transmit lines and the receive lines
via the pin control logic. Transmission and reception of serial data are synchronized and
take place at the same time, i.e., the same number of transmitted bits is also received.
Transmit data is written into the Transmitter Buffer register (TB) and is moved to the shift
register as soon as this is empty. An SSC master (CON.MS = 1) immediately begins
transmitting, while an SSC slave (CON.MS = 0) will wait for an active shift clock. When
the transfer starts, the busy flag CON.BSY is set and the Transmit Interrupt Request line
(TIR) will be activated to indicate that register TB may be reloaded again. When the
programmed number of bits (2...8) have been transferred, the contents of the shift
register are moved to the Receiver Buffer register (RB) and the Receive Interrupt
Request line (RIR) will be activated. If no further transfer is to take place (TB is empty),
CON.BSY will be cleared at the same time. Software should not modify CON.BSY, as
this flag is hardware controlled.
Note: Only one SSC can be the master at a given time.
The transfer of serial data bits can be programmed in a number of ways:
•
•
•
•
The data width can be specified from 2 to 8 bits
A transfer may start with either the LSB or the MSB
The shift clock may be idle low or idle high
The data bits may be shifted with the leading edge or the trailing edge of the shift clock
signal
• The baud rate may be set within a certain range depending on the module clock
• The shift clock can be generated (MS_CLK) or can be received (SS_CLK)
These features allow the SSC to be adapted to a wide range of applications requiring
serial data transfer.
The Data Width Selection supports the transfer of frames of any data length, from 2-bit
“characters” up to 8-bit “characters”. Starting with the LSB (CON.HB = 0) allows
communication with SSC devices in synchronous mode or with serial interfaces such as
the one in 8051. Starting with the MSB (CON.HB = 1) allows operation compatible with
the SPI interface.
Regardless of the data width selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right-aligned in registers TB and RB, with the LSB of the
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transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the
internal shift register logic. The unselected bits of TB are ignored; the unselected bits of
RB will not be valid and should be ignored by the receiver service routine.
The Clock Control allows the transmit and receive behavior of the SSC to be adapted to
a variety of serial interfaces. A specific shift clock edge (rising or falling) is used to shift
out transmit data, while the other shift clock edge is used to latch in receive data. Bit
CON.PH selects the leading edge or the trailing edge for each function. Bit CON.PO
selects the level of the shift clock line in the idle state. Thus, for an idle-high clock, the
leading edge is a falling one, a 1 - to - 0 transition (see Figure 10-10).
CON.
PO
CON.
PH
0
0
0
1
1
0
1
1
Shift Clock
MS_CLK/SS_CLK
Pins
MTSR/MRST
First
Bit
Transmit Data
Last
Bit
Latch Data
Shift Data
Figure 10-10 Serial Clock Phase and Polarity Options
When initializing the devices for serial communication, one device must be selected for
master operation while all other devices must be programmed for slave operation.
10.3.1.2 Full-Duplex Operation
The various devices are connected through three lines. The definition of these lines is
always determined by the master: the line connected to the master’s data output line
TXD is the transmit line; the receive line is connected to its data input line RXD; the shift
clock line is either MS_CLK or SS_CLK. Only the device selected for master operation
generates and outputs the shift clock on line MS_CLK. Since all slaves receive this clock,
their pin SCLK must be switched to input mode. The external connections are
hard-wired, and the function and direction of these pins are determined by the master or
slave operation of the individual device.
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Master
Device #1
Device #2
Shift Register
Clock
Slave
Shift Register
MTSR
Transmit
MTSR
MRST
Receive
MRST
CLK
Clock
CLK
Clock
Device #3
Slave
Shift Register
MTSR
MRST
CLK
Clock
Figure 10-11 SSC Full-Duplex Configuration
The data output pins MRST of all slave devices are connected together onto the single
receive line in the configuration shown in Figure 10-11. During a transfer, each slave
shifts out data from its shift register. There are two ways to avoid collisions on the receive
line due to different slave data:
• Only one slave drives the line, i.e., enables the driver of its MRST pin. All the other
slaves must have their MRST pins programmed as input so only one slave can put its
data onto the master's receive line. Only the receiving of data from the master is
possible. The master selects the slave device from which it expects data either by
separate select lines, or by sending a special command to this slave. The selected
slave then switches its MRST line to output until it gets a de-selection signal or
command.
• The slaves use open drain output on MRST. This forms a wired-AND connection. The
receive line needs an external pull-up in this case. Corruption of the data on the
receive line sent by the selected slave is avoided when all slaves not selected for
transmission to the master send ones only. Because this high level is not actively
driven onto the line, but only held through the pull-up device, the selected slave can
pull this line actively to a low level when transmitting a zero bit. The master selects the
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slave device from which it expects data either by separate select lines or by sending
a special command to this slave.
After performing the necessary initialization of the SSC, the serial interfaces can be
enabled. For a master device, the clock line will now go to its programmed polarity. The
data line will go to either 0 or 1 until the first transfer starts. After a transfer, the data line
will always remain at the logic level of the last transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data
transfer by writing the transmit data into register TB. This value is copied into the shift
register (assumed to be empty at this time), and the selected first bit of the transmit data
will be placed onto the TXD line on the next clock from the baud-rate generator
(transmission starts only if CON.EN = 1). Depending on the selected clock phase, a
clock pulse will also be generated on the MS_CLK line. At the same time, with the
opposite clock edge, the master latches and shifts in the data detected at its input line
RXD. This “exchanges” the transmit data with the receive data. Because the clock line
is connected to all slaves, their shift registers will be shifted synchronously with the
master’s shift register—shifting out the data contained in the registers, and shifting in the
data detected at the input line.
With the start of the transfer, the busy flag CON.BSY is set and the TIR will be activated
to indicate that register TB may be reloaded again. After the preprogrammed number of
clock pulses (via the data width selection), the data transmitted by the master is
contained in all the slaves’ shift registers, while the master’s shift register holds the data
of the selected slave. In the master and all slaves, the contents of the shift register are
copied into the receive buffer RB and the RIR is activated. If no further transfer is to take
place (TB is empty), CON.BSY will be cleared at the same time. Software should not
modify CON.BSY, as this flag is hardware controlled.
When configured as a slave device, the SSC will immediately output the selected first bit
(MSB or LSB of the transfer data) at the output pin once the contents of the transmit
buffer are copied into the slave's shift register. Bit CON.BSY is not set until the first clock
edge at SS_CLK appears.
Note: On the SSC, a transmission and a reception take place at the same time,
regardless of whether valid data has been transmitted or received.
Note: The initialization of the CLK pin on the master requires some attention in order to
avoid undesired clock transitions, which may disturb the other devices. Before the
clock pin is switched to output via the related direction control register, the clock
output level will be selected in the control register CON and the alternate output
be prepared via the related ALTSEL register, or the output latch must be loaded
with the clock idle level.
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10.3.1.3 Half-Duplex Operation
In a half-duplex mode, only one data line is necessary for both receiving and transmitting
of data. The data exchange line is connected to both the MTSR and MRST pins of each
device, the shift clock line is connected to the SCLK pin.
The master device controls the data transfer by generating the shift clock, while the slave
devices receive it. Due to the fact that all transmit and receive pins are connected to one
data exchange line, serial data may be moved between arbitrary stations.
As in full-duplex mode, there are two ways to avoid collisions on the data exchange line:
• only the transmitting device may enable its transmit pin driver
• the non-transmitting devices use open drain output and send only ones.
Since the data inputs and outputs are connected together, a transmitting device will clock
in its own data at the input pin (MRST for a master device, MTSR for a slave). By this
method, any corruptions on the common data exchange line are detected if the received
data is not equal to the transmitted data.
Master
Device #1
Transmit
Device #2
Shift Register
Clock
Slave
Shift Register
MTSR
MTSR
MRST
MRST
CLK
Clock
CLK
Common
Transmit/
Receive Device #3
Line
Clock
Slave
Shift Register
MTSR
MRST
CLK
Clock
Figure 10-12 SSC Half-Duplex Configuration
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10.3.1.4 Continuous Transfers
When the transmit interrupt request flag is set, it indicates that the transmit buffer TB is
empty and ready to be loaded with the next transmit data. If TB has been reloaded by
the time the current transmission is finished, the data is immediately transferred to the
shift register and the next transmission will start without any additional delay. On the data
line, there is no gap between the two successive frames. For example, two byte transfers
would look the same as one word transfer. This feature can be used to interface with
devices that can operate with or require more than 8 data bits per transfer. It is just a
matter of software specifying the total data frame length. This option can also be used to
interface with byte-wide and word-wide devices.
Note: This feature allows only multiples of the selected basic data width, because it
would require disabling/enabling of the SSC to reprogram the basic data width onthe-fly.
10.3.1.5 Port Control
The SSC uses three lines to communicate with the external world as shown in
Figure 10-13. Pin SCLK serves as the clock line, while pins MRST and MTSR serve as
the serial data input/output lines.
EIR
TBIR
MRST
Master
TIR
MTSR
MRST
P0.4/MTSR_1
Port
Control
P0.5/MRST_1
Master/ Slave
SSC
Module
(Kernel)
P0.3/SCLK_1
MTSR
Slave
Interrupt
System
SCLK
Figure 10-13 SSC Module I/O Interface
Operation of the SSC I/O lines depends on the selected operating mode (master or
slave). The direction of the port lines depends on the operating mode. The SSC will
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automatically use the correct kernel output or kernel input line of the ports when
switching modes.
Since the SSC I/O lines are connected with the bidirectional lines of the general purpose
I/O ports, software I/O control is used to control the port pins assigned to these lines. The
port registers must be programmed for alternate output and input selection. When
switching between master and slave modes, port registers must be reprogrammed.
10.3.1.6 Baud Rate Generation
The serial channel SSC has its own dedicated 16-bit baud-rate generator with 16-bit
reload capability, allowing baud rate generation independent of the timers. Figure 10-14
shows the baud-rate generator.
16-Bit Reload Register
fPCLK
. 2
.
f MS_CLK/SS_CLK
16-Bit Counter
fMS_CLK max in Master Mode< fPCLK /2
f SS_CLK max in Master Mode< fPCLK /4
Figure 10-14 SSC Baud-rate Generator
The baud-rate generator is clocked with the module clock fPCLK. The timer counts
downwards. Register BR is the dual-function Baud-rate Generator/Reload register.
Reading BR, while the SSC is enabled, returns the contents of the timer. Reading BR,
while the SSC is disabled, returns the programmed reload value. In this mode, the
desired reload value can be written to BR.
Note: Never write to BR while the SSC is enabled.
The formulas below calculate either the resulting baud rate for a given reload value, or
the required reload value for a given baud rate:
Baud rate =
fPCLK
BR =
2 x (<BR> + 1)
fPCLK
2 x Baud rate
-1
<BR> represents the contents of the reload register, taken as an unsigned 16-bit integer,
while baud rate is equal to fMS_CLK/SS_CLK as shown in Figure 10-14.
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The maximum baud rate that can be achieved when using a module clock of 26.7 MHz
is 13.3 MBaud in master mode (with <BR> = 0000H) or 6.7 MBaud in slave mode (with
<BR> = 0001H).
Table 10-3 lists some possible baud rates together with the required reload values and
the resulting deviation errors, assuming a module clock frequency of 26.7 MHz.
Table 10-3
Typical Baud Rates of the SSC (fhw_clk = 26.7 MHz)
Reload Value
Baud Rate (= fMS_CLK/SS_CLK)
Deviation
0000H
13.3 MBaud (only in Master mode)
0.0%
0001H
6.7 MBaud
0.0%
0009H
1.3 MBaud
0.0%
000CH
1 MBaud
2.5%
0011H
750 kBaud
1.2%
0013H
666.7 kBaud
0.0%
0015H
600 kBaud
1.0%
001AH
500 kBaud
1.2%
0031H
266.7 kBaud
0.0%
0042H
200 kBaud
0.5%
0063H
133.3 kBaud
0.0%
0084H
100 kBaud
0.25%
FFFFH
203.45 Baud
0.0%
10.3.1.7 Error Detection Mechanisms
The SSC is able to detect four different error conditions. Receive Error and Phase Error
are detected in all modes; Transmit Error and Baud Rate Error apply only to slave mode.
When an error is detected, the respective error flag is set and an error interrupt request
will be generated by activating the Error Interrupt Request line (EIR) (see Figure 10-15).
The error interrupt handler may then check the error flags to determine the cause of the
error interrupt. The error flags are not reset automatically, but rather must be cleared by
software after servicing. This allows servicing of some error conditions via interrupt,
while the others may be polled by software.
Note: The error interrupt handler must clear the associated (enabled) error flag(s) to
prevent repeated interrupt requests.
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Bits in Register
CON
TEN
Transmit
Error
&
TE
REN
Receive
Error
&
RE
>1
Error Interrupt
EIR
PEN
Phase
Error
&
PE
BEN
Baud rate
Error
&
BE
Figure 10-15 SSC Error Interrupt Control
A Receive Error (master or slave mode) is detected when a new data frame is
completely received, but the previous data was not read out of the register RB. This
condition sets the error flag CON.RE and, when enabled via CON.REN, sets the EIR.
The old data in the receive buffer RB will be overwritten with the new value and this lost
data is irretrievable.
A Phase Error (master or slave mode) is detected when the incoming data at pin MRST
(master mode) or MTSR (slave mode), sampled with the same frequency as the module
clock, changes between one cycle before and two cycles after the latching edge of the
shift clock signal SCLK. This condition sets the error flag CON.PE and, when enabled
via CON.PEN, sets the EIR.
A Baud Rate Error (slave mode) is detected when the incoming clock signal deviates
from the programmed baud rate by more than 100%, i.e., it is either more than double or
less than half the expected baud rate. This condition sets the error flag CON.BE and,
when enabled via CON.BEN, sets the EIR. Using this error detection capability requires
that the slave’s baud-rate generator be programmed to the same baud rate as the
master device. This feature detects false, additional or missing pulses on the clock line
(within a certain frame).
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Note: If this error condition occurs and bit CON.REN = 1, an automatic reset of the SSC
will be performed. This is done to re-initialize the SSC if too few or too many clock
pulses have been detected.
A Transmit Error (slave mode) is detected when a transfer was initiated by the master
(SS_CLK gets active), but the transmit buffer TB of the slave had not been updated since
the last transfer. This condition sets the error flag CON.TE and, when enabled via
CON.TEN, sets the EIR. If a transfer starts without the transmit buffer having been
updated, the slave will shift out the ‘old’ contents of the shift register, which normally is
the data received during the last transfer. This may lead to corruption of the data on the
transmit/receive line in half-duplex mode (open drain configuration) if this slave is not
selected for transmission. This mode requires that slaves not selected for transmission
only shift out ones; that is, their transmit buffers must be loaded with ‘FFFFH’ prior to any
transfer.
Note: A slave with push/pull output drivers not selected for transmission, will normally
have its output drivers switched off. However, in order to avoid possible conflicts
or misinterpretations, it is recommended to always load the slave's transmit buffer
prior to any transfer.
The cause of an error interrupt request (receive, phase, baud rate or transmit error) can
be identified by the error status flags in control register CON.
Note: In contrast to the EIR, the error status flags CON.TE, CON.RE, CON.PE, and
CON.BE are not reset automatically upon entry into the error interrupt service
routine, but must be cleared by software.
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10.3.2
Interrupts
An overview of the various interrupts in SSC is provided in Table 10-4.
Table 10-4
Interrupt
SSC Interrupt Sources
Signal
Description
Transmission TIR
starts
Indicates that the transmit buffer can be reloaded with new
data.
Transmission RIR
ends
The configured number of bits have been transmitted and
shifted to the receive buffer.
Receive
Error
EIR
This interrupt occurs if a new data frame is completely
received and the last data in the receive buffer was not
read.
Phase Error
EIR
This interrupt is generated if the incoming data changes
between one cycle before and two cycles after the latching
edge of the shift clock signal SCLK.
Baud Rate
Error (Slave
mode only)
EIR
This interrupt is generated when the incoming clock signal
deviates from the programmed baud rate by more than
100%.
Transmit
Error (Slave
mode only)
EIR
This interrupt is generated when TB was not updated since
the last transfer if a transfer is initiated by a master.
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10.3.3
Register Mapping
The addresses of the kernel SFRs are listed in Table 10-5.
Table 10-5
SFR Address List
Address
Register
A9H
PISEL
AAH
CONL
ABH
CONH
ACH
TBL
ADH
RBL
AEH
BRL
AFH
BRH
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10.3.4
Register Description
All SSC register names described in this section will be referenced in other chapters of
this document with the module name prefix “SSC_”, e.g., SSC_PISEL.
10.3.4.1 Port Input Select Register
The PISEL register controls the receiver input selection of the SSC module.
PISEL
Port Input Select Register
7
6
5
Reset Value: 00H
4
3
2
1
0
0
CIS
SIS
MIS
r
rw
rw
rw
Field
Bits
Type Description
MIS
0
rw
Master Mode Receiver Input Select
0
Receiver input is disabled for master mode.
1
Receiver input is enabled for master mode.
SIS
1
rw
Slave Mode Receiver Input Select
0
Receiver input is disabled for slave mode.
1
Receiver input is enabled for slave mode.
CIS
2
rw
Slave Mode Clock Input Select
0
Clock input is disabled.
1
Clock input is enabled.
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
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10.3.4.2 Configuration Register
The operating mode of the serial channel SSC is controlled by the control register CON.
This register contains control bits for mode and error check selection, and status flags
for error identification. Depending on bit EN, either control functions or status flags and
master/slave control are enabled.
CON.EN = 0: Programming Mode
CONL
Control Register Low
Reset Value: 00H
7
6
5
4
3
LB
PO
PH
HB
BM
rw
rw
rw
rw
rw
Field
Bits
Type Description
BM
[3:0]
rw
2
1
0
Data Width Selection
0000 Reserved. Do not use this combination.
0001 0111 Transfer Data Width is 2...8 bits (<BM>+1)
Note: BM[3] is fixed to 0.
HB
4
rw
Heading Control
0
Transmit/Receive LSB First
1
Transmit/Receive MSB First
PH
5
rw
Clock Phase Control
0
Shift transmit data on the leading clock edge,
latch on trailing edge
1
Latch receive data on leading clock edge, shift
on trailing edge
PO
6
rw
Clock Polarity Control
0
Idle clock line is low, leading clock edge is lowto-high transition
1
Idle clock line is high, leading clock edge is highto-low transition
LB
7
rw
Loop Back Control
0
Normal output
1
Receive input is connected with transmit output
(half-duplex mode)
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CONH
Control Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
MS
0
AREN
BEN
PEN
REN
TEN
rw
rw
r
rw
rw
rw
rw
rw
Field
Bits
Type Description
TEN
0
rw
Transmit Error Enable
0
Ignore transmit errors
1
Check transmit errors
REN
1
rw
Receive Error Enable
0
Ignore receive errors
1
Check receive errors
PEN
2
rw
Phase Error Enable
0
Ignore phase errors
1
Check phase errors
BEN
3
rw
Baud Rate Error Enable
0
Ignore baud rate errors
1
Check baud rate errors
AREN
4
rw
Automatic Reset Enable
0
No additional action upon a baud rate error
1
The SSC is automatically reset upon a baud rate
error.
MS
6
rw
Master Select
0
Slave mode. Operate on shift clock received via
SCLK.
1
Master mode. Generate shift clock and output it
via SCLK.
EN
7
rw
Enable Bit = 0
Transmission and reception disabled. Access to
control bits.
0
5
r
Reserved
Returns 0 if read; should be written with 0.
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CON.EN = 1: Operating Mode
CONL
Control Register Low
7
Reset Value: 00H
6
5
4
3
2
1
0
BC
r
rh
0
Field
Bits
Type Description
BC
[3:0]
rh
Bit Count Field
0001 1111 Shift counter is updated with every shifted bit
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
CONH
Control Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
MS
0
BSY
BE
PE
RE
TE
rw
rw
r
rh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
TE
0
rwh
Transmit Error Flag
0
No error
1
Transfer starts with the slave’s transmit buffer
not being updated
RE
1
rwh
Receive Error Flag
0
No error
1
Reception completed before the receive buffer
was read
PE
2
rwh
Phase Error Flag
0
No error
1
Received data changes around sampling clock
edge
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Field
Bits
Type Description
BE
3
rwh
Baud rate Error Flag
0
No error
1
More than factor 2 or 0.5 between slave’s actual
and expected baud rate
BSY
4
rh
Busy Flag
Set while a transfer is in progress
MS
6
rw
Master Select Bit
0
Slave mode. Operate on shift clock received via
SCLK.
1
Master mode. Generate shift clock and output it
via SCLK.
EN
7
rw
Enable Bit = 1
Transmission and reception enabled. Access to status
flags and Master/Slave control.
0
5
r
Reserved
Returns 0 if read; should be written with 0.
Note: The target of an access to CON (control bits or flags) is determined by the state of
CON.EN prior to the access; that is, writing C057H to CON in programming mode
(CON.EN = 0) will initialize the SSC (CON.EN was 0) and then turn it on
(CON.EN = 1). When writing to CON, ensure that reserved locations receive
zeros.
User’s Manual
Serial Interfaces, V 0.3
10-36
V 0.2, 2005-01
XC866
Serial Interfaces
10.3.4.3 Baud Rate Timer Reload Register
The SSC baud rate timer reload register BR contains the 16-bit reload value for the baud
rate timer.
BRL
Baud Rate Timer Reload Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
BR_VALUE[7:0]
rw
BRH
Baud Rate Timer Reload Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
BR_VALUE[15:8]
rw
Field
Bits
Type Description
BR_VALUE
[7:0] of
BRL,
[7:0] of
BRH
rw
User’s Manual
Serial Interfaces, V 0.3
Baud Rate Timer/Reload Register Value
Reading BR returns the 16-bit contents of the
baud rate timer. Writing to BR loads the baud rate
timer reload register with BR_VALUE.
10-37
V 0.2, 2005-01
XC866
Serial Interfaces
10.3.4.4 Transmit and Receive Buffer Register
The SSC transmitter buffer register TB contains the transmit data value.
TBL
Transmitter Buffer Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
TB_VALUE
rw
Field
Bits
Type Description
TB_VALUE
[7:0]
rw
Transmit Data Register Value
TB_VALUE is the data value to be transmitted.
Unselected bits of TB are ignored during
transmission.
The SSC receiver buffer register RB contains the receive data value.
RBL
Receiver Buffer Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
RB_VALUE
rh
Field
Bits
Type Description
RB_VALUE
[7:0]
rh
User’s Manual
Serial Interfaces, V 0.3
Receive Data Register Value
RB contains the received data value RB_VALUE.
Unselected bits of RB will not be valid and should
be ignored.
10-38
V 0.2, 2005-01
XC866
Timers
11
Timers
The XC866 provides three 16-bit timers, Timer 0, Timer 1 and Timer 2. They are useful
in many timing applications such as measuring the time interval between events and
generating signals at regular intervals.
Timer 0 and Timer 1 Features:
• Four operational modes:
– Mode 0: 13-bit timer
– Mode 1: 16-bit timer
– Mode 2: 8-bit timer with auto-reload
– Mode 3: Two 8-bit timers
Timer 2 Features:
• Selectable up/down counting
• 16-bit auto-reload mode
• 1 channel, 16-bit capture mode
11.1
Timer 0 and Timer 1
Timer 0 and Timer 1 are count-up timers which are incremented every machine cycle, or
in terms of the input clock, every 2 PCLK cycles. Both have four modes of operation that
are used in a variety of applications.
11.1.1
Basic Timer Operations
The operations of the two timers are controlled using the Special Function Registers
(SFRs) TCON and TMOD. To enable a timer, i.e., allow the timer to run, its control bit
TCON.TRx is set.
Note: The “x” (e.g., TCON.TRx) in this chapter denotes either 0 or 1.
Each timer consists of two 8-bit registers, TLx (low byte) and THx (high byte), which
default to 00H on reset. Setting or clearing TCON.TRx does not affect the timer registers.
Timer Overflow
When a timer overflow occurs, the timer overflow flag TCON.TFx is set, and an interrupt
may be raised if the interrupt enable control bit IEN0.ETx is set. The overflow flag is
automatically cleared when the interrupt service routine is entered.
When Timer 0 operates in mode 3, the Timer 1 control bits TR1, TF1 and ET1 are
reserved for TH0. See Section 11.1.2.4.
User’s Manual
Timers, V 0.4
11-1
V 0.2, 2005-01
XC866
Timers
External Control
In addition to pure software control, the timers can be enabled or disabled through
external port control. When a timer is enabled (TCON.TRx = 1) and TMOD.GATEx is
set, the respective timer will only run if the core external interrupt EXINTx = 1. This
facilitates pulse width measurements. However, this is not applicable for Timer 1 in
mode 3.
If TMOD.GATEx is cleared, the timer reverts to pure software control.
11.1.2
Timer Modes
Timers 0 and 1 are fully compatible and can be configured in four different operating
modes, as shown in Table 11-1. The bit field TxM in register TMOD selects the operating
mode to be used for each timer.
In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions
are specialized.
Table 11-1
Timer 0 and Timer 1 Modes
Mode
Operation
0
13-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This
mode is included solely for compatibility with Intel 8048 devices.
1
16-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit
counter.
2
8-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
3
Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
User’s Manual
Timers, V 0.4
11-2
V 0.2, 2005-01
XC866
Timers
11.1.2.1 Mode 0
Putting either Timer 0 or Timer 1 into mode 0 configures it as an 8-bit timer with a
divide-by-32 prescaler. Figure 11-1 shows the mode 0 operation.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the timer overflow flag TFx. The overflow flag TFx can then
be used to request an interrupt. The counted input is enabled for the timer when TRx = 1
and either GATEx = 0 or EXINTx = 1 (setting GATEx = 1 allows the timer to be controlled
by external input EXINTx to facilitate pulse width measurements). TRx is a control bit in
the register TCON; bit GATEx is in register TMOD.
The 13-bit register consists of all the 8 bits of THx and the lower 5 bits of TLx. The upper
3 bits of TLx are indeterminate and should be ignored. Setting the run flag (TRx) does
not clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1.
TL0
(5 Bits)
fPCLK/2
TH0
(8 Bits)
TF0
Interrupt
Control
TR0
GATE0
=1
&
>1
EXINT0
Timer0_Mode0
Figure 11-1 Timer 0, Mode 0: 13-bit Timer
User’s Manual
Timers, V 0.4
11-3
V 0.2, 2005-01
XC866
Timers
11.1.2.2 Mode 1
Mode 1 operation is similar to that of mode 0, except that the timer register runs with all
16 bits. Mode 1 operation for Timer 0 is shown in Figure 11-2.
TL0
(8 Bits)
fPCLK/2
TH0
(8 Bits)
TF0
Interrupt
Control
TR0
GATE0
=1
&
>1
EXINT0
Timer0_Mode1
Figure 11-2 Timer 0, Mode 1: 16-bit Timer
User’s Manual
Timers, V 0.4
11-4
V 0.2, 2005-01
XC866
Timers
11.1.2.3 Mode 2
In mode 2 operation, the timer is configured as an 8-bit counter (TLx) with automatic
reload, as shown in Figure 11-3 for Timer 0.
An overflow from TLx not only sets TFx, but also reloads TLx with the contents of THx
that has been preset by software. The reload leaves THx unchanged.
TL0
(8 Bits)
fPCLK/2
TF0
Interrupt
Control
Reload
TR0
GATE0
=1
&
TH0
(8 Bits)
>1
Timer0_Mode2
EXINT0
Figure 11-3 Timer 0, Mode 2: 8-bit Timer with Auto-Reload
User’s Manual
Timers, V 0.4
11-5
V 0.2, 2005-01
XC866
Timers
11.1.2.4 Mode 3
In mode 3, Timer 0 and Timer 1 behave differently. Timer 0 in mode 3 establishes TL0
and TH0 as two separate counters. Timer 1 in mode 3 simply holds its count. The effect
is the same as setting TR1 = 0.
The logic for mode 3 operation for Timer 0 is shown in Figure 11-4. TL0 uses the Timer 0
control bits GATE0, TR0 and TF0, while TH0 is locked into a timer function (counting
machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now
sets TF1 upon overflow and generates an interrupt if ET1 is set.
Mode 3 is provided for applications requiring an extra 8-bit timer. When Timer 0 is in
mode 3 and TR1 is set, Timer 1 can be turned on by switching it to any of the other
modes and turned off by switching it into mode 3.
Timer Clock
fPCLK/2
TL0
(8 Bits)
TF0
TH0
(8 Bits)
TF1
Interrupt
Control
TR0
&
=1
GATE0
>1
EXINT0
TR1
Interrupt
Timer0_Mode3
Figure 11-4 Timer 0, Mode 3: Two 8-bit Timers
User’s Manual
Timers, V 0.4
11-6
V 0.2, 2005-01
XC866
Timers
11.1.3
Register Map
Seven SFRs control the operations of Timer 0 and Timer 1. They can be accessed from
both the standard (non-mapped) and mapped SFR area. Table 11-2 lists the addresses
of these SFRs.
Table 11-2
SFR Address List
Address
Register
88H
TCON
89H
TMOD
8AH
TL0
8BH
TL1
8CH
TH0
8DH
TH1
User’s Manual
Timers, V 0.4
11-7
V 0.2, 2005-01
XC866
Timers
11.1.4
Register Description
The low and high bytes of both Timer 0 and Timer 1 can be combined to a one-timer
configuration depending on the mode used.
TLx (x = 0 - 1)
Timer x Register Low
7
6
Reset Value: 00H
5
4
3
2
1
0
VAL
rwh
THx (x = 0 - 1)
Timer x Register High
7
6
Reset Value: 00H
5
4
3
2
1
0
VAL
rwh
Field
Bits
Type Description
TLx.VAL
(x = 0 - 1)
[7:0]
rwh
Timer 0/1 Low Register
Operating Description
Mode
User’s Manual
Timers, V 0.4
0
“TLx” holds the 5-bit prescaler value.
1
“TLx” holds the lower 8-bit part of the
16-bit timer value.
2
“TLx” holds the 8-bit timer value.
3
TL0 holds the 8-bit timer value; TL1
is not used.
11-8
V 0.2, 2005-01
XC866
Timers
Field
Bits
Type Description
THx.VAL
(x = 0 - 1)
[7:0]
rwh
User’s Manual
Timers, V 0.4
Timer 0/1 High Register
Operating
Mode
Description
0
“THx” holds the 8-bit timer value.
1
“THx” holds the higher 8-bit part of
the 16-bit timer value.
2
“THx” holds the 8-bit reload value.
3
TH0 holds the 8-bit timer value;
TH1 is not used.
11-9
V 0.2, 2005-01
XC866
Timers
Register TCON controls the operations of Timer 0 and Timer 1.
TCON
Timer Control Register
Reset Value: 00H
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
rw
rw
rw
rw
rw
rw
rw
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
TR0
4
rw
Timer 0 Run Control
0
Timer is halted
1
Timer runs
TF0
5
rw
Timer 0 Overflow Flag
Set by hardware when Timer 0 overflows. Cleared by
hardware when the processor calls the interrupt
service routine.
TR1
6
rw
Timer 1 Run Control1)
0
Timer is halted
1
Timer runs
TF1
7
rw
Timer 1 Overflow Flag
Set by hardware when Timer 12) overflows. Cleared
by hardware when the processor calls the interrupt
service routine.
1)
Also affects TH0 if Timer 0 operates in mode 3.
2)
TF1 is set by TH0 instead if Timer 0 operates in mode 3.
User’s Manual
Timers, V 0.4
11-10
V 0.2, 2005-01
XC866
Timers
Register TMOD contains bits that select the operating modes of Timer 0 and Timer 1.
TMOD
Timer Mode Register
7
6
GATE1
0
rw
r
Reset Value: 00H
5
4
3
2
T1M
GATE0
0
T0M
rw
rw
r
rw
Field
Bits
Type Description
T0M[1:0]
T1M[1:0]
[1:0]
[5:4]
rw
1
0
Mode select bits
T0M/T1M
[1:0]
Function
00
13-bit timer (M8048 compatible
mode)
01
16-bit timer
10
8-bit auto-reload timer
11
Timer 0:
Timer 0 is divided into two parts.
TL0 is an 8-bit timer controlled by
the standard Timer 0 control bits,
and TH0 is the other 8-bit timer
controlled by the standard Timer 1
control bits.
Timer 1:
TL1 and TH1 are held (Timer 1 is
stopped).
GATE0
3
rw
Timer 0 Gate Flag
0
Timer 0 will only run if TCON.TR0 = 1
(software control).
1
Timer 0 will only run if EXINT0 pin = 1
(hardware control) and TCON.TR0 is set.
GATE1
7
rw
Timer 1 Gate Flag
0
Timer 1 will only run if TCON.TR1 = 1
(software control).
1
Timer 1 will only run if EXINT1 pin = 1
(hardware control) and TCON.TR1 is set.
User’s Manual
Timers, V 0.4
11-11
V 0.2, 2005-01
XC866
Timers
Field
Bits
Type Description
0
2, 6
r
Reserved
Returns 0 if read; should be written with 0.
Register IEN0 contains bits that enable interrupt operations in Timer 0 and Timer 1.
IEN0
Interrupt Enable Register
Reset Value: 00H
7
6
5
4
3
2
1
0
EA
0
ET2
ES
ET1
EX1
ET0
EX0
rw
r
rw
rw
rw
rw
rw
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
ET0
1
rw
Timer 0 Overflow Interrupt Enable
0
Timer 0 interrupt is disabled.
1
Timer 0 interrupt is enabled.
ET1
3
rw
Timer 1 Overflow Interrupt Enable1)
0
Timer 1 interrupt is disabled.
1
Timer 1 interrupt is enabled.
1)
When Timer 0 operates in mode 3, this interrupt indicates an overflow in the Timer 0 register, TH0.
User’s Manual
Timers, V 0.4
11-12
V 0.2, 2005-01
XC866
Timer
11.2
Timer 2
Timer 2 is a 16-bit general purpose timer that has two modes of operation, a 16-bit
auto-reload mode and a 16-bit one channel capture mode. If the prescalar is disabled,
Timer 2 counts with an input clock of PCLK/12.
11.2.1
Auto-Reload Mode
The auto-reload mode is selected when the bit CP/RL2 in register T2CON is zero. In this
mode, Timer 2 counts to an overflow value and then reloads its register contents with a
16-bit start value for a fresh counting sequence. The overflow condition is indicated by
setting bit TF2 in the T2CON register. This will then generate an interrupt request to the
core. The overflow flag TF2 must be cleared by software.
The auto-reload mode is further classified into two categories depending upon the DCEN
control bit in register T2MOD.
11.2.1.1 Up/Down Count Disabled
If DCEN = 0, the up-down count selection is disabled. The timer, therefore, functions as
a pure up counting timer only. The operational block diagram is shown in Figure 11-5.
If the T2CON register bit EXEN2 = 0, the timer starts to count up to a maximum of FFFFH
once the timer is started by setting the bit TR2 in register T2CON to 1. Upon overflow,
bit TF2 is set and the timer register is reloaded with the 16-bit reload value of the RC2
register. This reload value is chosen by software, prior to the occurrence of an overflow
condition. A fresh count sequence is started and the timer counts up from this reload
value as in the previous count sequence.
If EXEN2 = 1, the timer counts up to a maximum of FFFFH once TR2 is set. A 16-bit
reload of the timer registers from register RC2 is triggered either by an overflow condition
or by a negative/positive edge (chosen by the bit EDGESEL in register T2MOD) at input
pin T2EX. If an overflow caused the reload, the overflow flag TF2 is set. If a negative/
positive transition at pin T2EX caused the reload, bit EXF2 in register T2CON is set. In
either case, an interrupt is generated to the core and the timer proceeds to its next count
sequence. The EXF2 flag, similar to the TF2, must be cleared by software.
Note: When T2EX is used for the Timer 2 function, the bit BCON.T2EXIS must be set.
User’s Manual
Timer, V 0.4
11-13
V 0.2, 2005-01
XC866
Timer
PREN
f PCLK
prescaler
( ÷12)
THL2
TR2
Overflow
OR
RC2
TF2
Timer 2
OR
Interrupt
EXF2
EXEN2
T2EX
Figure 11-5 Auto-Reload Mode (DCEN = 0)
11.2.1.2 Up/Down Count Enabled
If DCEN = 1, the up-down count selection is enabled. The direction of count is
determined by the level at input pin T2EX. The operational block diagram is shown in
Figure 11-6.
A logic 1 at pin T2EX sets the Timer 2 to up counting mode. The timer, therefore, counts
up to a maximum of FFFFH. Upon overflow, bit TF2 is set and the timer register is
reloaded with a 16-bit reload value of the RC2 register. A fresh count sequence is started
and the timer counts up from this reload value as in the previous count sequence. This
reload value is chosen by software, prior to the occurrence of an overflow condition.
A logic 0 at pin T2EX sets the Timer 2 to down counting mode. The timer counts down
and underflows when the THL2 value reaches the value stored at register RC2. The
underflow condition sets the TF2 flag and causes FFFFH to be reloaded into the THL2
User’s Manual
Timer, V 0.4
11-14
V 0.2, 2005-01
XC866
Timer
register. A fresh down counting sequence is started and the timer counts down as in the
previous counting sequence.
In this mode, bit EXF2 toggles whenever an overflow or an underflow condition is
detected. This flag, however, does not generate an interrupt request.
FFFF H
(Down count reload)
EXF2
Underflow
PREN
fP CLK
prescaler
Timer 2
( ÷12)
THL2
OR
TF2
Interrupt
TR2
16-bit
Comparator
Overflow
RC2
T2EX
Figure 11-6 Auto-Reload Mode (DCEN = 1)
User’s Manual
Timer, V 0.4
11-15
V 0.2, 2005-01
XC866
Timer
11.2.2
Capture Mode
In order to enter the 16-bit capture mode, bits CP/RL2 and EXEN2 in register T2CON
must be set. In this mode, the down count function must remain disabled. The timer
functions as a 16-bit timer and always counts up to FFFFH, after which, an overflow
condition occurs. Upon overflow, bit TF2 is set and the timer reloads its registers with
0000H. The setting of TF2 generates an interrupt request to the core.
Additionally, with a falling/rising edge (chosen by T2MOD.EDGESEL) on pin T2EX, the
contents of the timer register (THL2) are captured into the RC2 register. If the capture
signal is detected while the counter is being incremented, the counter is first incremented
before the capture operation is performed. This ensures that the latest value of the timer
register is always captured.
When the capture operation is completed, bit EXF2 is set and can be used to generate
an interrupt request. Figure 11-7 describes the capture function of Timer 2.
PB_CLK
÷ 12
THL2
TR2
Overflow
RC2
TF2
Timer 2
OR
Interrupt
EXF2
EXEN2
T2EX
Figure 11-7 Capture Mode
User’s Manual
Timer, V 0.4
11-16
V 0.2, 2005-01
XC866
Timer
11.2.3
Register Map
All Timer 2 register names described in the following sections will be referenced in other
chapters of this document with the module name prefix “T2_”, e.g., T2_T2CON.
The Timer 2 SFRs are located in the standard (non-mapped) SFR area. Table 11-3 lists
the addresses of these SFRs.
Table 11-3
SFR Address List
Address
Register
C0H
T2CON
C1H
T2MOD
C2H
RC2L
C3H
RC2H
C4H
T2L
C5H
T2H
11.2.4
Register Description
Register T2MOD is used to configure Timer 2 for the various modes of operation.
T2MOD
Timer 2 Mode Register
7
6
Reset Value: 00H
5
4
3
0
EDGESEL
PREN
T2PRE
DCEN
r
rw
rw
rw
rw
Field
Bits
Type Description
DCEN
0
rw
User’s Manual
Timer, V 0.4
2
1
0
Up/Down Counter Enable
0
Up/Down Counter function is disabled.
1
Up/Down Counter function is enabled and
controlled by pin T2EX (Up = 1, Down = 0).
11-17
V 0.2, 2005-01
XC866
Timer
Field
Bits
Type Description
T2PRE
[3:1]
rw
Timer 2 Prescaler Bit
Selects the input clock for Timer 2 which is derived
from the peripheral clock.
000 fT2 = fPCLK
001 fT2 = fPCLK/2
010 fT2 = fPCLK/4
011 fT2 = fPCLK/8
100 fT2 = fPCLK/16
Others: reserved
PREN
4
rw
Prescaler Enable
0
Prescaler is disabled and the 2/12 divider
takes effect.
1
Prescaler is enabled (see T2PRE bit) and
the 2/12 divider is bypassed.
EDGESEL
5
rw
Edge Select in Capture Mode/Reload Mode
0
The falling edge at pin T2EX is selected.
1
The rising edge at pin T2EX is selected.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Timer, V 0.4
11-18
V 0.2, 2005-01
XC866
Timer
Register T2CON controls the operating modes of Timer 2. In addition, it contains the
status flags for interrupt generation.
T2CON
Timer 2 Control Register
7
6
TF2
EXF2
rwh
rwh
Reset Value: 00H
5
4
3
2
1
0
0
EXEN2
TR2
0
CP/RL2
r
rw
rwh
r
rw
Field
Bits
Type Description
CP/RL2
0
rw
Capture/Reload Select
0
Reload upon overflow or upon negative/
positive transition at pin T2EX (when
EXEN2 = 1).
1
Capture Timer 2 data register contents on
the negative/positive transition at pin T2EX,
provided EXEN2 = 1.
The negative or positive transition at pin
T2EX is selected by bit EDGESEL.
TR2
2
rwh
Timer 2 Start/Stop Control
0
Stop Timer 2
1
Start Timer 2
EXEN2
3
rw
Timer 2 External Enable Control
0
External events are disabled.
1
External events are enabled in capture/
reload mode.
EXF2
6
rwh
Timer 2 External Flag
In capture/reload mode, this bit is set by hardware
when a negative/positive transition occurs at pin
T2EX, if bit EXEN2 = 1. An interrupt request to the
core is generated, unless bit DCEN = 1. This bit
must be cleared by software.
TF2
7
rwh
Timer 2 Overflow/Underflow Flag
Set by a Timer 2 overflow/underflow. Must be
cleared by software.
0
1, [5:4] r
User’s Manual
Timer, V 0.4
Reserved
Returns 0 if read; should be written with 0.
11-19
V 0.2, 2005-01
XC866
Timer
Register RC2 is used for a 16-bit reload of the timer count upon overflow or a capture of
current timer count depending on the mode selected.
RC2L
Timer 2 Reload/Capture Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
RC2L
rwh
RC2H
Timer 2 Reload/Capture Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
RC2H
rwh
Field
Bits
RC2
[7:0] of rwh
RC2L,
[7:0] of
RC2H
User’s Manual
Timer, V 0.4
Type Description
Reload/Capture Value
If CP/RL2 = 0, these contents are loaded into the
timer register upon an overflow condition.
If CP/RL2 = 1, this register is loaded with the
current timer count upon a negative/positive
transition at pin T2EX when EXEN2 = 1.
11-20
V 0.2, 2005-01
XC866
Timer
Register T2 holds the current 16-bit value of the Timer 2 count.
T2L
Timer 2 Register Low
7
6
Reset Value: 00H
5
4
3
2
1
0
THL2
rwh
T2H
Timer 2 Register High
7
6
Reset Value: 00H
5
4
3
2
1
0
THL2
rwh
Field
Bits
THL2
[7:0] of rwh
T2L,
[7:0] of
T2H
User’s Manual
Timer, V 0.4
Type Description
Timer 2 Value
These bits indicate the current timer value.
11-21
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12
Capture/Compare Unit 6
The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which
can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor
control. The CCU6 also supports special control modes for block commutation and
multi-phase machines. The block diagram of the CCU6 module is shown in Figure 12-1.
The timer T12 can function in capture and/or compare mode for its three channels. The
timer T13 can work in compare mode only.
The multi-channel control unit generates output patterns, which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal
modulation.
Timer T12 Features:
• Three capture/compare channels, each channel can be used either as a capture or as
a compare channel
• Supports generation of a three-phase PWM (six outputs, individual signals for
highside and lowside switches)
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Generation of center-aligned and edge-aligned PWM
• Supports single-shot mode
• Supports many interrupt request sources
• Hysteresis-like control mode
Timer T13 Features:
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock frequency
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Supports single-shot mode
Additional Features:
•
•
•
•
•
•
•
Implements block commutation for Brushless DC-drives
Position detection via Hall-sensor pattern
Automatic rotational speed measurement for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
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XC866
Capture/Compare Unit 6
module kernel
compare
channel 2
1
compare
channel 3
compare
capture
T13
compare
start
compare
interrupt
control
1
2
3
2
2
trap
control
3
trap input
1
multichannel
control
output select
clock
control
channel 1
deadtime
control
Hall input
T12
1
output select
channel 0
address
decoder
1
CTRAP
CCPOS2
CCPOS1
CCPOS0
CC62
COUT62
CC61
COUT61
CC60
COUT60
COUT63
T13HR
T12HR
input / output control
port control
CCU6_block_diagram
Figure 12-1 CCU6 Block Diagram
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Capture/Compare Unit 6
12.1
Functional Description
12.1.1
Timer T12
The timer T12 is built with three channels in capture/compare mode. The input clock for
timer T12 can be from fCCU6 to a maximum of fCCU6/128 and is configured by bit field
T12CLK. In order to support higher clock frequencies, an additional prescaler factor of
1/256 can be enabled for the prescaler of T12 if bit T12PRE = 1.
The timer period, compare values, passive state selects bits and passive levels bits are
written to shadow registers and not directly to the actual registers, while the read access
targets the registers actually used (except for the three compare channels, where both
the actual and the shadow registers can be read). The transfer from the shadow registers
to the actual registers is enabled by setting the shadow transfer enable bit STE12.
If this transfer is enabled, the shadow registers are copied to the respective registers as
soon as the associated timer reaches the value zero the next time (being cleared in
edge-aligned mode or counting down to 1 in center-aligned mode). When timer T12 is
operating in center-aligned mode, it will also copy the registers (if enabled by STE12) if
it reaches the currently programmed period value (counting up).
When timer T12 is stopped, the shadow transfer takes place immediately if the
corresponding bit STE12 is set. Once the transfer is complete, the respective bit STE12
is cleared automatically.
Figure 12-2 shows an overview of Timer T12.
=1?
one-match
=0?
zero-match
=?
period-match
16
=?
T12PR
T12PS
period shadow transfer
compare shadow transfer
compare-match
16
CC6xR
CC6xSR
capture events
according to
bitfield MSEL6x
16
counter
register T12
T12clk
CCU6_T12_overv
Figure 12-2 T12 Overview
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Capture/Compare Unit 6
12.1.1.1 Timer Configuration
Register T12 represents the counting value of timer T12. It can be written only while timer
T12 is stopped. Write actions while T12 is running are not taken into account. Register
T12 can always be read by software.
In edge-aligned mode, T12 only counts up, whereas in center-aligned mode, T12 can
count up and down.
Timer T12 can be started and stopped by using bit T12R by hardware or software.
• Bit field T12RSEL defines the event on pin T12HR: rising edge, falling edge, or either
of these two edges, that can set the run bit T12R by hardware.
• If bit field T12RSEL = 00B, the external setting of T12R is disabled and the timer run
bit can only be controlled by software. Bit T12R is set/reset by software by setting bit
T12RR or T12RS.
• In single-shot mode, bit T12R is reset by hardware according to the function defined
by bit T12SSC. If bit T12SSC = 1, the bit T12R is reset by hardware when:
– T12 reaches its period value in edge-aligned mode
– T12 reaches the value 1 while counting down in center-aligned mode
Register T12 can be reset to zero by setting bit T12RES. Setting of T12RES has no
impact on run bit T12R.
12.1.1.2 Counting Rules
With reference to the T12 input clock, the counting sequence is defined by the following
counting rules:
T12 in edge-aligned mode (Bit CTM = 0):
The count direction is set to counting up (CDIR = 0). The counter is reset to zero if a
period-match is detected, and the T12 shadow register transfer takes place if STE12 = 1.
T12 in center-aligned mode (Bit CTM = 1):
• The count direction is set to counting up (CDIR = 0) if a one-match is detected while
counting down.
• The count direction is set to counting down (CDIR = 1) if a period-match is detected
while counting up.
• If STE12 = 1, shadow transfer takes place when:
– a period-match is detected while counting up
– a one-match is detected while counting down
The timer T12 prescaler is reset when T12 is not running to ensure reproducible timings
and delays.
12.1.1.3 Switching Rules
Compare actions take place in parallel for the three compare channels. Depending on
the count direction, the compare matches have different meanings. In order to get the
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Capture/Compare Unit 6
PWM information independent of the output levels, two different states have been
introduced for the compare actions: the active state and the passive state. Both these
states are used to generate the desired PWM as a combination of the control by T13, the
trap control unit and the multi-channel control unit. If the active state is interpreted as a
1 and the passive state as a 0, the state information is combined with a logical AND
function.
•
•
•
active AND active = active
active AND passive = passive
passive AND passive = passive
The compare states change with the detected compare-matches and are indicated by
the CC6xST bits. The compare states of T12 are defined as follows:
• passive if the counter value is below the compare value
• active if the counter value is above the compare value
This leads to the following switching rules for the compare states:
• set to the active state when the counter value reaches the compare value
counting up
• reset to the passive state when the counter value reaches the compare value
counting down
• reset to the passive state in case of a zero-match without compare-match
counting up
• set to the active state in case of a zero-match with a parallel compare-match
counting up
while
while
while
while
T12clk
compare-match
2
2
1
T12
1
0
active
compare
state
passive
CCU6_T12_center_cm2
Figure 12-3 Compared States for Compare Value = 2
The switching rules are considered only while the timer is running. As a result, write
actions to the timer registers while the timer is stopped do not lead to compare actions.
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Capture/Compare Unit 6
12.1.1.4 Compare Mode of T12
In compare mode, the registers CC6xR (x = 0 - 2) are the actual compare registers for
T12. The values stored in CC6xR are compared (all three channels in parallel) to the
counter value of T12. The register CC6xR can only be read by software and the
modification of the value is done by a shadow register transfer from register CC6xSR.
Register T12PR contains the period value for timer T12. The period value is compared
to the actual counter value of T12 and the resulting counter actions depend on the
defined counting rules.
Figure 12-4 shows an example in the center-aligned mode without dead-time. The bit
CC6xST indicates the occurrence of a capture or compare event of the corresponding
channel. It can be set (if it is 0) by the following events:
• a software set (MCC6xS)
• a compare set event (T12 counter value above the compare value) if the T12 runs and
if the T12 set event is enabled
• upon a capture set event
The bit CC6xST can be reset (if it is 1) by the following events:
• a software reset (MCC6xR)
• a compare reset event (T12 counter value below the compare value) if the T12 runs
and if the T12 reset event is enabled (including in single-shot mode at the end of the
T12 period)
• a reset event in the hysteresis-like control mode
The bit CC6xPS represents passive state select bit. The timer T12’s two output lines
(CC6x, COUT6x) can be selected to be in the passive state while CC6xST is 0 (with
CC6xPS = 0) or while CC6xST is 1 (with CC6xPS = 1).
The output level that is driven while the output is in the passive state is defined by the
corresponding bit in bit field PSL.
Hardware modifications of the compare state bits are only possible while timer T12 is
running. Therefore, the bit T12R can be used to enable/disable the modification by
hardware.
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12-6
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XC866
Capture/Compare Unit 6
period
value
compare
value
T12
0
CC6xST
Pin CC6x
(CC6xPS=0,
PSL=0)
Pin COUT6x
(COUT6xPS=1,
PSL=0)
passive
active
passive
active
passive
active
CCU6_T12_comp_states
Figure 12-4 Compare States of Timer T12
For the hysteresis-like compare mode (MSEL6x = 1001B) (see Section 12.1.1.9), the
setting of the compare state bit is possible only while the corresponding input
CCPOSx = 1 (inactive).
If the hall sensor mode (MSEL6x = 1000B) is selected (see Section 12.1.6), the
compare state bits of the compare channels 1 and 2 are modified by the timer T12 in
order to indicate that a programmed time interval has elapsed.
The set is only generated when bit CC6xST is reset; a reset can only take place when
the bit is set. Thus, the events triggering the set and reset actions of the CC6xST bit must
be combined. This OR-combination of the resulting set and reset permits the reload of
the dead-time counter to be triggered (see Figure 12-5). This is triggered only if bit
CC6xST is changed, permitting a correct PWM generation with dead-time and the
complete duty cycle range of 0% to 100% in edge-aligned and center-aligned modes.
12.1.1.5 Duty Cycle of 0% and 100%
These counting and switching rules ensure a PWM functionality in the full range between
0% and 100% duty cycle (duty cycle = active time/total PWM period). In order to obtain
a duty cycle of 0% (compare state never active), a compare value of T12P+1 must be
programmed (for both compare modes). A compare value of 0 will lead to a duty cycle
of 100% (compare state always active).
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Capture/Compare Unit 6
12.1.1.6 Dead-time Generation
In most cases, the switching behavior of the connected power switches is not
symmetrical with respect to the times needed to switch on and to switch off. A general
problem arises if the time taken to switch on is less than the time to switch off the power
device. This leads to a short-circuit in the inverter bridge leg, which may damage the
entire system. In order to solve this problem by hardware, the CCU6 contains a
programmable dead-time counter, which delays the passive to active edge of the
switching signals (the active to passive edge is not delayed).
T12
Center-aligned
T12
Edge-aligned
CC6xST
CC6xST
DTCx_o
Pin CC6x
(CC6xPS=0,
PSL=0)
Pin COUT6x
(COUT6xPS=1,
PSL=0)
CC6xST AND DTCx_o
CC6xST AND DTCx_o
Figure 12-5 PWM-signals with Dead-time Generation
Register T12DTC controls the dead-time generation for the timer T12 compare
channels. Each channel can be independently enabled/disabled for dead-time
generation by bit DTEx. If enabled, the transition from passive state to active state is
delayed by the value defined by bit field DTM (8-bit down counter, clocked with T12CLK).
The dead-time counter can only be reloaded when it is zero.
Each of the three channels works independently with its own dead-time counter, trigger
and enable signals. The value of bit field DTM is valid for all three channels.
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Capture/Compare Unit 6
12.1.1.7 Capture Mode
In capture mode, the bits CC6xST indicate the occurrence of the selected capture event
according to the bit fields MSEL6x.
• MSEL6x = 01XXB, double register capture mode (see Table 12-5)
• MSEL6x = 101XB or 11XXB, multi-input capture modes (see Table 12-7)
A rising and/or a falling edge on the pins CC6x or CCPOSx can be selected as the
capture event that is used to transfer the contents of timer T12 to the CC6xR and
CC6xSR registers. In order to work in capture mode, the capture pins must be configured
as inputs.
There are several ways to store the captured values in the registers. For example, in
double register capture mode, the timer value is stored in the channel shadow register
CC6xSR. The value previously stored in this register is simultaneously copied to the
channel register CC6xR. The software can then check the newly captured value while
still preserving the possibility of reading the value captured earlier.
Note: In capture mode, a shadow transfer can be requested according to the shadow
transfer rules, except for the capture/compare registers that are left unchanged.
12.1.1.8 Single-Shot Mode
The single-shot mode of timer T12 is selected when bit T12SSC is set to 1. In single-shot
mode, the timer T12 stops automatically at the end of its counting period. Figure 12-6
shows the functionality at the end of the timer period in edge-aligned and center-aligned
modes. If the end of period event is detected while bit T12SSC is set, the bit T12R and
all CC6xST bits are reset.
edge-aligned mode
T12P
T12P-1
center-aligned mode
period-match
while counting up
T12P-2
2
if T12SSC = '1'
0
1
T12
T12R
CC6xST
if T12SSC = '1'
one-match while
counting down
0
T12
T12R
CC6xST
CCU6_T12_singleshot
Figure 12-6 End of Single-Shot Mode of T12
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12-9
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Capture/Compare Unit 6
12.1.1.9 Hysteresis-Like Control Mode
The hysteresis-like control mode (MSEL6x = 1001B) offers the possibility of switching off
the PWM output, if the input CCPOSx becomes 0, by resetting bit CC6xST. This can be
used as a simple motor control feature by using a comparator to indicate, for example,
over-current. While CCPOSx = 0, the PWM outputs of the corresponding channel are
driving their passive levels. The setting of bit CC6xST is only possible while
CCPOSx = 1. Figure 12-7 shows an example of hysteresis-like control mode.
This mode can be used to introduce a timing-related behavior to a hysteresis controller.
A standard hysteresis controller detects if a value exceeds a limit and switches its output
according to the compare result. Depending on the operating conditions, the switching
frequency and the duty cycle may change constantly.
Period value
Compare
value
0
T12
Edge-aligned mode
Period value
Compare
value
T12
0
Center-aligned mode
CC6xST
Pin CC6x
(CC6xPS=0,
PSL=0)
Pin COUT6x
(COUT6xPS=1
PSL=0)
Pin CCPOSx
Figure 12-7 Hysteresis-Like Control Mode
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Capture/Compare Unit 6
12.1.2
Timer T13
The timer T13 is similar to timer T12, except that it has only one channel in compare
mode. The counter can only count up (similar to the edge-aligned mode of T12). The
input clock for timer T13 can be from fCCU6 to a maximum of fCCU6/128 and is configured
by bit field T13CLK. In order to support higher clock frequencies, an additional prescaler
factor of 1/256 can be enabled for the prescaler of T13 if bit T13PRE = 1.
The T13 shadow transfer, in case of a period-match, is enabled by bit STE13. During the
T13 shadow transfer, the contents of register CC63SR are transferred to register
CC63R. Both registers can be read by software, while only the shadow register can be
written by software.
The bits CC63PS, T13IM and PSL63 have shadow bits. The contents of these shadow
bits are transferred to the actually used bits during the T13 shadow transfer. Write
actions target the shadow bits, while read actions deliver the value of the actually used
bits.
=0?
zero-match
period-match
=?
16
=?
T13PR
compare-match
16
16
CC63R
counter
register T13
T13PS
T13 shadow transfer
CC63SR
T13clk
CCU6_t13_overv
Figure 12-8 T13 Overview
Timer T13 counts according to the same counting and switching rules as timer T12 in
edge-aligned mode. Figure 12-8 shows an overview of Timer T13.
12.1.2.1 Timer Configuration
Register T13 represents the counting value of timer T13. It can be written only while the
timer T13 is stopped. Write actions are not taken into account while T13 is running.
Register T13 can always be read by software. Timer T13 supports only edge-aligned
mode (counting up).
Timer T13 can be started and stopped by using bit T13R by hardware or software.
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Capture/Compare Unit 6
• Bit T13R is set/reset by software by setting bit T13RR or T13RS.
• In single-shot mode, if bit T13SSC = 1, the bit T13R is reset by hardware when T13
reaches its period value.
• Bit fields T13TEC and T13TED select the trigger event that will set bit T13R for
synchronization of different T12 compare events.
The T13 counter register can be reset to zero by setting bit T13RES. Setting of T13RES
has no impact on bit T13R.
12.1.2.2 Compare Mode
Register CC63R is the actual compare register for T13. The value stored in CC63R is
compared to the counter value of T13. The register CC63R can only be read by software
and the modification of the value is done by a shadow register transfer from register
CC63SR. The corresponding shadow register CC63SR can be read and written by
software.
Register T13PR contains the period value for timer T13. The period value is compared
to the actual counter value of T13 and the resulting counter actions depend on the
defined counting rules.
The bit CC63ST indicates the occurrence of a compare event of the corresponding
channel. It can be set (if it is 0) by the following events:
• a software set (MCC63S)
• a compare set event (T13 counter value above the compare value) if the T13 runs and
if the T13 set event is enabled
The bit CC63ST can be reset (if it is 1) by the following events:
• a software reset (MCC63R)
• a compare reset event (T13 counter value below the compare value) if the T13 runs
and if the T13 reset event is enabled (including in single-shot mode at the end of the
T13 period)
Timer T13 is used to modulate the other output signals with a T13 PWM. In order to
decouple COUT63 from the internal modulation, the compare state can be selected
independently by bits T13IM and COUT63PS.
12.1.2.3 Single-Shot Mode
The single-shot mode of timer T13 is selected when bit T13SSC is set to 1. In single-shot
mode, the timer T13 stops automatically at the end of its counting period. If the end of
period event is detected while bit T13SSC is set, the bit T13R and the bit CC63ST are
reset.
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Capture/Compare Unit 6
12.1.2.4 Synchronization of T13 to T12
The timer T13 can be synchronized on a T12 event. The events include:
•
•
•
•
•
•
•
a T12 compare event on channel 0
a T12 compare event on channel 1
a T12 compare event on channel 2
any T12 compare event on channel 0, 1, or 2
a period-match of T12
a zero-match of T12 (while counting up)
any edge of inputs CCPOSx
The bit fields T13TEC and T13TED select the event that is used to start timer T13. This
event sets bit T13R by hardware and T13 starts counting. Combined with the single-shot
mode, this can be used to generate a programmable delay after a T12 event.
5
compare-match while
counting up
T12
4
3
2
1
0
2
1
T13
0
T13R
CCU6_T13_sync
Figure 12-9 Synchronization of T13 to T12
Figure 12-9 shows the synchronization of T13 to a T12 event. The selected event in this
example is a compare-match (compare value = 2) while counting up. The clocks of T12
and T13 can be different (use other prescaler factor), but in this example T12CLK is
shown as equal to T13CLK for the sake of simplicity.
12.1.3
Modulation Control
The modulation control part combines the different modulation sources (CC6x_T12_o
and COUT6x_T12_o are the output signals that are configured with CC6xPS/
COUT6xPS; MOD_T13_o is the output signal after T13 Inverted Modulation (T13IM)).
Each modulation source can be individually enabled per output line. Furthermore, the
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Capture/Compare Unit 6
trap functionality is taken into account to disable the modulation of the corresponding
output line during the trap state (if enabled).
OR
T12MODENx
CC6x_T12_o,
COUT6x_T12_o
T13MODENx
MOD_T13_o
MCMEN
MCMPx
TRPENx
TRPS
O
R
A
N
D
O
R
0 = passive state
1 = active state
O
R
1
to output
pin CC6x,
COUT6x
0
PSLx
A
N
D
(1 x for each T12-related output)
CCU6_mod_ctr
Figure 12-10 Modulation Control of T12-related Outputs
For each of the six T12-related output lines (represented by “x”) in the Figure 12-10:
•
•
•
•
•
T12MODENx enables the modulation by a PWM pattern generated by timer T12
T13MODENx enables the modulation by a PWM pattern generated by timer T13
MCMPx chooses the multi-channel patterns
TRPENx enables the trap functionality
PSLx defines the output level that is driven while the output is in the passive state
As shown in Figure 12-11, the modulation control part for the T13-related output
COUT63 combines the T13 output signal (COUT63_T13_o is the output signal that is
configured by COUT63PS) and the enable bit ECT13O with the trap functionality. The
output level of the passive state is selected by bit PSL63.
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Capture/Compare Unit 6
ECT13O
COUT63_T13_o
A
N
D
A
N
D
0 = passive state
1 = active state
1
0
TRPEN13
TRPS
A
N
D
to output
pin
COUT63
PSL63
CCU6_T13_mod_ctr
Figure 12-11 Modulation Control of the T13-related Output COUT63
Figure 12-12 shows a modulation control example for CC60 and COUT60.
T13
CC60 (MCMP0, no modulation)
COUT60 (MCMP1, no modulation)
CC60 (T12, no modulation)
COUT60 (T12, no modulation)
CC60
(MCMP0 modulated with T12)
COUT60
(MCMP1 modulated with T12)
CC60
(MCMP0 modulated with T12 and 13)
COUT60
(MCMP1 modulated with T12 and T13)
Figure 12-12 Modulation Control Example for CC60 and COUT60
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Capture/Compare Unit 6
12.1.4
Trap Handling
The trap functionality permits the PWM outputs to react to the state of the input pin
CTRAP. This functionality can be used to switch off the power devices if the trap input
becomes active (e.g., as emergency stop).
During the trap state, the selected outputs are forced into the passive state and no active
modulation is possible. The trap state is entered immediately by hardware if the CTRAP
input signal becomes active and the trap function is enabled by bit TRPPEN. It can also
be entered by software by setting bit TRPF (trap input flag), thus leading to TRPS = 1
(trap state indication flag). The trap state can be left when the input is inactive by
software control and synchronized to the following events:
• TRPF is automatically reset after CTRAP becomes inactive (if TRPM2 = 0)
• TRPF must be reset by software after CTRAP becomes inactive (if TRPM2 = 1)
• synchronized to T12 PWM after TRPF is reset
(T12 period-match in edge-aligned mode or one-match while counting down in
center-aligned mode)
• synchronized to T13 PWM after TRPF is reset
(T13 period-match)
• no synchronization to T12 or T13
T12
T13
TRPF
CTRAP active
TRPS
sync. to T13
TRPS
sync. to T12
TRPS
no sync.
CCU6_trap_sync
Figure 12-13 Trap State Synchronization (with TRM2 = 0)
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Capture/Compare Unit 6
12.1.5
Multi-Channel Mode
The multi-channel mode offers the possibility of modulating all six T12-related outputs.
The bits in bit field MCMP are used to select the outputs that may become active. If the
multi-channel mode is enabled (bit MCMEN = 1), only those outputs that have a 1 at the
corresponding bit positions in bit field MCMP may become active.
This bit field has its own shadow bit field MCMPS, which can be written by software. The
transfer of the new value in MCMPS to the bit field MCMP can be triggered by and
synchronized to T12 or T13 events. This structure permits the software to write the new
value, which is then taken into account by the hardware at a well-defined moment and
synchronized to a PWM period. This avoids unintended pulses due to unsynchronized
modulation sources (T12, T13, SW).
write by software
SW
SEL
Correct
Hall Event
T13pm
T12pm
T12om
6
MCMPS
reset
O
R
set
R
O
R
A
N
D
T12c1cm
MCMP
6
no action
to modulation
selection
T12zm
write to
bitfield
MCMPS
with
STRMCM =
'1'
clear
T13zm
shadow transfer
interrupt
direct
set
SW
SYN
STR
IDLE
CCU6_mod_sync_int
Figure 12-14 Modulation Selection and Synchronization
Figure 12-14 shows the modulation selection for the multi-channel mode. The event that
triggers the update of bit field MCMP is chosen by SWSEL. If the selected switching
event occurs, the reminder flag R is set. This flag monitors the update request and it is
automatically reset when the update takes place. In order to synchronize the update of
MCMP to a PWM generated by T12 or T13, bit field SWSYN allows the selection of the
User’s Manual
CCU6, V 0.4
12-17
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
synchronization event, which leads to the transfer from MCMPS to MCMP. Due to this
structure, an update takes place with a new PWM period.
The update can also be requested by software by writing to bit field MCMPS with the
shadow transfer request bit STRMCM set. If this bit is set during the write action to the
register, the flag R is automatically set. By using this, the update takes place completely
under software control.
A shadow transfer interrupt can be generated when the shadow transfer takes place.
The possible hardware request events are:
•
•
•
•
•
a T12 period-match while counting up (T12pm)
a T12 one-match while counting down (T12om)
a T13 period-match (T13pm)
a T12 compare-match of channel 1 (T12c1cm)
a correct Hall event
The possible hardware synchronization events are:
• a T12 zero-match while counting up (T12zm)
• a T13 zero-match (T13zm)
User’s Manual
CCU6, V 0.4
12-18
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.1.6
Hall Sensor Mode
In Brushless-DC motors, the next multi-channel state values depend on the pattern of
the Hall inputs. There is a strong correlation between the Hall pattern (CURH) and the
modulation pattern (MCMP). Because of different machine types, the modulation
pattern for driving the motor can vary. Therefore, it is beneficial to have wide flexibility in
defining the correlation between the Hall pattern and the corresponding modulation
pattern. The CCU6 offers this by having a register which contains the actual Hall pattern
(CURHS), the next expected Hall pattern (EXPHS), and its output pattern (MCMPS). At
every correct Hall event, a new Hall pattern with its corresponding output pattern can be
loaded (from a predefined table) by software into the register MCMOUTS. This shadow
register can also be loaded by a write action on MCMOUTS with bit STRHP = 1. In case
of a phase delay (generated by T12 channel 1), a new pattern can be loaded when the
multi-channel mode shadow transfer (indicated by bit STR) occurs.
12.1.6.1 Sampling of the Hall Pattern
The Hall pattern (on CCPOSx) is sampled with the module clock fCCU6. By using the
dead-time counter DTC0 (mode MSEL6x = 1000B), a hardware noise filter can be
implemented to suppress spikes on the Hall inputs. In case of a Hall event, the DTC0 is
reloaded, and it starts counting and generates a delay between the detected event and
the sampling point. After the counter value of 1 is reached, the CCPOSx inputs are
sampled (without noise and spikes) and are compared to the current Hall pattern
(CURH) and to the expected Hall pattern (EXPH). If the sampled pattern equals to the
current pattern, it means that the edge on CCPOSx was due to a noise spike and no
action will be triggered (implicit noise filter by delay). If the sampled pattern equals to the
next expected pattern, the edge on CCPOSx was a correct Hall event, and the bit CHE
is set which causes an interrupt.
If it is required that the multi-channel mode and the Hall pattern comparison work
independently of timer T12, the delay generation by DTC0 can be bypassed. In this case,
timer T12 can be used for other purposes.
Bit field HSYNC defines the source for the sampling of the Hall input pattern and the
comparison to the current and the expected Hall pattern bit fields. The hall compare
action can also be triggered by software by writing a 1 to bit SWHC. The triggering
sources for the sampling by hardware include:
•
•
•
•
•
•
•
Any edge at one of the inputs CCPOSx (x = 0 - 2)
A T13 compare-match
A T13 period-match
A T12 period-match (while counting up)
A T12 one-match (while counting down)
A T12 compare-match of channel 0 (while counting up)
A T12 compare-match of channel 0 (while counting down)
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CCU6, V 0.4
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Capture/Compare Unit 6
This correct Hall event can be used as a transfer request event for register MCMOUTS.
The transfer from MCMOUTS to MCMOUT transfers the new CURH-pattern as well as
the next EXPH-pattern. In case the sampled Hall inputs were neither the current nor the
expected Hall pattern, the bit WHE (wrong Hall event) is set, which can also cause an
interrupt and set the IDLE mode to clear MCMP (modulation outputs are inactive). To
restart from IDLE, the transfer request of MCMOUTS must be initiated by software (bit
STRHP and bit fields SWSEL/SWSYN).
12.1.6.2 Brushless-DC Control
For Brushless-DC motors, there is a special mode (MSEL6x = 1000B) which is triggered
by a change of the Hall inputs (CCPOSx). In this case, T12’s channel 0 acts in capture
function, channel 1 and 2 act in compare function (without output modulation), and the
multi-channel-block is used to trigger the output switching together with a possible
modulation of T13.
After the detection of a valid Hall edge, the T12 count value is captured to channel 0
(representing the actual motor speed) and the T12 is reset. When the timer reaches the
compare value in channel 1, the next multi-channel state is switched by triggering the
shadow transfer of bit field MCMP (if enabled in bit field SWEN). This trigger event can
be combined with several conditions which are necessary to implement noise filtering
(correct Hall event) and to synchronize the next multi-channel state to the modulation
sources (avoiding spikes on the output lines). This compare function of channel 1 can be
used as a phase delay for the position input to the output switching which is necessary
if a sensorless back-EMF technique is used instead of Hall sensors. The compare value
in channel 2 can be used as a time-out trigger (interrupt) indicating that the motor’s
destination speed is far below the desired value (which can be caused by an abnormal
load change). In this mode, the modulation of T12 must be disabled (T12MODENx = 0).
CC60
act. speed
CC61
phase delay
CC62
timeout
Ch0 gets
captured
value for
act. speed
Ch2 compare
for timeout
capture
event resets
T12
Ch1 compare
for phase delay
CCPOS0
1
1
1
0
0
CCPOS1
0
0
1
1
1
CCPOS2
1
0
0
0
1
0
0
1
CC6x
COUT6y
Figure 12-15 Timer T12 Brushless-DC Mode (all MSEL6x = 1000B)
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CCU6, V 0.4
12-20
V 0.2, 2005-01
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Capture/Compare Unit 6
Table 12-1 lists an example of block commutation in BLDC motor control. If the input
signal combination CCPOS0-CCPOS2 changes its state, the outputs CC6x and
COUT6x are set to their new states.
Figure 12-16 shows the block commutation in rotate left mode and Figure 12-17 shows
the block commutation in rotate right mode. These figures are derived directly from
Table 12-1.
Table 12-1
Mode
Block Commutation Control Table
CCPOS0CCPOS2 Inputs
CC60 - CC62
Outputs
CCP CCP CCP CC60
OS0 OS1 OS2
CC61
CC62
COUT60 - COUT62
Outputs
COUT6 COUT6 COUT6
0
1
2
Rotate left,
1
0° phase shift 1
0
1
inactive inactive active
inactive active
0
0
inactive inactive active
active
inactive inactive
1
1
0
inactive active
inactive active
inactive inactive
0
1
0
inactive active
inactive inactive inactive active
0
1
1
active
inactive inactive inactive inactive active
0
0
1
active
inactive inactive inactive active
inactive
1
1
0
active
inactive inactive inactive active
inactive
1
0
0
active
inactive inactive inactive inactive active
1
0
1
inactive active
inactive inactive inactive active
0
0
1
inactive active
inactive active
0
1
1
inactive inactive active
active
0
1
0
inactive inactive active
inactive active
Slow-down
X
X
X
inactive inactive inactive active
Idle1)
X
X
X
inactive inactive inactive inactive inactive inactive
Rotate right
1)
inactive
inactive inactive
inactive inactive
active
inactive
active
In case the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (Wrong
Hall Event) is set, which can also cause an interrupt and set the IDLE mode to clear MCMP (modulation outputs
are inactive).
User’s Manual
CCU6, V 0.4
12-21
V 0.2, 2005-01
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Capture/Compare Unit 6
CCPOS0
1
1
1
0
0
0
CCPOS1
0
0
1
1
1
0
CCPOS2
1
0
0
0
1
1
CC60
CC61
CC62
COUT60
COUT61
COUT62
Figure 12-16 Block Commutation in Rotate Left Mode
CCPOS0
1
1
1
0
0
0
CCPOS1
1
0
0
0
1
1
CCPOS2
0
0
1
1
1
0
CC60
CC61
CC62
COUT60
COUT61
COUT62
Figure 12-17 Block Commutation in Rotate Right Mode
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CCU6, V 0.4
12-22
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.1.7
Interrupt Generation
The interrupt generation can be triggered by the interrupt event or the setting of the
corresponding interrupt bit in register IS by software. The interrupt is generated
independently of the interrupt flag in register IS. Register IS can only be read; write
actions have no impact on the contents of this register. The software can set or reset the
bits individually by writing to register ISS or register ISR, respectively.
If enabled by the related interrupt enable bit in register IEN, an interrupt will be
generated. The interrupt sources of the CCU6 module can be mapped to four interrupt
output lines by programming the interrupt node pointer register INP.
12.1.8
Port Connection
Table 12-2 shows how bits and bit fields must be programmed for the required I/O
functionality of the CCU6 I/O lines. This table also shows the values of the peripheral
input select registers.
Table 12-2
CCU6 I/O Control Selection
Port Lines
PISEL Register Bit
Input/Output Control
Register Bits
I/O
P3.6/CTRAP_0
ISTRP = 00B
P3_DIR.P6 = 0B
Input
P2.2/CTRAP_1
ISTRP = 01B
P2_DIR.P2 = 0B
Input
P0.2/CTRAP_2
ISTRP = 10B
P0_DIR.P2 = 0B
Input
P2.0/CCPOS0_0
ISPOS0 = 00B
P2_DIR.P0 = 0B
Input
P1.5/CCPOS0_1
ISPOS0 = 01B
P1_DIR.P5 = 0B
Input
P2.1/CCPOS1_0
ISPOS1 = 00B
P2_DIR.P1 = 0B
Input
P1.6/CCPOS1_1
ISPOS1 = 01B
P1_DIR.P6 = 0B
Input
P2.2/CCPOS2_0
ISPOS2 = 00B
P2_DIR.P2 = 0B
Input
P1.7/CCPOS2_1
ISPOS2 = 01B
P1_DIR.P7 = 0B
Input
P3.0/CC60
–
P3_DIR.P0 = 0B
Input
–
P3_DIR.P0 = 1B
Output
P3_ALTSEL0.P0 = 1B
P3_ALTSEL1.P0 = 0B
P3.1/COUT60
–
P3_DIR.P1 = 1B
Output
P3_ALTSEL0.P1 = 1B
P3_ALTSEL1.P1 = 0B
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CCU6, V 0.4
12-23
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Table 12-2
CCU6 I/O Control Selection (cont’d)
Port Lines
PISEL Register Bit
Input/Output Control
Register Bits
I/O
P3.2/CC61_0
ISCC61 = 00
P3_DIR.P2 = 0B
Input
–
P3_DIR.P2 = 1B
Output
P3_ALTSEL0.P2 = 1B
P3_ALTSEL1.P2 = 0B
P0.0/CC61_1
ISCC61 = 01
P0_DIR.P0 = 0B
Input
–
P0_DIR.P0 = 1B
Output
P0_ALTSEL0.P0 = 0B
P0_ALTSEL1.P0 = 1B
P3.3/COUT61_0
–
P3_DIR.P3 = 1B
Output
P3_ALTSEL0.P3 = 1B
P3_ALTSEL1.P3 = 0B
P0.0/COUT61_1
–
P0_DIR.P0 = 1B
Output
P0_ALTSEL0.P0 = 0B
P0_ALTSEL1.P0 = 1B
P3.4/CC62_0
ISCC62= 00
P3_DIR.P4 = 0B
Input
–
P3_DIR.P4 = 1B
Output
P3_ALTSEL0.P4 = 1B
P3_ALTSEL1.P4 = 0B
P0.4/CC62_1
ISCC62 = 01
P0_DIR.P4 = 0B
Input
–
P0_DIR.P4 = 1B
Output
P0_ALTSEL0.P4 = 0B
P0_ALTSEL1.P4 = 1B
P3.5/COUT62_0
–
P3_DIR.P5 = 1B
Output
P3_ALTSEL0.P5 = 1B
P3_ALTSEL1.P5 = 0B
P0.5/COUT62_1
–
P0_DIR.P5 = 1B
Output
P0_ALTSEL0.P5 = 0B
P0_ALTSEL1.P5 = 1B
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CCU6, V 0.4
12-24
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Table 12-2
CCU6 I/O Control Selection (cont’d)
Port Lines
PISEL Register Bit
Input/Output Control
Register Bits
I/O
P3.7/COUT63_0
–
P3_DIR.P7 = 1B
Output
P3_ALTSEL0.P7 = 1B
P3_ALTSEL1.P7 = 0B
P0.3/COUT63_1
–
P0_DIR.P3 = 1B
Output
P0_ALTSEL0.P3 = 0B
P0_ALTSEL1.P3 = 1B
P1.6/T12HR_0
IST12HR = 00
P1_DIR.P6 = 0B
Input
P0.0/T12HR_1
IST12HR = 01
P0_DIR.P0 = 0B
Input
P2.0/T12HR_2
IST12HR = 10
P2_DIR.P0 = 0B
Input
P1.7/T13HR_0
IST13HR = 00
P1_DIR.P7 = 0B
Input
P0.1/T13HR_1
IST13HR = 01
P0_DIR.P1 = 0B
Input
P2.1/T13HR_2
IST13HR = 10
P2_DIR.P1 = 0B
Input
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CCU6, V 0.4
12-25
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.2
Register Map
The CCU6 SFRs are located in the standard memory area (RMAP = 0) and are
organized into 4 pages. The CCU6_PAGE register is located at address A3H. It contains
the page value and the page control information.
CCU6_PAGE
Page Register for CCU6
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
0
PAGE
w
w
r
rw
0
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page
address.
When read, the value indicates the currently active
page = addr [y:x+1].
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
User’s Manual
CCU6, V 0.4
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
12-26
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
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CCU6, V 0.4
12-27
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
All CCU6 register names described in the following sections will be referenced in other
chapters of this document with the module name prefix “CCU6_”, e.g.,
CCU6_CC63SRL.
The addresses (non-mapped) of the CCU6 SFRs are listed in Table 12-3.
Table 12-3
SFR Address List for Pages 0-3
Address
Page 0
Page 1
Page 2
Page 3
9AH
CC63SRL
CC63RL
T12MSELL
MCMOUTL
9BH
CC63SRH
CC63RH
T12MSELH
MCMOUTH
9CH
TCTR4L
T12PRL
IENL
ISL
9DH
TCTR4H
T12PRH
IENH
ISH
9EH
MCMOUTSL
T13PRL
INPL
PISEL0L
9FH
MCMOUTSH
T13PRH
INPH
PISEL0H
A4H
ISRL
T12DTCL
ISSL
PISEL2
A5H
ISRH
T12DTCH
ISSH
–
A6H
CMPMODIFL
TCTR0L
PSLR
–
A7H
CMPMODIFH
TCTR0H
MCMCTR
–
FAH
CC60SRL
CC60RL
TCTR2L
T12L
FBH
CC60SRH
CC60RH
TCTR2H
T12H
FCH
CC61SRL
CC61RL
MODCTRL
T13L
FDH
CC61SRH
CC61RH
MODCTRH
T13H
FEH
CC62SRL
CC62RL
TRPCTRL
CMPSTATL
FFH
CC62SRH
CC62RH
TRPCTRH
CMPSTATH
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CCU6, V 0.4
12-28
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.3
Register Description
Table 12-4 shows all registers associated with the CCU6 module.
Table 12-4
CCU6 Module Registers
Register
Short Name
Register Full Name
Description
see
System Registers
PISEL0L
Port Input Select Register 0 Low
Page 12-31
PISEL0H
Port Input Select Register 0 High
Page 12-33
PISEL2
Port Input Select Register 2
Page 12-34
T12L
Timer T12 Counter Register Low
Page 12-35
T12H
Timer T12 Counter Register High
Page 12-35
T12PRL
Timer T12 Period Register Low
Page 12-36
T12PRH
Timer T12 Period Register High
Page 12-36
CC6xRL
Capture/Compare Register for Channel CC6x
Low
Page 12-37
CC6xRH
Capture/Compare Register for Channel CC6x
High
Page 12-37
CC6xSRL
Capture/Compare Shadow Register for Channel Page 12-38
CC6x Low
CC6xSRH
Capture/Compare Shadow Register for Channel Page 12-38
CC6x High
T12DTCL
Dead-Time Control Register for Timer T12 Low
Page 12-39
T12DTCH
Dead-Time Control Register for Timer T12 High
Page 12-39
T13L
Timer T13 Counter Register Low
Page 12-41
T13H
Timer T13 Counter Register High
Page 12-41
T13PRL
Timer T13 Period Register Low
Page 12-42
T13PRH
Timer T13 Period Register High
Page 12-42
CC63RL
Capture/Compare Register for Channel CC63
Low
Page 12-43
CC63RH
Capture/Compare Register for Channel CC63
High
Page 12-44
T12 Registers
T13 Registers
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CCU6, V 0.4
12-29
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Table 12-4
CCU6 Module Registers (cont’d)
Register
Short Name
Register Full Name
Description
see
CC63SRL
Capture/Compare Shadow Register for Channel Page 12-44
CC63 Low
CC63SRH
Capture/Compare Shadow Register for Channel Page 12-44
CC63 High
CCU6 Control Registers
CMPSTATL
Compare State Register Low
Page 12-45
CMPSTATH
Compare State Register High
Page 12-46
CMPMODIFL
Compare State Modification Register Low
Page 12-47
CMPMODIFH
Compare State Modification Register High
Page 12-47
TCTR0L
Timer Control Register 0 Low
Page 12-48
TCTR0H
Timer Control Register 0 High
Page 12-49
TCTR2L
Timer Control Register 2 Low
Page 12-52
TCTR2H
Timer Control Register 2 High
Page 12-54
TCTR4L
Timer Control Register 4 Low
Page 12-55
TCTR4H
Timer Control Register 4 High
Page 12-56
Modulation Control Registers
MODCTRL
Modulation Control Register Low
Page 12-57
MODCTRH
Modulation Control Register High
Page 12-58
TRPCTRL
Trap Control Register Low
Page 12-60
TRPCTRH
Trap Control Register High
Page 12-61
PSLR
Passive State Level Register
Page 12-63
MCMOUTSL
Multi_Channel Mode Output Shadow Register
Low
Page 12-65
MCMOUTSH
Multi_Channel Mode Output Shadow Register
High
Page 12-66
MCMOUTL
Multi_Channel Mode Output Register Low
Page 12-67
MCMOUTH
Multi_Channel Mode Output Register High
Page 12-69
MCMCTR
Multi_Channel Mode Control Register
Page 12-70
T12MSELL
T12 Capture/Compare Mode Select Register
Low
Page 12-72
User’s Manual
CCU6, V 0.4
12-30
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Table 12-4
CCU6 Module Registers (cont’d)
Register
Short Name
Register Full Name
Description
see
T12MSELH
T12 Capture/Compare Mode Select Register
High
Page 12-73
Interrupt Control Registers
ISL
Interrupt Status Register Low
Page 12-77
ISH
Interrupt Status Register High
Page 12-78
ISSL
Interrupt Status Set Register Low
Page 12-80
ISSH
Interrupt Status Set Register High
Page 12-81
ISRL
Interrupt Status Reset Register Low
Page 12-82
ISRH
Interrupt Status Reset Register High
Page 12-83
IENL
Interrupt Enable Register Low
Page 12-84
IENH
Interrupt Enable Register High
Page 12-85
INPL
Interrupt Node Pointer Register Low
Page 12-88
INPH
Interrupt Node Pointer Register High
Page 12-89
Note: For all CCU6 registers: the write-only bit positions (indicated by “w”) always deliver
the value of 0 when they are read out. If a hardware and a software request to
modify a bit occur simultaneously, the software wins.
12.3.1
System Registers
12.3.1.1 Port Input Selection
Registers PISEL0 and PISEL2 contain bit fields that select the actual input signals for
the module inputs. This permits the pin functionality of the device to be adapted as per
the application’s requirements. The output pins are chosen according to the registers in
the ports.
PISEL0L
Port Input Select Register 0 Low
7
6
5
Reset Value: 00H
4
3
2
1
0
ISTRP
ISCC62
ISCC61
ISCC60
rw
rw
rw
rw
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CCU6, V 0.4
12-31
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
ISCC60
[1:0]
rw
Input Select for CC60
This bit field defines the port pin that is used for the
CC60 capture input signal.
00
The input pin is selected for CC60_0.
01
Reserved
10
Reserved
11
Reserved
ISCC61
[3:2]
rw
Input Select for CC61
This bit field defines the port pin that is used for the
CC61 capture input signal.
00
The input pin is selected for CC61_0.
01
The input pin is selected for CC61_1.
10
Reserved
11
Reserved
ISCC62
[5:4]
rw
Input Select for CC62
This bit field defines the port pin that is used for the
CC62 capture input signal.
00
The input pin is selected for CC62_0.
01
The input pin is selected for CC62_1.
10
Reserved
11
Reserved
ISTRP
[7:6]
rw
Input Select for CTRAP
This bit field defines the port pin that is used for the
CTRAP input signal.
00
The input pin is selected for CTRAP_0.
01
The input pin is selected for CTRAP_1.
10
The input pin is selected for CTRAP_2.
11
Reserved
User’s Manual
CCU6, V 0.4
12-32
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
PISEL0H
Port Input Select Register 0 High
7
6
5
Reset Value: 00H
4
3
2
1
0
IST12HR
ISPOS2
ISPOS1
ISPOS0
rw
rw
rw
rw
Field
Bits
Type Description
ISPOS0
[1:0]
rw
Input Select for CCPOS0
This bit field defines the port pin that is used for the
CCPOS0 input signal.
00
The input pin is selected for CCPOS0_0.
01
The input pin is selected for CCPOS0_1.
10
Reserved
11
Reserved
ISPOS1
[3:2]
rw
Input Select for CCPOS1
This bit field defines the port pin that is used for the
CCPOS1 input signal.
00
The input pin is selected for CCPOS1_0.
01
The input pin is selected for CCPOS1_1.
10
Reserved
11
Reserved
ISPOS2
[5:4]
rw
Input Select for CCPOS2
This bit field defines the port pin that is used for the
CCPOS2 input signal.
00
The input pin is selected for CCPOS2_0.
01
The input pin is selected for CCPOS2_1.
10
Reserved
11
Reserved
IST12HR
[7:6]
rw
Input Select for T12HR
This bit field defines the port pin that is used for the
T12HR input signal.
00
The input pin is selected for T12HR _0.
01
The input pin is selected for T12HR_1.
10
The input pin is selected for T12HR_2.
11
Reserved
User’s Manual
CCU6, V 0.4
12-33
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
PISEL2
Port Input Select Register 2
7
6
Reset Value: 00H
5
4
3
2
1
0
0
IST13HR
r
rw
Field
Bits
Type Description
IST13HR
[1:0]
rw
Input Select for T13HR
This bit field defines the port pin that is used for the
T13HR input signal.
00
The input pin is selected for T13HR_0.
01
The input pin is selected for T13HR_1.
10
The input pin is selected for T13HR_2.
11
Reserved
0
[7:2]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
CCU6, V 0.4
12-34
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.3.2
Timer T12 – Related Registers
The generation of the patterns for a 3-channel PWM is based on timer T12. The registers
related to timer T12 can be concurrently updated (with well-defined conditions) in order
to ensure consistency of the three PWM channels.
Timer T12 supports capture and compare modes, which can be independently selected
for its three channels CC60, CC61 and CC62.
T12L
Timer T12 Counter Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
T12CVL
rwh
T12H
Timer T12 Counter Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
T12CVH
rwh
Field
Bits
Type Description
T12CV
[7:0] of
T12L,
[7:0] of
T12H
rwh
Timer T12 Counter Value
This register represents the 16-bit counter value of
timer T12.
Note: Once timer T12 is stopped, the internal clock divider is reset in order to ensure
reproducible timings and delays.
User’s Manual
CCU6, V 0.4
12-35
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
T12PRL
Timer T12 Period Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
T12PVL
rwh
T12PRH
Timer T12 Period Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
T12PVH
rwh
Field
Bits
T12PV
[7:0] of
rwh
T12PRL,
[7:0] of
T12PRH
User’s Manual
CCU6, V 0.4
Type Description
T12 Period Value
The value T12PV defines the counter value for T12,
which leads to a period-match. On reaching this
value, the timer T12 is set to zero (edge-aligned
mode) or changes its count direction to down
counting (center-aligned mode).
12-36
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
CC6xRL (x = 0 - 2)
Capture/Compare Register for Channel CC6x Low
7
6
5
4
3
Reset Value: 00H
2
1
0
CC6xVL (x = 0 - 2)
rh
CC6xRH (x = 0 - 2)
Capture/Compare Register for Channel CC6x High
7
6
5
4
3
Reset Value: 00H
2
1
0
CC6xVH (x = 0 - 2)
rh
Field
Bits
CC6xV
(x = 0 - 2)
[7:0] of
rh
CC6xRL,
[7:0] of
CC6xRH
User’s Manual
CCU6, V 0.4
Type Description
Channel x Capture/Compare Value
In compare mode, the bit fields CC6xV contain the
values that are compared to the T12 counter value. In
capture mode, the captured value of T12 can be read
from these registers.
12-37
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
CC6xSRL (x = 0 - 2)
Capture/Compare Shadow Register for Channel CC6x Low
7
6
5
4
3
2
Reset Value: 00H
1
0
CC6xSL (x = 0 - 2)
rwh
CC6xSRH (x = 0 - 2)
Capture/Compare Shadow Register for Channel CC6x High
7
6
5
4
3
2
Reset Value: 00H
1
0
CC6xSH (x = 0 - 2)
rwh
Field
Bits
CC6xS
(x = 0 - 2)
[7:0] of
rwh
CC6xSRL,
[7:0] of
CC6xSRH
User’s Manual
CCU6, V 0.4
Type Description
Shadow Register for Channel x Capture/Compare
Value
In compare mode, the contents of bit fields CC6xS
are transferred to the bit fields CC6xV during a
shadow transfer. In capture mode, the captured value
of T12 can be read from these registers.
12-38
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
T12DTCL
Dead-Time Control Register for Timer T12 Low
7
6
5
4
3
Reset Value: 00H
2
1
0
DTM
rw
Field
Bits
Type Description
DTM
[7:0]
rw
Dead-Time
Bit field DTM determines the programmable delay
between switching from the passive state to the
active state of the selected outputs. The switching
from the active state to the passive state is not
delayed.
T12DTCH
Dead-Time Control Register for Timer T12 High
Reset Value: 00H
7
6
5
4
3
2
1
0
0
DTR2
DTR1
DTR0
0
DTE2
DTE1
DTE0
r
rh
rh
rh
r
rw
rw
rw
Field
Bits
Type Description
DTE0
DTE1
DTE2
0
1
2
rw
User’s Manual
CCU6, V 0.4
Dead-Time Enable Bits
Bits DTEx (x = 0 - 2) enable and disable the deadtime generation for each compare channel (0, 1, 2)
of timer T12.
0
Dead-time generation is disabled. The
corresponding outputs switch from the passive
state to the active state (according to the
actual compare status) without any delay.
1
Dead-time generation is enabled. The
corresponding outputs switch from the passive
state to the active state (according to the
compare status) with the delay programmed in
bit field DTM.
12-39
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
DTR0
DTR1
DTR2
4
5
6
rh
Dead-Time Run Indication Bits
Bits DTRx (x = 0 - 2) indicate the status of the deadtime generation for each compare channel (0, 1, 2)
of timer T12.
0
The value of the corresponding dead-time
counter channel is 0.
1
The value of the corresponding dead-time
counter channel is not 0.
0
3, 7
r
Reserved
Returns 0 if read; should be written with 0.
Note: The dead-time counters are clocked with the same frequency as T12.
This structure allows symmetrical dead-time generation in center-aligned and in
edge-aligned PWM mode. A duty cycle of 50% leads to CC6x; COUT6x is
switched on for: 0.5 * period - dead-time.
Note: The dead-time counters are not reset by bit T12RES, but by bit DTRES.
User’s Manual
CCU6, V 0.4
12-40
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.3.3
Timer T13 – Related Registers
The generation of the patterns for a single-channel PWM is based on timer T13. The
registers related to timer T13 can be concurrently updated (with well-defined conditions)
in order to ensure consistency of the PWM signal. Timer T13 can be synchronized to
several timer T12 events.
Timer T13 supports only compare mode on its compare channel CC63.
T13L
Timer T13 Counter Register Low
7
6
Reset Value: 00H
5
4
3
2
1
0
T13CVL
rwh
T13H
Timer T13 Counter Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
T13CVH
rwh
Field
Bits
Type Description
T13CV
[7:0] of
T13L,
[7:0] of
T13H
rwh
Timer T13 Counter Value
This register represents the 16-bit counter value of
timer T13.
Note: Once timer T13 is stopped, the internal clock divider is reset in order to ensure
reproducible timings and delays.
User’s Manual
CCU6, V 0.4
12-41
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
T13PRL
Timer T13 Period Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
T13PVL
rwh
T13PRH
Timer T13 Period Register High
7
6
5
Reset Value: 00H
4
3
2
1
0
T13PVH
rwh
Field
Bits
T13PV
[7:0] of
rwh
T13PRL,
[7:0] of
T13PRH
User’s Manual
CCU6, V 0.4
Type Description
T13 Period Value
The value T13PV defines the counter value for T13,
which leads to a period-match. On reaching this
value, the timer T13 is set to zero.
12-42
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
CC63RL
Capture/Compare Register for Channel CC63 Low
7
6
5
4
3
Reset Value: 00H
2
1
0
CC63VL
rh
CC63RH
Capture/Compare Register for Channel CC63 High
7
6
5
4
3
Reset Value: 00H
2
1
0
CC63VH
rh
Field
Bits
Type Description
CC63V
[7:0] of
CC63RL,
[7:0] of
CC63RH
rh
User’s Manual
CCU6, V 0.4
Channel CC63 Compare Value
The bit fields CC63V contain the values that are
compared to the T13 counter value.
12-43
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
CC63SRL
Capture/Compare Shadow Register for Channel CC63 Low
7
6
5
4
3
2
Reset Value: 00H
1
0
CC63SL
rw
CC63SRH
Capture/Compare Shadow Register for Channel CC63 High
7
6
5
4
3
2
Reset Value: 00H
1
0
CC63SH
rw
Field
Bits
CC63S
[7:0] of
rw
CC63SRL,
[7:0] of
CC63SRH
User’s Manual
CCU6, V 0.4
Type Description
Shadow Register for Channel CC63 Compare
Value
The contents of bit fields CC63S are transferred to
the bit fields CC63V during a shadow transfer.
12-44
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.3.4
Capture/Compare Control Registers
Register CMPSTAT contains status bits that monitor the current capture and compare
state, and control bits that define the active/passive state of the compare channels.
CMPSTATL
Compare State Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
0
CC
63ST
CC
POS
0
rh
CC
61ST
CC
60ST
rh
CC
POS
1
rh
CC
62ST
r
CC
POS
2
rh
rh
rh
rh
Field
Bits
Type Description
CC60ST
CC61ST
CC62ST
CC63ST
0
1
2
6
rh
Capture/Compare State Bits
Bits CC6xST monitor the state of the capture/compare
channels. Bits CC6xST (x = 0 - 2) are related to T12;
bit CC63ST is related to T13.
0
In compare mode, the timer count is less than
the compare value. In capture mode, the
selected edge has not been detected since the
bit was reset by software.
1
In compare mode, the counter value is greater
than or equal to the compare value. In capture
mode, the selected edge has been detected.
CCPOS0
CCPOS1
CCPOS2
3
4
5
rh
Sampled Hall Pattern Bits
Bits CCPSOx (x = 0 - 2) indicate the value of the input
Hall pattern that has been compared to the current and
expected value. The value is sampled when the event
hcrdy (Hall compare ready) occurs.
0
The input CCPOSx has been sampled as 0.
1
The input CCPOSx has been sampled as 1.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
1)
1)
These bits are set and reset according to the T12 and T13 switching rules.
User’s Manual
CCU6, V 0.4
12-45
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
CMPSTATH
Compare State Register High
7
T13
IM
6
5
C
C
OUT63PS OUT62PS
rwh
rwh
rwh
Reset Value: 00H
4
3
2
1
0
CC
62PS
C
OUT61PS
CC
61PS
C
OUT60PS
CC
60PS
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
CC60PS
CC61PS
CC62PS
COUT60PS
COUT61PS
COUT62PS
COUT63PS
0
2
4
1
3
5
6
rwh
Passive State Select for Compare Outputs
Bits CC6xPS and COUT6xPS (x = 0 - 2) select the
state of the corresponding compare channel, which is
considered to be the passive state. During the passive
state, the passive level (defined in register PSLR) is
driven by the output pin. Bits CC6xPS and COUT6xPS
are related to T12, while bit CC63PS is related to T13.
0
The corresponding compare output drives
passive level while CC6xST is 0.
1
The corresponding compare output drives
passive level while CC6xST is 1.
In capture mode, these bits are not used.
T13IM2)
7
rwh
T13 Inverted Modulation
Bit T13IM inverts the T13 signal for the modulation of
the CC6x and COUT6x (x = 0 - 2) signals.
0
T13 output is not inverted.
1
T13 output is inverted for further modulation.
1)
1)
These bits have shadow bits and are updated in parallel to the capture/compare registers of T12 and T13,
respectively. A read action targets the actually used values, whereas a write action targets the shadow bits.
2)
This bit has a shadow bit and is updated in parallel to the compare and period registers of T13. A read action
targets the actually used values, whereas a write action targets the shadow bit.
User’s Manual
CCU6, V 0.4
12-46
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register CMPMODIF contains control bits that allow modification by software of the
capture/compare state bits.
CMPMODIFL
Compare State Modification Register Low
7
6
5
0
MCC
63S
r
w
4
Reset Value: 00H
3
2
1
0
0
MCC
62S
MCC
61S
MCC
60S
r
w
w
w
CMPMODIFH
Compare State Modification Register High
7
6
5
0
MCC
63R
r
w
4
Reset Value: 00H
3
2
1
0
0
MCC
62R
MCC
61R
MCC
60R
r
w
w
w
Field
Bits
Type Description
MCC60S1)
MCC61S1)
MCC62S1)
MCC63S1)
MCC60R2)
MCC61R2)
MCC62R2)
MCC63R2)
0
1
2
6
0
1
2
6
w
0
[5:3], r
7
Capture/Compare Status Modification Bits
These bits are used to set (MCC6xS) or reset
(MCC6xR) the corresponding CC6xST bits by
software.
This feature allows the user to individually change the
status of the output lines by software, e.g., when the
corresponding compare timer is stopped. This enables
a manipulation of CC6xST bits by a single data write
action.
MCC6xR, MCC6xS =
0,0 Bit CC6xST is not changed.
0,1 Bit CC6xST is set.
1,0 Bit CC6xST is reset.
1,1 Reserved (toggle)
Reserved
Returns 0 if read; should be written with 0.
1)
This bit field is contained in the Compare State Modification Register Low.
2)
This bit field is contained in the Compare State Modification Register High.
User’s Manual
CCU6, V 0.4
12-47
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register TCTR0 controls the basic functionality of both timers T12 and T13.
TCTR0L
Timer Control Register 0 Low
Reset Value: 00H
7
6
5
4
3
2
1
0
CTM
CDIR
STE12
T12R
T12
PRE
T12CLK
rw
rh
rh
rh
rw
rw
Field
Bits
Type Description
T12CLK
[2:0]
rw
Timer T12 Input Clock Select
Selects the input clock for timer T12 which is derived
from the peripheral clock according to the equation
fT12 = fCCU6/2<T12CLK>.
000 fT12 = fCCU6
001 fT12 = fCCU6/2
010 fT12 = fCCU6/4
011 fT12 = fCCU6/8
100 fT12 = fCCU6/16
101 fT12 = fCCU6/32
110 fT12 = fCCU6/64
111 fT12 = fCCU6/128
T12PRE
3
rw
Timer T12 Prescaler Bit
In order to support higher clock frequencies, an
additional prescaler factor of 1/256 can be enabled for
the prescaler for T12.
0
The additional prescaler for T12 is disabled.
1
The additional prescaler for T12 is enabled.
T12R1)
4
rh
Timer T12 Run Bit
T12R starts and stops timer T12. It is set/reset by
software by setting bit T12RR or T12RS, or it is reset
by hardware according to the function defined by bit
T12SSC.
0
Timer T12 is stopped.
1
Timer T12 is running.
User’s Manual
CCU6, V 0.4
12-48
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
STE12
5
rh
Timer T12 Shadow Transfer Enable
Bit STE12 enables or disables the shadow transfer of
the T12 period value, the compare values and passive
state select bits and levels from their shadow registers
to the actual registers if a T12 shadow transfer event
is detected. Bit STE12 is cleared by hardware after the
shadow transfer.
A T12 shadow transfer event is a period-match while
counting up or a one-match while counting down.
0
The shadow register transfer is disabled.
1
The shadow register transfer is enabled.
CDIR
6
rh
Count Direction of Timer T12
This bit is set/reset according to the counting rules of
T12.
0
T12 counts up.
1
T12 counts down.
CTM
7
rw
T12 Operating Mode
0
Edge-aligned mode:
T12 always counts up and continues counting
from zero after reaching the period value.
1
Center-aligned mode:
T12 counts down after detecting a period-match
and counts up after detecting a one-match.
1)
A concurrent set/reset action on T12R (from T12SSC, T12RR or T12RS) will have no effect. The bit T12R will
remain unchanged.
TCTR0H
Timer Control Register 0 High
7
6
Reset Value: 00H
5
4
3
0
STE
13
T13R
T13
PRE
T13CLK
r
rh
rh
rw
rw
User’s Manual
CCU6, V 0.4
12-49
2
1
0
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
T13CLK
[2:0]
rw
Timer T13 Input Clock Select
Selects the input clock for timer T13 which is derived
from the peripheral clock according to the equation
fT13 = fCCU6/2<T13CLK>.
000 fT13 = fCCU6
001 fT13 = fCCU6/2
010 fT13 = fCCU6/4
011 fT13 = fCCU6/8
100 fT13 = fCCU6/16
101 fT13 = fCCU6/32
110 fT13 = fCCU6/64
111 fT13 = fCCU6/128
T13PRE
3
rw
Timer T13 Prescaler Bit
In order to support higher clock frequencies, an
additional prescaler factor of 1/256 can be enabled for
the prescaler for T13.
0
The additional prescaler for T13 is disabled.
1
The additional prescaler for T13 is enabled.
T13R1)
4
rh
Timer T13 Run Bit
T13R starts and stops timer T13. It is set/reset by
software by setting bit T13RR or T13RS, or it is set/
reset by hardware according to the function defined by
bit T13SSC, and bit fields T13TEC and T13TED.
0
Timer T13 is stopped.
1
Timer T13 is running.
STE13
5
rh
Timer T13 Shadow Transfer Enable
Bit STE13 enables or disables the shadow transfer of
the T13 period value, the compare value and passive
state select bit and level from their shadow registers to
the actual registers if a T13 shadow transfer event is
detected. Bit STE13 is cleared by hardware after the
shadow transfer.
A T13 shadow transfer event is a period-match.
0
The shadow register transfer is disabled.
1
The shadow register transfer is enabled.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
1)
A concurrent set/reset action on T13R (from T13SSC, T13TEC, T13RR or T13RS) will have no effect. The bit
T12R will remain unchanged.
User’s Manual
CCU6, V 0.4
12-50
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Note: A write action to the bit field T12CLK or bit T12PRE is only taken into account
when the timer T12 is not running (T12R = 0). A write action to the bit field T13CLK
or bit T13PRE is only taken into account when the timer T13 is not running
(T13R = 0).
User’s Manual
CCU6, V 0.4
12-51
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register TCTR2 controls the single-shot and the synchronization functionality of both
timers T12 and T13. Both timers can run in single-shot mode. In this mode, they stop
their counting sequence automatically after one counting period with a count value of
zero. The single-shot mode and the synchronization of T13 to T12 allow the generation
of events with a programmable delay after well-defined PWM actions of T12. For
example, this feature can be used to trigger AD conversions, after a specified delay (to
avoid problems due to switching noise), synchronously to a PWM event.
TCTR2L
Timer Control Register 2 Low
7
6
5
Reset Value: 00H
4
3
2
1
0
0
T13
TED
T13
TEC
T13
SSC
T12
SSC
r
rw
rw
rw
rw
Field
Bits
Type Description
T12SSC
0
rw
Timer T12 Single-Shot Control
This bit controls the single-shot mode of T12.
0
The single-shot mode is disabled, no hardware
action on T12R.
1
The single-shot mode is enabled, the bit T12R is
reset by hardware if:
– T12 reaches its period value in edge-aligned
mode
– T12 reaches the value 1 while counting down
in center-aligned mode.
In parallel to the reset action of bit T12R, the bits
CC6xST (x = 0 - 2) are reset.
T13SSC
1
rw
Timer T13 Single-Shot Control
This bit controls the single-shot mode of T13.
0
No hardware action on T13R
1
The single-shot mode is enabled, the bit T13R is
reset by hardware if T13 reaches its period
value.
In parallel to the reset action of bit T13R, the bit
CC63ST is reset.
User’s Manual
CCU6, V 0.4
12-52
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
T13TEC
[4:2]
rw
T13 Trigger Event Control
Bit field T13TEC selects the trigger event to start T13
(automatic set of T13R for synchronization to T12
compare signals) according to following combinations:
000 No action
001 Set T13R on a T12 compare event
on channel 0
010 Set T13R on a T12 compare event
on channel 1
011 Set T13R on a T12 compare event
on channel 2
100 Set T13R on any T12 compare event
on channel 0, 1, or 2
101 Set T13R upon a period-match of T12
110 Set T13R upon a zero-match of T12 (while
counting up)
111 Set T13R on any edge of inputs CCPOSx
T13TED1)
[6:5]
rw
Timer T13 Trigger Event Direction
Bit field T13TED delivers additional information to
control the automatic set of bit T13R in case the trigger
action defined by T13TEC is detected.
00
Reserved, no action
01
While T12 is counting up
10
While T12 is counting down
11
Independent of the count direction of T12
0
7
r
Reserved
Returns 0 if read; should be written with 0.
1)
Example:
If the timer T13 is intended to start at any compare event on T12 (T13TEC = 100B), the trigger event direction
can be programmed to:
- counting up >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting up
- counting down >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting down
- independent of bit CDIR >> each T12 channel 0, 1, 2 compare match triggers T13R
The timer count direction is taken from the value of bit CDIR. As a result, if T12 is running in edge-aligned mode
(counting up only), T13 can only be started automatically if bit field T13TED = 01B or 11B.
User’s Manual
CCU6, V 0.4
12-53
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
TCTR2H
Timer Control Register 2 High
7
6
5
Reset Value: 00H
4
3
2
1
0
0
T13
RSEL
T12
RSEL
r
rw
rw
Field
Bits
Type Description
T12RSEL
[1:0]
rw
Timer T12 External Run Selection
Bit field T12RSEL defines the event of signal T12HR
that can set the run bit T12R by hardware.
00
The external setting of T12R is disabled.
01
Bit T12R is set if a rising edge of signal T12HR
is detected.
10
Bit T12R is set if a falling edge of signal T12HR
is detected.
11
Bit T12R is set if an edge of signal T12HR is
detected.
T13RSEL
[3:2]
rw
Timer T13 External Run Selection
Bit field T13RSEL defines the event of signal T13HR
that can set the run bit T13R by hardware.
00
The external setting of T13R is disabled.
01
Bit T13R is set if a rising edge of signal T13HR
is detected.
10
Bit T13R is set if a falling edge of signal T13HR
is detected.
11
Bit T13R is set if an edge of signal T13HR is
detected.
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
CCU6, V 0.4
12-54
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register TCTR4 allows the software control of the run bits T12R and T13R through
independent set and reset conditions. Furthermore, the timers can be reset (while
running) and the bits STE12 and STE13 can be controlled by software.
TCTR4L
Timer Control Register 4 Low
7
6
T12
STD
T12
STR
w
w
Reset Value: 00H
5
4
3
2
1
0
0
DT
RES
T12
RES
T12
RS
T12
RR
r
w
w
w
w
Field
Bits
Type Description
T12RR
0
w
Timer T12 Run Reset
Setting this bit resets the T12R bit.
0
T12R is not influenced.
1
T12R is cleared, T12 stops counting
T12RS
1
w
Timer T12 Run Set
Setting this bit sets the T12R bit.
0
T12R is not influenced.
1
T12R is set, T12 counts.
T12RES
2
w
Timer T12 Reset
0
No effect on T12
1
The T12 counter register is reset to zero. The
switching of the output signals is according to
the switching rules. Setting of T12RES has no
impact on bit T12R.
DTRES
3
w
Dead-Time Counter Reset
0
No effect on the dead-time counters
1
The three dead-time counter channels are reset
to zero.
T12STR
6
w
Timer T12 Shadow Transfer Request
0
No action
1
STE12 is set, enabling the shadow transfer.
T12STD
7
w
Timer T12 Shadow Transfer Disable
0
No action
1
STE12 is reset without triggering the shadow
transfer.
0
[5:4]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
CCU6, V 0.4
12-55
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
TCTR4H
Timer Control Register 4 High
7
6
5
T13
STD
T13
STR
w
w
Reset Value: 00H
4
3
2
1
0
0
T13
RES
T13
RS
T13
RR
r
w
w
w
Field
Bits
Type Description
T13RR
0
w
Timer T13 Run Reset
Setting this bit resets the T13R bit.
0
T13R is not influenced.
1
T13R is cleared, T13 stops counting.
T13RS
1
w
Timer T13 Run Set
Setting this bit sets the T13R bit.
0
T13R is not influenced.
1
T13R is set, T13 counts.
T13RES
2
w
Timer T13 Reset
0
No effect on T13
1
The T13 counter register is reset to zero. The
switching of the output signals is according to
the switching rules. Setting of T13RES has no
impact on bit T13R.
T13STR
6
w
Timer T13 Shadow Transfer Request
0
No action
1
STE13 is set, enabling the shadow transfer.
T13STD
7
w
Timer T13 Shadow Transfer Disable
0
No action
1
STE13 is reset without triggering the shadow
transfer.
0
[5:3]
r
Reserved
Returns 0 if read; should be written with 0.
Note: A simultaneous write of a 1 to bits which set and reset the same bit will trigger no
action (for example, writing 1 to bits T13RR and T13RS will not modify bit T13R).
The corresponding bit will remain unchanged.
User’s Manual
CCU6, V 0.4
12-56
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.3.5
Modulation Control Registers
12.3.5.1 Global Module Control
Register MODCTR contains control bits that enable the modulation of the corresponding
output signal by PWM pattern generated by the timers T12 and T13. Furthermore, the
multi-channel mode can be enabled as additional modulation source for the output
signals.
MODCTRL
Modulation Control Register Low
5
Reset Value: 00H
7
6
4
3
MCMEN
0
T12MODEN
rw
r
rw
Field
Bits
Type Description
T12MODEN
[5:0]
rw
User’s Manual
CCU6, V 0.4
2
1
0
T12 Modulation Enable
Setting these bits enables the modulation of the
corresponding compare channel by a PWM pattern
generated by timer T12. The bit positions correspond
to the following output signals:
Bit 0 Modulation of CC60
Bit 1 Modulation of COUT60
Bit 2 Modulation of CC61
Bit 3 Modulation of COUT61
Bit 4 Modulation of CC62
Bit 5 Modulation of COUT62
The enable feature of the modulation is defined as
follows:
0
The modulation of the corresponding output
signal by a T12 PWM pattern is disabled.
1
The modulation of the corresponding output
signal by a T12 PWM pattern is enabled.
12-57
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
MCMEN
7
rw
Multi-Channel Mode Enable
0
The modulation of the corresponding output
signal by a multi-channel pattern according to bit
field MCMP is disabled.
1
The modulation of the corresponding output
signal by a multi-channel pattern according to bit
field MCMP is enabled.
0
6
r
Reserved
Returns 0 if read; should be written with 0.
MODCTRH
Modulation Control Register High
5
Reset Value: 00H
7
6
4
3
ECT
13O
0
T13MODEN
rw
r
rw
Field
Bits
Type Description
T13MODEN
[5:0]
rw
User’s Manual
CCU6, V 0.4
2
1
0
T13 Modulation Enable
Setting these bits enables the modulation of the
corresponding compare channel by a PWM pattern
generated by timer T13. The bit positions correspond
to the following output signals:
Bit 0 Modulation of CC60
Bit 1 Modulation of COUT60
Bit 2 Modulation of CC61
Bit 3 Modulation of COUT61
Bit 4 Modulation of CC62
Bit 5 Modulation of COUT62
The enable feature of the modulation is defined as
follows:
0
The modulation of the corresponding output
signal by a T13 PWM pattern is disabled.
1
The modulation of the corresponding output
signal by a T13 PWM pattern is enabled.
12-58
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
ECT13O
7
rw
Enable Compare Timer T13 Output
0
The alternate output function COUT63 is
disabled.
1
The alternate output function COUT63 is
enabled for the PWM signal generated by T13.
0
6
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
CCU6, V 0.4
12-59
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register TRPCTR controls the trap functionality. It contains independent enable bits for
each output signal and control bits to select the behavior in case of a trap condition. The
trap condition is a low level on the CTRAP input pin, which is monitored (inverted level)
by bit TRPF (in register IS). While TRPF = 1 (trap input active), the trap state bit TRPS
(in register IS) is set to 1.
TRPCTRL
Trap Control Register Low
7
6
5
Reset Value: 00H
4
3
2
1
0
0
TRP
M2
TRP
M1
TRP
M0
r
rw
rw
rw
Field
Bits
Type Description
TRPM0,
TRPM1
[1:0]
rw
User’s Manual
CCU6, V 0.4
Trap Mode Control Bits 0, 1
These two bits define the behavior of the selected
outputs when leaving the trap state after the trap
condition has become inactive again.
A synchronization to the timer driving the PWM
pattern avoids unintended short pulses when leaving
the trap state. The combination (TRPM0 and
TRPM1) leads to:
00
The trap state is left (return to normal
operation according to TRPM2) when a zeromatch of T12 (while counting up) is detected
(synchronization to T12).
01
The trap state is left (return to normal
operation according to TRPM2) when a zeromatch of T13 is detected (synchronization to
T13).
10
Reserved
11
The trap state is left (return to normal
operation according to TRPM2) immediately
without any synchronization to T12 or T13.
12-60
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
TRPM2
2
rw
Trap Mode Control Bit 2
0
The trap state can be left (return to normal
operation = bit TRPS = 0) as soon as the input
CTRAP becomes inactive. Bit TRPF is
automatically cleared by hardware if the input
pin CTRAP becomes 1. Bit TRPS is
automatically cleared by hardware if bit TRPF
is 0 and if the synchronization condition
(according to TRPM0 and TRPM1) is
detected.
1
The trap state can be left (return to normal
operation = bit TRPS = 0) as soon as bit TRPF
is reset by software after the input CTRAP
becomes inactive (TRPF is not cleared by
hardware). Bit TRPS is automatically cleared
by hardware if bit TRPF = 0 and if the
synchronization condition (according to
TRPM0 and TRPM1) is detected.
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
TRPCTRH
Trap Control Register High
7
6
TRP
PEN
TRP
EN
13
rw
rw
User’s Manual
CCU6, V 0.4
5
Reset Value: 00H
4
3
2
1
0
TRPEN
rw
12-61
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
TRPEN
[5:0]
rw
Trap Enable Control
Setting these bits enables the trap functionality for the
following corresponding output signals:
Bit 0 Trap functionality of CC60
Bit 1 Trap functionality of COUT60
Bit 2 Trap functionality of CC61
Bit 3 Trap functionality of COUT61
Bit 4 Trap functionality of CC62
Bit 5 Trap functionality of COUT62
The enable feature of the trap functionality is defined
as follows:
0
The trap functionality of the corresponding
output signal is disabled. The output state is
independent of bit TRPS.
1
The trap functionality of the corresponding
output signal is enabled. The output is set to the
passive state while TRPS = 1.
TRPEN13
6
rw
Trap Enable Control for Timer T13
0
The trap functionality for T13 is disabled. Timer
T13 (if selected and enabled) provides PWM
functionality even while TRPS = 1.
1
The trap functionality for T13 is enabled. The
timer T13 PWM output signal is set to the
passive state while TRPS = 1.
TRPPEN
7
rw
Trap Pin Enable
0
The trap functionality based on the input pin
CTRAP is disabled. A trap can only be
generated by software by setting bit TRPF.
1
The trap functionality based on the input pin
CTRAP is enabled. A trap can be generated by
software by setting bit TRPF or by CTRAP = 0.
User’s Manual
CCU6, V 0.4
12-62
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register PSLR defines the passive state level driven by the output pins of the module.
The passive state level is the value that is driven by the port pin during the passive state
of the output. During the active state, the corresponding output pin drives the active state
level, which is the inverted passive state level. The passive state level permits the
adaptation of the driven output levels to the driver polarity (inverted or not inverted) of
the connected power stage.
PSLR
Passive State Level Register
5
Reset Value: 00H
7
6
4
3
2
PSL
63
0
PSL
rwh
r
rwh
1
0
Field
Bits
Type Description
PSL1)
[5:0]
rwh
Compare Outputs Passive State Level
The bits of this bit field define the passive level driven
by the module outputs during the passive state. The bit
positions are:
Bit 0 Passive level for output CC60
Bit 1 Passive level for output COUT60
Bit 2 Passive level for output CC61
Bit 3 Passive level for output COUT61
Bit 4 Passive level for output CC62
Bit 5 Passive level for output COUT62
The value of each bit position is defined as:
0
The passive level is 0.
1
The passive level is 1.
PSL632)
7
rwh
Passive State Level of Output COUT63
This bit field defines the passive level of the output pin
COUT63.
0
The passive level is 0.
1
The passive level is 1.
0
6
r
Reserved
Returns 0 if read; should be written with 0.
1)
Bit field PSL has a shadow register to allow for updates without undesired pulses on the output lines. The bits
are updated with the T12 shadow transfer. A read action targets the actually used values, while a write action
targets the shadow bits.
User’s Manual
CCU6, V 0.4
12-63
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
2)
Bit PSL63 has a shadow register to allow for updates without undesired pulses on the output line. The bit is
updated with the T13 shadow transfer. A read action targets the actually used values, while a write action
targets the shadow bits.
User’s Manual
CCU6, V 0.4
12-64
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.3.5.2 Multi-Channel Control
Register MCMOUTS contains bits that control the output states for multi-channel mode.
Furthermore, the appropriate signals for the block commutation by Hall sensors can be
selected. This register is a shadow register (that can be written) for register MCMOUT,
which indicates the currently active signals.
MCMOUTSL
Multi-Channel Mode Output Shadow Register Low
7
6
5
4
3
STR
MCM
0
MCMPS
w
r
rw
Reset Value: 00H
2
1
0
Field
Bits
Type Description
MCMPS
[5:0]
rw
Multi-Channel PWM Pattern Shadow
Bit field MCMPS is the shadow bit field for bit field
MCMP. The multi-channel shadow transfer is triggered
according to the transfer conditions defined by register
MCMCTR.
STRMCM
7
w
Shadow Transfer Request for MCMPS
Setting this bit during a write action leads to an
immediate update of bit field MCMP by the value
written to bit field MCMPS. This functionality permits
an update triggered by software. When read, this bit
always delivers 0.
0
Bit field MCMP is updated according to the
defined hardware action. The write access to bit
field MCMPS does not modify bit field MCMP.
1
Bit field MCMP is updated by the value written to
bit field MCMPS.
0
6
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
CCU6, V 0.4
12-65
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
MCMOUTSH
Multi-Channel Mode Output Shadow Register High
5
4
3
Reset Value: 00H
7
6
2
1
0
STR
HP
0
CURHS
EXPHS
w
r
rw
rw
Field
Bits
Type Description
EXPHS
[2:0]
rw
Expected Hall Pattern Shadow
Bit field EXPHS is the shadow bit field for bit field
EXPH. The bit field is transferred to bit field EXPH if an
edge on the hall input pins CCPOSx (x = 0 - 2) is
detected.
CURHS
[5:3]
rw
Current Hall Pattern Shadow
Bit field CURHS is the shadow bit field for bit field
CURH. The bit field is transferred to bit field CURH if
an edge on the hall input pins CCPOSx (x = 0 - 2) is
detected.
STRHP
7
w
Shadow Transfer Request for the Hall Pattern
Setting these bits during a write action leads to an
immediate update of bit fields CURH and EXPH by the
value written to bit fields CURHS and EXPHS. This
functionality permits an update triggered by software.
When read, this bit always delivers 0.
0
The bit fields CURH and EXPH are updated
according to the defined hardware action. The
write access to bit fields CURHS and EXPHS
does not modify the bit fields CURH and EXPH.
1
The bit fields CURH and EXPH are updated by
the value written to the bit fields CURHS and
EXPHS.
0
6
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
CCU6, V 0.4
12-66
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register MCMOUT specifies the multi-channel control bits that are currently used.
MCMOUTL
Multi-Channel Mode Output Register Low
5
4
Reset Value: 00H
7
6
3
0
R
MCMP
r
rh
rh
Field
Bits
Type Description
MCMP1)
[5:0]
rh
User’s Manual
CCU6, V 0.4
2
1
0
Multi-Channel PWM Pattern
Bit field MCMP is written by a shadow transfer from
bit field MCMPS. It contains the output pattern for the
multi-channel mode. If this mode is enabled by bit
MCMEN in register MODCTR, the output state of the
following output signal can be modified:
Bit 0 Multi-channel state for output CC60
Bit 1 Multi-channel state for output COUT60
Bit 2 Multi-channel state for output CC61
Bit 3 Multi-channel state for output COUT61
Bit 4 Multi-channel state for output CC62
Bit 5 Multi-channel state for output COUT62
The multi-channel patterns can set the related output
to the passive state.
0
The output is set to the passive state. The
PWM generated by T12 or T13 is not taken
into account.
1
The output can deliver the PWM generated by
T12 or T13 (according to register MODCTR).
12-67
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
R
6
rh
Reminder Flag
This reminder flag indicates that the shadow transfer
from bit field MCMPS to MCMP has been requested
by the selected trigger source. This bit is cleared
when the shadow transfer takes place and while
MCMEN = 0.
0
No shadow transfer from MCMPS to MCMP is
requested
1
A shadow transfer from MCMPS to MCMP has
been requested by the selected trigger source,
but has not been executed, because the
selected synchronization condition has not
occurred.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
1)
While IDLE = 1, bit field MCMP is cleared.
User’s Manual
CCU6, V 0.4
12-68
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
MCMOUTH
Multi-Channel Mode Output Register High
7
6
5
4
Reset Value: 00H
3
2
1
0
CURH
EXPH
r
rh
rh
0
Field
Bits
Type Description
EXPH1)
[2:0]
rh
Expected Hall Pattern
Bit field EXPH is written by a shadow transfer from bit
field EXPHS. The contents are compared after every
detected edge at the hall input pins in order to detect
the occurrence of the next desired (expected) hall
pattern or a wrong pattern.
If the current hall pattern at the hall input pins is equal
to the bit field EXPH, bit CHE (correct hall event) is set
and an interrupt request is generated (if enabled by bit
ENCHE).
If the current hall pattern at the hall input pins is not
equal to the bit fields CURH or EXPH, bit WHE (wrong
hall event) is set and an interrupt request is generated
(if enabled by bit ENWHE).
CURH
[5:3]
rh
Current Hall Pattern
Bit field CURH is written by a shadow transfer from bit
field CURHS. The contents are compared after every
detected edge at the hall input pins in order to detect
the occurrence of the next desired (expected) hall
pattern or a wrong pattern.
If the current Hall input pattern is equal to bit field
CURH, the detected edge at the hall input pins was an
invalid transition (e.g., a spike).
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
1)
The bits in the bit fields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx (x = 0 - 2)
in the following order (EXPH.2, EXPH.1, EXPH.0), (CURH.2, CURH.1, CURH.0), (CCPOS2, CCPOS1,
CCPOS0).
User’s Manual
CCU6, V 0.4
12-69
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register MCMCTR contains control bits for the multi-channel functionality.
MCMCTR
Multi-Channel Mode Control Register
7
6
5
Reset Value: 00H
4
3
2
1
0
0
SWSYN
0
SWSEL
r
rw
r
rw
Field
Bits
Type Description
SWSEL
[2:0]
rw
User’s Manual
CCU6, V 0.4
Switching Selection
Bit field SWSEL selects one of the following trigger
request sources (next multi-channel event) for the
shadow transfer from MCMPS to MCMP. The trigger
request is stored in the reminder flag R until the
shadow transfer is done and flag R is cleared
automatically with the shadow transfer. The shadow
transfer takes place synchronously with an event
selected in bit field SWSYN.
000 No trigger request will be generated
001 Correct hall pattern on CCPOSx detected
010 T13 period-match detected (while counting up)
011 T12 one-match (while counting down)
100 T12 channel 1 compare-match detected (phase
delay function)
101 T12 period match detected (while counting up);
else reserved, no trigger request will be
generated
12-70
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
SWSYN
[5:4]
rw
Switching Synchronization
Bit field SWSYN triggers the shadow transfer between
MCMPS and MCMP if it has been requested before
(flag R set by an event selected by SWSEL). This
feature permits the synchronization of the outputs to
the PWM source that is used for modulation (T12 or
T13).
00
Direct; the trigger event directly causes the
shadow transfer
01
T13 zero-match triggers the shadow transfer
10
A T12 zero-match (while counting up) triggers
the shadow transfer
11
Reserved; no action
0
3,
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
Note: The generation of the shadow transfer request by hardware is only enabled if bit
MCMEN = 1.
User’s Manual
CCU6, V 0.4
12-71
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register T12MSEL contains control bits that select the capture/compare functionality of
the three channels of timer T12.
T12MSELL
T12 Capture/Compare Mode Select Register Low
7
6
5
3
2
1
MSEL61
MSEL60
rw
rw
Field
Bits
MSEL60,
MSEL61
[3:0], rw
[7:4]
User’s Manual
CCU6, V 0.4
4
Reset Value: 00H
0
Type Description
Capture/Compare Mode Selection
These bit fields select the operating mode of the three
timer T12 capture/compare channels. Each channel
(n = 0 - 2) can be programmed individually either for
compare or capture operation according to:
0000 Compare outputs disabled, pins CC6n and
COUT6n can be used for I/O pins. No capture
action.
0001 Compare output on pin CC6n, pin COUT6n can
be used for I/O pins. No capture action.
0010 Compare output on pin COUT6n, pin CC6n can
be used for I/O pins. No capture action.
0011 Compare output on pins COUT6n and CC6n
01XX Double-register capture modes,
see Table 12-5.
1000 Hall sensor mode, see Table 12-6.
In order to enable the hall edge detection,
MSEL6x (x = 0 - 2) must be programmed to hall
sensor mode.
1001 Hysteresis-like mode, see Table 12-6
101X Multi-input capture modes, see Table 12-7
11XX Multi-input capture modes, see Table 12-7
12-72
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
T12MSELH
T12 Capture/Compare Mode Select Register High
7
6
5
4
3
Reset Value: 00H
2
1
D
BYP
HSYNC
MSEL62
rw
rw
rw
Field
Bits
Type Description
MSEL62
[3:0]
rw
User’s Manual
CCU6, V 0.4
0
Capture/Compare Mode Selection
These bit fields select the operating mode of the
three timer T12 capture/compare channels. Each
channel (n = 0 - 2) can be programmed individually
either for compare or capture operation according to:
0000 Compare outputs disabled, pins CC6n and
COUT6n can be used for I/O pins. No capture
action.
0001 Compare output on pin CC6n, pin COUT6n
can be used for I/O pins. No capture action.
0010 Compare output on pin COUT6n, pin CC6n
can be used for I/O pins. No capture action.
0011 Compare output on pins COUT6n and CC6n.
01XX Double-register capture modes,
see Table 12-5.
1000 Hall sensor mode, see Table 12-6.
In order to enable the hall edge detection, all
three MSEL6x must be programmed to hall
sensor mode.
1001 Hysteresis-like mode, see Table 12-6.
101X Multi-input capture modes, see Table 12-7.
11XX Multi-input capture modes, see Table 12-7.
12-73
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
HSYNC
[6:4]
rw
Hall Synchronization
Bit field HSYNC defines the source for the sampling
of the Hall input pattern and the comparison to the
current and the expected Hall pattern bit fields. In all
modes, a trigger by software by writing a 1 to bit
SWHC is possible.
000 Any edge at one of the inputs CCPOSx
(x = 0 - 2) triggers the sampling.
001 A T13 compare-match triggers the sampling.
010 A T13 period-match triggers the sampling.
011 The Hall sampling triggered by hardware
sources is switched off.
100 A T12 period-match (while counting up)
triggers the sampling.
101 A T12 one-match (while counting down)
triggers the sampling.
110 A T12 compare-match of channel 0 (while
counting up) triggers the sampling.
111 A T12 compare-match of channel 0 (while
counting down) triggers the sampling.
DBYP
7
rw
Delay Bypass
Bit DBYP determines if the source signal for the
sampling of the Hall input pattern (selected by
HSYNC) uses the dead-time counter DTC0 of timer
T12 as additional delay or if the delay is bypassed.
0
The delay bypass is not active. The dead-time
counter DTC0 generates a delay after the
source signal becomes active.
1
The delay bypass is active. The dead-time
counter DTC0 is not used by the sampling of
the Hall pattern.
Note: In the capture modes, all edges at the CC6x inputs lead to the setting of the
corresponding interrupt status flags in register IS. In order to monitor the selected
capture events at the CCPOSx inputs in the multi-input capture modes, the
CC6xST bits of the corresponding channel are set when detecting the selected
event. The interrupt status bits and the CC6xST bits must be reset by software.
User’s Manual
CCU6, V 0.4
12-74
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Table 12-5
Double-Register Compare Modes
Description
Double-Register Capture Modes
0100 The contents of T12 are stored in CC6nR after a rising edge and in CC6nSR after
a falling edge on the input pin CC6n.
0101 The value stored in CC6nSR is copied to CC6nR after a rising edge on the input
pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow
register CC6nSR. This feature is useful for time measurements between
consecutive rising edges on pins CC6n. COUT6n is I/O pin.
0110 The value stored in CC6nSR is copied to CC6nR after a falling edge on the input
pin CC6n. The actual timer value of T12 is simultaneously stored in the shadow
register CC6nSR. This feature is useful for time measurements between
consecutive falling edges on pins CC6n. COUT6n is I/O pin.
0111 The value stored in CC6nSR is copied to CC6nR after any edge on the input pin
CC6n. The actual timer value of T12 is simultaneously stored in the shadow
register CC6nSR. This feature is useful for time measurements between
consecutive edges on pins CC6n. COUT6n is I/O pin.
Table 12-6
Combined T12 Modes
Description
Combined T12 Modes
1000 Hall sensor mode:
Capture mode for channel 0, compare mode for channels 1 and 2. The contents
of T12 are captured into CC60 at a valid hall event (which is a reference to the
actual speed). CC61 can be used for a phase delay function between hall event
and output switching. CC62 can act as a time-out trigger if the expected hall
event is too late. The value 1000B must be programmed to MSEL0, MSEL1 and
MSEL2 if the hall signals are used. In this mode, the contents of timer T12 are
captured in CC60 and T12 is reset after the detection of a valid hall event. In
order to avoid noise effects, the dead-time counter channel 0 is started after an
edge has been detected at the hall inputs. On reaching the value of 000001B, the
hall inputs are sampled and the pattern comparison is done.
1001 Hysteresis-like control mode with dead-time generation:
The negative edge of the CCPOSx input signal is used to reset bit CC6nST. As
a result, the output signals can be switched to passive state immediately and
switched back to active state (with dead-time) if the CCPOSx is high and the bit
CC6nST is set by a compare event.
User’s Manual
CCU6, V 0.4
12-75
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Table 12-7
Multi-Input Capture Modes
Description
Multi-Input Capture Modes
1010 The timer value of T12 is stored in CC6nR after a rising edge at the input pin
CC6n. The timer value of T12 is stored in CC6nSR after a falling edge at the input
pin CCPOSx.
1011 The timer value of T12 is stored in CC6nR after a falling edge at the input pin
CC6n. The timer value of T12 is stored in CC6nSR after a rising edge at the input
pin CCPOSx.
1100 The timer value of T12 is stored in CC6nR after a rising edge at the input pin
CC6n. The timer value of T12 is stored in CC6nSR after a rising edge at the input
pin CCPOSx.
1101 The timer value of T12 is stored in CC6nR after a falling edge at the input pin
CC6n. The timer value of T12 is stored in CC6nSR after a falling edge at the input
pin CCPOSx.
1110 The timer value of T12 is stored in CC6nR after any edge at the input pin CC6n.
The timer value of T12 is stored in CC6nSR after any edge at the input pin
CCPOSx.
1111 Reserved (no capture or compare action)
User’s Manual
CCU6, V 0.4
12-76
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
12.3.6
Interrupt Control Registers
ISL
Capture/Compare Interrupt Status Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
T12
PM
T12
OM
ICC
62F
ICC
62R
ICC
61F
ICC
61R
ICC
60F
ICC
60R
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
ICC60R,
ICC61R,
ICC62R
0,
2,
4
rh
Capture, Compare-Match Rising Edge Flag
In compare mode, a compare-match has been
detected while T12 was counting up. In capture mode,
a rising edge has been detected at the input CC6x
(x = 0 - 2).
0
The event has not occurred since this bit was
reset.
1
The event described above has been detected.
ICC60F,
ICC61F,
ICC62F
1,
3,
5
rh
Capture, Compare-Match Falling Edge Flag
In compare mode, a compare-match has been
detected while T12 was counting down. In capture
mode, a falling edge has been detected at the input
CC6x (x = 0 - 2).
0
The event has not occurred since this bit was
reset.
1
The event described above has been detected.
T12OM
6
rh
Timer T12 One-Match Flag
0
A timer T12 one-match (while counting down)
has not been detected since this bit was reset.
1
A timer T12 one-match (while counting down)
has been detected.
T12PM
7
rh
Timer T12 Period-Match Flag
0
A timer T12 period-match (while counting up)
has not been detected since this bit was reset.
1
A timer T12 period-match (while counting up)
has been detected.
User’s Manual
CCU6, V 0.4
12-77
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
ISH
Capture/Compare Interrupt Status Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
STR
IDLE
WHE
CHE
TRP
S
TRP
F
T13
PM
T13
CM
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
T13CM
0
rh
Timer T13 Compare-Match Flag
0
A timer T13 compare-match has not been
detected since this bit was reset.
1
A timer T13 compare-match has been detected.
T13PM
1
rh
Timer T13 Period-Match Flag
0
A timer T13 period-match has not been detected
since this bit was reset.
1
A timer T13 period-match has been detected.
TRPF
2
rh
Trap Flag
The trap flag TRPF will be set by hardware if
TRPPEN = 1 and CTRAP = 0 or by software. If
TRPM2 = 0, bit TRPF is reset by hardware if the input
CTRAP becomes inactive (TRPPEN = 1). If
TRPM2 = 1, bit TRPF must be reset by software in
order to leave the trap state.
0
The trap condition has not been detected.
1
The trap condition has been detected (input
CTRAP has been 0 or by software).
TRPS1)
3
rh
Trap State
0
The trap state is not active.
1
The trap state is active. Bit TRPS is set while bit
TRPF = 1. It is reset according to the mode
selected in register TRPCTR.
CHE2)
4
rh
Correct Hall Event
0
A transition to a correct (expected) hall event
has not been detected since this bit was reset.
1
A transition to a correct (expected) hall event
has been detected.
User’s Manual
CCU6, V 0.4
12-78
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
WHE3)
5
rh
Wrong Hall Event
0
A transition to a wrong hall event (not the
expected one) has not been detected since this
bit was reset.
1
A transition to a wrong hall event (not the
expected one) has been detected.
IDLE4)
6
rh
IDLE State
This bit is set together with bit WHE (wrong hall event)
and it must be reset by software.
0
No action
1
Bit field MCMP is cleared, the selected outputs
are set to passive state.
STR
7
rh
Multi-Channel Mode Shadow Transfer Request
This bit is set when a shadow transfer from
MCMOUTS to MCMOUT takes places in multi-channel
mode.
0
The shadow transfer has not taken place.
1
The shadow transfer has taken place.
1)
During the trap state, the selected outputs are set to the passive state. The logic level driven during the passive
state is defined by the corresponding bit in register PSLR. Bit TRPS = 1 and TRPF = 0 can occur if the trap
condition is no longer active but the selected synchronization has not yet taken place.
2) On every valid hall edge, the contents of EXPH are compared with the pattern on pin CCPOSx and if both are
equal, bit CHE is set.
3)
On every valid hall edge, the contents of EXPH are compared with the pattern on pin CCPOSx. If both
comparisons (CURH and EXPH with CCPOSx) are not true, bit WHE (wrong hall event) is set.
4) Bit field MCMP is held to 0 by hardware as long as IDLE = 1.
Note: Not all bits in register IS can generate an interrupt. Other status bits have been
added, which have a similar structure for their set and reset actions.
Note: The interrupt generation is independent of the value of the bits in register IS, e.g.,
the interrupt will be generated (if enabled) even if the corresponding bit is already
set. The trigger for an interrupt generation is the detection of a set condition (by
hardware or software) for the corresponding bit in register IS.
Note: In compare mode (and hall mode), the timer-related interrupts are only generated
while the timer is running (TxR = 1). In capture mode, the capture interrupts are
also generated when the timer T12 is stopped.
User’s Manual
CCU6, V 0.4
12-79
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
ISSL
Capture/Compare Interrupt Status Set Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
S
T12
PM
w
S
T12
OM
w
S
CC
62F
w
S
CC
62R
w
S
CC
61F
w
S
CC
61R
w
S
CC
60F
w
S
CC
60R
w
Field
Bits
Type Description
SCC60R
0
w
Set Capture, Compare-Match Rising Edge Flag
0
No action
1
Bit ICC60R in register IS will be set.
SCC60F
1
w
Set Capture, Compare-Match Falling Edge Flag
0
No action
1
Bit ICC60F in register IS will be set.
SCC61R
2
w
Set Capture, Compare-Match Rising Edge Flag
0
No action
1
Bit ICC61R in register IS will be set.
SCC61F
3
w
Set Capture, Compare-Match Falling Edge Flag
0
No action
1
Bit ICC61F in register IS will be set.
SCC62R
4
w
Set Capture, Compare-Match Rising Edge Flag
0
No action
1
Bit ICC62R in register IS will be set.
SCC62F
5
w
Set Capture, Compare-Match Falling Edge Flag
0
No action
1
Bit ICC62F in register IS will be set.
ST12OM
6
w
Set Timer T12 One-Match Flag
0
No action
1
Bit T12OM in register IS will be set.
ST12PM
7
w
Set Timer T12 Period-Match Flag
0
No action
1
Bit T12PM in register IS will be set.
Note: If the setting by hardware of the corresponding flags leads to an interrupt, the
setting by software has the same effect.
User’s Manual
CCU6, V 0.4
12-80
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
ISSH
Capture/Compare Interrupt Status Set Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
S
STR
S
IDLE
S
WHE
S
CHE
S
WHC
S
TRPF
w
w
w
w
w
w
S
T13
PM
w
S
T13
CM
w
Field
Bits
Type Description
ST13CM
0
w
Set Timer T13 Compare-Match Flag
0
No action
1
Bit T13CM in register IS will be set.
ST13PM
1
w
Set Timer T13 Period-Match Flag
0
No action
1
Bit T13PM in register IS will be set.
STRPF
2
w
Set Trap Flag
0
No action
1
Bits TRPF and TRPS in register IS will be set.
SWHC
3
w
Software Hall Compare
0
No action
1
The Hall compare action is triggered.
SCHE
4
w
Set Correct Hall Event Flag
0
No action
1
Bit CHE in register IS will be set.
SWHE
5
w
Set Wrong Hall Event Flag
0
No action
1
Bit WHE in register IS will be set.
SIDLE
6
w
Set IDLE Flag
0
No action
1
Bit IDLE in register IS will be set.
SSTR
7
w
Set STR Flag
0
No action
1
Bit STR in register IS will be set.
User’s Manual
CCU6, V 0.4
12-81
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Register ISR contains the individual interrupt request reset bits to reset the
corresponding flags by software.
ISRL
Capture/Compare Interrupt Status Reset Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
R
T12
PM
w
R
T12
OM
w
R
CC
62F
w
R
CC
62R
w
R
CC
61F
w
R
CC
61R
w
R
CC
60F
w
R
CC
60R
w
Field
Bits
Type Description
RCC60R
0
w
Reset Capture, Compare-Match Rising Edge Flag
0
No action
1
Bit ICC60R in register IS will be reset.
RCC60F
1
w
Reset Capture, Compare-Match Falling Edge Flag
0
No action
1
Bit ICC60F in register IS will be reset.
RCC61R
2
w
Reset Capture, Compare-Match Rising Edge Flag
0
No action
1
Bit ICC61R in register IS will be reset.
RCC61F
3
w
Reset Capture, Compare-Match Falling Edge Flag
0
No action
1
Bit ICC61F in register IS will be reset.
RCC62R
4
w
Reset Capture, Compare-Match Rising Edge Flag
0
No action
1
Bit ICC62R in register IS will be reset.
RCC62F
5
w
Reset Capture, Compare-Match Falling Edge Flag
0
No action
1
Bit ICC62F in register IS will be reset.
RT12OM
6
w
Reset Timer T12 One-Match Flag
0
No action
1
Bit T12OM in register IS will be reset.
RT12PM
7
w
Reset Timer T12 Period-Match Flag
0
No action
1
Bit T12PM in register IS will be reset.
User’s Manual
CCU6, V 0.4
12-82
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
ISRH
Capture/Compare Interrupt Status Reset Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
R
STR
R
IDLE
R
WHE
R
CHE
0
R
TRPF
w
w
w
w
r
w
R
T13
PM
w
R
T13
CM
w
Field
Bits
Type Description
RT13CM
0
w
Reset Timer T13 Compare-Match Flag
0
No action
1
Bit T13CM in register IS will be reset.
RT13PM
1
w
Reset Timer T13 Period-Match Flag
0
No action
1
Bit T13PM in register IS will be reset.
RTRPF
2
w
Reset Trap Flag
0
No action
1
Bit TRPF in register IS will be reset (not taken
into account while input CTRAP = 0 and
TRPPEN = 1).
RCHE
4
w
Reset Correct Hall Event Flag
0
No action
1
Bit CHE in register IS will be reset.
RWHE
5
w
Reset Wrong Hall Event Flag
0
No action
1
Bit WHE in register IS will be reset.
RIDLE
6
w
Reset IDLE Flag
0
No action
1
Bit IDLE in register IS will be reset.
RSTR
7
w
Reset STR Flag
0
No action
1
Bit STR in register IS will be reset.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
CCU6, V 0.4
12-83
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
IENL
Capture/Compare Interrupt Enable Register Low
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
T12
PM
rw
EN
T12
OM
rw
EN
CC
62F
rw
EN
CC
62R
rw
EN
CC
61F
rw
EN
CC
61R
rw
EN
CC
60F
rw
EN
CC
60R
rw
Field
Bits
Type Description
ENCC60R
0
rw
Capture, Compare-Match Rising Edge Interrupt
Enable for Channel 0
0
No interrupt will be generated if the set condition
for bit ICC60R in register IS occurs.
1
An interrupt will be generated if the set condition
for bit ICC60R in register IS occurs. The
interrupt line that will be activated is selected by
bit field INPCC60.
ENCC60F
1
rw
Capture, Compare-Match Falling Edge Interrupt
Enable for Channel 0
0
No interrupt will be generated if the set condition
for bit ICC60F in register IS occurs.
1
An interrupt will be generated if the set condition
for bit ICC60F in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPCC60.
ENCC61R
2
rw
Capture, Compare-Match Rising Edge Interrupt
Enable for Channel 1
0
No interrupt will be generated if the set condition
for bit ICC61R in register IS occurs.
1
An interrupt will be generated if the set condition
for bit ICC61R in register IS occurs. The
interrupt line that will be activated is selected by
bit field INPCC61.
ENCC61F
3
rw
Capture, Compare-Match Falling Edge Interrupt
Enable for Channel 1
0
No interrupt will be generated if the set condition
for bit ICC61F in register IS occurs.
1
An interrupt will be generated if the set condition
for bit ICC61F in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPCC61.
User’s Manual
CCU6, V 0.4
12-84
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
ENCC62R
4
rw
Capture, Compare-Match Rising Edge Interrupt
Enable for Channel 2
0
No interrupt will be generated if the set condition
for bit ICC62R in register IS occurs.
1
An interrupt will be generated if the set condition
for bit ICC62R in register IS occurs. The
interrupt line that will be activated is selected by
bit field INPCC62.
ENCC62F
5
rw
Capture, Compare-Match Falling Edge Interrupt
Enable for Channel 2
0
No interrupt will be generated if the set condition
for bit ICC62F in register IS occurs.
1
An interrupt will be generated if the set condition
for bit ICC62F in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPCC62.
ENT12OM
6
rw
Enable Interrupt for T12 One-Match
0
No interrupt will be generated if the set condition
for bit T12OM in register IS occurs.
1
An interrupt will be generated if the set condition
for bit T12OM in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPT12.
ENT12PM
7
rw
Enable Interrupt for T12 Period-Match
0
No interrupt will be generated if the set condition
for bit T12PM in register IS occurs.
1
An interrupt will be generated if the set condition
for bit T12PM in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPT12.
IENH
Capture/Compare Interrupt Enable Register High
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
STR
EN
IDLE
EN
WHE
EN
CHE
0
EN
TRPF
rw
rw
rw
rw
r
rw
EN
T13
PM
rw
EN
T13
CM
rw
User’s Manual
CCU6, V 0.4
12-85
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
ENT13CM
0
rw
Enable Interrupt for T13 Compare-Match
0
No interrupt will be generated if the set condition
for bit T13CM in register IS occurs.
1
An interrupt will be generated if the set condition
for bit T13CM in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPT13.
ENT13PM
1
rw
Enable Interrupt for T13 Period-Match
0
No interrupt will be generated if the set condition
for bit T13PM in register IS occurs.
1
An interrupt will be generated if the set condition
for bit T13PM in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPT13.
ENTRPF
2
rw
Enable Interrupt for Trap Flag
0
No interrupt will be generated if the set condition
for bit TRPF in register IS occurs.
1
An interrupt will be generated if the set condition
for bit TRPF in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPERR.
ENCHE
4
rw
Enable Interrupt for Correct Hall Event
0
No interrupt will be generated if the set condition
for bit CHE in register IS occurs.
1
An interrupt will be generated if the set condition
for bit CHE in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPCHE.
ENWHE
5
rw
Enable Interrupt for Wrong Hall Event
0
No interrupt will be generated if the set condition
for bit WHE in register IS occurs.
1
An interrupt will be generated if the set condition
for bit WHE in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPERR.
User’s Manual
CCU6, V 0.4
12-86
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
ENIDLE
6
rw
Enable Idle
This bit enables the automatic entering of the idle state
(bit IDLE will be set) after a wrong hall event has been
detected (bit WHE is set). During the idle state, the bit
field MCMP is automatically cleared.
0
The bit IDLE is not automatically set when a
wrong hall event is detected.
1
The bit IDLE is automatically set when a wrong
hall event is detected.
ENSTR
7
rw
Enable Multi-Channel Mode Shadow Transfer
Interrupt
0
No interrupt will be generated if the set condition
for bit STR in register IS occurs.
1
An interrupt will be generated if the set condition
for bit STR in register IS occurs. The interrupt
line that will be activated is selected by bit field
INPCHE.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
CCU6, V 0.4
12-87
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
INPL
Capture/Compare Interrupt Node Pointer Register Low
7
6
5
4
3
Reset Value: 40H
2
1
0
INP
CHE
INP
CC62
INP
CC61
INP
CC60
rw
rw
rw
rw
Field
Bits
Type Description
INPCC60
[1:0]
rw
Interrupt Node Pointer for Channel 0 Interrupts
This bit field defines the interrupt output line, which is
activated due to a set condition for bit ICC60R (if
enabled by bit ENCC60R) or for bit ICC60F (if enabled
by bit ENCC60F).
00
Interrupt output line SR0 is selected.
01
Interrupt output line SR1 is selected.
10
Interrupt output line SR2 is selected.
11
Interrupt output line SR3 is selected.
INPCC61
[3:2]
rw
Interrupt Node Pointer for Channel 1 Interrupts
This bit field defines the interrupt output line, which is
activated due to a set condition for bit ICC61R (if
enabled by bit ENCC61R) or for bit ICC61F (if enabled
by bit ENCC61F).
00
Interrupt output line SR0 is selected.
01
Interrupt output line SR1 is selected.
10
Interrupt output line SR2 is selected.
11
Interrupt output line SR3 is selected.
User’s Manual
CCU6, V 0.4
12-88
V 0.2, 2005-01
XC866
Capture/Compare Unit 6
Field
Bits
Type Description
INPCC62
[5:4]
rw
Interrupt Node Pointer for Channel 2 Interrupts
This bit field defines the interrupt output line, which is
activated due to a set condition for bit ICC62R (if
enabled by bit ENCC62R) or for bit ICC62F (if enabled
by bit ENCC62F).
00
Interrupt output line SR0 is selected.
01
Interrupt output line SR1 is selected.
10
Interrupt output line SR2 is selected.
11
Interrupt output line SR3 is selected.
INPCHE
[7:6]
rw
Interrupt Node Pointer for the CHE Interrupt
This bit field defines the interrupt output line, which is
activated due to a set condition for bit CHE (if enabled
by bit ENCHE) or for bit STR (if enabled by bit
ENSTR).
00
Interrupt output line SR0 is selected.
01
Interrupt output line SR1 is selected.
10
Interrupt output line SR2 is selected.
11
Interrupt output line SR3 is selected.
INPH
Capture/Compare Interrupt Node Pointer Register High
7
6
5
4
3
Reset Value: 39H
2
1
0
0
INP
T13
INP
T12
INP
ERR
r
rw
rw
rw
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Capture/Compare Unit 6
Field
Bits
Type Description
INPERR
[1:0]
rw
Interrupt Node Pointer for Error Interrupts
This bit field defines the interrupt output line, which is
activated due to a set condition for bit TRPF (if enabled
by bit ENTRPF) or for bit WHE (if enabled by bit
ENWHE).
00
Interrupt output line SR0 is selected.
01
Interrupt output line SR1 is selected.
10
Interrupt output line SR2 is selected.
11
Interrupt output line SR3 is selected.
INPT12
[3:2]
rw
Interrupt Node Pointer for Timer T12 Interrupts
This bit field defines the interrupt output line, which is
activated due to a set condition for bit T12OM (if
enabled by bit ENT12OM) or for bit T12PM (if enabled
by bit ENT12PM).
00
Interrupt output line SR0 is selected.
01
Interrupt output line SR1 is selected.
10
Interrupt output line SR2 is selected.
11
Interrupt output line SR3 is selected.
INPT13
[5:4]
rw
Interrupt Node Pointer for Timer T13 Interrupts
This bit field defines the interrupt output line, which is
activated due to a set condition for bit T13CM (if
enabled by bit ENT13CM) or for bit T13PM (if enabled
by bit ENT13PM).
00
Interrupt output line SR0 is selected.
01
Interrupt output line SR1 is selected.
10
Interrupt output line SR2 is selected.
11
Interrupt output line SR3 is selected.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
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Analog-to-Digital Converter
13
Analog-to-Digital Converter
The XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with
eight multiplexed analog input channels. The ADC uses a successive approximation
technique to convert the analog voltage levels from up to eight different sources.
Features:
• Successive approximation
• 8-bit or 10-bit resolution
(TUE of ± 1 LSB and ± 2 LSB, respectively)
• Eight analog channels
• Four independent result registers
(configurable for FIFO functionality)
• Result data protection for slow CPU access
(wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter
(accumulation of up to 2 conversion results)
• Two independent conversion request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation with configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes
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Analog-to-Digital Converter
13.1
Structure Overview
The ADC module consists of two main parts, i.e., analog and digital, with each containing
independent building blocks.
The analog part includes:
• Analog input multiplexer
(for selecting the channel to be converted)
• Analog converter stage
(e.g., capacitor network and comparator as part of the ADC)
• Digital control part of the analog converter stage
(for controlling the analog-to-digital conversion process and generating the
conversion result)
The digital part defines and controls the overall functionality of the ADC module, and
includes:
• Digital data and conversion request handling
(for controlling the conversion trigger mechanisms and handling the conversion
results)
• Bus interface to the device-internal data bus
(for controlling the interrupts and register accesses)
The block diagram of the ADC module is shown in Figure 13-1. The analog input
channel x (x = 0 - 7) is available at port pin P2.x/ANx.
analog part
analog input 0
...
AD converter
analog input 7
digital part
data (result)
handling
conversion
control
request
control
analog clock fADCA
digital clock fADCD
bus
interface
fADC
Figure 13-1 Overview of ADC Building Blocks
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Analog-to-Digital Converter
13.2
Clocking Scheme
A common module clock fADC generates the various clock signals used by the analog
and digital parts of the ADC module:
• fADCA is input clock for the analog part.
• fADCI is internal clock for the analog part (defines the time base for conversion length
and the sample time). This clock is generated internally in the analog part, based on
the input clock fADCA to generate a correct duty cycle for the analog components.
• fADCD is input clock for the digital part. This clock is used for the arbiter (defines the
duration of an arbitration round) and other digital control structures (e.g., registers and
the interrupt generation).
The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz.
Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI
does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register
GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of
the ADC is not required.
fADCD
f ADC = fPCLK
arbiter
registers
interrupts
digital part
fADCA
CTC
÷ 32
f ADCI
÷4
MUX
÷3
÷2
clock prescaler
analog
components
analog part
Condition: f ADCI ≤ 10 MHz, where t ADCI =
1
f ADCI
Figure 13-2 Clocking Scheme
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Analog-to-Digital Converter
For module clock fADC = 26.7 MHz, the analog clock fADCI frequency can be selected as
shown in Table 13-1.
Table 13-1
fADCI Frequency Selection
Module Clock fADC
CTC
Prescaling Ratio
Analog Clock fADCI
26.7 MHz
00B
÷2
13.3 MHz (N.A)
01B
÷3
8.9 MHz
10B
÷4
6.7 MHz
11B (default)
÷ 32
833.3 kHz
As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00B when fADC is
26.7 MHz. During slow-down mode where fADC may be reduced to 13.3 MHz, 6.7 MHz
etc., CTC can be set to 00B as long as the divided analog clock fADCI does not exceed
10 MHz. However, it is important to note that the conversion error could increase due to
loss of charges on the capacitors, if fADC becomes too low during slow-down mode.
13.2.1
Conversion Timing
The analog-to-digital conversion procedure consists of the following phases:
•
•
•
•
Synchronization phase (tSYN)
Sample phase (tS)
Conversion phase
Write result phase (tWR)
conversion start
trigger
Source
interrupt
Sample Phase
Channel
interrupt
Result
interrupt
Conversion Phase
fADCI
BUSY Bit
SAMPLE Bit
t SYN
tS
Write Result Phase
tCONV
tWR
Figure 13-3 Conversion Timing
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Analog-to-Digital Converter
Synchronization Phase tSYN
One fADCI period is required for synchronization between the conversion start trigger
(from the digital part) and the beginning of the sample phase (in the analog part). The
BUSY and SAMPLE bits will be set with the conversion start trigger.
Sample Phase tS
During this period, the analog input voltage is sampled. The internal capacitor array is
connected to the selected analog input channel and is loaded with the analog voltage to
be converted. The analog voltage is internally fed to a voltage comparator. With the
beginning of the sampling phase, the SAMPLE and BUSY flags in register GLOBSTR
are set. The duration of this phase is common to all analog input channels and is
controlled by bit field STC in register INPCR0:
tS = (2 + STC) × tADCI
[13.1]
Conversion Phase
During the conversion phase, the analog voltage is converted into an 8-bit or 10-bit
digital value using the successive approximation technique with a binary weighted
capacitor network. At the beginning of the conversion phase, the SAMPLE flag is reset
(to indicate the sample phase is over), while the BUSY flag continues to be asserted. The
BUSY flag is deasserted only at the end of the conversion phase with the corresponding
source interrupt (of the source that started the conversion) asserted.
Write Result Phase tWR
At the end of the conversion phase, the corresponding channel interrupt (of the
converted channel) is asserted three fADCI periods later, after the limit checking has been
performed. The result interrupt is asserted, once the conversion result has been written
into the target result register.
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Analog-to-Digital Converter
Total Conversion Time tCONV
The total conversion time (synchronizing + sampling + charge redistribution) tCONV is
given by:
tCONV = tADC × (1 + r × (3 + n + STC))
[13.2]
where
r = CTC + 2 for CTC = 00B, 01B or 10B,
r = 32 for CTC = 11B,
CTC = Conversion Time Control,
STC = Sample Time Control,
n = 8 or 10 (for 8-bit and 10-bit conversion, respectively),
tADC = 1 / fADC
Example:
STC = 00H,
CTC = 01B,
fADC = 26.7 MHz,
n = 10,
tCONV = tADC × (1 + 3 × (3 + 10 + 0)) = 1.5 µs
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Analog-to-Digital Converter
13.3
Low Power Mode
The ADC module may be disabled, either partially or completely, when no conversion is
required in order to reduce power consumption:
• The analog part of the ADC module may be disabled by resetting the ANON bit. This
causes the generation of fADCI to be stopped and results in a reduction in power
consumption. Conversions are possible only by enabling the analog part (ANON = 1)
again. The wake-up time is approximately 100 ns.
Refer to Section 13.7.1 for register description of disabling the ADC analog part.
• If the ADC functionality is not required at all, it can be completely disabled by gating
off its clock input (fADC) for maximal power reduction. This is done by setting bit
ADC_DIS in register PMCON1 as described below. Refer to Chapter 8.1.4 for details
on peripheral clock management.
PMCON1
Power Mode Control Register 1
7
6
5
Reset Value: 00H
4
3
2
1
0
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
r
rw
rw
rw
rw
The function of the shaded bit is not described here
Field
Bits
Type Description
ADC_DIS
0
rw
ADC Disable Request. Active high.
0
ADC is in normal operation (default)
1
Request to disable the ADC
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
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Analog-to-Digital Converter
13.4
Functional Description
The ADC module functionality includes:
• Two different conversion request sources (sequential and parallel) with independent
registers. The request sources are used to trigger conversions due to external events
(synchronization to PWM signals), sequencing schemes, etc.
• An arbiter that regularly scans the request sources to find the channel with the highest
priority for the next conversion. The priority of each source can be programmed
individually to obtain the required flexibility to cover the desired range of applications.
• Control registers for each of the eight channels that define the behavior of each analog
input (such as the interrupt behavior, a pointer to a result register, a pointer to a
channel class, etc.).
• An input class register that delivers general channel control information (sample time)
from a centralized location.
• Four result registers (instead of one result register per analog input channel) for
storing the conversion results and controlling the data reduction. This allows the
creation of result data FIFOs.
• A decimation stage for conversion results, adding the incoming result to the value
already stored in the targeted result register. This stage allows fast consecutive
conversions without the risk of data loss for slow CPU clock frequency.
parallel request source 1
(arbitration slot 1)
channel control 7
.. .
arbiter
...
analog
part
channel control 0
analog input 7
analog input 0
input class 0
result register 3
...
data
reduction
sequential request source 0
(arbitration slot 0)
result register 0
Figure 13-4 ADC Block Diagram
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Analog-to-Digital Converter
13.4.1
Request Source Arbiter
The arbiter can operate in two modes that are selectable by bit ARBM:
• Permanent arbitration:
In this mode, the arbiter will continuously poll the request sources even when there is
no pending conversion request.
• Arbitration started by pending conversion request:
In this mode, the arbiter will start polling the request sources only if there is at least
one conversion pending request.
Once started, the arbiter polls the two request sources (source x at slot x, x = 0 - 1) to
find the analog channel with the highest priority that must be converted. For each
arbitration slot, the arbiter polls the request pending signal (REQPND) and the channel
number valid signal (REQCHNRV) of one request source. The sum of all arbitration slots
is called an arbitration round. An arbitration slot must be enabled (ASENx = 1) before it
can take part in the arbitration.
Each request source has a source priority that can be programmed via bit PRIOx.
Starting with request source 0 (arbitration slot 0), the arbiter checks if a request source
has a pending request (REQPND = 1) for a conversion. If more than one request source
is found with the same programmed priority level and a pending conversion request, the
channel specified by the request source that was found first is selected. The
REQCHNRV signal is also checked by the arbiter and a conversion can only be started
if REQCHNRV = 1 (and REQPND = 1). If both request sources are programmed with the
same priority, the channel number specified by request source 0 will be converted first
since it is connected to arbitration slot 0.
The period tARB of a complete arbitration round is fixed at:
tARB = 4 * tADCD
[13.3]
Refer to Section 13.7.2 for register description of priority and arbitration control.
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Analog-to-Digital Converter
13.4.2
Conversion Start Modes
At the end of each arbitration round, the arbiter would have found the request source with
the highest priority and a pending conversion request. It stores the arbitration result,
namely the channel number, the sample time and the targeted result register for further
actions.
If the analog part is idle, a conversion can be started immediately. If a conversion is
currently running, the arbitration result is compared to the priority of the currently running
conversion. If the current conversion has the same or a higher priority, it will continue to
completion. Immediately after its completion, the next conversion can begin. As soon as
the analog part is idle and the arbiter has output a conversion request, the conversion
will start.
In case the new conversion request has a higher priority than the current conversion, two
conversion start modes exist (selectable by bit CSMx, x = 0 - 1):
• Wait-for-Start:
In this mode, the current conversion is completed normally. The pending conversion
request will be treated immediately after the conversion is completed. The conversion
start takes place as soon as possible.
• Cancel-Inject-Repeat:
In this mode, the current conversion is aborted immediately if a new request with a
higher priority has been found. The new conversion is started as soon as possible
after the abort action. The aborted conversion request is restored in the request
source that has requested the aborted conversion. As a result, it takes part in the next
arbitration round. The priority of an active request source (including pending or active
conversion) must not be changed by software. The abort will not be accepted during
the last 3 clock cycles of a running conversion.
Refer to Section 13.7.2 for register description relating to conversion start control.
13.4.3
Channel Control
Each channel has its own control information that defines the target result register for the
conversion result (see Section 13.7.4). The only control information that is common to
all channels is the sampling time defined by the input class register (see Section 13.7.5).
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Analog-to-Digital Converter
13.4.4
Sequential Request Source
13.4.4.1 Overview
The sequential request source at arbitration slot 0 requests one conversion after another
for channel numbers between 0 and 7. The queue stage stores the requested channel
number and some additional control information. As a result, the order in which the
channels are to be converted is freely programmable without restrictions in the
sequence. The additional control information is used to enable the request source
interrupt (when the requested channel conversion is completed) and to enable the
automatic refill process.
A sequential source consists of a queue stage (Q0R0), a backup stage (QBUR0) and a
mode control register (QMR0). The backup stage stores the information about the latest
conversion requested after it has been aborted. If the backup register contains an
aborted request (V = 1), it is treated before the entry in the queue stage. This implies that
only the bit V in the backup register is cleared when the requested conversion is started.
If the bit V in the backup register is not set, the bit V in the queue stage is reset when the
requested conversion is started. The request source can take part in the source
arbitration if the backup stage or queue stage contains a valid request (V = 1).
data written
by CPU
queue input register
1
queue stage (CHNR, RF, ENSI)
V
w
abort of
conversion
start of
conversion
backup stage (CHNR, RF, ENSI)
set
reset
rh
V
OR
rh
Figure 13-5 Base Structure of Sequential Request Source
The automatic refill feature can be activated (RF = 1) to allow automatic re-insertion of
the pending request into the queue stage after a successful execution (conversion start).
Otherwise, the pending request will be discarded once it is executed. While the
automatic refill feature is enabled, software should not write data to the queue input
register.
The write address in which to enter a conversion request is given by the write-only queue
input register (QINR0). If the queue stage is empty (V = 0), the written value will be
stored there (bit V becomes set), or else the write action is ignored.
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Analog-to-Digital Converter
Refer to Section 13.7.6 for description of the sequential request source registers.
13.4.4.2 Request Source Control
If the conversion requested by the source is not related to an external trigger event
(EXTR = 0), the valid bit V = 1 directly requests the conversion by setting signals
REQPND and REQCHNRV to 1. In this case, no conversion will be requested if V = 0.
A gating mechanism allows the user to enable/disable conversion requests according to
bit ENGT.
CEV
conversion
started
OR
w
TREV
set
OR
w
reset
EV
rh
ENTR
AND
V
rw
1
REQTR
0
EXTR
rh
1
ENGT
0
TRMD
rw
rw
0
0
1
1
AND
AND
REQPND
REQCHNRV
Figure 13-6 Sequential Request Source Control
If the requested conversion is sensitive to an external trigger event (EXTR = 1), the
signal REQTR can be taken into account (with ENTR = 1) or the software can write
TREV = 1. Both actions set the event flag EV. The event flag EV = 1 indicates that an
external event has taken place and a conversion can be requested (EV can be set only
if a conversion request is valid with V = 1). In this case, the signal REQCHNRV is derived
from bit EV.
Bit TRMD (trigger mode) offers the possibility to wait, with the valid bit already set, for an
event to be detected before taking part in the arbitration. This ensures that the reaction
to an event is with minimum delay. If this feature is not desired (TRMD = 0), the event bit
EV can be used to generate both REQPND and REQCHNRV.
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Analog-to-Digital Converter
13.4.5
Parallel Request Source
13.4.5.1 Overview
The parallel request source at arbitration slot 1 generates one or more conversion
requests for channel numbers between 4 and 7 in parallel. The requests are always
treated one after the other (in separate arbitration rounds) in a predefined sequence
(higher channel numbers before lower channel numbers).
The parallel request source consists of a conversion request control register (CRCR1),
a conversion request pending register (CRPR1) and a conversion request mode register
(CRMR1). The contents of the conversion request control register are copied (overwrite)
to the conversion request pending register when a selected load event (LDE) occurs.
The type of the event defines the behavior and the trigger of the request source.
The activation of a conversion request to the arbiter may be started if the content of the
conversion pending register is not 0. The highest bit position number among the pending
bits with values equal to 1 specifies the channel number for conversion. To take part in
the source arbitration, both the REQCHNRV and REQPND signals must be 1.
Refer to Section 13.7.7 for description of the parallel request source registers.
13.4.5.2 Request Source Control
All conversion pending bits are ORed together to deliver an intermediate signal PND for
generating REQCHNRV and REQPND. The signal PND is gated with bit ENGT, allowing
the user to enable/disable conversion requests. See Figure 13-7.
data written
by CPU
conversion request control register
rwh
parallel load
LDE
conversion request pending register
rwh
...
bitwise
set/reset
by arbiter
bitwise OR
ENGT
PND
rw
0
0
1
1
AND
AND
REQPND
REQCHNRV
Figure 13-7 Parallel Request Source Control
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Analog-to-Digital Converter
The load event for a parallel load can be:
• External trigger at the input line REQTR. See Section 13.4.5.3.
• Write operation to a specific address of the conversion request control register.
See Section 13.4.5.4.
• Write operation with LDEV = 1 to the request source mode register.
See Section 13.4.5.4.
• Source internal action (conversion completed and PND = 0 for autoscan mode).
See Section 13.4.5.5.
Each bit (bit x, x = 4 - 7) in the conversion request control/pending registers corresponds
to one analog input channel. The bit position directly defines the channel number. The
bits in the conversion request pending register can be set or reset bitwisely by the arbiter:
• The corresponding bit in the conversion request pending register is automatically
reset when the arbiter indicates the start of conversion for this channel.
• The bit is automatically set when the arbiter indicates that the conversion has been
aborted.
A source interrupt can be generated (if enabled) when a conversion (requested by this
source) is completed while PND = 0. These rules apply only if the request source has
triggered the conversion.
13.4.5.3 External Trigger
The conversion request for the parallel source (and also the sequential source) can be
synchronized to an external trigger event. For the parallel source, this is done by
coupling the reload event to a request trigger input, REQTR.
13.4.5.4 Software Control
The load event for the parallel source can also be generated under software control in
two ways:
• The conversion request control register can be written at two different addresses
(CRCR1 and CRPR1). Accessed at CRCR1, the write action changes only the bits in
this register. Accessed at CRPR1, the load event will take place one clock cycle after
the write access. This automatic load event can be used to start conversions with a
single move operation. In this case, the information about the channels to be
converted is given as an argument in the move instruction.
• Bit LDEV can be written with 1 by software to trigger the load event. In this case, the
load event does not contain any information about the channels to be converted, but
always takes the contents of the conversion request control register. This allows the
conversion request control register to be written at a second address without
triggering the load event.
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Analog-to-Digital Converter
13.4.5.5 Autoscan
The autoscan is a functionality of the parallel source. If autoscan mode is enabled, the
load event takes place when the conversion is completed while PND = 0, provided the
parallel request source has triggered the conversion. This automatic reload feature
allows channels 4 and 7 to be constantly scanned for pending conversion requests
without the need for external trigger or software action.
13.4.6
Wait-for-Read Mode
The wait-for-read mode can be used for all request sources to allow the CPU to treat
each conversion result independently without the risk of data loss. Data loss can occur
if the CPU does not read a conversion result in a result register before a new result
overwrites the previous one.
In wait-for-read mode, the conversion request generated by a request source for a
specific channel will be disabled (and conversion not possible) if the targeted result
register contains valid data (indicated by its valid flag being set). Conversion of the
requested channel will not start unless the valid flag of the targeted result register is
cleared (data is invalid). The wait-for-read mode for a result register can be enabled by
setting bit WFR (see Section 13.7.8).
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Analog-to-Digital Converter
13.4.7
Result Generation
13.4.7.1 Overview
The result generation of the ADC module consists of several parts:
• A limit checking unit, comparing the conversion result to two selected boundary values
(BOUND0 and BOUND1). A channel interrupt can be generated according to the limit
check result.
• A data reduction filter, accumulating the conversion results. The accumulation is done
by adding the new conversion result to the value stored in the selected result register.
• Four result registers, storing the conversion results. The software can read the
conversion result from the result registers. The result register used to store the
conversion result is selected individually for each input channel.
analog
part
conversion
result
from channel
control
result
buffer
boundary values
add/sub
result register 0
VF0
result register 1
VF1
.. .
0
result register 3
result path control
limit check control
data reduction control
VF3
channel interrupt
DRC
event interrupt
Figure 13-8 Result Path
Refer to Section 13.7.8 for description of the result generation registers.
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13.4.7.2 Limit Checking
The limit checking and the data reduction filter are based on a common add/subtract
structure. The incoming result is compared with BOUND0, then with BOUND1.
Depending on the result flags (lower-than compare), the limit checking unit can generate
a channel interrupt. It can become active when the valid result of the data reduction filter
is stored in the selected result register.
n
new
result in
buffer?
y
compare result with
BOUND0
BOUND0
rw
compare result with
BOUND1
BOUND1
rw
data reduction filter
limit checking
channel
interrupt
Figure 13-9 Limit Checking Flow
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Analog-to-Digital Converter
13.4.7.3 Data Reduction Filter
Each result register can be controlled to enable or disable the data reduction filter. The
data reduction block allows the accumulation of conversion results for anti-aliasing
filtering or for averaging. A pseudo-parallel sampling on two analog inputs is possible by
converting the channels A - B - B - A in a quick sequence. The result register for A stores
the sum of both conversions of channel A and the result register B works similarly for
channel B.
conversion
ready
DRCTR = 1
c0
c1
c2
c3
c4
c5
c6
c7
c8
running
conversion
r0
r1
r2
r3
r4
r5
r6
r7
delivered
result
0
1
0
1
0
1
0
1
0
data reduction counter
DRC
0
r0
r0 +
r1
r2
r2 +
r3
r4
r4 +
r5
r6
r6 +
r7
content of
result register x
DRCTR = 0
valid flag for result register x
VFx
0
0
0
0
0
0
0
0
0
DRC
0
r0
r1
r2
r3
r4
r5
r6
r7
content of
result register x
VFx
Figure 13-10 Data Reduction Flow
If DRC is 0 and a new conversion result comes in, DRC is reloaded with its reload value
(defined by bit DRCTR in the result control register) and the value of 0 is added to the
conversion result (instead of the previous result register content). Then, the complete
result is stored in the selected result register. If the reload value is 0 (data reduction filter
disabled), accumulation is done over one conversion. Hence, a result event is generated
and the valid bit (VF) for the result register becomes set. If the reload value is 1 (data
reduction filter enabled), accumulation is done over two conversions. In this case, neither
a result event is generated nor the valid bit is set.
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Analog-to-Digital Converter
If DRC is 1 and a new conversion result comes in, the data reduction filter adds the
incoming result to the value already stored in the result register and decrements DRC.
After this addition, the complete result is stored in the selected result register. The result
event is generated and the valid bit becomes set.
It is possible to have an identical cycle behavior of the path to the result register, with the
data reduction filter being enabled or disabled. Furthermore, an overflow of the result
register is avoided, because a maximum of 2 conversion results are added (a 10-bit
result added twice delivers a maximum of 11 bits).
13.4.7.4 Result FIFO Functionality
The four result registers can be independently configured to provide a 2, 3 or 4-stage
FIFO functionality. This allows the storing of measurement results with ‘relaxed’ CPU
access timing.
If the FIFO mechanism is enabled (FEN = 1) for result register x (independent from the
read views), the following actions take place (the setting of result register x+1 has no
influence on these actions).
If the valid flag VFx is not set (result register x does not contain valid data) and VFx+1
(of result register x+1) is set, the contents of result register x+1 are transferred to result
register x. Furthermore, VFx becomes set and VFx+1 becomes reset. The setting of VFx
can generate an event interrupt.
A result interrupt x is generated when new data is stored in result register x if the previous
register (x-1) is not enabled for FIFO functionality.
13.4.7.5 Result Register View
In order to cover a wide range of applications, the content of result register x (x = 0 to 3)
is available as different read views at different addresses (see Figure 13-11):
• Normal read view RESRxL/H:
This view delivers the 8-bit or 10-bit conversion result.
• Accumulated read view RESRAxL/H:
This view delivers the accumulated 9-bit or 11-bit conversion result.
All conversion results (with or without accumulation) are stored in the result registers, but
can be viewed at either RESRxL/H or RESRAxL/H which shows different data alignment
and width.
When the data reduction filter is enabled (DRCTR = 1), read access should be
performed on RESRAxL/H as it shows the full 9-bit (R8:R0) or 11-bit (R10:R0)
accumulated conversion result. Reading from RESRxL/H gives the appended (MSB
unavailable) accumulated result.
When the data reduction filter is disabled (DRCTR = 0), the user can read the 8-bit or
10-bit conversion result from either RESRxL/H or RESRAxL/H. In particular, for 8-bit
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Analog-to-Digital Converter
conversion (without accumulation), the result can be read from RESRxH with a single
instruction. Hence, depending on the application requirement, the user can choose to
read from the different views.
Result Register x High
Result Register x Low
7
7
6
5
4
3
2
1
0
R10 R9 R8 R7 R6 R5 R4 R3
RESRxH
7
6
5
4
3
6
5
2
1
0
7
6
5
4
0
0
0
VF DRC
rh
3
6
5
4
2
1
0
CHNR
7
0
2
1
0
R9 R8 R7 R6 R5 R4 R3 R2
rh
7
6
R1 R0
1
0
CHNR
6
5
4
3
2
RESRAxL
1
0
R7 R6 R5 R4 R3 R2 R1
rh
3
2
RESRAxH
7
6
5
R0
0
0
4
5
4
3
0
VF DRC
3
2
VF DRC
rh
1
0
CHNR
rh
8-bit conversion (without accumulation)
8-bit conversion (with/without accumulation)
7
3
R2 R1 R0 VF DRC
RESRxL
R7 R6 R5 R4 R3 R2 R1 R0
4
2
1
CHNR
0
7
6
5
4
3
2
1
0
R8 R7 R6 R5 R4 R3 R2 R1
rh
7
6
5
R0
0
0
4
2
VF DRC
rh
10-bit conversion (with/without accumulation)
3
1
0
CHNR
rh
8-bit conversion (accumulated 9-bit)
7
0
6
5
4
3
2
1
0
R9 R8 R7 R6 R5 R4 R3
7
6
5
4
3
2
R2 R1 R0 VF DRC
rh
1
0
CHNR
rh
10-bit conversion (without accumulation)
7
6
5
4
3
2
1
0
R10 R9 R8 R7 R6 R5 R4 R3
rh
7
6
5
4
3
R2 R1 R0 VF DRC
2
1
0
CHNR
rh
10-bit conversion (accumulated 11-bit)
Figure 13-11 Result Register View
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Analog-to-Digital Converter
13.4.8
Interrupts
The ADC module provides 2 service request outputs SR[1:0] that can be activated by
different interrupt sources.
The interrupt structure of the ADC supports two different types of interrupt sources:
• Event Interrupts: Activated by events of the request sources (source interrupts) or
result registers (result interrupts).
• Channel Interrupts: Activated by the completion of any input channel conversion. They
are enabled according to the control bits for the limit checking. The settings are
defined individually for each input channel.
The interrupt compressor is an OR-combination of all incoming interrupt pulses for each
of the SR lines.
request
sources
to SR0
event interrupt
unit
to SR1
interrupt
compressor
arbiter
analog
part
limit
check
unit
channel
interrupt
routing
SR0
SR1
to SR0
to SR1
Figure 13-12 Interrupt Overview
Refer to Section 13.7.9 for description of the interrupt registers.
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13.4.8.1 Event Interrupts
event 7
event 6
to SR0
event 5
to SR0
event 4
CHINF4
to SR0
to SR1
to SR0
to SR1
rh
...
interrupt
trigger 0
AND
IEN
to SR1
to SR1
EVINP4
rw
rw
event 1
event 0
CHINF0
to SR0
to SR0
interrupt
trigger 0
ENSI
rw
. ..
rh
AND
to SR1
to SR1
EVINP0
rw
Figure 13-13 Event Interrupt Structure
Event interrupts can be generated by the request sources and the result registers. The
event interrupt enable bits are located in the request sources (ENSI) and result register
control (IEN). An interrupt node pointer (EVINP) for each event allows the selection of
the targeted service output line.
A request source event is generated when the requested channel conversion is
completed:
• Event 0: Request source event of sequential request source 0 (arbitration slot 0)
• Event 1: Request source event of parallel request source 1 (arbitration slot 1)
A result event is generated according to the data reduction control (see
Section 13.4.7.3):
•
•
•
•
Event 4: Result register event of result register 0
Event 5: Result register event of result register 1
Event 6: Result register event of result register 2
Event 7: Result register event of result register 3
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13.4.8.2 Channel Interrupts
The channel interrupts occur when a conversion is completed and the selected limit
checking condition is met. As a result, only one channel interrupt can be activated at a
time. An interrupt can be triggered according to the limit checking result by comparing
the conversion result with two selectable boundaries for each channel.
request
sources
boundaries
BOUND0 BOUND1
conversion finished
arbiter
analog
part
channel number
result
limit
check
unit
channel interrupt
trigger
channel number
channel
interrupt
routing
to SR0
to SR1
Figure 13-14 Channel Interrupt Overview
The limit checking unit uses two boundaries (BOUND0 and BOUND1) to compare with
the conversion result. With these two boundaries, the conversion result space is split into
three areas:
• Area I: The conversion result is below both boundaries.
• Area II: The conversion result is between the two boundaries.
• Area III: The conversion result is above both boundaries.
After a conversion has been completed, a channel interrupt can be triggered according
to the following conditions (selected by the limit check control bit field LCC):
•
•
•
•
•
•
•
•
LCC = 000: No trigger, the channel interrupt is disabled.
LCC = 001: A channel interrupt is generated if the conversion result is not in area I.
LCC = 010: A channel interrupt is generated if the conversion result is not in area II.
LCC = 011: A channel interrupt is generated if the conversion result is not in area III.
LCC = 100: A channel interrupt is always generated (regardless of the boundaries).
LCC = 101: A channel interrupt is generated if the conversion result is in area I.
LCC = 110: A channel interrupt is generated if the conversion result is in area II.
LCC = 111: A channel interrupt is generated if the conversion result is in area III.
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The channel-specific interrupt node pointer CHINPx (x = 0 to 7) selects the service
request output (SR[1:0]) that will be activated upon a channel interrupt trigger.
See Figure 13-15.
CHINF0
CHINP0
rh
to SR0
rw
CHINF1
CHINP1
rw
CHINF7
CHINP7
rh
. ..
. ..
rh
to SR1
rw
channel
number
Figure 13-15 Channel Interrupt Routing
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13.4.9
External Trigger Inputs
The sequential and parallel request sources has one request trigger input REQTRx
(x = 0 - 1) each, through which a conversion request can be started. The input to
REQTRx is selected from eight external trigger inputs (ETRx0 to ETRx7) via a
multiplexer depending on bit field ETRSELx. It is possible to bypass the synchronization
stages for external trigger requests that come synchronous to ADC. This selection is
done via bit SYNENx.
Refer to Section 13.7.9 for description of the external trigger control registers.
rising
edge
detect
ETRx0
ETRx1
...
syn. stages
REQTRx
ETRx7
ETRSELx
rw
SYNENx
rw
Figure 13-16 External Trigger Input
The external trigger inputs to the ADC module are driven by events occuring in the CCU6
module. See Table 13-2.
Table 13-2
External Trigger Input Source
External Trigger Input
CCU6 Event
ETRx0
T13 period-match
ETRx1
T13 compare-match
ETRx2
T12 period-match
ETRx3
T12 compare-match for channel 0
ETRx4
T12 compare-match for channel 1
ETRx5
T12 compare-match for channel 2
ETRx6
Shadow transfer event for multi-channel mode
ETRx7
Correct hall event for multi-channel mode
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13.5
ADC Module Initialization Sequence
The following steps is meant to provide a general guideline on how to initialize the ADC
module. Some steps may be varied or omitted depending on the application
requirements:
1. Configure global control functions:
• Select conversion width (GLOBCTR.DW)
• Select analog clock fADCI divider ratio (GLOBCTR.CTC)
2. Configure arbitration control functions:
• Select request source x
– priority (PRAR.PRIOx)
– conversion start mode (PRAR.CSMx)
• Enable arbitration slot x (PRAR.ASENx)
• Select arbitration mode (PRAR.ARBM)
3. Configure channel control information:
• Select channel x
– limit check control (CHCTRx.LCC)
– target result register (CHCTRx.RESRSEL)
• Select sample time for all channels (INPCR0.STC)
4. Configure result control information:
• Enable/disable result register x
– data reduction (RCRx.DRCTR)
– event interrupt (RCRx.IEN)
– FIFO functionality (RCRx.FEN)
– wait-for-read mode (RCRx.WFR)
– valid flag reset by read access (RCRx.VFCTR)
5. Configure interrupt control functions:
• Select channel x interrupt node pointer (CHINPR.CHINPx)
• Select event x interrupt node pointer (CHINPR.EVINFx)
6. Configure limit check boundaries:
• Select limit check boundaries for all channels (LCBR.BOUND0, LCBR.BOUND1)
7. Configure external trigger control functions:
• Select source x external trigger input (ETRCR.ETRSELx)
• Enable/disable source x external trigger input synchronization (ETRCR.SYNENx)
8. Setup sequential source:
• Enable conversion request (QMR0.ENGT)
• Enable/disable external trigger (QMR0.ENTR)
• Select trigger mode (QMR0.TRMD)
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9. Setup parallel source:
• Enable conversion request (CRMR1.ENGT)
• Enable/disable external trigger (CRMR1.ENTR)
• Enable/disable source interrupt (CRMR1.ENSI)
• Enable/disable autoscan (CRMR1.SCAN)
10.Turn on analog part:
• Set GLOBCTR.ANON (wait for 100 ns)
11.Start sequential request:
• Write to QINR0 (with information such as REQCHNR, RF, ENSI and EXTR)
• Generate a pending conversion request using any method described in
Section 13.4.4.2
12.Start parallel request:
• Write to CRCR1 (no load event) or CRPR1 (automatic load event) the channels to be
converted.
• Generate a load event (if not already available) to trigger a pending conversion
request, using any method described in Section 13.4.5.2
13.Wait for ADC conversion to be completed:
• The source interrupt indicates that the conversion requested by the source is
completed.
• The channel interrupt indicates that the corresponding channel conversion is
completed (with limit check performed).
• The result interrupt indicates that the result (with/without accumulation or FIFO) in the
corresponding result register is ready and can be read.
14.Read ADC result
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13.6
Register Map
The ADC SFRs are located in the standard memory area (RMAP = 0) and are organized
into 7 pages. The ADC_PAGE register is located at address D1H. It contains the page
value and page control information.
ADC_PAGE
Page Register for ADC
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
0
PAGE
w
w
r
rw
0
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
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ADC, V 0.3
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
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Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions of PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read, should be written with 0.
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All ADC register names described in the following sections will be referenced in other
chapters of this document with the module name prefix “ADC_”, e.g., ADC_GLOBCTR.
The addresses of the ADC SFRs are listed in Table 13-3 and Table 13-4.
Table 13-3
SFR Address List for Pages 0-2
Address
Page 0
Page 1
Page 2
CAH
GLOBCTR
CHCTR0
RESR0L
CBH
GLOBSTR
CHCTR1
RESR0H
CCH
PRAR
CHCTR2
RESR1L
CDH
LCBR
CHCTR3
RESR1H
CEH
INPCR0
CHCTR4
RESR2L
CFH
ETRCR
CHCTR5
RESR2H
D2H
–
CHCTR6
RESR3L
D3H
–
CHCTR7
RESR3H
Table 13-4
SFR Address List for Pages 3-6
Address
Page 3
Page 4
Page 5
Page 6
CAH
RESRA0L
RCR0
CHINFR
CRCR1
CBH
RESRA0H
RCR1
CHINCR
CRPR1
CCH
RESRA1L
RCR2
CHINSR
CRMR1
CDH
RESRA1H
RCR3
CHINPR
QMR0
CEH
RESRA2L
VFCR
EVINFR
QSR0
CFH
RESRA2H
–
EVINCR
Q0R0
D2H
RESRA3L
–
EVINSR
QBUR0/QINR0
D3H
RESRA3H
–
EVINPR
–
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Analog-to-Digital Converter
13.7
Register Description
13.7.1
General Function Registers
Register GLOBCTR contains bits that control the analog converter and the conversion
delay.
GLOBCTR
Global Control Register
Reset Value: 30H
7
6
5
4
3
2
1
ANON
DW
CTC
0
rw
rw
rw
r
0
Field
Bits
Type Description
CTC
[5:4]
rw
Conversion Time Control
This bit field defines the divider ratio for the divider
stage of the internal analog clock fADCI. This clock
provides the internal time base for the conversion
and sample time calculations.
00
fADCI = 1/2 × fADCA
01
fADCI = 1/3 × fADCA
10
fADCI = 1/4 × fADCA
11
fADCI = 1/32 × fADCA (default)
DW
6
rw
Data Width
This bit defines the conversion resolution.
0
The result is 10 bits wide (default).
1
The result is 8 bits wide.
ANON
7
rw
Analog Part Switched On
This bit enables the analog part of the ADC module
and defines its operation mode.
0
The analog part is switched off and
conversions are not possible.
To achieve minimal power consumption, the
internal analog circuitry is in its power-down
state and the generation of fADCI is stopped.
1
The analog part of the ADC module is
switched on and conversions are possible.
The automatic power-down capability of the
analog part is disabled.
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Analog-to-Digital Converter
Field
Bits
Type Description
0
[3:0]
r
Reserved
Returns 0 if read; should be written with 0.
Register GLOBSTR contains bits that indicate the current status of a conversion.
GLOBSTR
Global Status Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
CHNR
0
SAMPLE
BUSY
r
rh
r
rh
rh
Field
Bits
Type Description
BUSY
0
rh
Analog Part Busy
This bit indicates that a conversion is currently
active.
0
The analog part is idle.
1
A conversion is currently active.
SAMPLE
1
rh
Sample Phase
This bit indicates that an analog input signal is
currently sampled.
0
The analog part is not in the sampling phase.
1
The analog part is in the sampling phase.
CHNR
[5:3]
rh
Channel Number
This bit field indicates which analog input channel is
currently converted. This information is updated
when a new conversion is started.
0
2, [7:6]
r
Reserved
Returns 0 if read; should be written with 0.
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Analog-to-Digital Converter
13.7.2
Priority and Arbitration Register
Register PRAR contains bits that define the request source priority and the conversion
start mode. It also contains bits that enable/disable the conversion request treatment in
the arbitration slots.
PRAR
Priority and Arbitration Register
Reset Value: 00H
7
6
5
4
3
2
1
0
ASEN1
ASEN0
0
ARBM
CSM1
PRIO1
CSM0
PRIO0
rw
rw
r
rw
rw
rw
rw
rw
Field
Bits
Type Description
PRIO0
0
rw
Priority of Request Source 0
This bit defines the priority of the sequential request
source 0.
0
Low priority
1
High priority
CSM0
1
rw
Conversion Start Mode of Request Source 0
This bit defines the conversion start mode of the
sequential request source 0.
0
The wait-for-start mode is selected.
1
The cancel-inject-repeat mode is selected.
PRIO1
2
rw
Priority of Request Source 1
This bit defines the priority of the parallel request
source 1.
0
Low priority
1
High priority
CSM1
3
rw
Conversion Start Mode of Request Source 1
This bit defines the conversion start mode of the
parallel request source 1.
0
The wait-for-start mode is selected.
1
The cancel-inject-repeat mode is selected.
ARBM
4
rw
Arbitration Mode
This bit defines which arbitration mode is selected.
0
Permanent arbitration (default)
1
Arbitration started by pending conversion
request
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Analog-to-Digital Converter
Field
Bits
Type Description
ASENx
(x = 0 - 1)
[7:6]
rw
Arbitration Slot x Enable
Each bit enables an arbitration slot of the arbiter
round. ASEN0 enables arbitration slot 0, ASEN1
enables slot 1.
If an arbitration slot is disabled, a pending
conversion request of a request source connected to
this slot is not taken into account for arbitration.
0
The corresponding arbitration slot is disabled.
1
The corresponding arbitration slot is enabled.
0
5
r
Reserved
Returns 0 if read; should be written with 0.
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Analog-to-Digital Converter
13.7.3
External Trigger Control Register
Register ETRCR contains bits that select the external trigger input signal source and
enable synchronization of the external trigger input.
ETRCR
External Trigger Control Register
5
Reset Value: 00H
7
6
4
3
2
1
0
SYNEN1
SYNEN0
ETRSEL1
ETRSEL0
rw
rw
rw
rw
Field
Bits
Type Description
ETRSELx
(x = 0 - 1)
[2:0],
[5:3]
rw
External Trigger Selection for Request Source x
This bit field defines which external trigger input
signal is selected.
000 The trigger input ETRx0 is selected.
001 The trigger input ETRx1 is selected.
.....
.....
111 The trigger input ETRx7 is selected.
SYNENx
(x = 0 - 1)
6, 7
rw
Synchronization Enable
0
Synchronizing stage is not in external trigger
input REQTRx path.
1
Synchronizing stage is in external trigger input
REQTRx path.
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Analog-to-Digital Converter
13.7.4
Channel Control Registers
The channel control registers contain bits that select the targeted result register and
control the limit check mechanism. Register CHCTRx defines the settings for the input
channel x.
CHCTRx (x = 0 - 7)
Channel Control Register x
7
6
5
Reset Value: 00H
4
3
2
1
0
0
LCC
0
RESRSEL
r
rw
r
rw
Field
Bits
Type Description
RESRSEL
[1:0]
rw
Result Register Selection
This bit field defines which result register will be the
target of a conversion of this channel.
00
The result register 0 is selected.
01
The result register 1 is selected.
10
The result register 2 is selected.
11
The result register 3 is selected.
LCC
[6:4]
rw
Limit Check Control
This bit field defines the behavior of the limit
checking mechanism.
See coding in Section 13.4.8.2.
0
[3:2], 7
r
Reserved
Returns 0 if read; should be written with 0.
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Analog-to-Digital Converter
13.7.5
Input Class Register
Register INPCR0 contains bits that control the sample time for the input channels.
INPCR0
Input Class 0 Register
7
6
Reset Value: 00H
5
4
3
2
1
0
STC
rw
Field
Bits
Type Description
STC
[7:0]
rw
User’s Manual
ADC, V 0.3
Sample Time Control
This bit field defines the additional length of the
sample time, given in terms of fADCI clock cycles.
A sample time of 2 analog clock cycles is extended
by the programmed value.
13-37
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
13.7.6
Sequential Source Registers
These registers contain the control and status bits of sequential request source 0.
Register QMR0 contains bits that are used to set the sequential request source in the
desired mode.
QMR0
Queue Mode Register
Reset Value: 00H
7
6
5
4
3
2
1
0
CEV
TREV
FLUSH
CLRV
TRMD
ENTR
0
ENGT
w
w
w
w
rw
rw
r
rw
Field
Bits
Type Description
ENGT
0
rw
Enable Gate
This bit enables the gating functionality for the
request source.
0
The gating line is permanently 0.
The source is switched off.
1
The gating line is permanently 1.
The source is switched on.
ENTR
2
rw
Enable External Trigger
This bit enables the external trigger possibility. If
enabled, bit EV is set if a rising edge is detected at
the external trigger input REQTR when at least one
V bit is set in register Q0R0 or QBUR0.
0
The external trigger is disabled.
1
The external trigger is enabled.
TRMD
3
rw
Trigger Mode
This bit defines which trigger mode is selected.
In trigger mode 0, the output lines REQPND and
REQCHNRV can become active at the same time.
In trigger mode 1, the signal REQPND can become
active before REQCHNRV.
0
Trigger mode 0 is selected.
1
Trigger mode 1 is selected.
CLRV
4
w
Clear V Bits
0
No action
1
The bit V in register Q0R0 or QBUR0 is reset.
If QBUR0.V = 1, then QBUR0.V is reset.
If QBUR0.V = 0, then Q0R0.V is reset.
User’s Manual
ADC, V 0.3
13-38
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Field
Bits
Type Description
FLUSH
5
w
Flush Queue
0
No action
1
All bits V in the queue registers and bit EV are
reset. The queue contains no more valid entry.
TREV
6
w
Trigger Event
0
No action
1
A trigger event is generated by software. If the
source waits for a trigger event, a conversion
request is started.
CEV
7
w
Clear Event Bit
0
No action
1
Bit EV is cleared.
0
1
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V 0.3
13-39
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Register QSR0 contains bits that indicate the status of the sequential source.
QSR0
Queue Status Register
7
6
Reset Value: 20H
5
4
3
2
1
0
EMPTY
EV
0
r
rh
rh
r
0
Field
Bits
Type Description
EV
4
rh
Event Detected
This bit indicates that an event has been detected
while V = 1. Once set, this bit is reset automatically
when the requested conversion is started.
0
An event has not been detected.
1
An event has been detected.
EMPTY
5
rh
Queue Empty
This bit indicates if the queue (Q0R0) contains a
valid entry. It is incremented each time a new entry
is written to QINR0. It is decremented each time a
conversion request from the queue is started. A new
entry is ignored if the queue is filled (EMPTY = 0).
0
The queue is filled (1 valid entry).
1
The queue is empty.
0
[3:0],
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
Register Q0R0 contains bits that monitor the status of the current sequential request.
Q0R0
Queue 0 Register 0
Reset Value: 00H
7
6
5
4
3
EXTR
ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
r
rh
User’s Manual
ADC, V 0.3
13-40
2
1
0
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Field
Bits
Type Description
REQCHNR
[2:0]
rh
Request Channel Number
This bit field indicates the channel number that will
be or is currently requested.
V
4
rh
Request Channel Number Valid
This bit indicates if the data in REQCHNR, RF, ENSI
and EXTR is valid. Bit V is set when a valid entry is
written to the queue input register QINR0 (or by an
update by intermediate queue registers).
0
The data is not valid.
1
The data is valid.
RF
5
rh
Refill
This bit indicates if the pending request is discarded
after being executed (conversion start) or if it is
automatically refilled in the top position of the
request queue.
0
The request is discarded after conversion
start.
1
The request is refilled in the queue after
conversion start.
ENSI
6
rh
Enable Source Interrupt
This bit indicates if a source interrupt will be
generated when the conversion is completed. The
interrupt trigger becomes activated if the conversion
requested by the source has been completed and
ENSI = 1.
0
The source interrupt generation is disabled.
1
The source interrupt generation is enabled.
EXTR
7
rh
External Trigger
This bit defines if the conversion request is sensitive
to an external trigger event.
The event flag (bit EV) indicates if an external event
has taken place and a conversion can be requested.
0
Bit EV not used to start conversion request.
1
Bit EV is used to start conversion request.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V 0.3
13-41
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
The registers QBUR0 and QINR0 share the same register address. A read operation at
this register address will deliver the ‘rh’ bits of the QBUR0 register, while a write
operation to the same address will target the ‘w’ bits of the QINR0 register.
Register QBUR0 contains bits that monitor the status of an aborted sequential request.
QBUR0
Queue Backup Register 0
Reset Value: 00H
7
6
5
4
3
2
1
0
EXTR
ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
r
rh
Field
Bits
Type Description
REQCHNR
[2:0]
rh
Request Channel Number
This bit field is updated by bit field Q0R0.REQCHNR
when the conversion requested by Q0Rs is started.
V
4
rh
Request Channel Number Valid
This bit indicates if the data in REQCHNR, RF, ENSI,
and EXTR is valid. Bit V is set if a running conversion
is aborted. It is reset when the conversion is started.
0
The backup register does not contain valid
data, because the conversion described by
this data has not been aborted.
1
The data is valid. The aborted conversion is
requested before taking into account what is
requested by Q0R0.
RF
5
rh
Refill
This bit is updated by bit Q0R0.RF when the
conversion requested by Q0R0 is started.
ENSI
6
rh
Enable Source Interrupt
This bit is updated by bit Q0R0.ENSI when the
conversion requested by Q0R0 is started.
EXTR
7
rh
External Trigger
This bit is updated by bit Q0R0.EXTR when the
conversion requested by Q0R0 is started.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V 0.3
13-42
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Register QINR0 is the entry register for sequential requests.
QINR0
Queue Input Register 0
Reset Value: 00H
7
6
5
4
3
2
1
0
EXTR
ENSI
RF
0
REQCHNR
w
w
w
r
w
Field
Bits
Type Description
REQCHNR
[2:0]
w
Request Channel Number
This bit field defines the requested channel number.
RF
5
w
Refill
This bit defines the refill functionality.
ENSI
6
w
Enable Source Interrupt
This bit defines the source interrupt functionality.
EXTR
7
w
External Trigger
This bit defines the external trigger functionality.
0
[4:3]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V 0.3
13-43
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
13.7.7
Parallel Source Registers
These registers contain the control and status bits of parallel request source 1.
Register CRCR1 contains the bits that are copied to the pending register (CRPR1) when
the load event occurs. This register can be accessed at two different addresses (one
read view, two write views). The first address for read and write access is the address
given for CRCR1. The second address for write actions is given for CRPR1. A write
operation to CRPR1 leads to a data write to the bits in CRCR1 with an automatic load
event one clock cycle later.
CRCR1
Conversion Request Control Register 1
Reset Value: 00H
7
6
5
4
3
2
1
CH7
CH6
CH5
CH4
0
rwh
rwh
rwh
rwh
r
0
Field
Bits
Type Description
CHx
(x = 4 - 7)
x
rwh
Channel Bit x
Each bit corresponds to one analog channel, the
channel number x is defined by the bit position in the
register. The corresponding bit x in the conversion
request pending register will be overwritten by this bit
when the load event occurs.
0
The analog channel x will not be requested for
conversion by the parallel request source.
1
The analog channel x will be requested for
conversion by the parallel request source.
0
[3:0]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V 0.3
13-44
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Register CRPR1 contains bits that request a conversion of the corresponding analog
channel. The bits in this register have only a read view. A write operation to this address
leads to a data write to CRCR1 with an automatic load event one clock cycle later.
CRPR1
Conversion Request Pending Register 1
Reset Value: 00H
7
6
5
4
3
2
1
CHP7
CHP6
CHP5
CHP4
0
rwh
rwh
rwh
rwh
r
0
Field
Bits
Type Description
CHPx
(x = 4 - 7)
x
rwh
Channel Pending Bit x
Write view:
A write to this address targets the bits in register
CRCR1.
Read view:
Each bit corresponds to one analog channel; the
channel number x is defined by the bit position in the
register.
The arbiter automatically resets (at start of
conversion) or sets it again (at abort of conversion)
for the corresponding analog channel.
0
The analog channel x is not requested for
conversion by the parallel request source.
1
The analog channel x is requested for
conversion by the parallel request source.
0
[3:0]
r
Reserved
Returns 0 if read; should be written with 0.
Note: The bits that can be read from this register location are generally ‘rh’. They cannot
be modified directly by a write operation. A write operation modifies the bits in
CRCR1 (that is why they are marked ‘rwh’) and leads to a load event one clock
cycle later.
User’s Manual
ADC, V 0.3
13-45
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Register CRMR1 contains bits that are used to set the request source in the desired
mode.
CRMR1
Conversion Request Mode Register 1
Reset Value: 00H
7
6
5
4
3
2
1
0
0
LDEV
CLRPND
SCAN
ENSI
ENTR
0
ENGT
r
w
w
rw
rw
rw
r
rw
Field
Bits
Type Description
ENGT
0
rw
Enable Gate
This bit enables the gating functionality for the
request source.
0
The gating line is permanently 0.
The source is switched off.
1
The gating line is permanently 1.
The source is switched on.
ENTR
2
rw
Enable External Trigger
This bit enables the external trigger possibility. If
enabled, the load event takes place if a rising edge
is detected at the external trigger input REQTR.
0
The external trigger is disabled.
1
The external trigger is enabled.
ENSI
3
rw
Enable Source Interrupt
This bit enables the request source interrupt. This
interrupt can be generated when the last pending
conversion is completed for this source (while
PND = 0).
0
The source interrupt is disabled.
1
The source interrupt is enabled.
SCAN
4
rw
Autoscan Enable
This bit enables the autoscan functionality. If
enabled, the load event is automatically generated
when a conversion (requested by this source) is
completed and PND = 0.
0
The autoscan functionality is disabled.
1
The autoscan functionality is enabled.
User’s Manual
ADC, V 0.3
13-46
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Field
Bits
Type Description
CLRPND
5
w
Clear Pending Bits
0
No action
1
The bits in register CRPR1 are reset.
LDEV
6
w
Generate Load Event
0
No action
1
The load event is generated.
0
1, 7
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V 0.3
13-47
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
13.7.8
Result Registers
The result registers deliver the conversion results and, optionally, the channel number
that has lead to the latest update of the result register. The result registers are available
as different read views at different addresses. The following bit fields can be read from
the result registers, depending on the selected read address. For details on the
conversion result alignment and width, see Section 13.4.7.5.
Field
Bits
Type Description
RESULT RESRxL[7:6],
RESRxH
or
RESRAxL[7:5],
RESRAxH
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
CHNR
[2:0]
rh
Channel Number
This bit field contains the channel number of the
latest register update.
DRC
3
rh
Data Reduction Counter
This bit indicates how many conversion results
have still to be accumulated to generate the final
result for data reduction.
0
The final result is available in the result
register.
The valid flag is automatically set when this
bit field is set to 0.
1
One more conversion result must be added
to obtain the final result in the result register.
The valid flag is automatically reset when
this bit field is set to 1.
VF
4
rh
Valid Flag for Result Register x
This bit indicates that the contents of the result
register x are valid.
0
The result register x does not contain valid
data.
1
The result register x contains valid data.
User’s Manual
ADC, V 0.3
13-48
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Normal Read View RESRx
This view delivers the 8-bit or 10-bit conversion result and a 3-bit channel number. The
corresponding valid flag is cleared when the high byte of the register is accessed by a
read command, provided that bit RCRx.VFCR is set.
RESRxL (x = 0 - 3)
Result Register x Low
7
Reset Value: 00H
6
5
4
3
2
RESULT[1:0]
0
VF
DRC
CHNR
rh
r
rh
rh
rh
RESRxH (x = 0 - 3)
Result Register x High
7
6
1
0
Reset Value: 00H
5
4
3
2
1
0
RESULT[9:2]
rh
Accumulated Read View RESRAx
This view delivers the accumulated 9-bit or 11-bit conversion result and a 3-bit channel
number. The corresponding valid flag is cleared when the high byte of the register is
accessed by a read command, provided that bit RCRx.VFCR is set.
RESRAxL (x = 0 - 3)
Result Register x, View A Low
7
6
5
Reset Value: 00H
4
3
2
RESULT[2:0]
VF
DRC
CHNR
rh
rh
rh
rh
RESRAxH (x = 0 - 3)
Result Register x, View A High
7
6
5
1
0
Reset Value: 00H
4
3
2
1
0
RESULT[10:3]
rh
User’s Manual
ADC, V 0.3
13-49
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Writing a 1 to a bit position in register VFCR clears the corresponding valid flag in
registers RESRx/RESRAx. If a hardware event triggers the setting of a bit VFx and
VFCx = 1, the bit VFx is cleared (software overrules hardware).
VFCR
Valid Flag Clear Register
7
6
Reset Value: 00H
5
4
3
2
1
0
0
VFC3
VFC2
VFC1
VFC0
r
w
w
w
w
Field
Bits
Type Description
VFCx
(x = 0 - 3)
x
w
Clear Valid Flag for Result Register x
0
No action
1
Bit VFR.x is reset.
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
The result control registers RCRx contain bits that control the behavior of the result
registers and monitor their status.
RCRx (x = 0 - 3)
Result Control Register x
Reset Value: 00H
7
6
5
4
VFCTR
WFR
FEN
IEN
0
DRCTR
rw
rw
rw
rw
r
rw
User’s Manual
ADC, V 0.3
3
13-50
2
1
0
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Field
Bits
Type Description
DRCTR
0
rw
Data Reduction Control
This bit defines how many conversion results are
accumulated for data reduction. It defines the reload
value for bit DRC.
0
The data reduction filter is disabled.
The reload value for DRC is 0, so the
accumulation is done over 1 conversion.
1
The data reduction filter is enabled.
The reload value for DRC is 1, so the
accumulation is done over 2 conversions.
IEN
4
rw
Interrupt Enable
This bit enables the event interrupt related to the
result register x. An event interrupt can be generated
when DRC is set to 0 (after decrementing or by
reload).
0
The event interrupt is disabled.
1
The event interrupt is enabled.
FEN
5
rw
FIFO Enable
This bit enables the FIFO functionality for result
register x.
0
The FIFO functionality is disabled.
1
The FIFO functionality is enabled.
WFR
6
rw
Wait-for-Read Mode
This bit enables the wait-for-read mode for result
register x.
0
The wait-for-read mode is disabled.
1
The wait-for-read mode is enabled.
VFCTR
7
rw
Valid Flag Control
This bit enables the reset of valid flag (by read
access to high byte) for result register x.
0
VF unchanged by read access to RESRxH/
RESRAxH. (default)
1
VF reset by read access to RESRxH/
RESRAxH.
0
[3:1]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V 0.3
13-51
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
13.7.9
Interrupt Registers
Register CHINFR monitors the activated channel interrupt flags.
CHINFR
Channel Interrupt Flag Register
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINF7
CHINF6
CHINF5
CHINF4
CHINF3
CHINF2
CHINF1
CHINF0
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
CHINFx
(x = 0 - 7)
x
rh
Interrupt Flag for Channel x
This bit monitors the status of the channel interrupt x.
0
A channel interrupt for channel x has not
occurred.
1
A channel interrupt for channel x has occurred.
Writing a 1 to a bit position in register CHINCR clears the corresponding channel
interrupt flag in register CHINFR. If a hardware event triggers the setting of a bit CHINFx
and CHINCx = 1, the bit CHINFx is cleared (software overrules hardware).
CHINCR
Channel Interrupt Clear Register
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINC7
CHINC6
CHINC5
CHINC4
CHINC3
CHINC2
CHINC1
CHINC0
w
w
w
w
w
w
w
w
Field
Bits
Type Description
CHINCx
(x = 0 - 7)
x
w
User’s Manual
ADC, V 0.3
Clear Interrupt Flag for Channel x
0
No action
1
Bit CHINFR.x is reset.
13-52
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Writing a 1 to a bit position in register CHINSR sets the corresponding channel interrupt
flag in register CHINFR and generates an interrupt pulse.
CHINSR
Channel Interrupt Set Register
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINS7
CHINS6
CHINS5
CHINS4
CHINS3
CHINS2
CHINS1
CHINS0
w
w
w
w
w
w
w
w
Field
Bits
Type Description
CHINSx
(x = 0 - 7)
x
w
Set Interrupt Flag for Channel x
0
No action
1
Bit CHINFR.x is set and an interrupt pulse is
generated.
The bits in register CHINPR define the service request output line, SRx (x = 0 or 1), that
is activated if a channel interrupt is generated.
CHINPR
Channel Interrupt Node Pointer Register
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINP7
CHINP6
CHINP5
CHINP4
CHINP3
CHINP2
CHINP1
CHINP0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
CHINPx
(x = 0 - 7)
x
rw
User’s Manual
ADC, V 0.3
Interrupt Node Pointer for Channel x
This bit defines which SR lines becomes activated if
the channel x interrupt is generated.
0
The line SR0 becomes activated.
1
The line SR1 becomes activated.
13-53
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Register EVINFR monitors the activated event interrupt flags.
EVINFR
Event Interrupt Flag Register
Reset Value: 00H
7
6
5
4
EVINF7
EVINF6
EVINF5
EVINF4
rh
rh
rh
rh
Field
Bits
3
2
1
0
0
EVINF1
EVINF0
r
rh
rh
Type Description
EVINFx
[1:0],
(x = 0 - 1, 4 - 7) [7:4]
rh
Interrupt Flag for Event x
This bit monitors the status of the event interrupt x.
0
An event interrupt for event x has not occurred.
1
An event interrupt for event x has occurred.
0
r
Reserved
Returns 0 if read; should be written with 0.
[3:2]
Writing a 1 to a bit position in register EVINCR clears the corresponding event interrupt
flag in register EVINFR. If a hardware event triggers the setting of a bit EVINFx and
EVINCx = 1, the bit EVINFx is cleared (software overrules hardware).
EVINCR
Event Interrupt Clear Flag Register
Reset Value: 00H
7
6
5
4
EVINC7
EVINC6
EVINC5
EVINC4
w
w
w
w
Field
Bits
3
2
1
0
0
EVINC1
EVINC0
r
w
w
Type Description
EVINCx
[1:0],
(x = 0 - 1, 4 - 7) [7:4]
w
Clear Interrupt Flag for Event x
0
No action
1
Bit EVINFR.x is reset.
0
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V 0.3
[3:2]
13-54
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
Writing a 1 to a bit position in register EVINSR sets the corresponding event interrupt flag
in register EVINFR and generates an interrupt pulse (if the interrupt is enabled).
EVINSR
Event Interrupt Set Flag Register
Reset Value: 00H
7
6
5
4
EVINS7
EVINS6
EVINS5
EVINS4
w
w
w
w
Field
Bits
3
2
1
0
0
EVINS1
EVINS0
r
w
w
Type Description
EVINSx
[1:0],
(x = 0 - 1, 4 - 7) [7:4]
w
Set Interrupt Flag for Event x
0
No action
1
Bit EVINFR.x is set.
0
r
Reserved
Returns 0 if read; should be written with 0.
[3:2]
The bits in register EVINPR define the service request output line, SRx (x = 0 or 1), that
is activated if an event interrupt is generated.
EVINPR
Event Interrupt Node Pointer Register
Reset Value: 00H
7
6
5
4
EVINP7
EVINP6
EVINP5
EVINP4
rw
rw
rw
rw
Field
Bits
3
2
1
0
0
EVINP1
EVINP0
r
rw
rw
Type Description
EVINPx
[1:0],
(x = 0 - 1, 4 - 7) [7:4]
rw
Interrupt Node Pointer for Event 0
This bit defines which SR lines becomes activated if
the event 0 interrupt is generated.
0
The line SR0 becomes activated.
1
The line SR1 becomes activated.
0
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V 0.3
[3:2]
13-55
V 0.2, 2005-01
XC866
Analog-to-Digital Converter
The bit fields in register LCBR define the four MSB of the compare values (boundaries)
used by the limit checking unit. The values defined in bit fields BOUND0 and BOUND1
are concatenated with either four (8-bit conversion) or six (10-bit conversion) 0s at the
end to form the final value used for comparison with the converted result. For example,
the reset value of BOUND1 (BH) will translate into B0H for an 8-bit comparison, and 2C0H
for a 10-bit comparison.
LCBR
Limit Check Boundary Register
7
6
5
Reset Value: B7H
4
3
1
BOUND1
BOUND0
rw
rw
Field
Bits
Type Description
BOUNDx
(x = 0 - 1)
[3:0],
[7:4]
rw
User’s Manual
ADC, V 0.3
2
0
Boundary for Limit Checking
This bit field defines the four MSB of the compare
value used by the limit checking unit. The result of
the limit check is used for interrupt generation.
13-56
V 0.2, 2005-01
XC866
On-Chip Debug Support
14
On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
•
•
•
•
use the built-in debug functionality of the XC800 Core
add a minimum of hardware overhead
provide support for most of the operations by a Monitor Program
use standard interfaces to communicate with the Host (a Debugger)
Features:
•
•
•
•
•
Set breakpoints on instruction address and within a specified address range
Set breakpoints on internal RAM address
Support unlimited software breakpoints in Flash/RAM code region
Process external breaks
Step through the program code
User’s Manual
OCDS, V 0.2
14-1
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XC866
Functional Description
14.1
Functional Description
The OCDS functional blocks are shown in Figure 14-1. The Monitor Mode Control
(MMC) block at the center of OCDS system brings together control signals and supports
the overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals. After processing memory
address and control signals from the core, the MMC provides proper access to the
dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for
work-data and Monitor-stack). The OCDS system is accessed through the JTAG1),
which is an interface dedicated exclusively for testing and debugging activities and is not
normally used in an application. The dedicated MBC pin is used for external
configuration and debugging control.
Note: All the debug functionality described here can normally be used only after XC866
has been started in OCDS mode.
Note: For more information on boot configuration options, see Chapter 7.2.3.
JTAG Module
Primary
Debug
Interface
TMS
TCK
TDI
TDO
JTAG
Memory
Control
Unit
TCK
TDI
TDO
Control
User
Boot/
Program Monitor
Memory ROM
Reset
Monitor &
Bootstrap loader
Control line
Monitor Mode Control
MBC
OCDS
Interrupt
System
Control
Unit
User
Internal
RAM
NMI Report
Monitor
RAM
CPU Reset
Clock
- parts of OCDS
Reset Clock Debug PROG PROG Memory
Interface & IRAM Data Control
Addresses
XC800
Figure 14-1 XC866 OCDS: Block Diagram
1)
The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
User’s Manual
OCDS, V 0.2
14-2
V 0.2, 2005-01
XC866
On-Chip Debug Support
14.2
Debugging
The on-chip debug system can be described in two parts. The first part covers the
generation of Debug Events and the second part describes the Debug Actions that are
taken when a debug event is generated.
• Debug events:
– Hardware Breakpoints
– Software Breakpoints
– External Breaks
• Debug event actions:
– Call the Monitor Program
– Activate the MBC pin
The XC866 debug operation is based on close interaction between the OCDS hardware
and a specialized software called the Monitor program.
14.2.1
Debug Events
The OCDS system recognizes a number of different debug events, which are also called
breakpoints or simply breaks.
Depending on how the break events are processed in time, they can be classified into
three types of breakpoints:
• Break Before Make
The break happens just before the break instruction, i.e. the instruction causing the
break, is executed. Therefore, the break instruction itself will be the next instruction
from the user program flow but executed only after the relevant debug action has been
taken.
• Break After Make
The break happens immediately after the break instruction causing it has been
executed. Therefore, the break instruction itself has already been executed when the
relevant debug action is taken.
• Break Now
The events of this type are asynchronous to the code execution inside the XC866 and
there is no “instruction causing the debug event” in this case. The debug action is
performed by OCDS “as soon as possible” once the debug event is raised.
User’s Manual
OCDS, V 0.2
14-3
V 0.2, 2005-01
XC866
Debugging
14.2.1.1 Hardware Breakpoints
Hardware breakpoints are generated by observing certain address buses within the
XC866 system. The bus relevant to the hardware breakpoint type is continuously
compared against certain registers where addresses for the breakpoints have been
programmed.
The hardware breakpoints can be classified under two types:
• depending on the address bus supervised
– Breakpoints on Instruction Address
Program Memory Address (PROGA) is observed
– Breakpoints on IRAM Address
Internal Data Memory Addresses (SOURCE_A, DESTIN_A) are observed
• depending on the way comparison is done
– Equal breakpoints
Comparison is done only against one value; the break event is raised when only
this value is matched.
– Range breakpoints
Comparison is done against two values; the break event is raised when a value
observed is found belonging to the range between two programmed values
(inclusively).
Breakpoints on Instruction Address
These Instruction Pointer (IP) breakpoints are generated when a break address is
matched for the first byte of an instruction that is going to be executed i.e., for the
address within Program Memory where an instruction opcode is to be fetched from.
Note: In the cases of 2- and 3-byte instructions, the break will not be generated for
addresses of the second and third instruction bytes.
If the IP breakpoints are of the Break Before Make type, the instruction at the breakpoint
will be executed only after the proper debug action is taken.
The OCDS in XC866 supports both equal breakpoints and range breakpoints on
Instruction address (see “Configurations of Hardware Breakpoints” on Page 14-5).
Breakpoints on IRAM Address
These breakpoints are generated when a break address is matched with the address
from the Internal Data Memory (IRAM), to which location an instruction performs read or
write access.
The IRAM breakpoints are of the Break After Make type; the proper debug action is taken
immediately after the operation to the breakpoint address is already performed.
The OCDS in XC866 supports only range breakpoints on IRAM address.
User’s Manual
OCDS, V 0.2
14-4
V 0.2, 2005-01
XC866
On-Chip Debug Support
When the Internal Data Memory is RAM, the OCDS differentiates between a breakpoint
on read and a breakpoint on write operation to this IRAM.
Configurations of Hardware Breakpoints
The OCDS in XC866 allows the setting of up to 4 hardware breakpoints labeled HWBPx
(x = 0 - 3) (16-bit values) in various configurations as follows:
• HWBP0
• HWBP1
– two equal breakpoints on
Instruction Address=HWBP0 and Instruction Address=HWBP1, or
– one range breakpoint on HWBP0 <= Instruction Address <= HWBP1
• HWBP2
– one equal breakpoint on Instruction Address=HWBP2, or
– one range breakpoint on HWBP2L <= IRAM Read Address <= HWBP2H
• HWBP3
– one equal breakpoint on Instruction Address=HWBP3, or
– one range breakpoint on HWBP3L <= IRAM Write Address <= HWBP3H
In XC866, the Program Memory address is 16-bit wide, while the Internal Data Memory
addresses (both for Read and Write) are 8-bit wide. This is why the complete HWBP2
and HWBP3 values are used to generate IP breakpoints, while the low and high bytes
HWBPxL and HWBPxH (x = 2 - 3) are used separately to generate IRAM breakpoints.
Setting both the values to the same address for a range breakpoint leads to generation
of an equal breakpoint.
14.2.1.2 Software Breakpoints
These breakpoints use the XC800-specific (not 8051-standard) TRAP instruction,
decoded by the core while at the same time the TRAP_EN bit within the Extended
Operation (EO) register is set to 1.
Upon fetching a TRAP instruction, a Break Before Make breakpoint is generated and the
relevant Break Action is taken.
The software breakpoints are in fact similar in behavior to the equal breakpoints on
Instruction address, except that they are raised by a program code instead of specialized
(compare) logic.
An unlimited number of software breakpoints can be set by replacing the original
instruction opcodes in the user program. However, this is possible only at addresses
where a writable memory (RAM/Flash) is implemented.
Note: In order to continue user program execution after the debug event, an external
Debugger must restore the original opcode at the address of the current software
breakpoint.
User’s Manual
OCDS, V 0.2
14-5
V 0.2, 2005-01
XC866
Debugging
14.2.1.3 External Breaks
These debug events are of the Break Now type and can be raised in two ways:
• by a request via the JTAG interface; using a special sequence, an external device
connected to the JTAG can break a user program running on the XC866 and start a
debug session.
• by asserting low the dedicated Monitor and BootStrap loader Control line (MBC) while
the XC866 is running; used for reaction to asynchronous events from the external
world.
14.2.2
Debug Actions
In case of a debug event, the OCDS system can respond in two ways depending on the
current configuration.
14.2.2.1 Call the Monitor Program
XC866 comes with an on-chip Monitor program, factory-stored into the non-volatile
Monitor ROM (see Figure 14-1). Activating this program is the primary and basic OCDS
reaction to recognized debug events.
The OCDS hardware ensures that the Monitor is always safely started, and fully
independent of the current system status at the moment the debug action is taken. Also,
additional interrupt requests raised meanwhile will not disturb the Monitor’s functioning.
Once started, the Monitor runs with own stack- and data-work memory (see Monitor
RAM in Figure 14-1), which guarantees that all of the core and memory resources will
be found untouched when returning control back to the user program.
The functions of the XC866 Monitor include:
• communication with an external Debugger via the JTAG interface
• read/write access to arbitrary memory locations and Special Function Registers
(SFRs), including the Instruction Pointer
• configuring OCDS and setting/removing breakpoints
• executing single instruction (step-mode)
Note: Detailed descriptions of the Monitor program functionality and the JTAG
communication protocol are not provided in this document.
14.2.2.2 Activate the MBC pin
The MBC pin can be driven actively low by OCDS in reaction to debug events.
This functionality allows two alternative configurations:
• as an action additional to the Monitor program start
• as the only OCDS response while temporarily (for 4 SCLK clock cycles) suspending
the core activity; this is the fastest reaction to the external world
User’s Manual
OCDS, V 0.2
14-6
V 0.2, 2005-01
XC866
On-Chip Debug Support
14.3
Register Description
From the programmer’s point of view, OCDS is represented by a total of 8 registeraddresses (see Table 14-1), all located within the mapped SFR area.
Table 14-1
Register
Short Name
OCDS Directly Addressable Registers
Address
(mapped)
Register Full Name
MMCR
F1H
Monitor Mode Control Register
MMSR
F2H
Monitor Mode Status Register
MMBPCR
F3H
Monitor Mode Breakpoints Control Register
MMICR
F4H
Monitor Mode Interrupt Control Register
MMCR2
E9H
Monitor Mode Control Register 2
MMDR
F5H
Monitor Mode Data Register
HWBPSR
F6H
Hardware Breakpoints Select Register
HWBPDR
F7H
Hardware Breakpoints Data Register
Additionally, there are 8 Hardware Breakpoint registers, which are accessible indirectly
via HWBPSR and HWBPDR (see Table 14-2).
Table 14-2
OCDS Indirectly Accessible Registers
Register
Short Name
Register Full Name
HWBP0L
Hardware Breakpoint 0 Low Register
HWBP0H
Hardware Breakpoint 0 High Register
HWBP1L
Hardware Breakpoint 1 Low Register
HWBP1H
Hardware Breakpoint 1 High Register
HWBP2L
Hardware Breakpoint 2 Low Register
HWBP2H
Hardware Breakpoint 2 High Register
HWBP3L
Hardware Breakpoint 3 Low Register
HWBP3H
Hardware Breakpoint 3 High Register
Note: The OCDS registers are dedicated primarily to the on-chip Monitor program, and
the user is strongly advised not to access them, as this can cause an unexpected
behavior of the system.
User’s Manual
OCDS, V 0.2
14-7
V 0.2, 2005-01
XC866
Register Description
The Hardware Breakpoint registers can be used for general purposes only if the XC866
is not started in OCDS mode and no external device is connected to the JTAG interface.
See Table 14-1, Table 14-2 and the description below.
HWBPSR
Hardware Breakpoints Select Register mapped SFR (F6H)
7
6
5
4
3
Reset value: 00H
2
1
0
BPSEL_P
BPSEL
r
w
rw
0
Field
Bits
Type Description
BPSEL
[3:0]
rw
BreakPoint Register Select
BPSEL_P
4
w
Bit Protection
0
BPSEL unchangeable
1
BPSEL can be changed
0
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
Table 14-3
BPSEL
HWBPSR [3:0]: Selecting Hardware Breakpoint Registers
Register Selected
BPSEL
Register Selected
0xxx
Reserved
–
–
1000
HWBP0L
1001
HWBP0H
1010
HWBP1L
1011
HWBP1H
1100
HWBP2L
1101
HWBP2H
1110
HWBP3L
1111
HWBP3H
HWBPDR
Hardware Breakpoints Data Register mapped SFR (F7H)
7
6
5
4
3
2
Reset Value: 00H
1
0
HWBPxx
rw
User’s Manual
OCDS, V 0.2
14-8
V 0.2, 2005-01
XC866
On-Chip Debug Support
Field
Bits
Type Description
HWBPxx
[7:0]
rw
14.3.1
Data to be written into/read from a HWBPxx register,
as currently selected by HWBPSR (see Table 14-3)
JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the
device(s) connected to the JTAG interface. Its content is shifted out when
INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is
also true immediately after reset.
The JTAG ID register contents for the XC866 Flash devices are given in Table 14-4.
Table 14-4
JTAG ID Summary
Device Type
Device Name
JTAG ID
Flash
XC866L-4FRA
1010 0083H
XC866-4FRA
100F 5083H
XC866L-2FRA
1010 2083H
XC866-2FRA
1010 1083H
User’s Manual
OCDS, V 0.2
14-9
V 0.2, 2005-01
XC866
Keyword Index
15
Index
15.1
Keyword Index
This section lists a number of keywords which refer to specific details of the XC866 in
terms of its architecture, its functional units, or functions.
A
Accumulator 2-4
Alternate functions 6-10
Input 6-10
Output 6-3, 6-10
Analog input clock 13-3
Analog-to-Digital Converter 13-1
Interrupt 13-21
Channel 13-23
Event 13-22
Node pointer 13-24
Low power mode 13-7
Module clock 13-3
Register description 13-31
Register map 13-28
Arbitration round 13-9
Arbitration slot 13-9
Arithmetic 2-2
Asynchronous modes 10-2
Automatic refill 13-11
Autoscan 13-15
B
Baud rate 10-11
Baud rate clock 10-11
Baud rate generation 10-26
Baud-rate generator 10-10
Bit protection scheme 3-12
Bitaddressable 3-9
Boot options 7-6
BSL mode 7-6
OCDS mode 7-6
User mode 7-6
User’s Manual
Boot ROM 3-1
Boot ROM operating mode 3-26
BootStrap Loader Mode 3-27
OCDS mode 3-27
User mode 3-26
Booting scheme 7-6
BootStrap Loader 3-27, 4-6, 4-9
Brownout reset 7-5
Buffer mechanism 4-4
C
Cancel-Inject-Repeat 13-10
Capture/Compare Unit 6 12-1
Register description 12-29
Register map 12-28
Central Processing Unit 2-1
Circular stack memory 4-4
Clock source 7-11
Clock system 7-9
Continuous transfer operation 10-25
Conversion error 13-4
Conversion phase 13-5
Correction algorithm 4-8
CPU 2-1
D
Data Flash 4-2, 4-3
Data memory 3-3
Data pointer 2-4
Data reduction 13-17
Counter 13-18
Debug 14-3
Events 14-3
15-1
V 0.2, 2005-01
XC866
Keyword Index
D-Flash 4-2, 4-3
Digital input clock 13-3
Direct drive 7-11
Direct feed-through 6-4
Document
Acronyms 1-14
Terminology 1-13
Textual convention 1-12
Dynamic error detection 4-8
E
EEPROM emulation 4-4
Embedded voltage regulator 7-1
Features 7-2
Low power voltage regulator 7-2
Main voltage regulator 7-2
Threshold voltage levels 7-2
Error Correction Code 4-8
Extended operation 2-6
External breaks 14-6
Break now 14-6
External data memory 3-3
External oscillator 7-9, 7-11
F
Flash 4-1
Endurance 4-4
Erase mode 4-7
Non-volatile 4-1
Operating modes 4-7
Power-down mode 4-7
Program mode 4-7
Program width 4-6
Ready-to-read mode 4-7
Sector 4-3
Flash devices 3-1
Flash program memory 3-1
Flash Timer NMI 4-11
Full-duplex operation 10-21
G
H
Half-duplex operation 10-24
Hall sensor mode
Actual hall pattern 12-19
Block commutation 12-21
Brushless-DC 12-19, 12-20
Correct hall event 12-19
Expected Hall pattern 12-19
Hall pattern 12-19
Modulation pattern 12-19
Noise filter 12-19
Hamming code 4-8
Hardware breakpoints 14-4
Hardware reset 7-4
High-impedance 6-2
I
Idle mode 7-13, 8-2
In-Application Programming 4-10
Input class 13-8
Instruction decoder 2-2
Instruction timing 2-8, 2-10
CPU state 2-8
Mnemonic 2-10
Wait state 2-8
In-System Programming 4-9
Internal analog clock 13-3
Maximum frequency 13-3
Internal data memory 3-3
Internal RAM 3-1
Interrupt handling 5-23
Interrupt priority 5-21
Interrupt request flags 5-22
Interrupt response time 5-24
Interrupt source and vector 5-2, 5-8
Interrupt system 5-1
Register description 5-9
J
JTAG ID 14-9
Gate disturb 4-6
GPIO 6-1, 6-6
User’s Manual
15-2
V 0.2, 2005-01
XC866
Keyword Index
K
O
Kernel registers 6-5
Direction control register 6-7
Offset addresses 6-5
On-Chip Debug Support 14-1
Register description 14-7
Register map 14-7
On-chip oscillator 7-9
L
P
Limit checking 13-17
LIN 10-14–10-18
Baud rate detection 10-17
Break field 10-15
Header transmission 10-16
LIN frame 10-14
LIN protocol 10-14
Synch byte 10-15
M
Maskable interrupt 5-1
Extended 5-2
External 5-2
Internal 5-1
Memory organization 3-1
Special Function Registers 3-4
Address extension by mapping 3-4
Mapped 3-4
Standard 3-4
Address extension by paging 3-6
Local address extension 3-6
Save and restore 3-7
Minimum erase width 4-3
Modulation 12-13
Monitor mode control 14-2
Monitor RAM 14-2
Data 14-6
Stack 14-6
Monitor ROM 14-2
Multi-channel mode 12-17
Multifold replications 4-4
Multiprocessor communication 10-7
N
Non-maskable interrupt 5-1
Events 5-1
User’s Manual
P0 register description 6-5, 6-16
P1 register description 6-21
P2 register description 6-26
P3 register description 6-31
Parallel ports 6-1
Bidirectional port structure 6-3
Driver 6-2, 6-7
General port structure 6-3
General register description 6-5
Input port structure 6-4
Kernel registers
Open drain control register 6-7
Normal mode 6-2, 6-7
Open drain mode 6-2, 6-7
Parallel request source 13-13
Permanent arbitration 13-9
Personal computer host 4-9
P-Flash 4-2, 4-3
Phase-Locked Loop 7-9
Changing PLL parameters 7-11
Loss-of-Lock operation 7-10
Loss-of-Lock recovery 7-10
Pin
Configuration 1-5
Definitions and functions 1-6
PLL
Loss-of-lock 7-10
Startup 7-10
PLL base mode 7-12
PLL bypass 7-11
PLL mode 7-12
Power control 2-7
Power saving modes 8-1
Power supply system 7-1
Power-down mode 7-13, 8-3
15-3
V 0.2, 2005-01
XC866
Keyword Index
Entering power-down mode 8-3
Exiting power-down mode 8-3
Power-down wake-up reset 7-4
Power-on reset 7-2, 7-3
Prescaler mode 7-12
Prewarning period 9-2
Processor architecture 2-1
Instruction timing
Machine cycle 2-8
Register description 2-4
Program counter 2-3
Program Flash 4-2, 4-3
Program memory 3-3
Program status word 2-5
Pull-down device 6-8
Pull-up device 6-8
Pulse width modulation 12-1
R
Read access time 4-1
Receive-buffered 10-2
Request gating 13-12
Request trigger 13-12, 13-14, 13-25
CCU6 Event 13-25
Reset control 7-3
Module behavior 7-6
Result FIFO 13-19
Result read view 13-19
Accumulated 13-19
Normal 13-19
ROM devices 3-1, 3-2
ROM program memory 3-1
RS-232 4-9
S
Sample phase 13-5
Schmitt-Trigger 6-2, 6-4
Sectorization 4-3
Sequential request source 13-11
Serial data 6-2
Serial interfaces 10-1–10-18
Serial port 6-2
Slow-down mode 7-13, 8-2
User’s Manual
Software breakpoints 14-5
Break before make 14-5
Source priority 13-9
Special Function Register area 3-1
Stack pointer 2-4
Synchronization phase 13-5
Synchronous serial interface 10-19
Data width 10-20
Error detection 10-27
Baud rate error 10-28
Phase error 10-28
Receive error 10-28
Transmit error 10-29
Interrupts 10-27
Master mode 10-19
Operating mode 10-20
Right-aligned 10-20
Slave mode 10-19
T
Timer 0 and Timer 1 11-1–11-12
External control 11-2
Mode 0, 13-bit timer 11-3
Mode 1, 16-bit timer 11-4
Mode 2, 8-bit automatic reload timer
11-5
Mode 3, two 8-bit timers 11-6
Timer operations 11-1
Timer overflow 11-1
Timer 2 11-13–11-21
Auto-Reload mode 11-16
Capture mode 11-16
Up/Down Count Disabled 11-13
Up/Down Count Enabled 11-14
Timer T12 12-3
Capture mode 12-9
Center-aligned mode 12-4
Compare mode 12-6
Dead-time 12-8
Duty cycle 12-7
Edge-aligned mode 12-4
Hysteresis-like control mode 12-10
Shadow transfer 12-3
15-4
V 0.2, 2005-01
XC866
Keyword Index
Single-shot mode 12-9
Three-phase PWM 12-1
Timer T13 12-11
Compare mode 12-12
Shadow transfer 12-11
Single-shot mode 12-12
Total conversion time 13-6
Trap handling 12-16
Tristate 6-8
U
UART 10-2–10-13
Interrupt requests 10-5
Mode 1, 8-bit UART 10-2
Mode 2, 9-bit UART 10-5
Mode 3, 9-bit UART 10-5
V
VCO bypass 7-12
W
Wait-for-read mode 13-15
Wait-for-Start 13-10
Watchdog timer 9-1–9-8
Input frequency 9-3
Servicing 9-2
Time period 9-3
Watchdog timer reset 7-4
Window boundary 9-2
Wordline address 4-5
Write buffers 4-6
Write result phase 13-5
X
XC866 register overview 3-13
XRAM 3-1
User’s Manual
15-5
V 0.2, 2005-01
XC866
Register Index
15.2
Register Index
This section lists the references to the Special Function Registers of the XC866.
A
D
A 2-4
ADC_PAGE 13-28
DPH 2-4
DPL 2-4
B
E
B 2-4
BCON 10-12
BG 10-13
BRH 10-37
BRL 10-37
EO 2-6
ETRCR 13-35
EVINCR 13-54
EVINFR 13-54
EVINPR 13-55
EVINSR 13-55
EXICON0 5-12
EXICON1 5-13
C
CC63RH 12-43
CC63RL 12-43
CC63SRH 12-44
CC63SRL 12-44
CC6xRH (x = 0 - 2) 12-37
CC6xRL (x = 0 - 2) 12-37
CC6xSRH (x = 0 - 2) 12-38
CC6xSRL (x = 0 - 2) 12-38
CCU6_PAGE 12-26
CHCTRx (x = 0 - 7) 13-36
CHINCR 13-52
CHINFR 13-52
CHINPR 13-53
CHINSR 13-53
CMCON 7-17
CMPMODIFH 12-47
CMPMODIFL 12-47
CMPSTATH 12-46
CMPSTATL 12-45
CONH 10-34, 10-35
CONL 10-33, 10-35
CRCR1 13-44
CRMR1 13-46
CRPR1 13-45
User’s Manual
F
FEAH 4-8
FEAL 4-8
G
GLOBCTR 8-9, 13-31
GLOBSTR 13-32
H
HWBPDR 14-8
HWBPSR 14-8
I
ID 3-15
IEN0 5-9, 11-12
IEN1 5-10
IENH 12-85
IENL 12-84
INPCR0 13-37
INPH 12-89
INPL 12-88
IP 5-19
IP1 5-20
15-6
V 0.2, 2005-01
XC866
Register Index
IPH 5-19
IPH1 5-20
IRCON0 5-14
IRCON1 5-15
ISH 12-78
ISL 12-77
ISRH 12-83
ISRL 12-82
ISSH 12-81
ISSL 12-80
L
LCBR 13-56
M
MCMCTR 12-70
MCMOUTH 12-69
MCMOUTL 12-67
MCMOUTSH 12-66
MCMOUTSL 12-65
MMBPCR 14-7
MMCR 14-7
MMCR2 14-7
MMDR 14-7
MMICR 14-7
MMSR 14-7
MODCTRH 12-58
MODCTRL 12-57
MODPISEL 8-8, 10-13
N
NMICON 5-11
NMISR 5-17
O
OSC_CON 7-14, 8-10
P
P0_ALTSEL0 6-18
P0_ALTSEL1 6-18
P0_DATA 6-16
P0_DIR 6-16
P0_OD 6-17
User’s Manual
P0_PUDEN 6-18
P0_PUDSEL 6-17
P1_ALTSEL0 6-23
P1_ALTSEL1 6-23
P1_DATA 6-21
P1_DIR 6-21
P1_OD 6-22
P1_PUDEN 6-23
P1_PUDSEL 6-22
P2_DATA 6-26
P2_PUDEN 6-27
P2_PUDSEL 6-26
P3_ALTSEL0 6-33
P3_ALTSEL1 6-33
P3_DATA 6-31
P3_DIR 6-31
P3_OD 6-32
P3_PUDEN 6-33
P3_PUDSEL 6-32
PASSWD 3-12
PCON 2-7, 8-7, 10-10
PISEL 10-32
PISEL0H 12-33
PISEL0L 12-31
PISEL2 12-34
PLL_CON 7-15
PMCON0 7-7, 8-6, 9-8
PMCON1 8-8, 13-7
PORT_PAGE 6-11
PRAR 13-33
PSLR 12-63
PSW 2-5
Px_ALTSELn 6-10
Px_DATA 6-6
Px_DIR 6-7
Px_OD 6-7
Px_PUDEN 6-8
Px_PUDSEL 6-8
Q
Q0R0 13-40
QBUR0 13-42
QINR0 13-43
15-7
V 0.2, 2005-01
XC866
Register Index
QMR0 13-38
QSR0 13-40
R
RBL 10-38
RC2H 11-20
RC2L 11-20
RCRx (x = 0 - 3) 13-50
RESRAxH (x = 0 - 3) 13-49
RESRAxL (x = 0 - 3) 13-49
RESRxH (x = 0 - 3) 13-49
RESRxL (x = 0 - 3) 13-49
S
SBUF 10-7
SCON 5-17, 10-8
SCU_PAGE 3-10
SP 2-4
SYSCON0 3-4
TCTR4H 12-56
TCTR4L 12-55
THx (x = 0 - 1) 11-8
TLx (x = 0 - 1) 11-8
TMOD 11-11
TRPCTRH 12-61
TRPCTRL 12-60
V
VFCR 13-50
W
WDTCON 9-6
WDTH 9-7
WDTL 9-7
WDTREL 9-5
WDTWINB 9-7
T
T12DTCH 12-39
T12DTCL 12-39
T12H 12-35
T12L 12-35
T12MSELH 12-73
T12MSELL 12-72
T12PRH 12-36
T12PRL 12-36
T13H 12-41
T13L 12-41
T13PRH 12-42
T13PRL 12-42
T2CON 11-19
T2H 11-21
T2L 11-21
T2MOD 11-17
TBL 10-38
TCON 5-16, 11-10
TCTR0H 12-49
TCTR0L 12-48
TCTR2H 12-54
TCTR2L 12-52
User’s Manual
15-8
V 0.2, 2005-01
http://www.infineon.com
Published by Infineon Technologies AG