XR-T56L22 ...the analog plus company TM Low Power Repeater/Receiver June 1997-3 FEATURES APPLICATIONS Contains All The Active Components For A PCM Repeater Or Long Haul Line Receiver T1 PCM Repeater/Receiver Low Voltage Operation (5.1V) European 2.048Mbps PCM Repeater/Receiver T148C PCM Repeater/Receiver Low Power Consumption (8.75mA Max) Digital Multiplexers, CSUs, Switching Equipment 2Mbps Operation Capability ISDN Compatible Equipment: Fax Machines, Computers etc. Dual Matched ALBO Ports Internal Adjustable Phase Shift Circuitry Extracted Clock Output Internal Shunt Regulator Temperature Independent Current Biasing GENERAL DESCRIPTION The XR-T56L22 is a very low power monolithic repeater/ receiver IC designed for PCM carrier systems operating between 1.544Mbps and 2.37Mbps. The IC provides all the active circuitry required to implement one side of a PCM repeater. The XR-T56L22 features on-chip adjustable phase shifting, an extracted clock output and an on-board shunt regulator. The very low power consumption of the device makes it ideal for long haul “tandem” repeater applications. ORDERING INFORMATION Part No. Package Operating Temperature Range XR-T56L22AP 18 Lead 300 Mil PDIP -40°C to +85°C XR-T56L22AN 18 Lead 300 Mil CDIP -40°C to +85°C XR-T56L22AD 18 Lead 300 Mil Jedec SOIC -40°C to +85°C Rev. 1.02 1997 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 1 XR-T56L22 BLOCK DIAGRAM 2 ALBO1 3 ALBO PEAK DET. ALBO2 1 18 ALBO FIL ANA GND 5 6 AMP + I/P + AMP - 4 AMP - I/P AMP -O/P 7 AMP +O/P Clock Clock Bias GEN. Comparators 16 LC I/P 17 Clock Driver Clock AMP 11 Clock O/P LC Bias 15 Phase Cont. Data Comparators Voltage Ref. Gen. 13 VREF 14 9 Volt. Reg. D Q Data + REG Cont. CLK 12 Output Drivers +5 Data Latches VCC D 8 Q CLK DIG GND Figure 1. XT-T56L22 Block Diagram Rev. 1.02 2 10 Data - XR-T56L22 PIN CONFIGURATION ANA GND ALBO1 ALBO2 AMP-I/P AMP +I/P AMP -O/P AMP +O/P DIG GND DATA+ 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 ALBO FIL LC BIAS LC I/P PHASE CONT. REG CONT. VREF VCC CLOCK O/P DATA- ANA GND ALBO1 ALBO2 AMP-I/P AMP +I/P AMP -O/P AMP +O/P DIG GND DATA+ 18 Lead PDIP, CDIP (0.300”) 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 ALBO FIL LC BIAS LC I/P PHASE CONT. REG CONT. VREF VCC CLOCK O/P DATA- 18 Lead SOIC (Jedec, 0.300”) PIN DESCRIPTION Pin # Symbol Description 1 ANA GND 2 ALBO 1 ALBO PORT 1 Output. Port impedance varies between 25W and 20kW proportional to input signal level. 3 ALBO 2 ALBO PORT 2 Output. Similar to pin 2. Ground for Analog Sections of IC and Substrate. 4 AMP - I/P Inverting Input of Signal Preamp RIN > 20kW. 5 AMP + I/P Non-Inverting Input of Signal Preamp. RIN > 20kW. 6 AMP - O/P Inverting Output of Signal Pre-amp. Rout < 200W. DC level typically 3.2V. 7 AMP + O/P Non-inverting Output of Signal Pre-amp. Similar to pin 6. 8 DIG GND 9 DATA+ Positive Data Driver Output (Open Collector). VOL < 0.95V @ lOUT = 32mA. 10 DATA- Negative Data Driver Output (Open Collector). VOL < 0.95V @ lOUT = 32mA. 11 CLOCK O/P Phase Shifted Clock Output (Open Collector). Decouple to GND with 0.1mF if not required. With Rpull-up = 1K, VOL < 1.1V @ IOUT = 4mA. 12 VCC Input Pin of Shunt Regulator and Supply Pin for IC. For voltage feed applications the regulator must be disabled and a 5V + 5% supply connected. For line feed a current of 48-120mA is required. ICC < 8.75mA @ RON, ALBO = 25W typical. 13 VREF Output Voltage of Internal Reference of Shunt Regulator. For parallel operation of regulators should be tied to pin 13 of 2nd T56L22 device. VREF approxi-mately VCC/2. Decouple to GND with 0.1mF. 14 REG CONT Input Voltage of Shunt Regulator Amp. To inhibit regulator, pin should be tied to ground. For line feed operation decouple to GND with 0.1mF. For parallel operation of regulators tie pin 14 of 2nd T56L22 device. VREG approximately VREF. 15 PHASE CONT Phase Shift Adjust Input. A resistor to GND from the pin allows adjustment of phase shift from 905 to approximately 05. RP typical 1.8K to 1K. Vphase typical 340mV. 16 LC I/P Clock Amplifier Input. Pulsed with current from clock comparator. Connect LC tank between 16, 17 for clock recovery. Ickon = —110mA typical. 17 LC BIAS Clock Amplifier Reference Voltage. VLC = 3.6V typical. 18 ALBO FIL Control Pin for ALBO Ports. Voltage developed across a capacitor on this pin defines ALBO on impedance VALBO = 1.5V typical. Ground for Digital Portion of IC. Rev. 1.02 3 XR-T56L22 ELECTRICAL CHARACTERISTICS Test Conditions: TA = -40°C to +85°C, VCC = 5.1V ± 5% unless otherwise specified - refer to test circuit (Figure 6). Parameter Pin Min. 12 4.85 Typ. Max. Unit 5.35 V Conditions General Supply Voltage Supply Current 12 7 Pin 12, 13 to VCC1 8.75 mA Data Output Leakage Current 9, 10 100 A Vpull-up = 8V ALBO Port Off Voltage 2, 3 0.1 V VCC = 5.35 V1 Amplifier Pin Voltage 4, 5 3.7 V Amplifier Pin Voltage 6, 7 2.7 3.2 Amplifier Input Impedance 4, 5 40 Input Offset Voltage 4, 5 -10 Input Bias Current 4, 5 Input Offset Current 4, 5 Output Offset Voltage K 10 mV RS = 8.2K2 5 A RS = 8.2K2 -1 1 mV RS = 8.2K2 6, 7 -50 50 RS = 8.2K2 4, 5, 6, 7 40 dB 6, 7 1.9 V Input Offset Voltage 17, 16 0.5 Input Bias Current 17, 16 Common Mode Rejection Ratio Output Volage Swing Clock Amplifier AC Gain 40 -3db bandwidth 10 Delay 6 mV RS = 10K3 5 A 4 dB MHz 35 ns ALBO ALBO Filter Resistance 18-1 ALBO Impedance Match 2, 3 31 57 K 10 % On Current 1 1.3 2.4 mA Drive Current 18 0.4 1.4 mA 25 5 5 Maximum On Impedance 2, 3-1 Minimum Off Inpedance 2, 3-1 20 Notes 1 Internal regulator disabled. 2 Source Resistance. 3 R = Wou4d3 43wiw5qnd3 PIN 16 positive with respect to Pin 17 S 4 Pin 16 = Pin 17 = 3.6V 5f test = 1MHz Specifications are subject to change without notice Rev. 1.02 4 XR-T56L22 ELECTRICAL CHARACTERISTICS (CON’T) Parameter Pin Min. ALBO Threshold +Ve 7, 6 ALBO Threshold -Ve 7, 6 Typ. Max. Unit Conditions 1.4 1.6 V 1, 2 1.4 1.6 V 1, 2 ALBO Threshold Difference -3 3 % 3 Clock Drive on Current + Ve 80 140 A 4 Clock Drive on Current -Ve 80 140 A 4 Clock Drive Difference -3 3 % 3 Threshold Voltages Clock Threshold +Ve 7, 6 69 79 % 5 Clock Threshold -Ve 7, 6 69 79 % 5 -3 3 % 3 Clock Threshold Difference Data Threshold +Ve 7, 6 41 50 % 3 Data Threshold -Ve 7, 6 41 50 % 5 -3 3 % 3 Data Threshold Difference Data Output Stages Output Pulse Rise Time + Ve (Tr) 9 40 nS 10%-90%6 Output Pulse Rise -Time-Ve(Tr) 10 40 nS 10%-90%6 Output Pulse Fall Time+Ve(Tf) 9 40 nS 10%-90%6 Output Pulse Fall Time -Ve (Tf) 10 40 nS 10%-90%6 Output Pulse Width +Ve (Tw) 9 224 264 nS at 50% Output Pulse Width -Ve (Tw) 10 224 264 nS at 50% -12 12 nS at 50% Output Pulse Width Difference (dTw) Output Voltage (low) (VOL) 9, 10 0.6 0.95 V 6 Output Voltage Difference (VOL) 9, 10 -0.15 0.15 V 6 Notes 1 Pk/pk voltage at Pins 6 and 7 of a 1MHz sine wave derived through amplifier and measured differentially. 2 Pk/pk voltage at Pins 6 and 7 adjusted for a current increase of 2mA at pin 1. 3 Calculation only: percentage difference = [higher value/lower value]-1 x 100%. 4 V6 - V7 adjusted to ALBO threshold voltage (Pin 16 = 3.6V) 5 Figure taken as a percentage of ALBO threshold. 6 Using a 130 pull up resistor between 9, 10 and VCC and 15pF capacitance to GND. Specifications are subject to change without notice Rev. 1.02 5 XR-T56L22 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Pin Min. Typ. Max. Unit Conditions Clock Output Stage 1 Output Pulse Rise Time (Tr) 11 40 ns Output Pulse Fall Time (Tf) 11 40 ns Output Pulse Width (Tw) 11 224 264 ns Output Voltage 12 4.85 5.35 V Pin 13, 14 floating Voltage Regulation Over Temp. 12 %/°C Pin 13, 14 floating Load Regulation 12 0.027 %/mA 1mA to 100mA load Shunt Regulator 5.1 -0.02 Note 1 Using a 2K pull up resistor between 11 and VCC and 15pF capacitance to GND. ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . . -65°C to 150°C Operating Temperature . . . . . . . . . . . . . -40°C to 85°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V Supply Voltage Surge (10ms) . . . . . . . . . . . . . . . . . 25V Data Output Voltage (pin 9, 10) . . . . . . . . . . . . . . . 12V SYSTEM DESCRIPTION control the time at which the output signals from the preamplifier are sampled by the pulse regenerator circuits. The phase shifted clock signal is made available as an output from the circuit for interface applications. The clock phase adjustment is performed with a single pin using an external resistor. Adjustment of the position of the clock sampling edge by the phase shift circuit allows performance of the pulse regenerator to be optimized. The pulse regenerator performs the sampling and data slicing to regenerate the appropriate output pulse. These pulses are applied to an external output transformer to create the bipolar signal that drives the next section of twisted pair. With reference to the functional block diagram, the basic operation of the XR-T56L22 may be described as follows: The received bipolar signal, is applied to a linear amplifier and automatic equalizer. These circuits provide the necessary amount of gain and phase equalization to recover the transmitted data, and band limit the signal, to optimize repeater performance for near-end crosstalk produced by other systems operating within the same cable bundle. The preamplifier output signals which are balanced and of opposite phase, are applied to the clock extraction and pulse regenerator circuits. Here they are rectified and then applied to a high Q resonant circuit which extracts the 1.544/2.048 Mbps frequency component from the received signal. This signal is then sliced and fed to an adjustable phase shift circuit. A second slicer is used to Rev. 1.02 6 XR-T56L22 7.8 7.6 7.4 Typical ICC Vs. VCC Variation at T=25°C (Clock, Data Outputs + ALBO all Operating) (VIN=6V p-p (@2.04MBPS) I CC in (mA) 7.2 7.0 6.8 6.6 6.4 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 VCC in Volts Figure 2. Supply Current Variation with VCC (Regulator Inhibited) 120 Max Clock Drive Current = 100A @ Albo Thresholds 110 Clk Drive ( A) 100 90 80 70 60 50% CLK Drive Max 50 40 30 20 10 1.8 1.6 1.4 1.2 1.0 .8 VALBOTHLD = 1.44 CLK VCLKTHLD = 1.02v .6 .4 .2 0 .2 .4 VPREAMP OUT (V) .6 .8 1.0 1.2 1.4 1.6 1.8 CLK THLD(+) ALBO THLD(+) Figure 3. Clock Drive Current Against Preamp Output Voltage Rev. 1.02 7 XR-T56L22 50 Phase in Degrees 60 Differential Gain 40 Phase 30 10 0 –10 –20 –30 Gain A V IN DS 20 0 –45 –90 –135 –180 –40 Frequency In Hertz 104 105 106 107 108 Figure 5. Preamp Gain/Phase Characteristics Preamp Output (Approx. 1.5 pK to pK) Oscillator Input Pin 16 Clock Output Pin 12 Data Pos. Pin 18 Data Neg. Pin 1 Figure 4. Typical T56L22 Waveforms Rev. 1.02 8 XR-T56L22 + IM R3 C1 8.22UF C2 8.22UF 51 C3 1µF 18 2 17 3 16 4 15 5 14 6 13 7 12 C18 R1 3.9K R2 100 1 C11 15µF R7 680 R5 R4 8.2K 100 C4 R6 7.5K 1µF VCC R13 1µF 51 C7 8.1µF R11 1.8K C8 8.22µF R18 8 11 1K R9 9 10 138 R8 130 D+ D- CLK Figure 6. AC Parameter Test Circuit Rev. 1.02 9 C9 8.1µF VCC C5 8.22µF + C6 47µF XR-T56L22 Rev. 1.02 10 Figure 8. XR–T56L22 E1 Evaluation Circuit Rev. 1.02 11 XR-T56L22 Figure 9. XR–T56L22 T1 Evaluation Circuit XR-T56L22 18 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev. 1.00 18 10 1 9 E1 E D Seating Plane A2 A L α A1 B e INCHES SYMBOL eA eB B1 MILLIMETERS MIN MAX MIN MAX A 0.145 0.210 3.68 5.33 A1 0.015 0.070 0.38 1.78 A2 0.115 0.195 2.92 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 0.845 0.925 21.46 23.50 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 7.11 e 0.100 BSC 2.54 BSC eA 0.300 BSC 7.62 BSC eB 0.310 0.430 7.87 10.92 L 0.115 0.160 2.92 4.06 α 0° 15° 0° 15° Note: The control dimension is the inch column Rev. 1.02 12 C XR-T56L22 18 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) Rev. 1.00 18 10 1 9 E E1 D A1 Base Plane Seating Plane A L c e B α B1 INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.100 0.200 2.54 5.08 A1 0.015 0.070 0.38 1.78 B 0.014 0.026 0.36 0.66 B1 0.045 0.065 1.14 1.65 c 0.008 0.018 0.20 0.46 D 0.860 0.960 21.84 24.38 E1 0.250 0.310 6.35 7.87 E 0.300 BSC 7.62 BSC e 0.100 BSC 2.54 BSC L 0.125 0.200 3.18 5.08 α 0° 15° 0° Note: The control dimension is the inch column 15° Rev. 1.02 13 XR-T56L22 18 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) Rev. 1.00 D 18 10 E H 1 9 C A Seating Plane B e α A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.447 0.463 11.35 11.75 E 0.291 0.299 7.40 7.60 e 0.050 BSC MAX 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 α 0° 8° 0° 8° Note: The control dimension is the millimeter column Rev. 1.02 14 XR-T56L22 Notes Rev. 1.02 15 XR-T56L22 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1997 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.02 16