Preliminary XRD64L44 Dual 10-Bit 50MSPS CMOS ADC March 2000-1 APPLICATIONS FEATURES • 10-Bit Resolution • Medical Ultrasound Imaging • • • • • • • • • • • I & Q Modems Two Monolithic Complete 10-Bit ADCs 50 MSPS Conversion Rate BENEFITS On-Chip Track-and-Hold • • • • On-Chip Voltage Reference Low 5 pF Input Capacitance TTL/CMOS Outputs Tri-State Output Buffers Reduction of Components Reduction of System Cost High Performance @ Low Power Dissipation Long Term Time and Temperature Stability Single +3V or +5V Power Supply Operation Low Power Dissipation: 250mW-typ @ 3.0V -40°C to +85°C Operation Temperature Range GENERAL DESCRIPTION The XRD64L44 is two 10-bit, monolithic, 50 MSPS ADCs. Manufactured using a standard CMOS process, the XRD64L44 offers low power, low cost and excellent performance. The on-chip track-and-hold amplifier(T/H) and voltage reference (VREF) eliminate the need for external active components, requiring only an external ADC conversion clock for the application. The XRD64L44 analog input can be driven with ease due to the high input impedance of RIN = 25KOhms and CIN = 5pF. ADC. This auto-calibration circuit is transparent to the user after the initial 3.4ms calibration (168,000 initial clock cycles). The design architecture uses 17 time- interleaved 10bit SAR ADCs in each converter to achieve high conversion rate of 50 MSPS minimum. In order to insure and maintain accurate 10-bit operation with respect to time and temperature, XRD64L44 incorporates an auto-calibration circuit which continuously adjusts and matches the offset and linearity of each The XRD64L44 internal reference provides cost savings and simplifies the design/development. The output voltage of the internal reference is set by two external resistors. The internal reference can be disabled if an external reference is used for a power savings of 50mW. The power dissipation is only 250mW at 50 MSPS and 225mW at 40 MSPS with +3.0V power supply. The digital output data is straight binary format, and the tri-state disable function is provided for common bus interface. ORDERING INFORMATION Part Number Package Type Temperature Range XRD64L44AIV 64-Lead TQFP -40°C to +85°C Rev. P1.00 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 XRD64L44 Preliminary VCLMPA VINA+ VINA- 10 Bit A/D's Bandgap ADC A A/D 1a VBG VFBK + - 11 DA9 - DA0, OTRA VRHF TRI_A A/D 17a K DIFF SYNCO PD CKIN CLAMP CONTROL LOGIC 10 Bit A/D's ADC B A/D 1b VRLF 11 VCMO + A/D 17b VCLMPB VINB+ VINB- Figure 1. XRD64L44 Simplified Block Diagram Rev. P1.00 2 DB9 - DB0, OTRB TRI_B OTRB PD DVDD TRI_B DIFF CLAMP 32 DA0 16 31 DA1 15 30 DA2 14 29 DA3 13 28 DA4 12 DGND VCLMPB 11 27 DOVDD VCLMPA 3 10 DGND VRLF Rev. P1.00 9 26 DOGND 8 AGND 7 25 DVDD 6 DB3 DGND 24 DGND 5 DB4 DOVDD 23 DA5 4 DB5 DOGND 22 DA6 3 DB6 DB2 21 DA7 2 DB7 DB1 20 DA8 58 59 60 1 DB8 DB0 19 DA9 50 XRD64L44 64QFP DB9 SYNCO 18 OTRA 33 49 34 VRLF AGND 35 VRHF AGND 36 VRHF AVDD 37 61 AVDD 38 62 AGND 39 63 VINA- 40 64 VINA+ 41 51 55 VINB+ AGND 42 57 VINB- 56 AGND 43 VFBK AGND 44 VBG AVDD 45 52 AGND 46 53 DGND 47 54 VCMO 48 CKIN 17 XRD64L44 Preliminary TRI_A XRD64L44 Preliminary PIN DESCRIPTION Pin # 1 2 Symbol VBG Description Bandgap Voltage Output VFBK Analog Reference Feedback 3 4 VRHF VRHF Top Voltage Reference Force Top Voltage Reference Force 5 VRLF Bottom Voltage Reference Force 6 VRLF Bottom Voltage Reference Force 7 8 VCLMPA VCLMPB 9 AGND Analog Ground 10 DGND Digital Ground 11 DGND Digital Ground 12 13 PD DVDD Power Down Digital Supply Voltage 14 TRI_B Tri-state for the B Channel Outputs 15 DIFF 16 17 CLAMP TRI_A Digital Clamp Control Tri-state for the A Channel Outputs 18 19 CKIN SYNCO Clock Input Data Valid Output 20 DB0 Digital Output Bit 0 (LSB) ADC B 21 22 DB1 DB2 Digital Output Bit 1 ADC B Digital Output Bit 2 ADC B 23 24 DOGND DOVDD 25 DGND 26 27 DB3 DB4 Digital Output Bit 3 ADC B Digital Output Bit 4 ADC B 28 DB5 Digital Output Bit 5 ADC B 29 DB6 Digital Output Bit 6 ADC B 30 DB7 Digital Output Bit 7 ADC B 31 DB8 Digital Output Bit 8 ADC B 32 DB9 33 34 OTRB DA0 35 DA1 Digital Output Bit 1 ADC A 36 37 DA2 DA3 Digital Output Bit 2 ADC A Digital Output Bit 3 ADC A Analog Input Clamp A Analog Input Clamp B Differential / Single-Ended Input Mode Digital Output Ground Digital Output Supply Voltage Digital Ground Digital Output Bit 9 (MSB) ADC B Over Range Digital Output Bit ADC B Digital Output Bit 0 (LSB) ADC A 38 DA4 39 DOVDD Digital Output Bit 4 ADC A 40 DOGND Digital Output Ground 41 DVDD Digital Supply Voltage Digital Output Supply Voltage Rev. P1.00 4 Preliminary PIN DESCRIPTION (CONT'D) Pin # 42 Symbol DGND Description Digital Ground 43 DA5 Digital Output Bit 5 ADC A 44 DA6 Digital Output Bit 6 ADC A 45 DA7 Digital Output Bit 7 ADC A 46 DA8 Digital Output Bit 8 ADC A 47 DA9 48 OTRA Digital Output Bit 9 ADC A 49 VCMO Differential Common Mode Voltage Output 50 DGND Digital Ground 51 AGND Analog Ground 52 AVDD Analog Supply Voltage 53 AGND Analog Ground 54 AGND Analog Ground 55 VINB- Analog Input B(-) 56 VINB+ Analog Input B(+) 57 AGND Analog Ground 58 VINA+ Analog Input A(+) Over Range Digital Output Bit ADC A 59 VINA- Analog Input A(-) 60 AGND Analog Ground 61 AVDD Analog Supply Voltage 62 AVDD Analog Supply Voltage 63 AGND Analog Ground 64 AGND Analog Ground Rev. P1.00 5 XRD64L44 XRD64L44 Preliminary ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25°C AVDD = DVDD = +3.3V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 50 MSPS, 50% Duty Cycle, Differential Input Mode Symbol Parameter Min. Typ. Max. Unit -1.0 +/-0.4 1.0 LSB Conditions/Comments DC ACCURACY DNL Differential Non-Linearity INL Integral Non-Linearity +/-1.1 LSB MON Monotonicity No Missing Codes Guaranteed by Test FSE Full Scale Error +10 mV F.S. = (VRHF - VRLF)x0.97 ZSE Zero Scale Error 5 mV Single Ended Mode ANALOG INPUT INVR Input Voltage Range INRES Input Resistance INCAP Input Capacitance INBW Input Bandwidth VRHFx0.97 V 0 20 KOhms 5 pF 400 MHz VRLF Grounded -1dB Small Signal REFERENCE INPUT, INTERNAL BANDGAP REFERENCE AND REFERENCE BUFFER RLAD RLADTCO VBG VBGTC Ladder Resistance 100 125 150 Ohms Ladder Resistance Tempco +0.8 Ohms/°C Bandgap Output Voltage Range 1.25 V 30 ppm/°C Bandgap Reference Tempco VRLF 0.0 2.0 VRHF VRLF+1.0 AVdd-0.6 VRHF External Reference AVdd VRLF+1.0 VRHF PSRR Internal Reference Buffer 6 V V Internal Reference Buffer V External mV/V CONVERSION and TIMING CHARACTERISTICS (CL = 10pF) MAXCON Maximum Conversion Rate MINCON Minimum Conversion Rate PDEL 50 60 MSPS 100 KSPS Pipeline Delay(Latency) 17 tad Aperture Delay Time 4 APJT CLK Aperture Jitter Time 12 ps tr Digital Output Rise Time 3 ns tf Digital Output Fall Time 3 tpd Output Data Propagation Delay 6 14 tden Output Data Enable Delay 6 14 tdis Output Data Disable Delay 5 CLKDC Clock Duty Cycle 40 50 Rev. P1.00 6 Clock Cycles Digital Data Delay ns Peak-to Peak ns ns Guaranteed by Design ns Guaranteed by Design ns 60 % Guaranteed by Design XRD64L44 Preliminary ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25°C AVDD = DVDD = +3.3V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V, 50% Duty Cycle, Differential Input Mode SymbolParameter Min. Typ. Max. Unit Conditions/Comments DYNAMIC PERFORMANCE Fs = 40MHz SNR SINAD Signal-to-Noise Ratio Not Including Harmonics Fin = 1.0 MHz 60 dB fin = 4.0 MHz 60 dB fin = 1.0 MHz 58 dB fin = 4.0 MHz 58 dB fin = 12.5 MHz 57 dB fin = 1.0 MHz 9.5 Bit fin = 4.0 MHz 9.5 Bit fin = 12.5 MHz 9.3 Bit Signal-to Noise and Distortion ENOB Effective Number of Bits SFDR Spurious Free Dynamic Range SFDR fin = 4.0 MHz 70 dB Crosstalk fin = 4.0 MHz 75 dB Rev. P1.00 7 XRD64L44 Preliminary ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25°C AVDD = DVDD = +3.3V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V, 50% Duty Cycle, Differential Input Mode SymbolParameter Min. Typ. Max. Unit Conditions/Comments DYNAMIC PERFORMANCE Fs = 50MHz SNR SINAD Signal-to-Noise Ratio Not Including Harmonics Fin = 1.0 MHz 56 58 dB fin = 4.0 MHz 56 58 dB fin = 1.0 MHz 55 57 dB fin = 4.0 MHz 54 57 dB fin = 12.5 MHz 54 56 dB fin = 1.0 MHz 9.0 9.3 Bit fin = 4.0 MHz 9.0 9.3 Bit fin = 12.5 MHz 8.8 9.1 Bit Signal-to Noise and Distortion ENOB Effective Number of Bits SFDR Spurious Free Dynamic Range SFDR fin = 4.0 MHz 70 dB Crosstalk fin = 4.0 MHz 75 dB Rev. P1.00 8 XRD64L44 Preliminary ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25°C AVDD = DVDD = +3.3V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 50 MSPS, 50% Duty Cycle, Differential Input Mode SymbolParameter Min. Typ. Max. Unit Conditions/Comments DIGITAL INPUTS DVINH Digital Input High Voltage DVINL Digital Input Low Voltage DIINH 2.5 V 0.5 V Digital Input High Current (The DIFF input has an internal pull-up resistor, TRI_A and TRI_B have internal pull-down resistors CKIN Clock Input -5.0 0.05 5.0 nA DIFF Differential/Single-Ended Input -1.0 -0.25 1.0 uA -50.0 uA TRI_A/TRI_B A/B Channel Tri-State DIINL -125.0 -90.0 Digital Input Low Current (The DIFF input has an internal pull-up resistor, TRI_A and TRI_B have internal pull-down resistors CKIN Clock Input -5.0 0.05 5.0 nA DIFF Differential/Single-Ended Input 50.0 90.0 125.0 uA -1.0 0.25 1.0 uA 5 8 pF TRI_A/TRI_B A/B Channel Tri-State DINC Digital Input Capacitance DIGITAL OUTPUTS (CL = 10 pF) DOHV Digital Output High Voltage DOLV Digital Output Low Voltage IOZ DVdd -0.4VDVdd-0.3V High-Z Leakage V IOH = 1.5 mA IOL = 1.5 mA 0.3 0.4 V -20 0.2 20 nA 3.0 3.3 3.6 V POWER SUPPLIES ` AVDD Analog Power Supply Voltage DVDD Digital Power Supply Range AV DD V DVDD = AVDD Fs = 40 MHz, AVdd = DVdd = 3.0V, CL = 10pF, Fin = 10MHz AIDD Analog Supply Current 37 mA DIDD Digital Supply Current 15 mA DOIDD Output Driver Current 15 mA VRHF Top Voltage Ref Force Current PDISS Power Dissipation 8 mA 225 mW VRHF/125, VRHF = 1.0V Fs = 50 MHz, AVdd = DVdd = 3.0V, CL = 10pF, Fin = 10MHz AIDD Analog Supply Current 38 mA DIDD Digital Supply Current 19 mA DOIDD Output Driver Current 18 mA VRHF Top Voltage Ref Force Current 8 mA PDISS Power Dissipation 250 mW Rev. P1.00 9 VRHF/125, VRHF = 1.0V XRD64L44 Preliminary ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 VDD to GND ○ ○ ○ ○ ○ VRT & VRB VIN All Inputs All Outputs Storage Temperature ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ +7.0V Lead Temperature (Soldering 10 seconds) 300°C Maximum Junction Temperature 150°C Package Power Dissipation Ratings (TA= +70°C) SSOP θJA = 89.4°C/W ○ VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V -65°C to 150°C ○ ○ ○ ○ ○ ESD ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 2000V min ○ ○ ○ Notes: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND Rev. P1.00 10 XRD64L44 Preliminary 65 60.00 SINAD in db SINAD in db 55.00 60 50.00 45.00 55 40.00 3.0V 3.2V 3.4V 3.6V 50 2.8V 3.0V 2.90MHz 3.2V 3.4V 6.90MHz 9.90MHz 3.6V Fclk = 53.3MHz Fclk = 56.7MHz Fclk = 60.0MHz Figure 3 - SINAD vs. Fclock and Vdd DIFFERENTIAL INPUT MODE Figure 2 - SINAD vs. Fin and Vdd @Fc = 40.0MHz, DIFFERENTIAL INPUT MODE 0.00 0.00 Single Tone 8192 Point FFT SFDR -72.66 SINAD -57.97 -40.00 Single Tone 8192 Point FFT SFDR -69.77 SINAD -57.11 -20.00 Relative Power in db -20.00 Relative Power in db Fclk = 50.0MHz -60.00 -80.00 -100.00 -40.00 -60.00 -80.00 -100.00 -120.00 -120.00 DC DC 4.0 8.1 12.1 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 16.1 Frequency in MHz Frequency in MHz Figure 4 - FFT Spectrum @Fclock = 40.0MHz, Fin = 4.0MHz, DIFFERENTIAL INPUT MODE Figure 5 - FFT Spectrum @Fclock = 40.0MHz, Fin = 10.0MHz, DIFFERENTIAL INPUT MODE 60 0.00 Relative Power in db SINAD in db 55 50 45 Single Tone 8192 Point FFT SFDR -62.57 SINAD -55.25 -20.00 -40.00 -60.00 -80.00 -100.00 -120.00 40 2.8V 3.0V 3.2V 3.4V DC 3.6V 4.0 8.1 12.1 16.1 Frequency in MHz 2.90MHz 6.90MHz 9.90MHz Figure 6 - SINAD vs. Fin and Vdd @Fc = 40.0MHz, SINGLE-ENDED INPUT MODE Figure 7 - FFT Spectrum @Fclock = 40.0MHz, Fin = 4.0MHz, Single-ended INPUT MODE Rev. P1.00 11 XRD64L44 Preliminary 60.00 Single Tone 8192 Point FFT SFDR -60.95 SINAD -54.48 -20.00 -40.00 SINAD in db Relative Power in db 0.00 -60.00 -80.00 55.00 50.00 -100.00 -120.00 45.00 DC 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 2.80V 3.00V Frequency in MHz 6.90MHz 3.40V 3.60V 9.90MHz Figure 9 - SINAD vs. Fin and Vdd @Fc = 50.0MHz, DIFFERENTIAL INPUT MODE Figure 8 - FFT Spectrum @Fclock = 40.0MHz, Fin = 10.0MHz, Single-ended INPUT MODE 0.00 0.00 Single Tone 8192 Point FFT SFDR -66.93 SINAD -56.70 -20.00 Relative Power in db -20.00 Relative Power in db 3.20V 2.90MHz -40.00 -60.00 -80.00 Single Tone 8192 Point FFT SFDR -66.93 SINAD -56.70 -40.00 -60.00 -80.00 -100.00 -100.00 -120.00 -120.00 DC DC 4.0 8.0 12.0 16.0 20.0 2.5 5.0 7.5 24.1 10.0 12.5 15.0 17.5 20.0 22.5 Frequency in MHz Frequency in MHz Figure 10 - FFT Spectrum @Fclock = 50.0MHz, Fin = 4.0MHz, DIFFERENTIAL INPUT MODE Figure 11 - SINAD @Fclock = 50.0MHz, Fin = 12.5MHz, DIFFERENTIAL INPUT MODE 0.00 Single Tone 8192 Point FFT SFDR -64.15 SINAD -50.91 -40.00 60.00 55.00 SINAD in db Relative Power in db -20.00 -60.00 -80.00 50.00 45.00 -100.00 40.00 24.1 22.6 21.1 19.6 18.1 16.6 15.1 13.6 12.1 9.0 10.5 7.5 6.0 4.5 3.0 1.5 DC -120.00 2.80V Frequency in MHz Figure 12 - FFT Spectrum @Fclock = 50.0MHz, Fin = 24.1MHz, DIFFERENTIAL INPUT MODE 3.00V 3.20V 3.40V 2.90MHz 6.90MHz 9.90MHz Figure 13 - SINAD vs. Fin and Vdd @Fc = 50.0MHz, SINGLE-ENDED INPUT MODE Rev. P1.00 12 3.60V XRD64L44 Preliminary 0.00 0.00 Single Tone 8192 Point FFT SFDR -64.09 SINAD -54.21 -20.00 Relative Power in db Relative Power in db -20.00 -40.00 -60.00 -80.00 DC 4.0 8.0 12.0 16.0 20.0 DC 24.0 Figure 14 - SINAD @Fclock = 50.0MHz, Fin = 4.0MHz, SINGLE-ENDED INPUT MODE Single Tone 8192 Point FFT SFDR -53.43 SINAD -47.36 Relative Power in db -60.00 -80.00 -100.00 -120.00 6.0 9.0 12.1 15.1 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 Figure 15 - FFT SPECTRUM @Fclock = 50.0MHz, Fin = 12.5MHz, SINGLE-ENDED INPUT MODE 0.00 3.0 2.5 Frequency in MHz Fre quency in M Hz DC -80.00 -120.00 -120.00 -40.00 -60.00 -100.00 -100.00 -20.00 -40.00 Single Tone 8192 Point FFT SFDR -54.01 SINAD -51.75 18.1 21.1 24.1 Frequency in MHz Figure 16 - SINAD @Fclock = 50.0MHz, Fin = 24.1MHz, SINGLE-ENDED INPUT MODE Rev. P1.00 13 XRD64L44 Preliminary Notes Rev. P1.00 14 Preliminary XRD64L44 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1999 EXAR Corporation Datasheet February 1999 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. P1.00 15