19-1745; Rev 1; 11/03 KIT ATION EVALU E L B AVAILA 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference ♦ Single 3.0V Operation ♦ Excellent Dynamic Performance 59.5dB SNR at fIN = 20MHz 74dBc SFDR at fIN = 20MHz ♦ Low Power 19mA (Normal Operation) 5µA (Shutdown Mode) ♦ Fully Differential Analog Input ♦ Wide 2Vp-p Differential Input Voltage Range ♦ 400MHz -3dB Input Bandwidth ♦ On-Chip 2.048V Precision Bandgap Reference ♦ CMOS-Compatible Three-State Outputs ♦ 32-Pin TQFP Package ♦ Evaluation Kit Available Ordering Information PART MAX1444EHJ TEMP RANGE -40°C to +85°C PIN-PACKAGE 32 TQFP Pin Configuration GND REFOUT D0 D1 D2 D3 ________________________Applications REFIN TOP VIEW REFP Higher speed, pin-compatible versions of the MAX1444 are also available. Please refer to the MAX1446 data sheet (60Msps) and the MAX1448 data sheet (80Msps). The MAX1444 has parallel, offset binary, CMOS-compatible three-state outputs that can be operated from 1.7V to 3.6V to allow flexible interfacing. The device is available in a 5x5mm 32-pin TQFP package and is specified over the extended industrial (-40°C to +85°C) temperature range. Features 32 31 30 29 28 27 26 25 Ultrasound Imaging REFN 1 24 D4 CCD Imaging COM 2 23 OGND Baseband and IF Digitization VDD 3 22 T.P. Digital Set-Top Boxes GND 4 21 OVDD Video Digitizing Applications GND 5 IN+ 6 19 D6 IN- 7 18 D7 GND 8 17 D8 Functional Diagram appears at end of data sheet. MAX1444 9 10 11 12 13 14 15 16 VDD VDD GND CLK PD GND OE D9 20 D5 TQFP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1444 General Description The MAX1444 10-bit, 3V analog-to-digital converter (ADC) features a pipelined 10-stage ADC architecture with fully differential wideband track-and-hold (T/H) input and digital error correction incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in imaging and digital communications. The MAX1444 operates from a single 2.7V to 3.6V supply, consuming only 57mW while delivering a 59.5dB signal-to-noise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a 400MHz -3dB bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1444 features a 5µA power-down mode for idle periods. An internal 2.048V precision bandgap reference is used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered, direct, or externally derived reference for applications requiring increased accuracy or a different input voltage range. MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND.........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 18.7mW/°C above +70°C)......1495.3mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 10 Bits Integral Nonlinearity INL fIN = 7.51MHz, TA ≥ +25°C ±0.6 ±1.9 LSB Differential Nonlinearity DNL fIN = 7.51MHz, no missing codes guaranteed ±0.4 ±1.0 LSB <±0.1 ±1.7 % FS 0 ±2 % FS Offset Error TA ≥ +25°C Gain Error ANALOG INPUT Input Differential Range VDIFF Common-Mode Voltage Range VCOM Input Resistance RIN Input Capacitance CIN Differential or single-ended inputs Switched capacitor load ±1.0 V VDD/2 ±0.5 V 50 kΩ 5 pF 5.5 Cycles CONVERSION RATE Maximum Clock Frequency fCLK 40 Data Latency MHz DYNAMIC CHARACTERISTICS (fCLK = 40MHz, 4096-point FFT) Signal-to-Noise Ratio SNR fIN = 7.51MHz 57.5 59.5 fIN = 19.91MHz 56.3 59.5 fIN = 39.9MHz (Note 1) Signal-to-Noise and Distortion (Up to 5th harmonic) SINAD fIN = 7.51MHz 57 fIN = 19.91MHz 56.1 fIN = 39.9MHz (Note 1) Spurious-Free Dynamic Range SFDR 2 59.4 59 dB 58.3 fIN = 7.51MHz 67 fIN = 19.91MHz 66 fIN = 39.9 MHz (Note 1) dB 58.5 75 74 72.5 _______________________________________________________________________________________ dBc 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER Third-Harmonic Distortion SYMBOL HD3 CONDITIONS MIN TYP fIN = 7.51MHz -75 fIN = 19.91MHz -74 fIN = 39.9MHz (Note 1) MAX UNITS dBc -72.5 Two-Tone Intermodulation Distortion IMD f1 = 11.5MHz at -6.5dBFS f2 = 13.5MHz at -6.5dBFS (Note 2) -76 dBc Third-Order Intermodulation Distortion IM3 f1 = 11.5MHz at -6.5dBFS f2 = 13.5MHz at -6.5dBFS (Note 2) -76 dBc Total Harmonic Distortion (First 4 Harmonics) THD Small-Signal Bandwidth Full-Power Bandwidth FPBW Aperture Delay tAD Aperture Jitter tAJ fIN = 7.51MHz -73.8 -65 fIN = 19.91MHz -72.2 -65 fIN = 39.9MHz (Note 1) -70 Input at -20dBFS, differential inputs 500 MHz Input at -0.5dBFS, differential inputs 400 MHz 1 2 ns psRMS For 1.5 × full-scale input Overdrive Recovery Time dBc 2 ns ±1 % ±0.25 Degrees 0.2 LSBRMS REFOUT 2.048 ±1% V TCREF 60 ppm/°C 1.25 mV/mA Differential Gain Differential Phase Output Noise IN+ = IN- = COM INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) REFIN Input Voltage VREFIN 2.048 V Positive Reference Output Voltage VREFP 2.012 V Negative Reference Output Voltage VREFN 0.988 V Common-Mode Level VCOM VDD / 2 V Differential Reference Output Voltage Range ∆VREF REFIN Resistance RREFIN ∆VREF = VREFP - VREFN, TA ≥ +25°C 0.98 1.024 >50 1.07 V MΩ _______________________________________________________________________________________ 3 MAX1444 ELECTRICAL CHARACTERISTICS (continued) MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL CONDITIONS MIN TYP MAX UNITS ISOURCE 5 mA ISINK -250 µA ISOURCE 250 µA ISINK -5 mA UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance REFP, REFN, COM Input Capacitance RREFP, RREFN Measured between REFP and COM and REFN and COM CIN 4 kΩ 15 pF 1.024 ±10% V Differential Reference Input Voltage Range ∆VREF COM Input Voltage Range VCOM VDD / 2 ±10% V REFP Input Voltage VREFP VCOM + ∆VREF / 2 V REFN Input Voltage VREFN VCOM ∆VREF / 2 V ∆VREF = VREFP - VREFN DIGITAL INPUTS (CLK, PD, OE) Input High Threshold Input Low Threshold 4 CLK 0.8 × VDD PD, OE 0.8 × OVDD VIH V CLK 0.2 × VDD PD, OE 0.2 × OVDD VIL _______________________________________________________________________________________ V 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER Input Hysteresis SYMBOL CONDITIONS MIN VHYST Input Leakage Input Capacitance TYP MAX 0.1 V IIH VIH = VDD = OVDD ±5 IIL VIL = 0 ±5 CIN UNITS 5 µA pF DIGITAL OUTPUTS (D9–D0) Output Voltage Low VOL ISINK = 200µA Output Voltage High VOH ISOURCE = 200µA Three-State Leakage Current ILEAK OE = OVDD Three-State Output Capacitance COUT OE = OVDD 0.2 OVDD 0.2 V V ±10 5 µA pF POWER REQUIREMENTS Analog Supply Voltage VDD 2.7 3.0 3.6 Output Supply Voltage OVDD 1.7 3.0 3.6 V 19 27 mA Shutdown, clock idle, PD = OE = OVDD 4 15 Operating, fIN = 19.91MHz at -0.5dBFS 4.5 Shutdown, clock idle, PD = OE = OVDD 1 Analog Supply Current IVDD Output Supply Current IOVDD Power-Supply Rejection PSRR Operating, fIN = 19.91MHz at -0.5dBFS V µA mA 20 µA Offset ±0.1 mV/V Gain ±0.1 %/V TIMING CHARACTERISTICS CLK Rise to Output Data Valid Figure 6 (Note 3) 5 OE Fall to Output Enable tENABLE tDO Figure 5 10 8 ns ns OE Rise to Output Disable tDISABLE Figure 5 15 ns CLK Pulse Width High tCH Figure 6, clock period 25ns 12.5 ±3.8 ns CLK Pulse Width Low tCL Figure 6, clock period 25ns 12.5 ±3.8 ns 1.7 µs Wake-up Time tWAKE (Note 4) Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH / VIL. Note 4: REFIN is driven externally. REFP, COM, and REFN are left floating while powered down. _______________________________________________________________________________________ 5 MAX1444 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) 2ND HARMONIC -60 -40 -50 3RD HARMONIC 2ND HARMONIC -40 -70 -80 -80 -90 -90 -90 -100 -100 -100 6 8 10 12 14 16 18 20 0 2 4 6 8 2ND HARMONIC -60 -80 4 3RD HARMONIC -50 -70 10 12 14 16 18 20 0 5 10 15 20 25 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT (fIN = 7.51MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) FFT PLOT (fIN = 19.91MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE ENDED) -20 AMPLITUDE (dB) 3RD HARMONIC -50 2ND HARMONIC -60 4 2 -30 -40 -50 -70 -80 -80 -90 -90 3RD HARMONIC 2ND HARMONIC -60 -70 -100 6 2 4 6 8 10 12 14 16 18 20 0 -2 -4 -6 -100 0 MAX1444-06 SINAD = 59.1dB SNR = 59.2dB THD = -74.6dBc SFDR = 77.6dBc -20 -30 -40 0 -10 GAIN (dB) SINAD = 59.7dB SNR = 60dB THD = -71.8dBc SFDR = 75dBc MAX1444-05 0 -10 -8 0 2 4 6 8 10 12 14 16 18 20 1 100 10 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY (SINGLE ENDED) TWO-TONE INTERMODULATION 8192-POINT IMD (DIFFERENTIAL INPUT) SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY 4 f1 = 11.5MHz AT -6.5dB FS f2 = 13.5MHz AT -6.5dB FS IMD = -76dBc -10 -20 0 -2 -30 75 70 SFDR (dBc) AMPLITUDE (dB) 2 80 -40 -50 -60 DIFFERENTIAL 65 60 55 SINGLE ENDED -70 -4 50 -80 -6 45 -90 -100 -8 1 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 1000 MAX1444-09 VIN = 100mVp-p MAX1444-08 0 MAX1444-07 6 6 -30 -70 2 SINAD = 58.1dB SNR = 58.4dB THD = -69.7dBc SFDR = 72.4dBc -20 -30 -60 0 -10 AMPLITUDE (dB) AMPLITUDE (dB) 3RD HARMONIC MAX1444-04 AMPLITUDE (dB) -40 0 AMPLITUDE (dB) -20 -30 -50 SINAD = 58.9dB SNR = 59.1dB THD = -72.8dBc SFDR = 75.2dBc -10 FFT PLOT (fIN = 47MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1444-02 SINAD = 59dB SNR = 59.3dB THD = -71.6dBc SFDR = 73dBc -20 0 MAX1444-01 0 -10 FFT PLOT (fIN = 19.91MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) MAX1444-03 FFT PLOT (fIN = 7.51MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) GAIN (dB) MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference 40 0 5 10 15 20 ANALOG INPUT FREQUENCY (MHz) 25 1 10 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 100 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY -50 61 SINGLE ENDED DIFFERENTIAL 58 57 SINAD (dB) -55 59 THD (dBc) -60 56 DIFFERENTIAL SINGLE ENDED -75 1 10 100 45 1 10 100 1 10 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER 65 MAX1444-13 fIN = 19.91MHz fIN = 19.91MHz -50 MAX1444-15 ANALOG INPUT FREQUENCY (MHz) 75 fIN = 19.91MHz -55 60 -60 65 55 THD (dBc) SNR (dB) 70 50 -65 -70 60 45 55 50 -75 -80 40 -15 -12 -9 -6 -3 0 -15 -12 -9 -6 -3 -15 0 -12 -9 -6 -3 ANALOG INPUT POWER (dB FS) ANALOG INPUT POWER (dB FS) ANALOG INPUT POWER (dB FS) SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE SIGNAL-TO-NOISE RATIO vs. TEMPERATURE 70 MAX1444-17 84 MAX1444-16 fIN = 19.91MHz fIN = 19.91MHz 66 55 76 62 50 45 SNR (dB) 80 SFDR (dBc) 60 72 -12 -9 -6 -3 ANALOG INPUT POWER (dB FS) 0 58 50 64 -15 fIN = 19.91MHz 54 68 40 0 MAX1444-18 SFDR (dBc) 53 SINGLE ENDED 54 SINAD (dB) DIFFERENTIAL 49 -70 55 65 57 -65 MAX1444-14 SNR (dB) 60 80 65 MAX1444-11 -45 MAX1444-10 62 61 SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY MAX1444-12 SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX1444 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE PLUS DISTORTION vs. TEMPERATURE fIN = 19.91MHz fIN = 19.91MHz 0.4 MAX1444-21 70 MAX1444-19 -60 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (BEST STRAIGHT LINE) MAX1444-20 TOTAL HARMONIC DISTORTION vs. TEMPERATURE 0.3 66 -64 -72 62 58 0 -0.1 -0.2 54 -76 0.1 INL (LSB) -68 SINAD (dB) THD (dBc) 0.2 -0.3 50 -80 -15 10 35 60 -15 10 35 60 85 0 200 400 600 800 1000 1200 TEMPERATURE (°C) TEMPERATURE (°C) DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE (VREFIN = 2.048V) 0.3 0.04 10 8 0.03 0.1 0 -0.1 -0.2 0.02 OFFSET ERROR (LSB) GAIN ERROR (LSB) 0.2 0.01 0 -0.01 -0.02 6 4 -0.03 -0.3 MAX1444-24 0.05 MAX1444-22 0.4 2 -0.04 -0.4 -0.05 200 400 600 800 1000 1200 0 -40 -15 10 35 60 DIGITAL OUTPUT CODE TEMPERATURE (°C) ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs. TEMPERATURE 22 22 20 20 -40 -15 10 35 60 85 TEMPERATURE (°C) 24 MAX1444-25 24 85 DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE 6 MAX1444-26 0 MAX1444-27 DNL (LSB) -0.4 -40 85 MAX1444-23 -40 fIN = 7.51MHz 5 18 16 18 1 0 14 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 3 2 16 14 8 IOVDD (mA) IVDD (mA) 4 IVDD (mA) MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference -40 -15 10 35 TEMPERATURE (°C) 60 85 1.6 2.0 2.4 2.8 OVDD (V) _______________________________________________________________________________________ 3.2 3.6 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY fIN = 7.51MHz OE = OVDD PD = VDD 4.5 4 10 MAX1444-30 5.0 MAX1444-28 5 DIGITAL POWER-DOWN CURRENT vs. DIGITAL POWER SUPPLY MAX1444-29 DIGITAL SUPPLY CURRENT vs. TEMPERATURE PD = VDD OE = OVDD 8 IOVDD (µA) IVDD (µA) IOVDD (mA) 4.0 3 3.5 2 6 4 3.0 1 2.0 0 -40 -15 10 35 60 0 2.70 85 2.85 3.00 3.15 3.30 3.45 3.60 1.2 1.8 2.4 3.0 TEMPERATURE (°C) VDD (V) OVDD (V) SNR/SINAD, THD/SFDR vs. CLOCK FREQUENCY (OVER-CLOCKING) INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 65 VREFOUT (V) THD SNR 2.10 2.08 2.08 2.06 2.06 2.04 3.6 MAX1444-33 75 70 2.10 VREFOUT (V) SFDR MAX1444-32 fIN = 13.24MHz MAX1444-31 80 2.04 60 2.02 SINAD 55 50 2.02 2.00 2.00 34 38 42 fCLK (MHz) 46 50 2.70 2.85 3.00 3.15 3.30 VDD (V) 3.45 3.60 -40 -15 10 35 60 85 TEMPERATURE (°C) OUTPUT NOISE HISTOGRAM (DC INPUT) 70000 MAX1444-34 30 64515 63000 56000 49000 COUNTS SNR/SINAD, THD/SFDR (dB, dBc) 2 2.5 42000 35000 28000 21000 14000 7000 0 869 152 0 N+1 N+2 0 N-2 N-1 N DIGITAL OUTPUT CODE _______________________________________________________________________________________ 9 MAX1444 Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 Pin Description PIN NAME 1 REFN Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 2 COM Common-Mode Voltage Output. Bypass to GND with a >0.1µF capacitor. 3, 9, 10 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. 4, 5, 8, 11, 14, 30 GND Analog Ground 6 IN+ Positive Analog Input. For single-ended operation, connect signal source to IN+. 7 IN- Negative Analog Input. For single-ended operation, connect IN- to COM. 12 CLK Conversion Clock Input 13 PD Power Down Input. High: Power-down mode. Low: Normal operation. 15 OE Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. 16–20 D9–D5 Three-State Digital Outputs D9–D5. D9 is the MSB. 21 OVDD Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. 22 T.P. 23 OGND Output Driver Ground 24–28 D4–D0 Three-State Digital Outputs D4–D0. D0 is the LSB. 29 REFOUT 31 REFIN Reference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. 32 REFP Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. 10 FUNCTION Test Point. Do not connect. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-divider. ______________________________________________________________________________________ 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1444 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1-bit resolution. Input Track-and-Hold Circuit Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors (C2a and C2b). Switches S2a and S2b set the common mode for the amplifier input. The resulting differential voltage is held on C2a and C2b. Switches S4a, S4b, S5a, S5b, S1, S2a, and S2b are then opened before S3a, S3b, and S4c are closed, connecting capacitors C1a and C1b to the amplifier output. This charges C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first-stage quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier allows the MAX1444 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs (IN+ and IN-) can be driven either differentially or single-ended. It is recommended to match the impedance of IN+ and IN- and set the common-mode voltage to midsupply (VDD/2) for optimum performance. Analog Input and Reference Configuration The MAX1444 full-scale range is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The ADC’s full-scale range is user-adjustable through the REFIN pin, which provides a high input impedance for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered, low-impedance outputs. INTERNAL BIAS COM S5a S2a C1a S3a MDAC VIN Σ T/H x2 VOUT S4a IN+ OUT C2a FLASH ADC DAC S4c 1.5 BITS S1 OUT INS4b C2b C1b S3b VIN STAGE 1 STAGE 2 STAGE 10 S5b S2b INTERNAL BIAS DIGITAL ALIGNMENT LOGIC 10 D9–D0 VIN = INPUT VOLTAGE BETWEEN IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED) Figure 1. Pipelined Architecture—Stage Blocks COM CLK TRACK TRACK HOLD HOLD INTERNAL NON-OVERLAPPING CLOCK SIGNALS Figure 2. Internal T/H Circuit ______________________________________________________________________________________ 11 MAX1444 Detailed Description MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1444 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider if an application requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a >10nF capacitor to GND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In this mode, REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip buffers of REFP, COM, and REFN. With their buffers shut down, these pins become high impedance inputs and can be driven by external reference sources. Clock Input (CLK) The MAX1444 CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the falling edge of the clock signal, mandating this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the ADC as follows: SNR = 20log (1 / 2πfINtAJ) where fIN represents the analog input frequency, and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1444 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), or signal-to-noise plus distortion (SINAD) versus clock duty cycle. Output Enable (OE), Power Down (PD), and Output Data (D0–D9) All data outputs, D0 (LSB) through D9 (MSB), are TTL/CMOS-logic compatible. There is a 5.5 clock-cycle latency between any particular sample and its valid output data. The output coding is straight offset binary (Table 1). With OE and PD (power down) high, the digital output enters a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power down. The capacitive load on the digital outputs D0–D9 should be kept as low as possible (<15pF) to avoid large digital currents that could feed back into the analog portion of the MAX1444, thus degrading its dynamic performance. The use of buffers on the ADC’s digital outputs can further isolate the digital outputs from heavy capacitive loads. Figure 5 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid. Table 1. MAX1444 Output Code for Differential Inputs DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY VREF × 511/512 +Full Scale -1LSB 11 1111 1111 VREF × 510/512 +Full Scale -2LSB 11 1111 1110 VREF × 1/512 +1LSB 10 0000 0001 0 Bipolar Zero 10 0000 0000 - VREF × 1/512 -1LSB 01 1111 1111 - VREF × 511/512 Negative Full Scale + 1LSB 00 0000 0001 - VREF × 512/512 Negative Full Scale 00 0000 0000 *VREF = VREFP - VREFN 12 ______________________________________________________________________________________ 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference -60 fIN = 13.24MHz AT-0.5dB FS 85 MAX1444 90 fIN = 13.24MHz AT-0.5dB FS -64 THD (dBc) SFDR (dBc) 80 75 -68 -72 70 -76 65 60 -80 20 30 40 50 60 70 20 30 CLOCK DUTY CYCLE (%) Figure 3a. Spurious-Free Dynamic Range vs. Clock Duty Cycle (Differential Input) 61 50 60 70 Figure 4a. Total Harmonic Distortion vs. Clock Duty Cycle (Differential Input) 61 fIN = 13.24MHz AT-0.5dB FS 60 fIN = 13.24MHz AT-0.5dB FS 60 SINAD (dB) SNR (dB) 40 CLOCK DUTY CYCLE (%) 59 58 59 58 57 56 57 20 30 40 50 60 70 20 30 CLOCK DUTY CYCLE (%) 40 50 60 70 CLOCK DUTY CYCLE (%) Figure 3b. Signal-to-Noise Ratio vs. Clock Duty Cycle (Differential Input) Figure 4b. Signal-to-Noise Plus Distortion vs. Clock Duty Cycle (Differential Input) OE tDISABLE tENABLE OUTPUT DATA D9–D0 HIGH-Z VALID DATA HIGH-Z Figure 5. Output Enable Timing ______________________________________________________________________________________ 13 MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference System Timing Requirements Using Transformer Coupling Figure 6 shows the relationship between the clock input, analog input, and data output. The MAX1444 samples at the falling edge of the input clock. Output data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles. Figure 5 shows the relationship between the input clock parameters and the valid output data. An RF transformer (Figure 8) provides an excellent solution for converting a single-ended source signal to a fully differential signal, required by the MAX1444 for optimum performance. Connecting the transformer’s center tap to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. __________Applications Information Figure 7 shows a typical application circuit containing a single-ended to differential converter. The internal reference provides a VDD/2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter follows the op amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the RISO and CIN values to optimize the filter performance to suit a particular application. For the application in Figure 7, an RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor. In general, the MAX1444 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower since both inputs (IN+, IN-) are balanced, and each of the inputs only requires half the signal swing compared to single-ended mode. Single-Ended AC-Coupled Input Signal Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. 5.5 CLOCK-CYCLE LATENCY N ANALOG INPUT N+1 N+2 N+3 N+4 N+5 N+6 N+7 tAD CLOCK INPUT tCL tDO DATA OUTPUT N-6 N-5 N-4 N-3 tCH N-2 N-1 N Figure 6. System and Output Timing Diagram 14 ______________________________________________________________________________________ N+1 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 +5V 0.1µF LOWPASS FILTER IN+ MAX4108 RISO 50Ω 0.1µF 300Ω CIN 22pF 0.1µF -5V MAX1444 600Ω 300Ω 600Ω COM +5V 0.1µF +5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω 0.1µF -5V IN- MAX4108 RISO 50Ω CIN 22pF 300Ω -5V 0.1µF 300Ω 300Ω 600Ω Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion REFP 25Ω IN+ 10pF 0.1µF VIN 3 T1 VIN 0.1µF 4 MAX1444 N.C. 5 2 1 6 MINI-CIRCUITS ADT1–1WT IN+ MAX4108 100Ω COM 2.2µF 1kΩ RISO CIN 1kΩ MAX1444 0.1µF COM REFN 0.1µF RISO 25Ω IN100Ω 10pF RISO = 50Ω CIN = 22pF Figure 8. Using a Transformer for AC Coupling INCIN Figure 9. Single-Ended AC-Coupled Input ______________________________________________________________________________________ 15 MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference 3.3V 0.1µF 3.3V N.C. 0.1µF 2.048V 1 MAX6062 31 0.1µF 2 16.2kΩ 3 32 1 5 162Ω 1µF 4 3 MAX4250 2 10Hz LOWPASS FILTER 29 2 1 100µF 0.1µF 0.1µF REFOUT REFIN REFP MAX1444 N=1 REFN COM 0.1µF 10Hz LOWPASS FILTER 0.1µF N.C. 29 31 32 1 0.1µF 2 0.1µF 0.1µF 2.2µF 10V REFOUT REFIN REFP MAX1444 N = 1000 REFN COM 0.1µF NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs. Figure 10. Buffered External Reference Drives Up to 1000 ADCs Buffered External Reference Drives Multiple ADCs Multiple-converter systems based on the MAX1195 are well suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source. A precision bandgap reference like the MAX6062 generates an external DC level of 2.048V (Figure 10), and exhibits a noise voltage density of 150nV/√Hz. Its output passes through a one-pole lowpass filter (with 10Hz cutoff fre- 16 quency) to the MAX4250, which buffers the reference before its output is applied to a second 10Hz lowpass filter. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level. The passive 10Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision ADC operation. ______________________________________________________________________________________ 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 3.3V 0.1µF N.C. 29 31 REFOUT REFIN 1 2.0V 2 32 3.3V 21.5kΩ 3 MAX6066 1 1 47Ω 1/4 MAX4252 2 2 21.5kΩ 3 REFP MAX1444 2.0V AT 8mA 4 11 10µF 6V 330µF 6V 0.1µF 0.1µF N=1 REFN COM 0.1µF 1.47kΩ 1µF 1.5V 3.3V 5 3.3V 1.5V AT 0mA 4 7 47Ω 1/4 MAX4252 0.1µF 6 11 21.5kΩ MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 10µF 6V 330µF 6V 1.47kΩ 1.0V 3.3V 10 1.0V AT -8mA 4 8 47Ω 0.1µF 1/4 MAX4252 21.5kΩ 21.5kΩ 9 11 10µF 6V N.C. 330µF 6V 29 31 1.47kΩ 32 1 2 0.1µF 0.1µF 2.2µF 10V REFOUT REFIN REFP MAX1444 N = 32 REFN COM 0.1µF NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs. Figure 11. Unbuffered External Reference Drives Up to 32 ADCs Unbuffered External Reference Drives Multiple ADCs Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage-divider (Figure 11), the MAX6066 generates a DC level of 2.500V. The buffered outputs of this divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy that depends on the tolerance of the divider resistors. The three voltages are buffered by the MAX4252, which provides low noise and low DC offset. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3nV/√Hz. The 2.0V and 1.0V reference voltages set the differential full-scale range of the associated ADCs at 2VP-P. The 2.0V and 1.0V buffers drive the ADC’s internal ladder resistances between them. Note that the common power supply for all active components removes any concern regarding ______________________________________________________________________________________ 17 MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications that require more than 32 matched ADCs, a voltage reference and divider string common to all converters is highly recommended. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Grounding, Bypassing, and Board Layout Aperture Jitter Figure 12 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. The MAX1444 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider using a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces. Keep all signal lines short and free of 90° turns. Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 12). Dynamic Parameter Definitions Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum A/D noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR(MAX) = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. CLK ANALOG INPUT Static Parameter Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. The MAX1444’s static linearity parameters are measured using the best straight-line fit method. tAD tAJ SAMPLED DATA (T/H) T/H TRACK HOLD Figure 12. T/H Aperture Timing 18 ______________________________________________________________________________________ TRACK 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from: ENOB = (SINAD − 1.76dB) Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale. 6.02dB Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the input signal’s first four harmonics to the fundamental itself. This is expressed as: Chip Information TRANSISTOR COUNT: 5684 PROCESS: CMOS V22 + V32 + V42 + V52 THD = 20 × log V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Functional Diagram CLK VDD MAX1444 GND CONTROL IN+ T/H ADC IN- PD REF D E C 10 OUTPUT DRIVERS OVDD REF SYSTEM + BIAS REFOUT REFIN REFP COM REFN D9–D0 OGND OE ______________________________________________________________________________________ 19 MAX1444 Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 32L,TQFP.EPS MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.