XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER JULY 2006 REV. 1.0.0 FUNCTIONAL DESCRIPTION FEATURES The XRK39910 is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications. It has eight zero delay LVTTL outputs. When the OE pin is held low, all the outputs are synchronously enabled. However, if OE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the PE is held high, all the outputs are synchronized with the positive edge of the CLKIN. When PE is held low, all the outputs are synchronized with the negative edge of CLKIN. The FB_IN signal is compared with the input CLKIN signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. FIGURE 1. FUNCTIONAL BLOCK DIAGRAM Q0 H CLKIN Q1 M Ref VCO L Q2 Eight zero delay outputs • • • • Synchronous output enable 12mA balanced drive outputs Output frequency: 15MHz to 85MHz <250ps of output to output skew Low Jitter: <200ps peak-to-peak 3 skew grades External feedback, internal loop filter Selectable positive synchronization or negative 3-level inputs for PLL range control PLL bypass for DC testing Available in SOIC package FIGURE 2. PIN C ONFIGURATION CLKIN 1 24 GND VDDPLL 2 23 Bypass FSEL 3 22 nc nc 4 21 OE PE 5 20 VDD VDD 6 19 Q7 Q0 7 18 Q6 Q1 8 17 GND GND XRK39910 9 16 Q5 Q2 10 15 Q4 Q4 Q3 11 14 VDD Q5 VDD 12 13 FB_IN PLL FB_IN • • • • • • • • Q3 Feedback FSEL* PE Bypass* Q6 Q7 OE * Tri-Level inputs Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com edge XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 TABLE 1: ORDERING INFORMATION PRODUCT N UMBER ACCURACY TEMP R ANGE XRK39910CD-2 250ps 0°C to +70°C XRK39910ID-2 250ps -40°C to +85°C XRK39910CD-5 500ps 0°C to +70°C XRK39910ID-5 500ps -40°C to +85°C XRK39910CD-7 750ps 0°C to +70°C XRK39910ID-7 750ps -40°C to +85°C TABLE 2: ABSOLUTE MAXIMUM RATINGS(1) SYMBOL D ESCRIPTION MAX UNIT -0.5 to +7 V -0.5 to VDD+0.5 V -0.5 to +5.5 V 530 mW -65 to +150 °C Supply Voltage to Ground VI DC Input Voltage CLKIN Input Voltage Maximum Power Dissipation (TA = 85°C) TSTG Storage Temperature NOTE: (1) Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. TABLE 3: CAPACITANCE (TA= +25 °C, f= 1MH Z, VIN= 0V) PARAMETER DESCRIPTION CIN Input Capacitance TYP MAX UNIT 5 7 pF NOTE: Capacitance applies to all inputs except BYPASS and FSEL. It is characterized but not production tested . TABLE 4: PIN D ESCRIPTIONS PIN NAME PIN N UMBER TYPE DESCRIPTION CLKIN 1 IN VDDPLL 2 FSEL(1,3) 3 IN Frequency range select: PE 5 IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. VDD 6,12,14,20 Reference Clock Input PWR Power supply for phase locked loop and other internal circuitry. FSEL = GND:15 to 35MHz FSEL = MID (or open): 25 to 60MHz FSEL = VDD: 40 to 85MHz PWR Power supply for output buffers. 2 XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 TABLE 4: PIN D ESCRIPTIONS PIN NAME PIN N UMBER TYPE DESCRIPTION Q 0 - Q7 7,8,10,11, 15,16,18,19 OUT GND 9,17,24 FB_IN 13 IN Feedback Input OE(2) 21 IN Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q 3 may be used as the feedback signal to maintain phase lock. Set OE LOW for normal operation. BYPASS(1,2) 23 IN When MID or HIGH, disable PLL (except for conditions of Note 2). CLKIN goes to all outputs. Set LOW for normal operations. Eight clock output. PWR Ground. NOTE: 1. Tri-Level Input 2. When BYPASS = MID and OE = HIGH, PLL remains active. 3. This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved. TABLE 5: RECOMMENDED OPERATING RANGE SYMBOL VDD TA DESCRIPTION Power Supply Voltage Ambient Operating Temperature XRK39910-2, -5, -7 (INDUSTRIAL) XRK39910-2, -5, -7 (COMMERCIAL) MIN. MAX. MIN. MAX. 3 3.6 3 3.6 V -40 +85 0 +70 °C UNIT TABLE 6: DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE SYMBOL PARAMETER C ONDITIONS MIN. VIH Input HIGH Voltage Guranteed Logic HIGH (CLKIN, FB_IN, OE, PE Inputs Only) VIL Input LOW Voltage Guaranteed Logic LOW (CLKIN, FB_IN, OE, PE Inputs Only) VIHH Input HIGH Voltage (1) 3-Level Inputs Only (FSEL, BYPASS) VDD-0.6 VIMM Input MID Voltage (1) 3-Level Inputs Only (FSEL, BYPASS) VDD/2-0.3 VILL Input LOW Voltage (1) Input Leakage Current (CLKIN, FB_IN Inputs Only) IIN MAX. 2 UNIT V 0.8 V V VDD/2+0.3 V 3-Level Inputs Only (FSEL, BYPASS) 0.6 V VIN = VDD or GND VDD = Max. +5 μA 3 XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 TABLE 6: DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE SYMBOL I3 PARAMETER C ONDITIONS MAX. UNIT HIGH Level +400 μA VIN = VDD/2 MID Level +200 VIN = GND LOW Level +400 3-Level Input DC Current (BYPASS, FSEL) VIN = VDD MIN. IPU Input Pull-Up current (PE) VDD = Max., VIN = GND +100 μA IPD Input Pull-Down Current (OE) VDD= Max., VIN = VDD +100 μA VOH Output HIGH Voltage VDD = Min., IOH = -12mA VOL Output LOW Voltage VDD = Min., IOL = 12mA 2.4 V 0.55 V NOTE: (1) These inputs are normally wired to V DD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. TABLE 7: POWER SUPPLY CHARACTERISTICS SYMBOL PARAMETER TEST C ONDITIONS(1) TYP. MAX. UNIT 25 mA IDDQ Quiescent Power Supply Current VDD=Max., BYPASS=MID, CLKIN=LOW VDD/PE=LOW, OE=LOW, All outputs unloaded 8 ITOT Total Power Supply Current VDD=3.3V, FREF=25MHz, C L=160pF(1) 34 VDD=3.3V, FREF=33MHz, C L=160pF(1) 42 VDD=3.3V, FREF=66MHz, C L=160pF(1) 76 mA NOTE: (1) For eight outputs, each loaded with 20pF. TABLE 8: INPUT TIMING R EQUIREMENTS DESCRIPTION(1) SYMBOL M IN. MAX. UNIT 10 ns/V tR, tF Maximum input rise and fall times, 0.8V to 2V tPWC Input clock pulse, HIGH or LOW 3 DH Input duty cycle 10 90 % Ref Reference Clock Input 15 85 MHz NOTE: (1) Where pulse width implied by D H is less than tPWC limit, tPWC limit applies. 4 ns XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 TABLE 9: SWITCHING CHARACTERISTICS OVER OPERATING RANGE XRK39910-2 SYMBOL XRK39910-7 UNIT MIN FREF XRK39910-5 PARAMETER CLKIN Frequency Range TYP M AX MIN TYP MAX MIN TYP MAX FSEL = LOW 15 35 15 35 15 35 FSEL = MED 25 60 25 60 25 60 FSEL = HIGH 40 85 40 85 40 85 MHz tRPWH CLKIN Pulse Width HIGH 3 3 3 ns tRPWL CLKIN Pulse Width LOW 3 3 3 ns tSKEW Output Skew (All Outputs) [1, 3, 4] 0.1 tDEV Device-to-Device Skew [1, 2, 5] tPD CLKIN Input to FB_IN Propagation Delay [1, 7] -0.25 0.25 0.25 0.75 0.5 0.3 0.75 ns 1.65 ns 1.25 0 0.25 -0.5 0 0.5 -0.7 0 0.7 ns tODCV Output Duty Cycle Variation from 50% [1] -1.2 0 1.2 -1.2 0 1.2 -1.2 0 1.2 ns tORISE Output Rise Time [1] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns tOFALL Output Fall Time [1] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns tLOCK PLL Lock Time [1,6] tJR Cycle-to-Cycle Output Jitter [1] 0.5 0.5 0.5 ms RMS 25 25 25 ps Peak-to-Peak 200 200 200 NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load. 3. tSKEW is the skew between all outputs. See AC TEST LOADS. 4. For XRK39910-2 tSKEW is measured with CL = 0pF; for CL = 20pF, tSKEW = 0.35ns Max. 5. tDEV is the output-to-output skew between any two devices operating under the same conditions. 6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits. 7. tPD is measured with CLKIN input rise and fall times (from 0.8V to 2V ) of 1ns. 5 XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 FIGURE 3. AC TIMING D IAGRAM (PE= HIGH TIMING) tREF tRPWH tRPWL CLKIN tODCV tPD tODCV FB_IN tJR Qx output tSKEW tSKEW Other Qx output FIGURE 4. AC TIMING D IAGRAM (PE= LOW TIMING) tREF tRPWH tRPWL CLKIN tODCV tPD tODCV FB_IN tJR Qx output tSKEW tSKEW Other Qx output NOTE: Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 20pF and terminated with 75Ω to VDD/2. tDEV: The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.). tODCV: The deviation of the output from a 50% duty cycle. tORISE and tOFALL are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits. 6 XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 FIGURE 5. AC TEST LOADS AND WAVEFORMS V DD 150Ω Output 150Ω 20pF AC Test Loads <1ns <1ns 3.0V 2.0V Vth = 1.5V 0.8V 0V LVTTL Input Test Waveform tORISE 2.0V 0.8V LVTTL Output Waveform 7 tOFALL XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 PACKAGE DIMENSIONS 24 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) rev. 1.00 D 24 13 E H 1 12 C A Seating Plane α e B A1 L Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.598 0.614 15.20 15.60 E 0.291 0.299 7.40 7.60 e 0.050 BSC 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 α 0° 8° 0° 8° 8 XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 REVISION HISTORY REVISION # DATE 1.0.0 July 18, 2006 DESCRIPTION Initial release. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet July 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 9