EXAR XRK69773IR

XRK69773
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
APRIL 2006
REV. P1.0.0
GENERAL DESCRIPTION
The XRK69773 is a PLL based LVCMOS Clock Generator
targeted for high performance and low skew clock distribution applications. The XRK69773 can select between one
of three reference inputs and provides 14 LVCMOS outputs
-12 outputs (3 banks of 4) for clock distribution, 1 for feedback and 1 for synchronization.
The XRK69773 is a highly flexible device. It has 3 selectable inputs, (one differential and two single-ended inputs) to
support system clock redundancy. Up to three different
clock frequencys can be generated and outputted on the
three output banks. Switching the internal reference clock
is controlled by the control input, CLK_SEL.
The XRK69773 uses PLL technology to frequency lock its
outputs to the input reference clock. The divider in the feedback path will determine the frequency of the VCO. Each of
the separate output banks can individually divide down the
VCO output frequency. This allows the XRK69773 to generate a multitude of different bank frequency ratios and output-to-input frequency ratios.
The outputs of the XRK69773 can individually be immobilized, in the low state, by use of the clock stop feature. All
outputs except QC0 and QFB can be immobilized through a
2 pin serial interface. Global output disabling and reset can
be achieved the control input MR/OE.
The XRK69773 also has a QSYNC output which can be
used for system synchronization purposes. It monitors
Bank A and Bank C outputs and goes low one period of the
faster clock prior to coincident rising edges of Bank A and
Bank C clocks. QSYNC then goes high again when the
coincident rising edges of Bank A and Bank C occur. This
feature is used primarily in applications where Bank A and
Bank C are running at different frequencies, and is
particularly useful when they are running at non-integer
multiples of one another.
The XRK69773 has an output frequency range of 8.33MHz
to 240MHz and an input frequency range of 5MHz to
120MHz.
FEATURES
• Fully Integrated PLL
• Selectable Differential PECL or LVCMOS inputs for
reference clock source
• 14 LVCMOS outputs
•
•
•
•
■
3 banks with 4 outputs each. Frequencies can
be individually controlled by bank
■
1 dedicated feedback with frequency control
■
1 Sync
VCO Range 200MHz to 480MHz
Output freq. range: 8.33MHz to 240MHz
Max Output Skew of 250ps
Cycle-to-cycle jitter: 150ps (typ)
APPLICATIONS
• System Clock generator
• Zero Delay Buffer
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRK69773CR
52-LEAD LQFP
0°C to +70°C
XRK69773IR
52-LEAD LQFP
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
FIGURE 1. B LOCK D IAGRAM OF THE XRK69773
PECL
PECL
XTAL
0
DIVIDER SELECT
VDD
0
Ref
VCO
1
CLK0
CLK1
÷2
0
0
1
QA1
STOP
QA2
BANK B
÷4, ÷6,
÷8, ÷10
BANK C
÷2, ÷4,
÷6, ÷8
STOP
QA3
÷4, ÷6, ÷8,
÷10, ÷12,
÷16, ÷20
STOP
QB0
STOP
QB1
STOP
QB2
STOP
QB3
FB
VDD
Sync Pulse
REF_SEL
FB_IN
STOP
÷4, ÷6,
÷8, ÷12
200-480MHz
CLK_SEL
QA0
BANK A
1
PLL
1
STOP
FB
VCO_SEL
PLL_EN
VDD
QC0
2
FSEL_A[1:0]
2
FSEL_B[1:0]
STOP
QC1
STOP
QC2
STOP
QC3
2
FSEL_C[1:0]
0
3
FSEL_FB[2:0]
1
POWER-ON RESET
VDD
QFB
INV_CLK
STOP
STOP_DATA
12
SERIAL
INTERFACE
STOP_CLK
MR/OE
QA0
VDD
QA1
GND
QA2
VDD
QA3
FSEL_A0
FSEL_A1
FSEL_B0
FSEL_B1
52
1
51
50
49
48
47
46
45
44
43
42
41
40
39
GND
2
38
QB0
STOP_CLK
3
37
VDD
STOP_DATA
4
36
QB1
FSEL_FB2
5
35
GND
PLL_EN
6
34
QB2
REF_SEL
7
33
VDD
CLK_SEL
8
32
QB3
CLK0
9
31
FB_IN
CLK1
10
30
GND
PECL
11
29
QFB
PECL
12
28
VDD
FSEL_C1
22
23
24
25
2
27
26
FSEL_FB1
QC2
21
QSYNC
VDD
20
GND
19
QC0
18
VDD
17
QC1
16
FSEL_C0
15
QC3
13
14
GND
VDD_PLL
XRK69773
INV_CLK
GND
___
MR/OE
GND
VCO_SEL
FIGURE 2. PIN OUT OF THE XRK69773
FSEL_FB0
QSYNC
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
PIN DESCRIPTIONS
PIN #
NAME
TYPE
DESCRIPTION
1, 15, 24, 30,
35, 39, 47, 51
GND
POWER
Power supply ground
2
MR/OE
INPUT*
Master reset and output enable. High = output enabled, Low = device
reset & outputs tri-stated
3
STOP_CLK
INPUT*
Clock input for serial control.
4
STOP_DATA
INPUT*
Data input for serial control
5, 26, 27
FSEL_FB[2:0]
INPUT*
Select inputs for control of feedback divide value.
6
PLL_EN
INPUT*
PLL bypass. High = PLL, Low = PLL bypass
7
REF_SEL
INPUT*
Xtal or CLK select. High = Xtal input selected, Low = CLK0 or CLK1
selected
8
CLK_SEL
INPUT*
CLK0 or CLK1 Select. High = CLK1 selected, Low= CLK0 selected
9
10
CLK0
CLK1
INPUT*
INPUT*
PLL Reference Clock Inputs
11
12
PECL
PECL
INPUT
Diffferential LVPECL Clock Input
13
VDD_PLL
POWER
Analog supply for PLL
14
INV_CLK
INPUT*
Invert clock select for QC3 & QC2. High = invert, Low = normal operation
16, 18, 21, 23
QC[3:0]
OUTPUT
Clock outputs (Bank C)
17, 22, 33,
37, 45, 49
VDD
POWER
Power supply for outputs.
19,20
FSEL_C[1:0]
INPUT*
Bank C divide select pins.
25
QSYNC
OUTPUT
Synchronization output for Bank A and Bank C.
28
VDD
POWER
Power supply for core
29
QFB
OUTPUT
Feedback clock output
31
FB_IN
INPUT*
32, 34 ,36 ,38
QB[3:0]
OUTPUT
40, 41
FSEL_B[1:0]
INPUT*
Bank B divide select pins.
42, 43
FSEL_A[1:0]
INPUT*
Bank A divide select pins.
44, 46, 48, 50
QA[3:0]
OUTPUT
52
VCO_SEL
INPUT*
Feedback input
Clock outputs (Bank B)
Clock outputs (Bank A)
VCO select. High = VCO/1, Low = VCO/2.
* 25KΩ pull-up resistor
3
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
1.0 ELECTRICAL SPECIFICATIONS
TABLE 1: GENERAL SPECIFICATIONS
SYMBOL
CHARACTERISTICS
VTT
Output Termination Voltage
ESDMM
ESD Protection (Machine model)
200
V
ESDHBM
ESD Protection (Human body
model)
2000
V
LU
Latch-up Immunity
200
mA
CIN
Input capacitance
CONDITION
MIN
TYP
MAX
VDD÷2
per input
UNIT
V
4
pf
TABLE 2: ABSOLUTE MAXIMUM RATINGS
SYMBOL
CHARACTERISTICS
VDD
Supply Voltage
VIN
CONDITION
MIN
TYP
MAX
UNIT
-0.3
3.9
V
DC Input Voltage
-0.3
VDD + 0.3
V
VOUT
DC Output Voltage
-0.3
VDD + 0.3
V
IIN
DC Input Current
+/-20
mA
IOUT
DC Output Current
+/-50
mA
TS
Storage Temperature
125
°C
-65
TABLE 3: DC CHARACTERISTICS (VDD = 3.3V +/- 5%)
SYMBOL
CHARACTERISTICS
VDD_PLL
PLL Supply Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
VPP
Peak to Peak Input Voltage PECL and PECL
LVPECL
250
VCMR
Common Mode Range PECL and PECL
LVPECL
1.0
VOH
Output High Voltage
IOH = -24mA
2.4
VOL
Output Low Voltage
IOL = 24mA
IOL = 12mA
ZOUT
Output Impedance
IPU
Input Current
VIN = GND or VDD
IDD_PLL
PLL Supply Current
@ VDD_PLL Pin
IDDQ
Quiescent Supply Current
CONDITION
MIN
TYP
MAX
UNIT
3.0
VDD
V
2.0
VDD+ 0.3
V
0.8
V
mV
VDD - 0.6
V
0.55
0.30
-100
8
V
Ω
14 -17
4
V
200
μA
13.5
mA
35
mA
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
TABLE 4: AC CHARACTERISTICS (VDD = 3.3V +/- 5%)
SYMBOL
CHARACTERISTICS
CONDITION
MIN
fREF
Input reference frequencya
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
PLL bypass mode
fVCO
VCO frequency range
fMAX
Output frequencya
fSTOP_CLK
Serial interface frequency
VPP
Peak to Peak Input Voltage
PECL and PECL
LVPECL
VCMR
Common Mode Range PECL
and PECL
LVPECL
tPW
CLKx pulse width
ItR, ItF
Input CLKx Rise/Fall time
0.8V to 2.0V
Propagation Delay (static
6.25MHz < fREF < 65.0MHz
t(∅)
÷2 output
÷4 output
÷6 output
÷8 output
÷10 output
÷12 output
÷16 output
÷20 output
÷24 output
fREF = 50MHz & FB = ÷8
Output to output skew
MAX
UNIT
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
120
80.0
60.0
48.0
40.0
30.0
24.0
20.0
15.0
12.0
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
200
480
MHz
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
240.0
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
20.0
MHz
400
1000
mV
1.2
VDD - 0.9
V
2.0
phase offset) CLKx to FB_INb 65.0MHz < fREF < 125MHz
tSK(O)
TYP
ns
-3
-4
-166
Bank A (QAx to QAy)
Bank B (QBx to QBy)
Bank C (QCx to QCy)
all outputs (QXy to QWz)c
DC
Output duty cycled
OtR, OtF
Output Rise/Fall time
(T÷2)-200
0.55 to 2.4V
5
0.1
T÷2
1
ns
+3
+4
+166
°
°
ps
100
100
100
250
ps
ps
ps
ps
(T÷2)+200
ps
1.0
ns
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
TABLE 5: AC CHARACTERISTICS (CON’T) (VDD = 3.3V +/- 5%)
SYMBOL
CHARACTERISTICS
tPLZ, tPHZ
CONDITION
MIN
TYP
MAX
UNIT
Output Disable Time
8
ns
tPZL, tPZH
Output Enable Time
8
ns
tJIT(CC)
Cycle-to-Cycle Jitter
All outputs in same divider
config.
200
ps
tJIT(PER)
Period Jitter
All outputs in same divider
config.
150
ps
tJIT(Ø)
I/O Phase Jitter RMS (1σ)
VCO = 400MHz
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
11
86
13
88
16
19
21
22
27
30
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
BW
PLL closed loop bandwidth
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
tLOCK
PLL Lock Time
150
1.20-3.50
0.70-2.50
0.50-1.80
0.45-1.20
0.30-1.00
0.25-0.70
0.20-0.55
0.17-0.40
0.12-0.30
0.11-0.28
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
10
NOTES:
a. PLL locked, except when configured in bypass mode.
b. t(Ø)[s] = t(Ø)[°] ÷ (fref x 360°)
c. Not including Qsync output
d. T is the output period.
FIGURE 3. TEST LOAD
Transmission Line
Z = 50Ω
50Ω
VTT
6
ms
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
2.0 CONFIGURATION TABLES
TABLE 6: FUNCTION CONTROLS
CONTROL PIN
LOGIC 0
LOGIC 1
MR/OE
Resets the output divide circuitry and serial
interface, tri-states all outputs
Enables all outputs - normal operation
PLL_EN
PLL bypass mode enabled. This is a test
mode in which the reference clock is provided
to the output dividers in place of the VCO.
PLL enabled - normal operation
REF_SEL
CLKx selected as ref source to PLL
PECL & PECL inputs selected as ref source to
PLL
CLK_SEL
CLK0 selected
CLK1 selected
INV_CLK
QC2 & QC3 are in phase with QC1 & QC4
QC2 & QC3 are 180° out of phase with QC1 &
QC4
VCO_SEL
VCO ÷ 2
no divide of VCO
TABLE 7: BANK OUTPUT D IVIDER CONTROLS
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
FSEL_A1
FSEL_A0
QA
FSEL_B1
FSEL_B0
QB
FSEL_C1
FSEL_C0
QC
0
0
÷4
0
0
÷4
0
0
÷2
0
1
÷6
0
1
÷6
0
1
÷4
1
0
÷8
1
0
÷8
1
0
÷6
1
1
÷12
1
1
÷10
1
1
÷8
TABLE 8: FEEDBACK D IVIDER CONTROL
FSEL_FB2
FSEL_FB1
FSEL_FB0
QFB
0
0
0
÷4
0
0
1
÷6
0
1
0
÷8
0
1
1
÷10
1
0
0
÷8
1
0
1
÷12
1
1
0
÷16
1
1
1
÷20
7
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
3.0 QSYNC TIMING
FIGURE 4. QSYNC TIMING DIAGRAM
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
fVCO
1:1 Mode
QA
QC
QSYNC
2:1 Mode
QA
QC
QSYNC
3:1 Mode
QC(/2)
QA(/6)
QSYNC
3:2 Mode
QA(/4)
QC(/6)
QSYNC
4:1 Mode
QC(/2)
QA(/8)
QSYNC
4:3 Mode
QA(/6)
QC(/8)
QSYNC
6:1 Mode
QA(/12)
QC(/2)
QSYNC
XRK69773 INDIVIDUAL OUTPUT DISABLE (STOP CLOCK) CIRCUITRY
The user can write to the serial input register through the STOP_DATA input by supplying a logic ’0’ start bit
followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the
free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the XRK69773 can
sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. A logic "0" to any
stop bit location will disable the corresponding device output while a logic "1" will enable. All outputs are by
default, enabled.
FIGURE 5. STOP CLOCK CIRCUIT PROGRAMMING
STOP_CLK
STOP_DATA
START
QA0
QA1
QA2
QA3
QB0
8
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
FIGURE 6. OUTPUT-TO-OUTPUT SKEW tSK(O)
VCC
VCC÷2
GND
VCC
VCC÷2
GND
tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device.
FIGURE 7. PROPOGATION DELAY (t(Ø), STATIC PHASE OFFSET) TEST REFERENCE
VCC
CCLKx
VCC÷2
GND
VCC
VCC÷2
FB_IN
GND
t(Ø)
FIGURE 8. OUTPUT DUTY C YCLE (DC)
VCC
VCC÷2
GND
tp
T0
DC=tP/T0 x 100%
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
FIGURE 9. I/O JITTER
CCLKx
FB_IN
TJIT(I/O) = |T0-T1mean |
The deviation in t0 for a controlled edge with respect to a t 0 mean in a random
sample of cycles
9
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
FIGURE 10. CYCLE-TO-CYCLE JITTER
TN
TN+1
TJIT(CC)= |TN-TN+1 |
The variation in cycle time of a signal between adjacent cycles, over a random
sample of adjacent cycle pairs
FIGURE 11. PERIOD JITTER
T0
TJIT(Per)= |TN-1/f0 |
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
FIGURE 12. OUTPUT TRANSITION TIME TEST R EFERENCE
VCC=3.3V
2.4
0.55
OtF
OtR
10
E
PRELIMINARY
REV. P1.0.0
PACKAGE DIMENSIONS
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
52 LEAD LOW-PROFILE QUAD FLAT PACK
(10 mm x 10 mm X 1.4 mm LQFP, 1.0 mm Form)
Rev. 1.00
Note: The control dimension is in millimeters.
SYMBOL
A
A1
A2
B
C
D
D1
e
L
α
INCHES
MIN
MAX
0.055
0.063
0.002
0.006
0.053
0.057
0.010
0.014
0.004
0.009
0.465
0.480
0.390
0.398
0.0256 BSC
0.029
0.041
0°
7°
MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.25
0.35
0.11
0.23
11.80
12.20
9.90
10.10
0.65 BSC
0.73
1.03
0°
7°
α
11
PRELIMINARY
XRK69773
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
REVISION HISTORY
REVISION #
DATE
P1.0.0
April 7, 2006
DESCRIPTION
Initial release.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet April 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
12