PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION 1 Z86E64 1 CMOS Z8 OTP MICROCONTROLLER FEATURES Device ROM (KB) RAM* (Bytes) I/O Lines Voltage Range Z86E64 32 236 52 4.5-5V Note: *General-Purpose ■ Low-Power Consumption: 200 mW (max) ■ Fast Instruction Pointer: 0.75 µs @ 16 MHz ■ Two Standby Modes: STOP and HALT ■ Full-Duplex UART ■ All Digital Inputs are TTL Levels ■ Auto Latches ■ RAM and ROM Protect ■ Two Programmable 8-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler ■ Six Vectored, Priority Interrupts from Eight Different Sources ■ Low EMI Mode Option ■ 68-Pin Leaded Chip-Carrier GENERAL DESCRIPTION The Z86E64 is a member of the Z8 single-chip microcontroller family. The Z86E64 can address both external memory and pre-programmed ROM, which enables this Z8 MCUTM to be used in high-volume applications where code flexibility is required. The Z86E64 is a pin compatible, One-Time-Programmable (OTP) version of the Z86C64. The Z86E64 contains 32 KB of EPROM memory in place of the 32 KB of ROM on the Z86C64. There are three basic address spaces available to support this wide range of configuration: Program Memory, Data Memory, and 236 general-purpose registers. The Z86E64 offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many industrial and advanced scientific applications. CP96DZ83200 (10/96) For applications demanding powerful I/O capabilities, the Z86E64’s dedicated input and output lines are grouped into six ports. Each port consists of eight lines, except port 6, which has four lines. Each port is configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. The Z86E64 offers two on-chip counter/timers with a large number of user-selectable modes, and an Universal Asynchronous Receiver/Transmitter (UART). See figure 1 forFunctional Block description. Note: All Signals with a preceding front slash, "/", are active Low, for example: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power VCC VDD Ground GND VSS PRELIMINARY 1 Z86E64 CMOS Z8 OTP Microcontroller GENERAL DESCRIPTION (Continued) Vcc Output Input GND Port 3 ALU Program Memory 32,768 x 8-Bit Flags Counter/ Timers (2) Register Pointer Interrupt Control Port 5 Port 4 Port 0 Port 2 I/O (Bit Programmable) Program Counter Register File 256 x 8-Bit 4 I/O (Bit Programmable) /AS /DS R//W /RESET Machine Timing and Instruction Control UART Port 6 XTAL Port 1 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) Figure 1. Z86E64 Functional Block Diagram 2 PRELIMINARY CP96DZ83200 Z86E64 CMOS Z8 OTP Microcontroller 6 5 4 3 2 1 0 7 P2 6 P2 5 P2 P4 1 1 P4 6 7 P3 8 1 P3 P3 7 XT AL 1 XT AL P4 2 5 VC C P4 4 P4 3 P4 2 P3 9 0 /R es et PIN DESCRIPTION 68 67 66 65 64 63 62 61 R//W 10 60 P24 /P0DS 11 59 P23 /DS 12 58 P22 P46 13 57 P60 P47 14 56 P61 /P1DS 15 55 P21 /AS 16 54 P20 /DTimers 17 53 SCLK P35 18 52 /SYNC /ROMless 19 51 GND GND 20 50 P33 P32 21 49 P34 P50 22 48 P62 P51 23 47 P63 P00 24 46 P17 P01 25 45 P16 P02 26 44 P15 Z86E64 PLCC 4 P1 7 P1 2 P1 3 P5 3 P5 4 P5 5 P1 0 P1 1 P5 6 P5 4 5 P0 6 P0 7 VC C P5 2 P0 P0 P0 3 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Figure 2. Z86E64 68-Pin PLCC Pin Assignments CP96DZ83200 PRELIMINARY 3 Z86E64 CMOS Z8 OTP Microcontroller PIN DESCRIPTION (Continued) Table 1. Z86E64 68-Pin PLCC Pin Identification Pin # Symbol Function Direction 1-2 3 4 5 6 7 8 9 10 11 12 13-14 15 16 17 18 19 20 21 22-23 24-31 32 33-36 37-38 39-40 41-46 47-48 49 50 51 52 53 54-55 56-57 58-63 64-65 66 67 68 P44-P43 VCC P45 XTAL2 XTAL1 P37 P30 /RESET R//W /P0DS /DS P47-P46 /P1DS /AS /DTIMER P35 /ROMless GND P32 P51-P50 P07-P00 VCC P55-P52 P11-P10 P56-P57 P17-P12 P63-P62 P34 P33 GND /SYNC SCLK P21-P20 P60-P61 P27-P22 P41-P40 P31 P36 P42 Port 4, Pins 3,4 Power Supply Port 4, Pin 5 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Reset Read/Write Port 0 Data Strobe Data Strobe Port 4, Pins 6,7 Port 1, Data Strobe Address Strobe DTIMER Port 3, Pin 5 ROM/ROMless control Ground Port 3, Pin 2 Port 5, Pins 0,1 Port 0, Pins 0,1,2,3,4,5,6,7 Power Supply Port 5, Pins 2,3,4,5 Port 1, Pins 0,1 Port 5, Pins 6,7 Port 1, Pins 2,3,4,5,6,7 Port 6, Pins 3,2 Port 3, Pin 4 Port 3, Pin 3 Ground Synchronization System Clock Port 2, Pins 0,1 Port 6, Pins 1,0 Port 2, Pins 2,3,4,5,6,7 Port 4, Pins 0,1 Port 3, Pin 1 Port 3, Pin 6 Port 4, Pin 2 In/Output Input In/Output Output Input Output Input Input Output Output Output In/Output Output Output Input Output Input Input Input In/Output In/Output Input In/Output In/Output In/Output In/Output In/Output Output Input Input Output Output In/Output In/Output In/Output In/Output Input Output In/Output 4 PRELIMINARY CP96DZ83200 Z86E64 CMOS Z8 OTP Microcontroller DC CHARACTERISTICS VCC = 4.5V to 5.5V TA = 0°C to +70°C Sym Parameter Min Max Input Voltage Max 1 Typical at 25°C Units Conditions 7 V IIN <250 µA V V P30-P33 Only in OTP mode Driven by External Clock Generator Driven by External Clock Generator VCH Max Input Voltage Clock Input High Voltage 3.8 12.5V VCC VCL Clock Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage –0.3 0.8 V VOH Output High Voltage 2.4 VOL Output Low Voltage VRH Reset Input High Voltage VRl Reset Input Low Voltage V IOH = –2.0 mA 0.4 V IOL = +2.0 mA 3.8 VCC V –0.3 0.8 V IIL Input Leakage –10 10 µA 0V < VIN < +5.25V IOL Output Leakage –10 10 µA 0V < VIN < +5.25V IIR Reset Input Current –50 µA VCC= +5.25V, VRL = 0V ICC Supply Current 50 25 mA @ 12 MHz 35 5 mA mA @ 16 MHz Standby Current 60 15 20 10 mA HALT Mode VIN = 0V, VCC @ 16 MHz 20 5 µA STOP Mode VIN = 0V, VCC @ 12 MHz 20 5 µA STOP Mode VIN = 0V, VCC @ 16MHz ICC1 ICC2 Standby Current CP96DZ83200 PRELIMINARY 5 Z86E64 CMOS Z8 OTP Microcontroller AC CHARACTERISTICS External I/O or Memory Read or Write Timing Diagram R//W 13 12 Port 0, /DM 16 3 19 Port 1 A 7 -A 1 D 0 7 - D IN 0 2 9 /AS 8 18 11 4 5 /DS (Read) 6 17 10 Port 1 A 7 -A D - D OUT 7 0 0 14 15 7 /DS (Write) Figure 3. External I/O or Memory Read/Write Timing 6 PRELIMINARY CP96DZ83200 Z86E64 CMOS Z8 OTP Microcontroller External I/O or Memory Read and Write Timing Table VCC = 4.5V to 5.5V 1 TA = 0°C to 70°C 12 MHz No Symbol Parameter Min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDI(DS) TdDM(AS) Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req’d Valid /AS Low Width Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req’d Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay /DS Rise to R//W Not Valid Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req’d Valid /AS Rise to /DS Fall Delay Data Input Setup to /DS Rise /DM Valid to /AS Fall Delay Max 35 45 16 MHz Min Units Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns [2,3] [2,3] [1,2,3] [2,3] 20 30 220 55 0 185 110 180 35 0 135 80 130 0 45 55 30 35 35 35 75 0 35 30 20 30 25 30 255 55 75 50 Max 200 40 60 30 [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [2,3] Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics. Standard Test Load All timing references use 2.0V for a logic 1 and 0.8V for a logic 0. Clock Dependent Formulas Number 1 2 3 4 6 7 8 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TwDSR TwDSW TdDSR(DR) CP96DZ83200 Clock Dependent Formulas Equation 0.40TpC + 0.32 0.59TpC – 3.25 2.38TpC + 6.14 0.66TpC – 1.65 2.33TpC – 10.56 1.27TpC + 1.67 1.97TpC – 42.5 10 11 12 13 14 15 16 17 18 19 PRELIMINARY TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TsDI(DS) TdDM(AS) 0.8TpC 0.59TpC – 3.14 0.4TpC 0.8TpC – 15 0.4TpC 0.88TpC – 19 4TpC – 20 0.91TpC – 10.7 0.8TpC – 10 0.9TpC – 26.3 7 Z86E64 CMOS Z8 OTP Microcontroller AC CHARACTERISTICS (Continued) Additional Timing Diagram 3 1 Clock 2 T 2 3 IN 4 IRQ N 5 Figure 4. Additional Timing AC CHARACTERISTICS Additional Timing Table VCC = 4.5V to 5.5V TA = 0°C to +70°C 12 MHz No Symbol Parameter 1 2 3 4 5 6 7 8A 8B 9 TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Times Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times 16 MHz Min Max Min Max Units Notes 83 500 15 62.5 500 10 ns ns ns ns [1] [1] [1] [2] [2] [2] [2] [2,4] [2,5] [2,3] 41 75 5TpC 8TpC 100 70 5TpC 5TpC 31 50 5TpC 8TpC 100 50 5TpC 5TpC ns ns Notes: 1. Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. 2. Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. 3. Interrupt references request via Port 3. 4. Interrupt request via Port 3 (P31-P33). 5. Interrupt request via Port 30. 8 PRELIMINARY CP96DZ83200 Z86E64 CMOS Z8 OTP Microcontroller 1 Data In Data In Valid 1 Next Data In Valid 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Figure 5. Input Handshake Timing Data Out Valid Data Out Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Figure 6. Output Handshake Timing CP96DZ83200 PRELIMINARY 9 Z86E64 CMOS Z8 OTP Microcontroller AC CHARACTERISTICS (Continued) Handshake Timing Table VCC = 4.5V to 5.5V TA = 0°C to +70°C 12 MHz No Symbol Parameter Min 1 2 3 4 5 6 7 8 9 10 11 TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdDO(DAV) TcLDAV0(RDY) TcLDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Data In Setup Time Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay 0 145 110 10 PRELIMINARY Max Notes 16 MHz Min Max 0 145 110 115 115 0 115 115 0 TpC 0 TpC 0 115 110 115 110 115 115 Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT CP96DZ83200 Z86E64 CMOS Z8 OTP Microcontroller 1 Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or nonconformance with some aspects of the CPS may be found, Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on © 1996 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. CP96DZ83200 either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com PRELIMINARY 11 Z86E64 CMOS Z8 OTP Microcontroller 12 PRELIMINARY CP96DZ83200