INTERSIL ZL9010M

Digital DC/DC PMBus 10A Power Module
ZL9010M
Features
The ZL9010M is a 10A variable output, step-down
PMBus-compliant digital power supply. Included in the module
is a high-performance digital PWM controller, power MOSFETs,
an inductor, and all the passive components required for a
highly integrated DC/DC power solution. This power module
has built-in auto-compensation algorithms, which eliminates
the need for manual compensation design work. The
ZL9010M operates over a wide input voltage range and
supports an output voltage range of 0.6V to 3.6V, which can be
set by external resistors or via PMBus. Only bulk input and
output capacitors are needed to finish the design. The output
voltage can be precisely regulated to as low as 0.6V with ±1%
output voltage regulation over line, load, and temperature
variations.
• Complete digital switch mode power supply
The ZL9010M functions as a switch mode power supply with
added benefits of auto compensation, programmable power
management features, parametric monitoring, and status
reporting capabilities.
• Server, telecom, and datacom
• Auto compensating PID filter
• ±1% output voltage accuracy
• External synchronization
• Output voltage tracking
• Current sharing and phase interleaving
• Programmable sequencing (delay and ramp time)
• Snapshot™ parametric capture
• PMBus compliant
Applications
• Industrial and medical equipment
• General purpose point of load
Related Literature
The ZL9010M is packaged in a thermally enhanced, compact
(17.2mm x 11.45mm) and low profile (2.5mm) over-molded
high-density array (HDA) package module suitable for
automated assembly by standard surface mount equipment.
The ZL9010M is Pb-free and RoHS compliant.
• See AN2033, “Zilker Labs PMBus Command Set - DDC
Products”
• See AN2034, “Configuring Current Sharing on the ZL2004
and ZL2006”
Figure 1 represents a typical implementation of the ZL9010M.
For PMBus operation, it is recommended to tie the Enable pin
(EN) to SGND.
VDD
VIN
4.5V TO
13.2V
DGND
POWER-GOOD
OUTPUT
ENABLE
PG
EXT SYNC
DDC BUS
EN
VIN
(EPAD)
SYNC
VOUT
(EPAD)
ZL9010M
DDC
2.5mm
FB+
FB-
SGND
RTN
mm
V1
PGND
(EPAD)
5
11.4
SDA
SA
RSA
VOUT
COUT
SCL
I2C/PMbus
2x22µF
16V
17. 2
mm
RSET
*Patent pending package
FIGURE 1. TYPICAL APPLICATION CIRCUIT
March 5, 2013
FN8422.0
1
FIGURE 2. SMALL FOOTPRINT PACKAGE
WITH LOW PROFILE AT 2.5mm
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ZL9010M
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinout Internal Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Bias and Input Voltage Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Trade-offs with Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Completing a Power Supply Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection of the Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection of the Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
13
13
13
13
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C/PMbus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C/PMbus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Spreading for a Single-phase Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tracking Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring via I2C/PMbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SnapShot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
14
15
15
16
17
17
18
18
19
19
20
20
20
21
21
22
23
23
23
23
23
23
24
24
Layout Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
25
25
26
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2
FN8422.0
March 5, 2013
ZL9010M
Pin Configuration
V25
PG
EN
DDC
XTEMP
VDD
VDD
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
A
PAD1
VIN
SGND C
V25
V25
B
PAD2
DGND D
PGND
V25
ZL9010M
(32 LD HDA)
TOP VIEW
SYNC E
SA F
PGND
PAD3
SGND
SCL G
PAD4
SW
VR
SDA H
SALRT J
FC0 K
PAD5
VOUT
4
V1
SS
VTRK
5
6
7
8
FB-
3
TEST
2
FB+
1
V1
L
9
10 11 12 13 14 15 16 17
Pin Descriptions
PIN
LABEL
TYPE
DESCRIPTION
A1, A2,
B3, B6
V25
PWR
A3
PG
0
Power-good output. Provide open-drain power-good signal. By default, the PG pin asserts if the output is within
+15/-10% of the target voltage. These limits and the polarity of the pin may be changed via the I2C/PMbus interface.
A4
EN
I
Enable input. This pin is factory set as active high. Pull-up to enable the module switching and pull-down to disable
switching. If the module is controlled through PMbus command, tie a 10kΩ resistor from this pin to SGND to avoid this
pin floating.
A5
DDC
I/O
Digital-DC bus (open drain). The DDC pin on all Digital modules in one application should be connected together. This
dedicated bus provides the communication channel between modules for features such as sequencing, fault spreading,
and current sharing.
A6
XTEMP
I
External temperature sensor input. Connect to an external 2N3904 transistor with a diode configuration. See Figure 25
on page 24.
A7, A8
VDD
PWR
Internal 2.5V reference. It is used to power internal circuitry.
Controller input voltage. Tie to VIN directly.
C1
SGND
PWR
Signal ground. Connect to low impedance ground plane.
D1
DGND
PWR
Digital ground. Common return for digital signals. Connect to low impedance ground plane.
E1
SYNC
I/O
F1
SA
I
F10
PGND
PWR
G1
SCL
I/O
Serial clock. I2C/PMbus interface pin.
H1
SDA
I/O
Serial data. I2C/PMbus interface pin.
H9
VR
PWR
J1
SALRT
O
Clock synchronization. Used for synchronization to external frequency reference.
Serial address select pin. Used to assign unique PMbus address to each module and phase spreading.
Power ground. Connect to low impedance ground plane.
Internal 5V reference. Used to power internal drivers. The current limit for the VR pin is 10mA. Please consider this when
using the VR pin for driving external circuitry.
Serial alert. I2C/PMbus interface pin.
3
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March 5, 2013
ZL9010M
Pin Descriptions
(Continued)
PIN
LABEL
TYPE
K1
FC0
I
Mode Setting. Used to set the single-phase/current sharing mode, auto-compensation, and SYNC configuration. See
Table 9 on page 19.
DESCRIPTION
L1, L2
V1
I
Output voltage selection pin. It is used to program the output voltage through pin-strap setting or connecting a resistor from
the V1 pin to SGND. See “SINGLE RESISTOR VOUT SETTING” on page 15. The set voltage on this pin is the maximum
allowed output voltage in I2C/PMbus programming.
L3
SS
I
Soft-start pin. Set SS pin by pin-strapping or connecting a resistor to SGND using the appropriate resistor. The pin can
program the delay from when EN is asserted until the output voltage starts to ramp, the output voltage ramp time during
turn on/off, and input undervoltage lockout (UVLO) level (see Table on page 17). This pin can also set tracking ratio and
upper track limit (see Table 10 on page 21).
L4
VTRK
I
Tracking sense input. Used to track an external voltage source.
L6
FB+
I
Output voltage positive feedback. Positive inputs of differential remote sense for the regulator. Connect to the output
rail or the regulation point of load/processor.
L7
FB-
I
Output voltage negative feedback. Negative input of the differential remote sense for the regulator. Connect to the
negative rail or ground of the load/processor.
L8
TEST
I
Test pin. For factory test use. Solder down the pin for mechanical strength, but do not connect the pin.
PAD1
VIN
PWR
Power inputs. Input voltage range: 4.5V to 13.2V. Tie directly to the input rail. When the input is between 4.5V to 5.5V,
VIN should be tied directly to VCC.
PAD2
PGND
PWR
Power ground. Power ground pins for both input and output returns.
PAD3
SGND
PWR
Signal ground. Connect to low impedance ground plane (see Figure 26 on page 25).
PAD4
SW
PWR
Switch node. Use for monitoring switching frequency. SW pad should be floating or used for snubber connections. To
achieve better thermal performance, the SW planes can also be used for heat removal with thermal vias connected to
large inner layers (see Figure 26 on page 25).
PAD5
VOUT
PWR
Power Output. Apply output load between these pins and PGND pins. Output voltage range: 0.6V to 3.6V.
4
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March 5, 2013
ZL9010M
Pinout Internal Circuit
EN
FC0 SS VTRK V1
A4
L4
L3
K1
V1
L1
VDD VDD
L2
A7
A8
VR
V25
V25
V25
V25
VIN
H9
A1
A2
B3
B6
Pad
14 1
3
A3
L
PG
FILTER
LDO
2.2µF
LDO
SS
OV/UV
POWER MANAGEMENT
INTERLEAVE
MGN
OC/UC
CURRENT SHARE
AUTOCOMP
VCC
PLL
E1
D-PWM
NVM
GH
GATE DRIVE LOGIC
SYNC
OUT
PWMH
Pad 4
SW
145
Pad
VOUT
0.5µH
GATE DRIVER
PWML
GL
NLR
GND
SUPERVISOR
DIGITAL
COMPENSATOR
PROTECTION
CSA
L8
ISENB
L6
FB+
L7
FB-
A6
XTEMP
VOUT
22
SCL
ADC
G1
SDA
H1
SA
F1
DDC
A5
COMMUNICATION
VSA
VDD
22
J1
ADC
SGND
TEMP
SENSOR
DGND
DIGITAL CONTROLLER
D1
F10
DGND
PGND
Pad
14 2
PGND
Pad
14 3
C1
SGND
SGND
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ZL9010MIRZ
PART
MARKING
ZL9010M
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
32 Ld 17.2x11.45 HDA
PKG.
DWG. #
Y32.17.2x11.45
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate
-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ZL9010M. For more information on MSL please see Tech Brief TB363.
5
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ZL9010M
Absolute Maximum Ratings
Thermal Information
(Note 4)
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
32 Ld HDA Package (Notes 7, 8) . . . . . . . .
15
1
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
DC Supply Voltage for VDD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Input Voltage for VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
MOSFET Drive Reference for VR Pin . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
2.5V Logic Reference for V25 Pin. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Logic I/O Voltage for PG, EN, DDC, SYNC,
PG, SCL, SDA, SALRT, FC0, V1, SS Pins . . . . . . . . . . . . . . . . . -0.3V to 6V
Analog Input Voltages XTEMP, VTRK,
FB+, FB-, ISENB Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Switch Node for SW Pin
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(PGND - 0.3V) to 30V
Transient (<100ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . (PGND - 5V) to 30V
Ground Voltage Differential (DGND - SGND, PGND - SGND)
for DGND, SGND and PGND Pins . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . 1000V
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
Input Supply Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . 4.5V to 13.2V
Input Supply For Controller, VDD (Note 5) . . . . . . . . . . . . . . . . 4.5V to 13.2V
Driver Supply Voltage, VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Output Voltage Range, VOUT (Note 6) . . . . . . . . . . . . . . . . . . . 0.54V to 3.6V
Output Current Range, IOUT(DC) (Note 18) . . . . . . . . . . . . . . . . . . 0A to 10A
Operating Junction Temperature Range, TJ. . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Voltage measured with respect to SGND.
5. VIN supplies the power FETs. VDD supplies the controller. VIN can be tied to VDD. For VDD ≤ 5.5V, VDD should be tied to VR.
6. Includes ±10% margin limits.
7. θJA is simulated in free air with device mounted on a four-layer FR-4 test board (76.2 x 114.3 x 1.6mm) with 80% coverage, 2oz Cu on top and bottom
layers, plus two, buried, one-ounce Cu layers with coverage across the entire test board area. Multiple vias were used, with via diameter = 0.3mm on
1.2mm pitch.
8. For θJC, the “case” temperature is measured at the center of the package underside.
Electrical Specifications
VIN = VDD = 12V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
(Note 9) (Note 10) (Note 9)
UNIT
INPUT AND SUPPLY CHARACTERISTICS
Input Bias Supply Current, IDD
VIN = VDD = 13.2V, fSW = 400kHz, no load
–
35
45
mA
Input Bias Shutdown Current, IDDS
EN = 0V, no I2C/PMbus activity
–
15.5
20
mA
Input Supply Current, IVIN
VIN = 12V, IOUT = 10A, VOUT = 1.2V, fSW = 400kHz
–
1.22
–
A
VR Reference Output Voltage (Note 11)
VDD > 6V
4.5
5.2
5.7
V
V25 Reference Output Voltage (Note 11)
VR > 3V
2.25
2.5
2.75
V
Output Voltage Adjustment Range (Note 11)
VIN > VOUT. Does not include margin limits.
0.6
–
3.3
V
Output Voltage Set-point Resolution
Set using resistors. (See Table 1)
–
50 - 200
–
mV
Set using I2C/PMbus with temperature compensation
applied
–
±0.025
–
% FS
Output Voltage Accuracy (Notes 11, 12)
Includes line, load, temp
-1
–
1
%
VSEN Input Bias Current (Note 11)
VSEN = 5.5V
–
110
200
µA
Output Load Current (Note 19)
VIN = 12V, VOUT = 1.2V
–
10
–
A
Peak-to-peak Output Ripple Voltage, ΔVOUT (Note 12) IOUT = 6A, VOUT = 1.2V, COUT = 1000µF
–
20
–
mV
Soft-start Delay Duration Range (Notes 11, 13)
5
–
20
ms
0.005
–
500
s
OUTPUT CHARACTERISTICS
Set using SS pin or resistor
Set using I2C/PMbus
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FN8422.0
March 5, 2013
ZL9010M
Electrical Specifications
VIN = VDD = 12V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
CONDITIONS
Soft-start Delay Duration Accuracy (Notes 11, 13)
Soft-start Ramp Duration Range (Notes 11, 13)
MIN
TYP
MAX
(Note 9) (Note 10) (Note 9)
UNIT
Turn-on delay (Note 15)
–
-0.25/+4
–
ms
Turn-off delay (Note 15)
–
-0.25/+4
–
ms
Set using SS pin or resistor
2
–
20
ms
Set using I2C
0
–
200
ms
–
100
–
µs
Soft-start Ramp Duration Accuracy (Note 11)
DYNAMIC CHARACTERISTICS
Voltage Change for Positive Load Step
IOUT = 2A to 10A, slew rate = 1.6A/μs, VOUT = 1.2V
(see Figure 19)
–
4
–
%
Voltage Change for Positive Load Step
IOUT = 10A to 2A, slew rate = 1.6A/μs, VOUT = 1.2V
(see Figure 19)
–
4
–
%
300
–
1000
kHz
-5
–
5
%
-
–
95
%
150
–
–
ns
-13
–
13
%
–
100
–
kHz
-10
–
10
µA
Logic Input Low, VIL
–
–
0.8
V
Logic Input High, VIH
2.0
–
–
V
OSCILLATOR AND SWITCHING CHARACTERISTICS (Note 11)
Switching Frequency Range
Switching Frequency Set-point Accuracy
Predefined settings (See Table 1)
Maximum PWM Duty Cycle
Factory setting (Note 18)
Minimum SYNC Pulse Width
Input Clock Frequency Drift Tolerance
External clock source
LOGIC INPUT/OUTPUT CHARACTERISTICS (Note 11)
PMbus Speed
Logic Input Bias Current
EN, PG, SCL, SDA pins
Logic Output Low, VOL
IOL ≤ 4mA (Note 17)
–
–
0.4
V
Logic Output High, VOH
IOH ≥ -2mA (Note 17)
2.25
–
–
V
–
110
200
µA
-100
–
+ 100
mV
TRACKING (Note 11)
VTRK Input Bias Current
VTRK = 5.5V
VTRK Tracking Ramp Accuracy
100% Tracking, VOUT -VTRK, no prebias
VTRK Regulation Accuracy
100% Tracking, VOUT -VTRK
-1
–
1
%
Configurable via I2C/PMbus
2.85
–
16
V
-150
–
150
mV
Factory setting
–
3
–
%
Configurable via I2C/PMbus
0
–
100
%
–
–
2.5
µs
FAULT PROTECTION CHARACTERISTICS (Note 11)
UVLO Threshold Range
UVLO Set-point Accuracy
UVLO Hysteresis
UVLO Delay
Power-Good VOUT Threshold
Factory setting
–
90
–
% VOUT
Power-Good VOUT Hysteresis
Factory setting
–
5
–
%
Power-Good Delay (Note 16)
Configurable via I2C/PMbus
0
–
500
s
VSEN Undervoltage Threshold
Factory setting
–
85
–
% VOUT
Configurable via I2C/PMbus
0
–
110
% VOUT
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FN8422.0
March 5, 2013
ZL9010M
Electrical Specifications
VIN = VDD = 12V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
CONDITIONS
VSEN Overvoltage Threshold
MIN
TYP
MAX
(Note 9) (Note 10) (Note 9)
UNIT
Factory setting
–
115
–
% VOUT
Configurable via I2C/PMbus
0
–
115
% VOUT
–
5
–
% VOUT
16
–
µs
VSEN Undervoltage Hysteresis
VSEN Undervoltage/Overvoltage Fault Response
Time
Factory setting
–
Configurable via I2C/PMbus
5
–
60
µs
Thermal Protection Threshold
(Controller Junction Temperature)
Factory setting
–
125
–
°C
-40
–
125
°C
–
15
–
°C
Configurable via I2C/PMbus
Thermal Protection Hysteresis
NOTES:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10. Parameters with TYP limits are not production tested unless otherwise specified.
11. Parameters are 100% tested for internal controller prior to module assembly.
12. VOUT measured at the termination of the FB+ and FB- sense points.
13. The device requires a delay period following an enable signal and prior to ramping its output.
14. Precise ramp timing mode is only valid when using the EN pin to enable the device rather than PMBus enable.
15. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable
signal.
16. Factory setting for Power-Good delay is set to the same value as the soft-start ramp time.
17. Nominal capacitance of logic pins is 5pF.
18. Maximum duty cycle is limited by the equation MAX_DUTY(%) = [1 - (150×10-9 × fSW)] × 100 and not to exceed 95%
19. The load current is related to the thermal derating curves. The maximum allowed current is derated while the output voltage goes higher than 2.5V.
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ZL9010M
Typical Performance Curves
Operating conditions: TA = +25°C, No air flow, COUT = 3 x 100µF + 1 x 330µF.
Typical values are used unless otherwise noted.
100
100
95
95
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
90
80
75
3.3V 471kHz
2.5V 615kHz
1.8V 615kHz
1.2V 400kHz
1.0V 400kHz
0.6V 400kHz
70
65
60
55
50
0
1
2
3
4
5
6
7
80
75
70
3.3V 800kHz
2.5V 800kHz
1.8V 615kHz
1.2V 400kHz
1.0V 400kHz
0.6V 400kHz
65
60
55
50
45
8
9
10
40
0
1
2
3
4
IOUT (A)
FIGURE 3. ZL9010M EFFICIENCY, VIN = 5V
100mV/DIV
5
IOUT (A)
6
7
8
9
10
FIGURE 4. ZL9010M EFFICIENCY, VIN = 12V
100mV/DIV
VIN = 12V
VOUT = 1.2V
IOUT STEP = 2A TO 10A
SLEW 1.6A/µs
fSW = 615kHz
VIN = 12V
VOUT = 1.8V
IOUT STEP = 2A TO 10A
SLEW 1.6A/µs
fSW = 615kHz
2A/DIV
2A/DIV
200µs/DIV
200µs/DIV
FIGURE 5. VOUT = 1.2V TRANSIENT RESPONSE
100mV/DIV
FIGURE 6. VOUT = 1.8V TRANSIENT RESPONSE
100mV/DIV
VIN = 12V
VOUT = 2.5V
IOUT STEP = 2A TO 10A
SLEW 1.6A/µs
fSW = 615kHz
VIN = 12V
VOUT = 3.3V
IOUT STEP = 2A TO 10A
SLEW 1.6A/µs
fSW = 800kHz
2A/DIV
2A/DIV
200µs/DIV
FIGURE 7. VOUT = 2.5V TRANSIENT RESPONSE
9
200µs/DIV
FIGURE 8. VOUT = 3.3V TRANSIENT RESPONSE
FN8422.0
March 5, 2013
ZL9010M
Typical Performance Curves
Operating conditions: TA = +25°C, No air flow, COUT = 3 x 100µF + 1 x 330µF.
Typical values are used unless otherwise noted. (Continued)
20mV/DIV
20mV/DIV
20mV/DIV
20mV/DIV
VIN = 12V
VOUT = 1.2V
fSW = 615kHz
VIN = 12V
VOUT = 1.8V
fSW = 615kHz
20mV/DIV
20mV/DIV
2µs/DIV
2µs/DIV
FIGURE 9. VOUT = 1.2V OUTPUT VOLTAGE RIPPLE
FIGURE 10. VOUT = 1.8V OUTPUT VOLTAGE RIPPLE
20mV/DIV
20mV/DIV
20mV/DIV
20mV/DIV
VIN = 12V
VOUT = 2.5V
fSW = 615kHz
VIN = 12V
VOUT = 3.3V
fSW = 800kHz
20mV/DIV
20mV/DIV
2µs/DIV
2µs/DIV
FIGURE 11. VOUT = 2.5V OUTPUT VOLTAGE RIPPLE
1.4
1.4
VIN = 12V
VOUT = 1.2V
tFALL = 5ms
1.2
1.0
1.0
0.8
0.6
0.4
0.8
0.6
0.4
0.2
0.2
0
0
-0.2
0
1
2
3
4
5
6
7
TIME (ms)
FIGURE 13. SOFT-STOP RAMP-DOWN
10
8
9
VIN = 12V
VOUT = 1.2V
tRISE = 5ms
1.2
VOUT (V)
VOUT (V)
FIGURE 12. VOUT = 3.3V OUTPUT VOLTAGE RIPPLE
10
-0.2
0
1
2
3
4
5
6
7
8
9
10
TIME (ms)
FIGURE 14. SOFT-START RAMP-UP
FN8422.0
March 5, 2013
ZL9010M
Derating Curves
Operating conditions: TA = +25°C, No air flow. fSW corresponds to those used in Efficiency curves.
COUT = 3 x 100µF + 1 x 330µF. Typical values are used unless otherwise noted.
10
10
9
9
8
8
5VIN _1VOUT
7
6
5
IOUT (A)
IOUT (A)
7
5VIN _3.3VOUT
4
5
4
3
2
2
1
1
0
0
70
80
90
100
120
110
130
12VIN_1.8VOUT
6
3
60
12VIN_1VOUT
12VIN_3.3VOUT
60
70
80
AMBIENT TEMPERATURE (°C)
FIGURE 15. DERATING CURVE, 5V IN
FOR VARIOUS OUTPUT VOLTAGES, NO AIR FLOW
100
120
110
130
FIGURE 16. DERATING CURVE, 12V IN
FOR VARIOUS OUTPUT VOLTAGES, NO AIR FLOW
2.5
3.5
3.0
2.0
1.0V 400kHz
1.5
1.0
3.3V 800kHz
2.5
LOSS (W)
LOSS (W)
90
AMBIENT TEMPERATURE (°C)
2.0
1.5
1.8V 615kHz
3.3V 471kHz
1.0
0.5
0.5
0.0
0
1
2
3
4
5
6
IOUT (A)
FIGURE 17. POWER LOSS CURVE, 5V IN
FOR VARIOUS OUTPUT VOLTAGES
11
7
8
9
10
0.0
1.0V 400kHz
0
1
2
3
4
5
6
IOUT (A)
7
8
9
10
FIGURE 18. POWER LOSS CURVE, 12V IN
FOR VARIOUS OUTPUT VOLTAGES
FN8422.0
March 5, 2013
B6
V25.B6
A8
B3
V25.B3
VDD.A8
A7
VDD.A7
DDC
XTEMP
A6
EN
DDC
(Note 21)
A5
A3
A4
EN
PG
A2
PGND.F10
SALRT
FC0
L1
V1.L1
RSET L2
V1.L2
L3
SS
L4
VTRK
K1
C1
C2
C3
22µF
22µF
330µF (Optional)
PAD2
GND
PAD4
SDA
VR
J1
SW
ZL9010M
PAD1
SCL
F10
H1
SA
H9
SDA
SALRT
I2C/PMbus
(Note 20)
SYNC
ISENB
G1
PGND.PAD2
FB-
F1
SCL
SGND
DGND
L8
E1
(See Table 3 for RSA value) RSA
SGND.C1
L7
D1
VIN
VIN
FB+
C1
SGND
FERRITE BEAD
BLM15BD102SN1D, OR 2.2Ω
SGND.PAD3
L6
PAD3
V25.A2
V25.A1
A1
ZL9010M
VOUT
PAD5
VOUT
C4
C5
C6
C7
100µF
100µF
100µF
330µF
(Note 22)
GND
SGND
(See Table 4 for
RSET value)
SGND
FIGURE 19. TEST CIRCUIT FOR ALL PERFORMANCE AND DERATING CURVES
NOTES:
20. The I2C/PMbus requires pull-up resistors. Please refer to the I2C/PMbus specifications for more details.
21. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices connected).
The 10kΩ default value, assuming a maximum of 100pF per device, provides the necessary 1µs pull-up rise time. Please refer to “Digital-DC Bus”
on page 23 for more details.
22. Additional capacitance may be required to meet specific transient response targets.
Application Information
Internal Bias and Input Voltage
Considerations
Beside VIN supplying the main power conversion, the ZL9010M
employs two internal low dropout (LDO) regulators to supply bias
voltages for internal circuitry allowing it to operate from a single
input supply. The internal bias regulators are as indicated in the
following:
VR - The VR LDO provides a regulated 5V bias supply for the
MOSFET driver circuits. It is powered from the VDD pin.
V25 - The V25 LDO provides a regulated 2.5V bias supply for
the main controller circuitry. It is powered from an internal 5V
node.
When the input supply (VDD) is higher than 5.5V, the VR pin should
not be connected to any other pin. Due to the dropout voltage
associated with the VR bias regulator, the VDD pin can be connected
to the VR pin for designs operating from a supply below 5.5V. The
internal bias regulators are not designed to be outputs for
powering other circuitry, so keep current into the VDD pin below
80mA.
auto-compensation may not work correctly as the VDD voltage is
used to measure input voltage as part of the Pre-Bias and
Auto-compensation calculation.
Pre-programming Configuration
The Intersil digital power module allows pre-programming before
the main power rail is supplied to the VIN pins of the module. If
the system bias (i.e., 3.3V bias) is available, the power module
can be programmed to load the configuration file or change the
settings without main power being on. See Figure 20 for an
example with 3.3V bias voltage and 12V input voltage for the
main power rail. To pre-program the module without applying
power to the VIN pin, the bias voltage 3.3V is applied to pin VR
through a Schottky diode such that 3.0 < VR and less than VDD
when VIN is applied. The body diode of the PMOS will be reverse
biased, and prevent back feeding to the VIN rail. When the main
power rail 12V VIN is ON, the PMOS is ON to supply the power to
the module. In this case, only small voltage is dropped on the
PMOS, so the controller can still detect the input voltage
accurately. If there are more Intersil digital modules on the
board, only one PMOS (as shown in Figure 20) is required to drive
the VIN voltages of all modules.
Typically, VDD is connected directly to VIN. In the case that VDD is
powered separately from VIN, the recommended power
sequence is to keep EN low, power VDD, and then VIN. When the
voltage is applied to VIN, VDD should also be applied to avoid
unintentional turn-on of the internal high-side MOSFET. If the VDD
voltage is different from VIN, Pre-bias start-up and
12
FN8422.0
March 5, 2013
ZL9010M
In addition to the bulk capacitance, some low Equivalent Series
Resistance (ESR) ceramic capacitance should be placed as close
as possible to decouple between the drain terminal of the high
side MOSFET (VIN PAD1) and the source terminal of the low side
MOSFET (PGND PAD2). This is used to reduce voltage ringing
created by the switching current across parasitic circuit
elements. This ripple’s (ICINrms) impact should be considered,
and can be determined from Equation 2:
I CINrms = I OUT × D × ( 1 – D )
FIGURE 20. PRE-PROGRAMMING CONFIGURATION
Design Trade-offs with Switching Frequency
For design of the buck power stage, there is a trade-off when
choosing switching frequency to achieve higher power supply
efficiency, output ripple, and transient response. For output
voltages below 2.0V, a lower switching frequency results in higher
efficiency. A lower output ripple and faster transient response is
achieved with higher switching frequencies, and thereby can
reduce the required amount of output capacitance. Also, given
an input to output voltage relation, there is a limitation on the
allowable switching frequency due to normal part operation. See
“Switching Frequency and PLL” for more considerations.
To start the design with a goal of high efficiency, select a
frequency based on Table 1. To achieve good transient response,
a minimum switching frequency of 615kHz is recommended.
TABLE 1. OPTIMAL SWITCHING FREQUENCY FOR EFFICIENCY
V0-VIN
3.3V
(kHz)
5.0V
(kHz)
12.0V
(kHz)
0.6 - 1.5
300
400
400
1.5 - 2.5
300
615
615
2.5 - 3.6
300
471
800
(EQ. 2)
Without capacitive filtering near the power supply circuit, this
current would flow through the supply bus and return planes,
coupling noise into other system circuitry. The input capacitors
should be rated at 1.2X the ripple current calculated in
Equation 2 to avoid overheating of the capacitors due to the high
ripple current, which can cause premature failure.
Selection of the Output Capacitors
The ZL9010M is designed for low output voltage ripple. The
output voltage ripple and transient requirements can be met with
bulk output capacitors (COUT) with low ESR; the recommended
minimum ESR is <6MΩ. COUT can be a low ESR tantalum
capacitor, a low ESR polymer capacitor or a ceramic capacitor.
The typical output capacitance range is from 200µF to 1200µF,
and decoupling ceramic output capacitors are used per phase.
The optimized output capacitance is 700µF with an ESR of 5mΩ.
The maximum recommended product of output capacitance and
equivalent ESR value is given by [COUT x ESR] <3600 (µF x mΩ).
With a step load faster than 0.2A/µs, the recommended amount
of output capacitor is 100µF per ampere of step load. Additional
output filtering may be needed if further reduction of output
ripple or dynamic transient spikes are required.
Functional Description
Completing a Power Supply Design
Multi-mode Pins
To achieve a power supply design with digital capabilities using
ZL9010M, only input and output capacitors and two resistors are
needed. The two resistors are installed on the SA and V1 pins for
setting the I2C address and output voltage, respectively.
In order to simplify circuit design, the ZL9010M family
incorporates patented multi-mode pins that allow the user to
easily configure many aspects of the device without
programming. Most power management features can be
configured using these pins. The multi-mode pins can respond to
two types of configurations summarized in Table 2: pin strapping
and resistor programming. These pins are sampled when power is
applied or by issuing a PMBus Restore command (see Application
Note AN2033).
Selection of the Input Capacitor
The input filter capacitor should be based on how much ripple
the supply can tolerate on the DC input line. The larger the
capacitor, the less ripple expected, but consideration should be
taken for the higher surge current during power-up. The
ZL9010M provides the soft-start function that controls and limits
the current surge. The value of the input capacitor can be
calculated by Equation 1:
D • (1 – D)
C IN ( MIN ) = I O • ------------------------------------------•F
V
P-P ( MAX )
S
Where:
CIN(MIN) is the minimum input capacitance (µF) required
IO is the output current (A)
D is the duty cycle (VO/VIN)
VP-P(MAX) is the maximum peak-to-peak voltage (V)
FS is the switching frequency (Hz)
13
(EQ. 1)
With pin strapping, parameters can be set by strapping the pins
in one of three possible states: LOW, OPEN, or HIGH. These pins
can be connected to SGND for logic LOW as this pin provides a
voltage lower than 0.8V. For logic OPEN, they have no connection.
These pins can be connected to the V25 pin for logic HIGH
settings as this pin provides a regulated voltage higher than 2V
when power is applied to the VDD pin.
Resistor programming allows a greater range of adjustability
when connecting a finite value resistor (in a specified range)
between the multi-mode pin and SGND. Standard 1% resistor
values are used, and only every fourth standard resistor value is
used so the device can reliably recognize the value of resistance
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March 5, 2013
ZL9010M
connected to the pin while eliminating the error associated with
the resistor accuracy. Up to 31 unique selections are available
using a single resistor.
TABLE 2. MULTI-MODE PIN CONFIGURATION
PIN TIED TO
VALUE
LOW (Logic LOW)
<0.8VDC
OPEN (N/C)
No connection
HIGH (Logic HIGH)
>2.0VDC
Resistor to SGND
Set by resistor value
ZL9010M supports 100kHz and 400kHz I2C clock speed with
communication interval of 20ms between STORE and RESTORE
commands, and ~2ms for other general commands.
I2C/PMbus Module Address Selection
Each module must have its own unique serial address to
distinguish between other devices on the bus. The module
address is set by connecting a resistor between the SA pin and
SGND. Table 3 lists the available module addresses.
TABLE 3. PMbus ADDRESS VALUES
RSA (kΩ)
PMbus ADDRESS
LOW
0x23
OPEN
0x24
HIGH
0x25
10
0x50
11
0x51
12.1
0x52
SA sets the I2C address, phase spreading, and Reference/Member
assignment in current sharing mode. The effective phase spreading
depends on the mode of operation. The Reference/Member is
pre-assigned in current sharing mode, and up to 8 two-phase
with 5 three-phase current-shared group is possible.
13.3
0x53
14.7
0x54
16.2
0x55
17.8
0x56
FC0 is used to distinguish between the two modes of operation,
and is used in combination with SA in current sharing mode. FC0
pin strapping and resistor programming in the range of
10kΩ - 42.2kΩ set the operation to single-phase mode, while the
range of 46.4kΩ - 178kΩ is for current sharing mode. FC0 also
sets the Autcomp and Sync configuration.
19.6
0x57
21.5
0x58
23.7
0x59
26.1
0x5A
28.7
0x5B
SYNC sets the switching frequency, and is only effective in
single-phase mode, as SYNC pins are connected together in
current-sharing mode.
31.6
0x5C
34.8
0x5D
38.3
0x5E
42.2
0x5F
There are five multi-mode pins in ZL9010M: FC0, SA, SYNC, SS,
V1. The multi-mode pin configuration can set ZL9010M power
management features and mode of operation to both
single-phase and current-sharing without any programming. SA
and V1 are the only two pins that must be set for a general
single-phase operation, which use the default settings associated
with the other three pins, or overriding other parameters via the
I2C/PMbus.
SS sets the ramp timing, UVLO, and tracking. V1 sets the output
voltage. SS and V1 are the same purpose in single-phase and
current-share modes.
46.4
0x60
I2C/PMbus Communications
51.1
0x61
The ZL9010M provides an I2C/PMbus digital interface that
56.2
0x62
enables the user to configure all aspects of the module operation
as well as monitor the input and output parameters. The
ZL9010M can be used with any I2C host device. In addition, the
module is compatible with PMbus version 2.0 and includes a
SALRT line to help mitigate bandwidth limitations related to
continuous fault monitoring. Pull-up resistors are required on the
I2C/PMbus as specified in the PMbus 2.0 specification. The
ZL9010M accepts most standard PMBus commands. When
controlling the device with PMBus commands, it is
recommended that the enable pin be tied to SGND.
61.9
0x63
68.1
0x64
75
0x65
82.5
0x66
90.9
0x67
100
0x68
110
0x69
The PMbus device address and VOUT_MAX are the only
parameters that must be set by external pins. All other device
parameters can be set via the I2C/PMbus. The device address is
set using the SA pin. VOUT_MAX is determined as 10% greater
than the voltage set by the V1 pin.
14
121
0x6A
133
0x6B
147
0x6C
162
0x6D
178
0x6E
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ZL9010M
Phase Spreading for a Single-phase Mode of
Operation
When multiple point-of-load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time can dramatically reduce input
capacitance requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively spread out over
a period of time, the peak current drawn at any given moment is
reduced, and the power losses proportional to the IRMS2 are
reduced dramatically.
To enable spreading, all converters must be synchronized to the
same switching clock. The FC0 pin is used to set the
configuration of the SYNC pin for each device as described in
“Switching Frequency and PLL” on page 18.
Selecting the phase offset for the device in a standalone mode of
operation is accomplished by selecting a device address
according to the following equation:
Phase offset = device address x 45°
For example:
• A device address of 0x50 or 0x60 would configure no phase
offset
• A device address of 0x51 or 0x61 would configure 45° of
phase offset
• A device address of 0x52 or 0x62 would configure 90° of
phase offset
The phase offset of each device may also be set to any value
between 0° and 360° in 22.5° increments via the I2C/PMbus
interface. Refer to Application Note AN2033 for further details.
Output Voltage Selection
The output voltage may be set to a voltage between 0.6V and
3.6V provided that the input voltage is higher than the desired
output voltage by an amount sufficient to prevent the device
from exceeding its maximum duty cycle specification.
The V1 pins are used to set the output voltage using a single
resistor, RSET between the V1 pins and SGND. Table 4 lists the
available output voltage settings with a single resistor.
TABLE 4. SINGLE RESISTOR VOUT SETTING
RSET (kΩ)
VOUT
LOW
1.20
OPEN
1.50
HIGH
3.30
10
0.60
11
0.65
12.1
0.70
13.3
0.75
14.7
0.80
15
TABLE 4. SINGLE RESISTOR VOUT SETTING (Continued)
RSET (kΩ)
VOUT
16.2
0.85
17.8
0.90
19.6
0.95
21.5
1.00
23.7
1.05
26.1
1.10
28.7
1.15
31.6
1.20
34.8
1.25
38.3
1.30
42.2
1.40
46.4
1.50
51.1
1.60
56.2
1.70
61.9
1.80
68.1
1.90
75
2.00
82.5
2.10
90.9
2.20
100
2.30
110
2.50
121
2.80
133
3.00
147
3.30
162
3.60
The output voltage may also be set to any value between 0.6V
and 3.6V using a PMBus command over the I2C/PMbus
interface. See Application Note AN2033 for details.
The RSET resistors program places an upper limit in output
voltage setting through PMBUS programming to 10% above the
value set by the resistors.
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ZL9010M
Start-up Procedure
The ZL9010M follows a specific internal start-up procedure after
power is applied to the VDD pin. Table 5 describes the start-up
sequence.
If the device is to be synchronized to an external clock source, the
clock frequency must be stable prior to asserting the EN pin. The
device requires approximately 5ms to 6ms to check for specific
values stored in its internal memory. If the user has stored values
in memory, those values will be loaded. The device will then
check the status of all multi-mode pins and load the values
associated with the pin settings.
Once this process is completed, the device is ready to accept
commands via the I2C/PMbus interface and the device is ready
to be enabled. Once enabled, the device requires a minimum
delay period following an enable signal and prior to ramping its
output, as described in “Soft-start Delay and Ramp Times” on
page 17. If a soft-start delay period less than the minimum has
been configured (using PMBus commands), the device will
default to the minimum delay period. If a delay period greater
than the minimum is configured, the device will wait for the
configured delay period prior to starting to ramp its output.
After the delay period has expired, the output will begin to ramp
towards its target voltage according to the pre-configured
soft-start ramp time that has been set using the SS pin. It should
be noted that if the EN pin is tied to VDD, the device will still
require approximately 5ms to 6ms before the output can begin
its ramp-up as described in Table 5.
TABLE 5. ZL9010M START-UP SEQUENCE
STEP #
STEP NAME
DESCRIPTION
TIME DURATION
1
Power Applied
Input voltage is applied to the ZL9010M’s VDD pin
2
Internal Memory Check
3
Multi-mode Pin Check
The device will check for values stored in its internal memory. This step Approximately 5ms to 6ms
is also performed after a Restore command.
(device will ignore an enable
signal or PMBus traffic during this
The device loads values configured by the multi-mode pins.
period)
4
Device Ready
The device is ready to accept an enable signal.
5
Pre-ramp Delay
The device requires a minimum delay period following an enable signal and prior to ramping its output, as described in “Soft-start Delay and
Ramp Times” on page 17.
16
Depends on input supply ramp
time
-
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ZL9010M
Soft-start Delay and Ramp Times
It may be necessary to set a delay when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to precisely set the time
required for VOUT to ramp to its target value after the delay
period has expired. These features may be used as part of an
overall inrush current management strategy or to precisely
control how fast a load IC is turned on. The ZL9010M gives the
system designer several options for precisely and independently
controlling both the delay and ramp time periods.
The soft-start delay period begins when the EN pin is asserted and
ends when the delay time expires. The soft-start ramp timer enables
a precisely controlled ramp to the nominal VOUT value that begins
once the delay period has expired. The ramp-up is guaranteed
monotonic and its slope may be precisely set using the SS pin.
The soft start delay and ramp times can be set to a custom value
by pin-strapping or connecting a resistor from the SS pin to SGND
using the appropriate resistor value from Table 6. See “Input
Undervoltage Lockout” on page 19 for further explanation of
UVLO setting using SS pin. The value of this resistor is measured
upon start-up or Restore and will not change if the resistor is
varied after power has been applied to the ZL9010M.
TABLE 6. SOFT-START PIN-STRAP/RESISTOR SETTINGS
With the SS pin OPEN, the default value for delay time and ramp
time is 5ms. The soft-start delay and ramp times are set to
custom values via the I2C/PMbus interface. When the delay time
is set to 0ms, the device begins its ramp-up after the internal
circuitry has initialized (approximately 2ms). When the soft-start
ramp period is set to 0ms, the output ramps up as quickly as the
output load capacitance and loop settings allow. It is generally
recommended to set the soft-start ramp to a value greater than
500µs to prevent inadvertent fault conditions due to excessive
inrush current.
The ZL9010M has a minimum tON_DELAY requirement that is a
function of the operating mode. Table 7 shows the different
mode configurations and the minimum tON_DELAY required for
each mode. Current sharing is configured with the
ISHARE_CONFIG PMBus command, Auto compensation is
configured with the AUTO_COMP_CONFIG command, and
Standby Mode is configured as Low Power with the
USER_CONFIG command. See Application Note AN2033 for
details. Resistor programming on the SS pin with a delay time of
20ms can be used to satisfied the minimum tON_DELAY of 15ms.
TABLE 7. MINIMUM tON_DELAY vs OPERATING MODE
CURRENT
SHARING
AUTOCOMP
LOW-POWER
STANDBY
MIN.
tON_DELAY
(ms)
RSS
(kΩ)
DELAY TIME
(ms)
RAMP TIME
(ms)
UVLO
(V)
X
Disabled
False
5
LOW
5
2
4.5
Disabled
Enabled
False
5
Disabled
X
True
10
Enabled
Disabled
True
15
Enabled
Enabled
X
15
OPEN
5
5
HIGH
10
10
10
5
2
11
5
5
12.1
10
13.3
20
14.7
5
16.2
10
17.8
20
19.6
5
21.5
10
23.7
5
26.1
10
28.7
20
31.6
5
34.8
10
38.3
20
42.2
5
46.4
10
51.1
5
56.2
10
61.9
20
68.1
5
75
10
82.5
20
3
Power-Good
10
2
4.5
A PG delay period is defined as the time when all conditions
within the ZL9010M for asserting PG are met, to when the PG pin
is actually asserted. This feature is commonly used instead of
using an external reset controller to control external digital logic.
5
By default, the ZL9010M PG delay is set to 1ms, and may be
changed using the I2C/PMbus as described in Application Note
AN2033.
10
2
5
10
17
The ZL9010M provides a Power-Good (PG) signal that indicates
the output voltage is within a specified tolerance of its target
level and no fault condition exists. By default, the PG pin asserts
if the output is within +15/-10% of the target voltage. These
limits and the polarity of the pin may be changed via the
I2C/PMbus interface. See Application Note AN2033 for details.
10.8
By default, the ZL9010M PG delay is set equal to the soft-start
ramp time setting. Therefore, if the soft-start ramp time is set to
6ms, the PG delay is set to 6ms. The PG delay may be set
independently of the soft-start ramp using the I2C/PMbus as
described in Application Note AN2033.
If Auto Comp is enabled, the PG timing is further controlled by
the PG Assert parameter, as described in “Loop Compensation”
on page 18.
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ZL9010M
Switching Frequency and PLL
SYNC SETTING VIA I2C CONSIDERATION
The ZL9010M incorporates an internal phase-locked loop (PLL)
to clock the internal circuitry. The PLL can be driven by an
external clock source connected to the SYNC pin. When using the
internal oscillator, the SYNC pin can be configured as a clock
source for other Zilker Labs devices. With the FC0 pin, the SYNC
pin can be configured as input, Auto detect, and Output. Pinstrap
resistor setting to “input” mode is applicable for member devices
used in current sharing mode only.
The switching frequency can be set to any value between 300kHz
and 1.0MHz using the I2C/PMbus interface. The available
frequencies below 1.0MHz are defined by fSW = 8MHz/N, where the
whole number N is 8 ≤ N ≤ 27. See Application Note AN2033 for
details.
When multiple modules are used together, connecting the SYNC
pins together will force all devices to synchronize with each other.
One device must set its SYNC pin as an output and the remaining
devices must have their SYNC pins set as Auto Detect.
SYNC AUTO DETECT
In Auto Detect mode, the module will check for a clock signal on
the SYNC pin immediately after power-up. In this case, the
incoming clock signal must be in the range of 300kHz to 1.0MHz
and must be stable within 10µs after V25 rises above 2.25V. If
the device is in Low Power Mode, it will check for a clock signal
on the SYNC pin immediately after EN goes true. In this case, the
incoming clock signal must be in range and stable before EN
goes true. If a clock signal is present, the ZL9010M's oscillator
will then synchronize with the rising edge of the external clock.
If no incoming clock signal is present, the ZL9010M will
configure the switching frequency according to an external
resistor, RSYNC, connected between SYNC and SGND using Table 8,
given that FC0 used pin-strap or has a resistor RFC0 in the range of
10 to 13.3kΩ. When FC0 is OPEN, or used with resistor settings in
the range, the switching frequency of the ZL9010M is set to a
default of 615kHz. The module will only read the SYNC pin
connection during the first start-up sequence; changes to SYNC
pin connections will not affect fSW until the power (VDD) is cycled
off and on. Frequency modifications without restarting the VDD
power can disable the SYNC auto detect function.
SYNC OUTPUT
When the SYNC pin is configured as an output via I2C, the device
will run from its internal oscillator and will drive the resulting
internal oscillator signal onto the SYNC pin so other devices can
be synchronized to it. The SYNC pin will not be checked for an
incoming clock signal while in this mode.
When FC0 is used with resistor settings in the range of
14.7 to 31.6kΩ, the ZL9010M drives the SYNC pin with frequency
as described in Table 9, and will ignore any resistor settings on
SYNC pin. Similarly, when FC0 is used with selected value of
resistors in the range of 46.4-178kΩ, the ZL9010M operates in
current sharing mode with the SYNC pin providing clock out.
When FC0 is used with resistor settings in the range of
34.8 to 42.2kΩ, the ZL9010M will first read the SYNC pin
connection, and drives the SYNC pin with the frequency
described in Table 8. In this mode, the SYNC pin should not be
pin strapped to LOW or HIGH (voltage source). It is recommended
to connect a buffer with high impedance, as seen by the SYNC
pin of the module providing the clock out, to subsequently drive
the SYNC pin of other devices.
If a value other than fSW = 8MHz/N is entered using a PMBus
command, the internal circuitry will select the valid switching
frequency value that is closest to the entered value. For example,
if 810kHz is entered, the device will select 800kHz (N = 10).
TABLE 8. SWITCHING FREQUENCY PIN-STRAP/RESISTOR SETTINGS
SYNC PIN/
RSYNC (kΩ)
fSW
(kHz)
SYNC PIN/
RSYNC (kΩ)
LOW
400
23.7
471
OPEN
615
26.1
533
HIGH
800
28.7
571
14.7
296
31.6
615
16.2
320
34.8
727
17.8
364
38.3
800
19.6
400
46.4
889
21.5
421
51.1
1000
fSW
(kHz)
Loop Compensation
The ZL9010M operates as a voltage-mode synchronous buck
controller with a fixed frequency PWM scheme. The module is
internally compensated via the I2C/PMbus interface. The auto
compensation feature measures the characteristics of the power
train and calculates the proper tap coefficients, and can be
configured according to an external resistor, RFC0, connected
between FC0 and SGND in Table 9.
If the device is configured to store auto comp values, the
calculated compensation values will be saved in the Auto Comp
Store and may be read back through the PID_TAPS command. If
repeat mode is enabled, the first Auto Comp results after the first
ramp will be stored; the values calculated periodically are not
stored in the Auto Comp Store. When compensation values are
saved in the Auto Comp Store, the device will use those
compensation values on subsequent ramps. In repeat mode, the
latest Auto Comp results will always be used during operation.
Stored Auto Comp results can only be cleared by disabling Auto
Comp Store, which is not permitted while the output is enabled.
However, sending the AUTOCOMP_CONTROL command while
enabled in Store mode will cause the next results to be stored,
overwriting previously stored values. If auto compensation is
disabled, the device will use the compensation parameters that
are stored in the DEFAULT_STORE or USER_STORE.
If the PG Assert parameter is set to "Use PG Delay," PG will be
asserted according to the POWER_GOOD_DELAY command,
after which Auto Comp will begin. When Auto Comp is enabled,
the user must not program a Power-Good Delay that will expire
before the ramp is finished. If PG Assert is set to "After Auto
Comp," PG will be asserted immediately after the first Auto
Comp cycle completes (POWER_GOOD_DELAY will be ignored).
The routine can be set via the I2C/PMbus interface to execute
one time after ramp or periodically while regulating, and have
18
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ZL9010M
either PG Assert behavior described earlier. Note that the Auto
Compensation feature requires a minimum tON_DELAY as
described in “Soft-start Delay and Ramp Times” on page 17.
The Auto Comp Gain control scales the Auto Comp results to
allow a trade-off between transient response and steady-state
duty cycle jitter. A setting of 100% will provide the fastest
transient response while a setting of 10% will produce the lowest
jitter.
With resistor settings, auto compensation can only be set to
execute one time after ramp with option to store auto comp
values. With auto compensation disabled, PG is asserted
according to POWER_GOOD_DELAY. With auto compensation
executed once and auto comp values not stored, PG is asserted
after auto compensation is complete at every start-up event.
With auto compensation executed once and auto comp values
stored, PG is asserted after auto compensation is complete at
the first start-up event, and is asserted according to
POWER_GOOD_DELAY for subsequent start-up event along with
using the stored auto comp values from the first start-up. By
default with FC0 OPEN, auto compensation is configured to
execute one time after ramp with 70% Auto Comp Gain, PG
asserted immediately after the first Auto Comp cycle completes,
and auto comp values not stored.
Note that if Auto Comp is enabled, for best results VIN must be
stable before Auto Comp begins, as shown in Equation 3.
ΔVin
100%
--------------------- ( in% ) ≤ --------------------------------------Vin Nom
256 • Vout
---------------------------1+
Vin Nom
(EQ. 3)
The auto compensation function can also be configured via the
AUTO_COMP_CONFIG command and controlled using the
AUTO_COMP_CONTROL command over the I2C/PMbus interface.
Please refer to Application Note AN2033 for further details.
TABLE 9. FC0 PIN-STRAP/RESISTOR SETTINGS
LOW
OPEN
HIGH
12.1
13.3
SYNC PIN
CONFIG
SYNC
OVERRIDE
Auto Comp Disabled
Single
10
11
STORE
VALUES
70
50
Single
90
Not Stored
Auto Detect
Store in Flash
Not Stored
Store in Flash
AC
FC0 PIN/ SINGLE/
RFC0 (kΩ) DISABLE AC GAIN
14.7
19.6
26.1
70
34.8
400kHz
Store in Flash
615kHz
Not Stored
Single
70
Store in Flash
Auto Comp Disabled
800kHz
Not Stored
Single
70
Store in Flash
Auto Comp Disabled
38.3
42.2
Output
Auto Comp Disabled
28.7
31.6
SYNC
OVERRIDE
Not Stored
Single
21.5
23.7
SYNC PIN
CONFIG
Auto Comp Disabled
16.2
17.8
STORE
VALUES
Not Stored
Single
70
Depend on
RSYNC
Store in Flash
Adaptive Diode Emulation
Adaptive diode emulation mode turns off the low-side FET gate
drive at low load currents to prevent the inductor current from
going negative, reducing the energy losses and increasing overall
efficiency. Diode emulation is available to single-phase devices
only.
Note: the overall bandwidth of the device may be reduced when
in diode emulation mode. Disabling the diode emulation prior to
applying significant load steps is recommended.
The input undervoltage lockout (UVLO) prevents the ZL9010M
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range.
The UVLO threshold (VUVLO) can be set between 2.85V and 16V
using the I2C/PMbus interface.
Once an input undervoltage fault condition occurs, the device
can respond in a number of ways, as follows:
1. Continue operating without interruption.
Not Stored
Store in Flash
AUTOCOMP CONFIG
Input Undervoltage Lockout
AUTOCOMP CONFIG
AC
FC0 PIN/ SINGLE/
RFC0 (kΩ) DISABLE AC GAIN
TABLE 9. FC0 PIN-STRAP/RESISTOR SETTINGS (Continued)
Auto Detect
2. Continue operating for a given delay period, followed by
shutdown if the fault still exists. The device remains in
shutdown until instructed to restart.
3. Initiate an immediate shutdown until the fault is cleared. The
user can select a specific number of retry attempts.
The default response from a UVLO fault is an immediate
shutdown of the module. The controller continuously checks for
the presence of the fault condition. If the fault condition is no
longer present, the ZL9010M is re-enabled.
Please refer to Application Note AN2033 for details on how to
configure the UVLO threshold or to select specific UVLO fault
response options via the I2C/PMbus interface.
19
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ZL9010M
Output Overvoltage Protection
The ZL9010M offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at the FB+ pin) to a threshold set to 15% higher
than the target output voltage (the default setting). If the FB+
voltage exceeds this threshold, the PG pin de-asserts, and the
controller can then respond in a number of ways, as follows:
that has been selected. See “Output Overvoltage Protection” on
page 20 for response options due to an overvoltage condition.
Note that pre-bias protection is not offered for current sharing
groups that also have tracking enabled. VDD must be the same
voltage as VIN for proper prebias start-up in single module
operation.
1. Initiate an immediate shutdown until the fault is cleared. The
user can select a specific number of retry attempts.
2. Turn off the high-side and the low-side MOSFETs until the
device attempts a restart.
The default response from an overvoltage fault is to immediately
shut down. The controller continuously checks for the presence
of the fault condition, and when the fault condition no longer
exists, the device is re-enabled.
For continuous overvoltage protection when operating from an
external clock, the only allowed response is an immediate
shutdown.
Please refer to Application Note AN2033 for details on how to
select specific overvoltage fault response options via I2C/PMbus.
Output Pre-Bias Protection
An output pre-bias condition exists when an externally applied
voltage is present on a power supply’s output before the power
supply’s control IC is enabled. Certain applications require that
the converter not be allowed to sink current during start-up if a
pre-bias condition exists at the output. The ZL9010M provides
pre-bias protection by sampling the output voltage prior to
initiating an output ramp.
If a pre-bias voltage lower than the target voltage exists after the
pre-configured delay period has expired, the target voltage is set
to match the existing pre-bias voltage, and both drivers are
enabled. The output voltage is then ramped to the final
regulation value at the preconfigured ramp rate.
The actual time the output takes to ramp from the pre-bias
voltage to the target voltage varies, depending on the pre-bias
voltage, but the total time elapsed from when the delay period
expires and when the output reaches its target value, will match
the pre-configured ramp time (see Figure 21).
If a pre-bias voltage higher than the target voltage exists after the
pre-configured delay period has expired, the target voltage is set
to match the existing pre-bias voltage, and both drivers are
enabled with a PWM duty cycle that would ideally create the
pre-bias voltage.
Once the pre-configured soft-start ramp period has expired, the
PG pin is asserted (assuming the pre-bias voltage is not higher
than the overvoltage limit). The PWM then adjusts its duty cycle
to match the original target voltage, and the output ramps down
to the preconfigured output voltage.
If a pre-bias voltage higher than the overvoltage limit exists, the
device does not initiate a turn-on sequence and declares an
overvoltage fault condition to exist. In this case, the device
responds based on the output overvoltage fault response method
20
FIGURE 21. OUTPUT RESPONSES TO PRE-BIAS VOLTAGES
Output Overcurrent Protection
The ZL9010M can protect the power supply from damage if the
output is shorted to ground or if an overload condition is imposed
on the output. The following overcurrent protection response
options are available:
1. Initiate a shutdown and attempt to restart an infinite number
of times with a preset delay period between attempts.
2. Initiate a shutdown and attempt to restart a preset number of
times with a preset delay period between attempts.
3. Continue operating for a given delay period, followed by
shutdown if the fault still exists.
4. Continue operating through the fault (this could result in
permanent damage to the power supply).
5. Initiate an immediate shutdown.
The default response from an overcurrent fault is an immediate
shutdown of the controller. The controller continuously checks for
the presence of the fault condition, and if the fault condition no
longer exists, the device is re-enabled.
Please refer to Application Note AN2033 for details on how to
select specific overcurrent fault response options via I2C/PMbus.
FN8422.0
March 5, 2013
ZL9010M
Thermal Overload Protection
The ZL9010M includes a thermal sensor that continuously
measures the internal temperature of the module and shuts
down the controller when the temperature exceeds the preset
limit. The default temperature limit is set to +125°C in the
factory, but the user may set the limit to a different value if
desired. See Application Note AN2033 for details. Note that
setting a higher thermal limit via the I2C/PMbus interface may
result in permanent damage to the controller. Once the module
has been disabled due to an internal temperature fault, the user
may select one of several fault response options as follows:
1. Initiate a shutdown and attempt to restart an infinite number
of times with a preset delay period between attempts.
2. Initiate a shutdown and attempt to restart a preset number of
times with a preset delay period between attempts.
3. Continue operating for a given delay period, followed by
shutdown if the fault still exists.
4. Continue operating through the fault (this could result in
permanent damage to the power supply).
5. Initiate an immediate shutdown.
If the user has configured the module to restart, the controller
waits the preset delay period (if configured to do so) and then
checks the module temperature. If the temperature has dropped
below a threshold that is approximately +15°C lower than the
selected temperature fault limit, the controller attempts to
re-start. If the temperature still exceeds the fault limit, the
controller waits the preset delay period and retries again.
The default response from a temperature fault is an immediate
shutdown of the module. The controller continuously checks for
the fault condition, and once the fault has cleared, the ZL9010M
is re-enabled.
Please refer to Application Note AN2033 for details on how to
select specific temperature fault response options via I2C/PMbus.
Voltage Tracking
Numerous high performance systems place stringent demands
on the order in which the power supply voltages are turned on.
This is particularly true when powering FPGAs, ASICs, and other
advanced processor devices that require multiple supply voltages
to power a single die. In most cases, the I/O interface operates at
a higher voltage than the core and therefore the core supply
voltage must not exceed the I/O supply voltage according to the
manufacturers' specifications. Voltage tracking protects these
sensitive ICs by limiting the differential voltage between multiple
power supplies during the power-up and power down sequence.
The ZL9010M integrates a lossless tracking scheme that allows
its output to track a voltage that is applied to the VTRK pin with
no external components required. The VTRK pin is an analog
input that, when tracking mode is enabled, configures the
voltage applied to the VTRK pin to act as a reference for the
device’s output regulation. Figure 22 illustrates the typical
connection of two tracking modules.
The ZL9010M offers two modes of tracking as follows, and can
be configured according to an external resistor, RSS, connected
between SS and SGND in Table 10 or via I2C/PMbus. The
tON_DELAY time is set to 5ms, and tOFF_DELAY time is set to
21
35ms. The RAMP time is set to 2ms, but can track to a slower
RAMP time, i.e., >2ms.
TABLE 10. TRACKING RESISTOR SETTINGS
RSS
(kΩ)
TRACK RATIO
(%)
90.9
100
100
147
178
Limited by target Output does not decrease
before PG
Limited by VTRK Output does not decrease
before PG
121
162
RAMP-UP/DOWN BEHAVIOR
Output always follows VTRK
110
133
UPPER TRACK
LIMIT
Output always follows VTRK
50
Limited by target Output does not decrease
before PG
Output always follows VTRK
Limited by VTRK Output does not decrease
before PG
Output always follows VTRK
1. Coincident. This mode configures the module to ramp its
output voltage at the same rate as the voltage applied to the
VTRK pin. Two options are available for this mode:
- Track at 100% VOUT limited. Member rail tracks the
reference rail and stops when the member reaches its target
voltage (Figure 23A).
- Track at 100% VTRK limited. Member rail tracks the
reference at the instantaneous voltage value applied to the
VTRK pin (Figure 23B).
2. Ratiometric. This mode configures the module to ramp its
output voltage at a rate that is a percentage of the voltage
applied to the VTRK pin. The default setting is 50%, but an
external resistor string may be used to configure a different
tracking ratio:
- Track at 50% VOUT limited. Member rail tracks the reference
rail and stops when the member reaches 50% of the target
voltage (Figure 24A).
- Track at 50% VTRK limited. Member rail tracks the
reference at the instantaneous voltage value applied to the
VTRK pin until the member rail reaches 50% of the
reference rail voltage, or if the member is configured to less
than 50% of the reference the member will achieve its
configured target (Figure 24B).
The master module device in a tracking group is defined as the
device that has the highest target output voltage within the
group. This master device will control the ramp rate of all
tracking devices and is not configured for tracking mode. A delay
of at least 6ms must be configured into the master device, and
the user may also configure a specific ramp rate. Any device that
is configured for tracking mode will ignore its soft-start delay and
its output will take on the turn-on/turn-off characteristics of the
reference voltage present at the VTRK pin. All of the ENABLE pins
in the tracking group must be connected together and driven by a
single logic source. Tracking is configured via the I2C/PMbus
interface by using the TRACK_CONFIG PMBus command. Please
refer to Application Note AN2033 for further details on
configuring tracking mode using PMBus.
FN8422.0
March 5, 2013
ZL9010M
Tracking Groups
VOUT_R
SDA
VOUT_M
SCL
ZL
SDA
VOUT
REFERENCE
VTRK
COUT R
SCL
ZL
COUT M
MEMBER
FIGURE 22. PMBus TRACKING CONFIGURATION
tON_DLY(REF) > tON_DLY(MEM) + tON_RISE(REF)
+ 5ms > tON_DLY(MEM) + 6ms
Ton Dly
0
~~
Coincident Tracking
Track @ 100% Vout Limited
Vref > Vmem VRef
Vmem
Toff Dly
Vref=1.8V
Vmem=0.9V
Track @ 100% Vtrk Limited
Vref = Vmem VRef
~
EN
A.
0
Vmem
Toff Dly
Ton Dly
Vref=1.8V
Vmem=1.8V
EN
FIGURE 23. COINCIDENT TRACKING
This delay allows the member device(s) to prepare their control
loops for tracking following the assertion of ENABLE.
The member device Time-Off Delay has been redefined to
describe the time that the VTRK pin will follow the reference
voltage after enable is de-asserted. The delay setting sets the
timeout for the member's output voltage to turn off in the event
that the reference output voltage does not achieve zero volts.
The member device(s) must have a minimum Time-Off Delay of
as shown in Equation 5:
~~
Ton Dly
Vmem
Vref=1.8V
Vmem=0.9V
Toff Dly
EN
The configuration settings for Figures 23 and 24 are shown in
Tables 11 through 14. In each case the reference and member
rise times are set to the same value.
TABLE 11. TRACKING CONFIGURATION FIGURE 23A
RAIL
Ton Dly
~~
A.
Track @ 50% Vtrk Limited
Vref = 1.8V
Vref
Vmem = 0.9V
VOUT tON DLY tON RISE tOFF DLY tOFF FALL
(V)
(ms)
(ms)
(ms)
(ms)
Reference 1.8
Vmem
Toff Dly
Member
Vref=1.8V
Vmem=0.9V
EN
B.
0.9
When the ZL9010M is configured to the voltage tracking mode,
the voltage applied to the VTRK pin acts as a reference for the
member device(s) output regulation. When the Auto
Compensation algorithm is used the soft-start values (Rise/Fall
times) are used to calculate the loop gain used during the
turn-on/turn-off ramps. If current sharing is used, constrain the
rise/fall time between 5 and 20ms to ensure current sharing
while ramping.
5
5
5
Tracking Disabled
5
5
15
5
100% VOUT Limited
VOUT tON DLY tON RISE tOFF DLY tOFF FALL
(V)
(ms)
(ms)
(ms)
(ms)
Reference 1.8
FIGURE 24. RATIOMETRIC TRACKING
MODE
15
TABLE 12. TRACKING CONFIGURATION FIGURE 23B
RAIL
Member
1.8
MODE
15
5
5
5
Tracking Disabled
5
5
15
5
100% V TRK Limited
TABLE 13. TRACKING CONFIGURATION FIGURE 24A
RAIL
VOUT tON DLY tON RISE tOFF DLY tOFF FALL
(V)
(ms)
(ms)
(ms)
(ms)
Reference 1.8
Member
0.9
MODE
15
5
5
5
Tracking Disabled
5
5
15
5
50% VOUT Limited
TABLE 14. TRACKING CONFIGURATION FIGURE 24B
RAIL
VOUT tON DLY tON RISE tOFF DLY tOFF FALL
(V)
(ms)
(ms)
(ms)
(ms)
Reference 1.8
Member
22
(EQ. 5)
All of the ENABLE pins must be connected together and driven by
a single logic source or a PMBus Broadcast Enable command
may be used.
Ratiometric Tracking
Track @ 50% Vout Limited
Vref = 1.8V
VRef
Vmem= 0.9V
0
(EQ. 4)
tOFF_DLY(MEM) > tOFF_DLY(REF)
+ tOFF_FALL(REF) + 5ms
B.
0
In a tracking group, the device configured to the highest voltage
within the group is defined as the reference device. The device(s)
that track the reference is called member device(s). The
reference device will control the ramp delay and ramp rate of all
tracking devices and is not placed in the tracking mode. The
reference device is configured to the highest output voltage for
the group and all other device(s)’ output voltages are meant to
track and never exceed the reference device output voltage. The
reference device must be configured to have a minimum
Time-On Delay and Time-On Rise as shown in Equation 4:
1.8
MODE
15
5
5
5
Tracking Disabled
5
5
15
5
50% V TRK Limited
FN8422.0
March 5, 2013
ZL9010M
Voltage Margining
The ZL9010M offers a simple means to vary its output higher or
lower than its nominal voltage setting in order to determine
whether the load device is capable of operating over its specified
supply voltage range. The MGN command is set through the
I2C/PMbus interface.
The module’s output will be forced higher than its nominal set
point when the MGN command is set HIGH, and the output will
be forced lower than its nominal set point when the MGN
command is set LOW. Default margin limits of VNOM ±5% are
pre-loaded in the factory, but the margin limits can be modified
through the I2C/PMbus interface to as high as VNOM + 10% or as
low as 0V, where VNOM is the nominal output voltage set point
determined by the V1 pin.
The margin limits and the MGN command can both be set
individually through the I2C/PMbus interface. Additionally, the
transition rate between the nominal output voltage and either
margin limit can be configured through the I2C interface. Please
refer to Application Note AN2033 for further instructions on
modifying the margining configurations.
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to
communicate between Zilker Labs Digital-DC modules and
devices. This dedicated bus provides the communication channel
between devices for features such as sequencing, fault
spreading, and current sharing. The DDC pin on all Digital-DC
devices in an application should be connected together. A pull-up
resistor is required on the DDC bus in order to guarantee the rise
time as shown in Equation 6:
Rise Time = R PU∗ C LOAD ≈ 1μs
(EQ. 6)
where RPU is the DDC bus pull-up resistance and CLOAD is the
bus loading. The pull-up resistor may be tied to an external 3.3V
or 5V supply as long as this voltage is present prior to or during
device power-up. As a rule of thumb, each device connected to
the DDC bus presents approximately 10pF of capacitive loading,
and each inch of FR4 PCB trace introduces approximately 2pF.
The ideal design uses a central pull-up resistor that is wellmatched to the total load capacitance. The minimum pull-up
resistance should be limited to a value that enables any device to
assert the bus to a voltage that ensures a logic 0 (typically 0.8V
at the device monitoring point), given the pull-up voltage and the
pull-down current capability of the ZL9010M (nominally 4mA).
Output Sequencing
A group of Digital-DC modules or devices may be configured to
power-up in a predetermined sequence. This feature is especially
useful when powering advanced processors, FPGAs, and ASICs
that require one supply to reach its operating voltage prior to
another supply reaching its operating voltage in order to avoid
latch-up. Multi-device sequencing can be achieved by configuring
each device through the I2C/PMbus interface.
Multiple device sequencing is configured by issuing PMBus
commands to assign the preceding device in the sequencing
chain as well as the device that follows in the sequencing chain.
23
The Enable pins of all devices in a sequencing group must be tied
together and driven high to initiate a sequenced turn-on of the
group. Enable must be driven low to initiate a sequenced turnoff
of the group.
Refer to Application Note AN2033 for details on sequencing via
the I2C/PMbus interface.
Fault Spreading
Digital DC modules and devices can be configured to broadcast a
fault event over the DDC bus to the other devices in the group.
When a non-destructive fault occurs and the device is configured
to shut down on a fault, the device shuts down and broadcasts
the fault event over the DDC bus. The other devices on the DDC
bus shut down together, if configured to do so, and attempt to
re-start in their prescribed order, if configured to do so.
Monitoring via I2C/PMbus
A system controller can monitor a wide variety of different
ZL9010M system parameters through the I2C/PMbus interface.
The device can monitor for fault conditions by monitoring the
SALRT pin, which will be pulled low when any number of
pre-configured fault conditions occur.
The module can be monitored continuously for any number of
power conversion parameters including the following:
• Input voltage
• Output voltage
• Output current
• Internal temperature
• External temperature
• Switching frequency
• Duty cycle
The PMBus host should respond to SALRT as follows:
1. ZL device pulls SALRT low.
2. PMBus host detects that SALRT is now low, performs
transmission with Alert Response Address to find which ZL
device is pulling SALRT low.
3. PMBus host talks to the ZL device that has pulled SALRT low.
The actions that the host performs are up to the system
designer.
If multiple devices are faulting, SALRT will still be low after doing
the above steps and will require transmission with the Alert
Response Address repeatedly until all faults are cleared.
Please refer to Application Note AN2033 for details on how to
monitor specific parameters via the I2C/PMbus interface.
Temperature Monitoring Using the XTEMP Pin
The ZL9010M supports measurement of an external device
temperature using either a thermal diode integrated in a
processor, FPGA or ASIC, or using a discrete diode-connected
2N3904 NPN transistor. Figure 25 illustrates the typical
connections required.
FN8422.0
March 5, 2013
ZL9010M
Non-Volatile Memory and Device Security
Features
XTEMP
100 pF
ZL
2N3904
SGND
Discrete NPN
XTEMP
100pF
ZL
SGND
µP
FPGA
DSP
ASIC
Embedded Thermal Diode
FIGURE 25. EXTERNAL TEMPERATURE MONITORING
SnapShot Parameter Capture
The ZL9010M offers a special feature that enables the user to
capture parametric data during normal operation or following a
fault. The SnapShot functionality is enabled by setting bit 1 of
MISC_CONFIG to 1.
See AN2033 for details on using SnapShot in addition to the
parameters supported. The SnapShot feature enables the user to
read parameters via a block read transfer through the PMbus.
This can be done during normal operation, although it should be
noted that reading the 22 bytes occupies the PMbus for some
time.
The SNAPSHOT_CONTROL command enables the user to store
the SnapShot parameters to Flash memory in response to a
pending fault, as well as to read the stored data from Flash
memory after a fault has occurred. Table 15 describes the usage
of this command. Automatic writes to Flash memory following a
fault are triggered when any fault threshold level is exceeded,
provided that the specific fault’s response is to shut down
(writing to Flash memory is not allowed if the device is configured
to re-try following the specific fault condition).
It should also be noted that the module’s VDD voltage must be
maintained during the time when the controller is writing the
data to Flash memory; a process that requires between 700µs to
1400µs depending on whether the data is set up for a block
write. Undesirable results may be observed if the device’s VDD
supply drops below 3.0V during this process.
TABLE 15. SNAPSHOT_CONTROL COMMAND
DATA
VALUE
DESCRIPTION
1
Copies current SNAPSHOT values from Flash memory to
RAM for immediate access using SNAPSHOT command.
2
Writes current SNAPSHOT values to Flash memory. Only
available when device is disabled.
If the module experiences a fault and power is lost, the user can
extract the last SnapShot parameters stored during the fault by
writing a 1 to SNAPSHOT_CONTROL (transfers data from Flash
memory to RAM) and then issuing a SNAPSHOT command (reads
data from RAM via PMbus).
24
The ZL9010M has internal non-volatile memory where user
configurations are stored. Integrated security measures ensure
that the user can only restore the module to a level that has been
made available to them.
During the initialization process, the ZL9010M checks for stored
values contained in its internal non-volatile memory. The
ZL9010M offers two internal memory storage units that are
accessible by the user as follows:
1. Default Store: The ZL9010M has a default configuration that is
stored in the default store in the controller. The module can be
restored to its default settings by issuing a
RESTORE_DEFAULT_ALL command over the PMbus.
2. User Store: The user can modify certain power supply settings
as described in this data sheet. The user stores their
configuration in the user store.
Please refer to Application Note AN2033 for details on how to set
specific security measures via the I2C/PMbus interface.
Layout Guide
To achieve stable operation, low losses, and good thermal
performance some layout considerations are necessary
(Figure 26).
• Establish a continuous ground plane connecting DGND pin and
PGND pin F10 with via directly the ground plane.
• Establish SGND island connecting (pad 3, pin C1) and the
return path of analog signals and resistor programming pin
signals
• Establish PGND island connecting PGND (pad 2, 5, pin F10).
• Make a single point connection between SGND and PGND
islands.
• Place a high frequency ceramic capacitor between (1) VIN and
PGND (pad 2) (2) VOUT and PGND (pad 5) as close to the
module as possible to minimize high frequency noise. High
frequency ceramic capacitors close to the module between
VOUT and PGND will help to minimize noise at the output
ripple.
• Use large copper areas for power path (VIN, PGND, VOUT, SW)
to minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers.
• Connect remote sensed traces FB+ and FB- to the regulation
point to achieve a tight output voltage regulation, and keep
them in parallel. Route a trace from FB- to a location near the
load ground, and a trace from FB+ to the point-of-load where
the tight output voltage is desired.
• Avoid routing any sensitive signal traces, such as the VOUT,
FB+, FB- sensing point near the SW pad.
FN8422.0
March 5, 2013
ZL9010M
size of 17.2mm x 11.45mm x 2.5mm. Figure 27 shows typical
reflow profile parameters. These guidelines are general design
rules. Users could modify parameters according to their
application.
PGND
VIN
SGND
DGND
The bottom of the ZL9010M is a lead-frame footprint, which is
attached to the PCB by surface mounting process. The PCB
layout pattern is shown in the Package Outline Drawing
Y32.17.2x11.45 on page 27. The PCB layout pattern is
essentially 1:1 with the HDA exposed pad and I/O termination
dimensions. The thermal lands on the PCB layout should match
1:1 with the package exposed die pads.
SW
VR
FB-
FB+
PGND
SGND
VOUT
Thermal Vias
KELVIN SENSING LINES
PGND
SGND
PCB Layout Pattern Design
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under the
thermal land. The vias should be about 0.3mm to 0.33mm in
diameter with the barrel plated to about 1.0 ounce copper. Although
adding more vias (by decreasing via pitch) will improve the thermal
performance, diminishing returns will be seen as more and more
vias are added. Simply use as many vias as practical for the thermal
land size and your board design rules allow.
PGND
Stencil Pattern Design
FIGURE 26. RECOMMENDED LAYOUT
Thermal Considerations
Experimental power loss curves along with θJA from thermal
modeling analysis can be used to evaluate the thermal
consideration for the module. The derating curves are derived
from the maximum power allowed while maintaining the
temperature below the maximum junction temperature of
+125°C. In actual application, other heat sources and design
margin should be considered.
Package Description
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joins. Stencil aperture size to land size ratio should
typically be 1:1. The aperture width may be reduced slightly to help
prevent solder bridging between adjacent I/O lands. To reduce
solder paste volume on the larger thermal lands, it is
recommended that an array of smaller apertures be used instead
of one large aperture. It is recommended that the stencil printing
area cover 50% to 80% of the PCB layout pattern. A typical solder
stencil pattern is shown in the Package Outline Drawing
Y32.17.2x11.45 on page 27. The gap width pad to pad is 0.6mm.
The user should consider the symmetry of the whole stencil
pattern when designing its pads. A laser cut, stainless steel stencil
with electropolished trapezoidal walls is recommended.
Electropolishing “smooths” the aperture walls resulting in reduced
surface friction and better paste release which reduces voids.
Using a trapezoidal section aperture (TSA) also promotes paste
release and forms a "brick like" paste deposit that assists in firm
component placement. A 0.1mm to 0.15mm stencil thickness is
recommended for this large pitch (1.3mm) HDA.
The structure of ZL9010M belongs to the High Density Array (HDA)
package. This kind of package has advantages, such as good
thermal and electrical conductivity, low weight and small size. The
HDA package is applicable for surface mounting technology. The
ZL9010M contains several types of devices, including resistors,
capacitors, inductors and control ICs. The ZL9010M is a copper
lead-frame based package with exposed copper thermal pads,
which have good electrical and thermal conductivity. The copper
lead frame and multi component assembly is overmolded with
polymer mold compound to protect these devices.
The package outline and typical PCB layout pattern design and
typical stencil pattern design are shown in the package outline
drawing Y32.17.2x11.45 on page 27. The module has a small
25
FN8422.0
March 5, 2013
ZL9010M
Reflow Parameters
300
PEAK TEMPERATURE ~+245°C;
TYPICALLY 60s-150s ABOVE +217°C
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
250
TEMPERATURE (°C)
Due to the low mount height of the HDA, "No Clean" Type 3 solder
paste per ANSI/J-STD-005 is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board, so it
is not practical to define a specific soldering profile just for the
HDA. The profile given in Figure 27 is provided as a guideline, to
be customized for varying manufacturing practices and
applications.
200
SLOW RAMP (3°C/s MAX)
AND SOAK FROM +150°C
TO +200°C FOR 60s~180s
150
100
RAMP RATE ≤1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 27. TYPICAL REFLOW PROFILE
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
March 5, 2013
FN8422.0
CHANGE
Initial Release
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26
FN8422.0
March 5, 2013
Package Outline Drawing
Y32.17.2x11.45
32 I/O 17.2mm x 11.45mm x 2.5mm HDA MODULE
Rev 1, 11/12
PIN A1 INDICATOR
C = 0.35
7.00
DATUM A
17.20
A
TERMINAL #A1
INDEX AREA
B
SEE DETAIL B
0.10
A
B
C
D
E
F 10.00
G
H
J
K
L
C AB
27
10.40±0.15
11.45
0.10 C 2X
16.50±0.15
0.10
C AB
0.10 C 2X
TOP VIEW
SEE DETAIL A
10 9 8 7 6 5 4 3 2 1
0.90±0.10
DATUM B
BOTTOM VIEW
ZL9010M
1.00
0.18±0.10
2.50 MAX
0.10 C
0.08 C
1.00
SEATING PLANE
0.025 MAX
SIDE VIEW
C
3
0.10 C A B
0.05 C
27x(0.60±0.05)
0.55±0.10
NOTES:
1.
All dimensions are in millimeters.
2.
1.0mmx1.0mm represents the basic land grid pitch.
3.
“27” is the total number of I/O (excluding large pads).
All 27 I/O’s are centered in a fixed row and column
matrix at 1.0mm pitch BSC.
4.
Dimensioning and tolerancing per ASME Y14.5M-1994.
5.
Tolerance for exposed DAP edge location dimension on
page 2 is ±0.1mm.
2.00
0.55±0.10
3
DETAIL B
27x(0.60±0.05)
1.00
FN8422.0
March 5, 2013
TERMINAL TIP
0.95
±0.10
DETAIL A
28
7.95
4.75
0.60
2.00
3.20
4.80
0.38
4.35
5.45
1.30
3.30
5.40
7.60
3.87
4.60
1.85
3.88
1.48
0.46
6
3.20
7
CENTERLINE POSITION DETAILS FOR THE 5 EXPOSED DAPS
SIZE DETAILS FOR THE 5 EXPOSED DAPS
BOTTOM VIEW
BOTTOM VIEW
a
NOTES:
6. Shown centerline measurement of 0.46mm applies to ZL9006M module. For the ZL9010M module, this measurement is 0.33mm. All other measures identical for both the ZL9006M and ZL9010M modules.
7. Shown pad edge measurement of 3.87mm applies to ZL9006M module. For the ZL9010M module, this measurement is 3.60mm. All other measurements are identical for both the ZL9006M and ZL9010M
modules.
ZL9010M
4.20
4.38
1.80
4.00
FN8422.0
March 5, 2013
8.60
8.35
7.75
7.35
6.75
6.35
5.75
5.35
4.75
4.35
3.75
3.35
2.75
2.35
1.75
1.35
0.75
0.00
2.75
6.75
6.95
7.65
8.25
8.60
29
5.73
5.28
3.48
2.48
1.48
1.23
0.48
0.00
0.13
1.53
1.98
8 2.39
3.28
5.13
5.73
8.35
7.75
7.35
6.75
5.95
5.75
5.35
4.75
3.35
2.75
2.35
1.75
1.35
0.75
0.35
0.00
0.25
0.65
1.25
2.75
2.95
6.25
8.15
TERMINAL AND PAD EDGE DETAILS
BOTTOM VIEW
NOTES:
8. Shown edge pad measurement of 2.39mm applies to ZL9006M module. For the ZL9010M module, this measurement is 2.13mm. All other measurements are identical for both the ZL9006M & ZL9010M
modules.
ZL9010M
5.48
4.88
4.48
3.88
3.48
2.88
2.48
1.88
1.48
0.88
0.48
0.00
0.13
0.53
1.13
1.53
2.13
2.53
3.13
3.53
4.13
4.53
5.13
FN8422.0
March 5, 2013
5.10
5.40
5.60
6.10
6.60
7.05
7.75
8.15
8.60
3.90 4.10
2.90
1.34
0.77
0.34
0.00
0.23
0.66
1.23
1.77
3.34
2.34
2.77
4.34
3.77
5.34
4.77
6.34
5.77
7.34
4.54
4.97
5.73
8.00
8.60
7.10
7.30
1.53
2.39
3.28
5.13
5.73
PCB LAND PATTERN (FOR REFERENCE)
STENCIL OPENING EDGE POSITION (FOR REFERENCE)
TOP VIEW
TOP VIEW
8.15
5.30
6.00
0.48
0.00
0.13
6.25
5.10
1.97
1.48
2.95
2.75
6.20
0.43
2.48
1.25
0.65
0.25
0.00
0.35
0.75
1.35
1.75
2.35
2.75
3.35
8.34
1.38
3.48
4.75
5.35
5.75 5.95
6.35
6.75
7.35
7.75
8.35
4.00
4.90
5.73
8.60
5.11
3.42
3.54
2.90
4.11
3.10
3.80
3.11
2.46
1.46
1.02
0.46
0.22
0.11
0.98
1.54
2.11
2.54
4.27
3.75
5.73
5.28
5.48
4.88
4.48
3.88
3.48
2.88
2.48
1.88
1.48
1.22
0.88
0.48
0.00
0.13
0.53
1.13
1.98 1.53
2.13
2.53
3.13
3.53
4.13
4.53
5.13
ZL9010M
0.00
0.54
1.11
1.78
6.77
8.34
0.89
7.77
8.60
1.89
3.46
7.77
7.34
6.77
6.34
5.77
5.75
5.34
4.77 4.95
4.75
3.95 3.75
3.34
2.95
2.77
2.34
1.77
1.34
0.77
2.89
4.46
8.60
8.25
7.65
6.95
6.75
3.89
5.73
5.13
4.48
3.95
3.63
2.57
2.37
1.58
1.33
0.57
0.23
0.03
0.78
0.87
1.07
5.46
2.75
4.89
0.00
0.75
1.35
1.75
2.35
2.75
3.35
3.75
4.35
4.75
5.35
5.75
6.35
6.75
7.35
7.75
8.35
8.60
30
5.73
FN8422.0
March 5, 2013