USBvisionTM II Data Decoder
ZR36505
VBI Data and Remote Control Interface for ZR6504
Data Sheet
Revision 1.00
November 1999.
Zoran reserves the right to make changes without further notice to any product herein. Zoran makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Zoran assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. Zoran products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure of the Zoran product could create a situation
where personal injur y or death may occur.
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
Table of Contents:
1.
2.
SERIAL CONTROL ............................................................................................................................ 7
VBI DATA QUALIFIER .................................................................................................................. 12
2.1
2.2
2.3
3.
4.
5.
6.
VBI Input Interface................................................................................................................................ 12
VBI Lines Qualifier................................................................................................................................. 13
VBI and IRD (Remote Control) Data Format...................................................................................... 17
Bulk Interface.......................................................................................................................................... 21
Programmable I/O Pins ....................................................................................................................... 25
Soft Reset operation ............................................................................................................................. 26
Mechanical Specification.................................................................................................................... 27
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
ZR36505 - VBI (Teletext) pipe and Remote Control interface for USB TV applications
The ZR36505 is a complimentary chip for the ZR36504 in USB TV applications. Combined with certain
video decoders, it adds a VBI (Vertical Blank Interval) data pipe to the system, which utilizes the general
purpose Bulk channel of the NT1004. The VBI is used by TV broadcast providers to send digital data
hidden in the analog video signal. One or more video lines, taken from lines 1-21 of each video field are
used for carrying this information - each line providing about 9,600 bits/sec data rate.
The ZR36505 provides the application S/W with access to data such as Teletext, Close-Caption,
Intercast, IR receiver samples, etc. It uses a 1KByte SRAM buffer to grabe the processed data from the
video decoder during the Blank Interval time slot, and sends this data to the USB through the
ZR36504 Bulk pipe during the time left prior to beginning of next Blak Interval. For the remote Control
interface, the input pin IO_1 is sampled at 4Ksamp/sec rate, and the sampled bits are moved to host
computer via the (NT1004) for S/W process.
Features
•
Enables Teletext and Close-Caption
•
Supports WST625, WST525, CC625, CC525, US NABTS, MOJI (Japanese), and JFS formats
•
Provides Remote Control interface with IR receiver (sampled at 4K samp./sec.)
•
Low Cost, Low Power, 3.3v operated
•
24-pin SOIC package
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
Product Description
Refer to Fig.1 for an internal Block Diagram of the ZR36505.
ZR36505 CHIP
from
ZR36504
Serial
Control
pins
Control Registers
IIC
Serial Interface
Status Registers
Prog.
I/O
General
purpose
I/O pins
(Remote
Control,
IRD,
etc.)
Remote Control
IR Binary Sampler
(4KHz)
from
Video
Decoder.
27MHz
VBI DATA
QUALIFIER
1KB
Buff
BULK
INTERFAC
E
to
ZR36504
Bulk pins
(0-2Mbps)
48MHz
from
ZR36504
Fig.1 ZR36505 Block Diagram
The IIC block uses the LRNACK mode of the ZR36504 serial control bus to provide
access to its internal registers. The address range for output registers and input registers is
0x00-0x07 each.
The internal Input and Output Registers are used by the Host (PC S/W via ZR36504) to
control the parameters of the ZR36505 blocks and to read their status. There are two
general I/O pins to be used by S/W for specific designs.
The VBI DATA QUALIFIER block can be programmed to restrict VBI data capture to
any specified range of lines within the video field. Also, a specific data type can be defined,
to filter out all other types of VBI data.
The 1KByte Buffer is used for capturing all VBI data from every coming video field (after
qualification), and sending it via the Bulk Interface. This is done for one field at a time, and
Write/Read cannot be done simultaneously.
The BULK INTERFACE block is designed to match the ZR36504 specification. It can
coexist with an audio Codec source to share the same clock and data pins of the NT1004.
Finally, The ZR36505 uses 2 clock sources: 27MHz for VBI data, and 48MHz (from
NT1004) for the other blocks. The ZR36505 does not require a crystal of its own.
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
Pin Assignments (Top View)
VSYNC_IN
1
24
VDD
HSYNC_IN
2
23
IICCK
3
22
IICDT
21
IO1/IRD_IN
YIN0
YIN1
4
YIN2
5
YIN3
NT1005
USBTeletextTM
20
IO2
6
19
BCLK
YIN4
7
18
FS_L
YIN5
8
17
BLK_FULL
YIN6
9
16
BLK_EN
DAT_OUT
YIN7
10
15
CLK27
11
14
GND
GND
12
13
CLK48
Table 1 - PIN DESCRIPTIONS
PIN NUMBER
SIGNAL
I/O
DESCRIPTION
24
VDD
Digital 3.3V power supply
12, 14
GND
Digital ground connection
1
VSYNC_IN
I
Video Vertical-Sync input signal from Video Deco der
2
HSYNC_IN
I
Video Vertical-Sync input signal from Video Decoder
3-10
YIN0-YIN7
I
11
CLK27
I
13
CLK48
I
15
DAT_OUT
O
16
BLK_EN
O
17
BLK_FULL
I
18
FS_L
I
VBI data-bus from Video Decoder. Usually used also for delivering
the digital video samples.
VBI clock from Video Decoder. Used to sample the VBI data in
it s positive edge. This clock is used for capturing and storing the
VBI data.
This is the ZR36505 Global clock, which comes from the
NT1004.
VBI Data Output pin, goes to DAT_IN pin of the
ZR36504(which is used for both Audio CODEC T x chan and
Bulk Data in This pin is Open Drain, and is set to high -z upon
Power-On or Soft Reset. It requires an external pull-up resistor.
Bulk Data Enable output. When set to '1', Bulk output data at
DAT_OUT pin is sampled into the ZR36504by falling edge of
BCLK .
This pin is set to Hi-Z upon Power -On or Soft Reset.
"Bulk-Fifo full" indication signal from NT1004. This signal is
normally '0', and is set to '1' when the ZR36504Bulk -Fifo is full.
Audio Codec Frame-Sync pulse for Left channel., which comes
from the NT1004. The ZR36505 uses this signal to trigger the
beginning of its VBI Bulk data output immediately after the 16th
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
bit of audio Left.
I
Bulk -data clock (ZR36504uses this clock for both Audio CODEC
and Bulk Data). This clock must be set to 2.024MHz for proper
operation with ZR36505.
SIGNAL
I/O
DESCRIPTION
20-21
IO-1/IRD_IN
IO-2
I/O
22
IICDT
I/O
23
IICCK
I
General Programmable I/O pins. Each of these 2 pins has a 5volt Tolerant Open Drain output, and it is supposed to be
connected to an external pull-up resistor. The host uses these
pins as programmable output ports by writing '0' or '1'. By writing
'1' and read back, the host can use these pins as input ports - as
this allows any external source to force the pull-up resistor.
These outputs are set to high -z upon Power-On or Soft Reset.
The pin IO-1 is also used as the input for IRD data. This pin is
internally sampled at 4KHz sampling rate.
This pin is used for sending and receiving serial control data
between the ZR36505 (slave) and ZR36504(master). It operates
in the LRNACK mode of operation (refer to the ZR36504data
sheet). This pin is Open Drain, and is set to high-z upon Power On or Soft Reset.
This pin is used as the sampling clock for sending and receiving
serial control data between the ZR36505 (slave) and
ZR36504(master). It operates in the LRNACK mode of
operation (refer to the ZR36504data sheet).
19
BCLK
Table 1 - PIN DESCRIPTIONS (continued)
PIN NUMBER
Table 2 - ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to GND)
Rating
Symbol
Value
Unit
Vdd - GND
-0.5 to 4.6
V
Voltage, any pin to GND
V
-0.5 to Vdd+0.5
V
DC Current Drain per Pin (Excluding Vdd, GND)
I
±10
mA
TA
0 to +70
T stg
-65 to +150
DC Supply Voltage
Operating Temperature Range
Storage Temperature Range
o
o
C
C
Table 3 - ELECTRICAL CHARACTERISTICS (Vdd=3.3V, TA = 0 to 70 o C)
Characteristic
Symbol
Min
Typ
Max
Unit
DC Supply Voltage (Vdd to GND)
Vdd
3.0
3.3
3.6
V
DC Supply Current (@ Vdd=3.3V)
ICC
-
12
18
High Level Input Voltage (other than XIN, CAPTRN, and
RESIN)
Low Level Input Voltage (other than XIN, CAPTRN, and
RESIN)
Input Current
Input Capacitance
November-99
VI = Vdd+0.3 or GND
mA
*
VIH
2.0
-
Vdd+0.3
V
VIL
-0.3
-
0.8
V
Iin
Cin
-10
+1
+10
µA
-
2.5
7.0
pF
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
IOZ
-10
+1
+10
µA
-
2.0
7.0
pF
High Level Output Voltage (@ Iout = -4mA)
Cout
VOH
2.4
-
Vdd
V
Low Level Output Voltage (@ Iout = 4mA)
VOL
0
-
0.4
V
3-State Output Leakage Current
VO = Vdd+0.3 or GND
Output Capacitance
1. SERIAL CONTROL
The ZR36505 uses a Serial Control Interface to access its internal registers.
Table 4 - ZR36505 Registers List:
Reg.
Reg. Name
Function
Address
0
LINE_LEN_L
d7-d0: LINE_LEN[7..0]
1
LINE_LEN_H
d2-d0: LINE_LEN[10..8]
d7-d3: reserved
2
LINE_WIN_L
d7-d0: WIN_OFFSET[7..0]
3
LINE_WIN_H
d7-d3: WIN_LEN[4..0]
d2-d1: reserved
d0: WIN_OFFSET[8]
4
VBI_REG
d7: EN_TYPE_QUALIFIER '1': enable '0': disable
d6: EN_WIN_QUALIFIER '1': enable '0': disable
d5: EN_RAW_SAMPLES '1': enable '0': disable
d4: EN_VBI_QUALIFIER '1': enable '0': disable
d3-d0: DATA_TYPE_QUALIFIER[3..0]
5
BLK_OPER_
d3: BCLK_RATE '1': 2048KHz '0': 1544KHz
MODE
d2: AUDIO_DAT '1': exists '0': does not exist
d1: AUDIO_RATE '1': 16KS/s '0': 8KS/s
d0: AUDIO_STEREO '1': stereo '0': mono
d7: BLK_IO_EN '1': En bulk output pins. '0': Disable.
d6-d4: reserved
6
IO_REG
d0: IO_1 Read/Write level of ZR36505 pin IO-1
d1: IO_2 Read/Write level of ZR36505 pin IO-2
d7-d2: reserved
7
SOFT_RESET
d0: SOFT_RESET '1' : Perform RESET
Default
Value
00H
00H
00H
00H
00H
00H
00H
00H
This reg is always read 0x00 (even after writing 0x01).
Writing 0x01 to this register will result in a general reset
operation to the ZR36505, leaving all registers in their
default values.
The serial bus consists of a clock signal and a data signal, which relate to the ZR36505 as a
bus slave (where the ZR36504 is used as the bus master).
The ZR36505 device address is 0xEE for a Write operation, and 0xEF for a Read
operation.
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
The diagram in the following page specifies general Read and Write transactions. In both
transactions the register address is auto-incremented, which requires from the host computer
to define the address of the first register only. The data bytes are then sent or received one
after the other from the first register to the last one (any number of registers is possible). A
Read transaction requires a Write sequence of 0 data bytes, in order to define the first
address register to be read.
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
Write transaction
S
0xEE
AK
Register
Addrss n
AK
DATA(n)
AK
DATA(n+1) AK
DATA(n+j) AK
P
Optional
Read transaction
S
0xEE
AK
Register
Addrss n
AK
P
S
0xEF
AK
DATA(n)
Define Register Address n
S
= START Condition
DATA
= Host Data
AK
DATA(n+1) AK
DATA(n+j) NAK P
Optional
P
= STOP Condition
DATA
= NT1005 Data
AK
AK
= Host ACK
NAK
= Host NACK
= NT1005 ACK
It is recommended to set the ZR36504(master) chip to its IIC LRNACK mode of
operation to communicate with the ZR36505.
The following waveforms and timing diagrams specify the IIC serial interface bus in the
signal level:
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
IICCK
Data is sampled on the down going edge of IICCK
x
IICDT
D7
D6
D5
D4
D3
D2
D1
D0
Start
Ack
Stop
IICCK
IICDT
Write ADDRESS
R/W Byte 1
R/W Byte N
NOTE: Start is defined when the IICDT turns from '1' to '0' while the IICCK is '1'. Stop is defined when
the IICDT turns from '0' to '1' while the IICCK is '1'. The Address byte is written like any other byte.
IICCK
IICCK
Stop
IICDT
Stop
IICDT
Ack
End of Write sequence
Nack
End of Read sequence
Start/Stop Timings
tSU:STA
tHD:STA
tSU:STO
IICCK
IICDT
Data Timings
tHIGH
tLOW
IICCK
tHD:DI
IICDT OUT
tHD:DO
Dn
tSU:DO
Dn+1
tSU:DI
IICDT IN
November-99
Data Valid
Data Valid
Page 10 of 10
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
Table 5 - SERIAL CONTROL TIMINGS
Symbol
Parameter
Min
Max
Unit
tSU:STA
START condition setup time
5300
-
ns
tHD:STA
START condition hold time
5300
-
ns
tSU:STO
STOP condition setup time
5300
-
ns
tHIGH
Clock high time
5300
-
ns
tLOW
Clock low time
5300
-
ns
tSU:DO
Data output setup time
2500
2670
ns
tHD:DO
Data output hold time
2500
2670
ns
tSU:DI
Data input setup time
20
-
ns
tHD:DI
Data input hold time
0
-
ns
Fiicck
Frequency of IICCK clock signal
0
100
KHz
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
2. VBI DATA QUALIFIER
2.1 VBI Input Interface
The ZR36505 is designed to connect to the 8-bit VBI output bus of the Video Decoder
(Philips SAA7113 in its CCIR-656 mode of operation). This bus is sampled by the rising
edge of CLK27 (27MHz clock, which is also provided by the Video Decoder chip), and
provides the processed data bytes in the Blank lines. The same bus contains the Y/U/V
video data on the valid video lines, which go directly to the NT1004.
The VBI input interface consists of the following signals:
Y_IN[7..0] ( Inputs )
This is the 8-bit VBI bus (contains also the Y/U/V samples in non-blank lines).
VSYNC_IN ( Input )
This is the negative Vertical Synchronization pulse, which indicates the start of a new video
field (Interlace mode).
HSYNC_IN ( Input )
This is the negative Horizontal Synchronization pulse, which indicates the start of a new
video line.
CLK27 ( Input )
This signal is the video pixel clock. It is used by the ZR36505 to sample all the other inputs
in the digital video interface. It is also used by all state machines and logic to capture the
VBI data into the 1Kbyte on-chip memory.
The timing of the VBI input bus, as expected by the ZR36505 is specified in the following
timing diagram:
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ZORAN Corporation
VSYNC_IN
USBvision II Data Decoder
First Line
in a field
ZR36505 Data Sheet
Last Line
in a field
HSYNC_IN
Detail
VSYNC_IN
about 64us
HSYNC_IN
CLK27
Y_IN[7..0]
xx
B0
B1
B2
B3
xx
90%
CLK_27
10%
tSU > 15ns
VSYNC_IN,
HSYNC_IN,
Y_IN[7..0]
tH > 10ns
90%
90%
VALID
10%
10%
2.2 VBI Lines Qualifier
The VBI lines are defined in the range 2-21 of the 1st and 2nd fields, but in most TV
stations not all the VBI lines are used for digital data.
The ZR36505 provides a way of restricting the search range, and filtering out the undesired
data. This allows the ZR36505 to produce smaller buffers of data to be delivered via the
USB Bulk channel, which do not interfere with the isochroneous video and audio channels.
To do this, the ZR36505 uses the following qualifiers:
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
Line Window Qualifier (Regs. 0-3):
LINE_LEN_L (Reg. 0)
D7
D6
D5
LINE_LEN_H (Reg. 1)
D7
D6
D5
resrved
resrved
resrved
LINE_WIN_L (Reg. 2)
D7
D6
D5
LINE_WIN_H (Reg. 3)
D7
D6
D5
D4
WIN_LEN[4..0]
1
2
3
4
D4
D3
LINE_LEN[7..0]
D4
resrved
D2
D3
resrved
D2
D4
D3
WIN_OFFSET[7..0]
D3
D2
resrved
D2
D1
resrved
D1
D0
D1
D0
LINE_LEN[10..8]
D1
D0
D0
WIN_OFFSET[8]
WIN_OFFSET[8..0]
WIN_LEN[4..0]
LINE_LEN[10..0]
21
23
24
last
line
The dark window represents the Line Window Qualifier. LINE_LEN[10..0] is counted
from the up-going edge of the HSYNC_IN pulse and relates to CLK27 cycles, and
WIN_OFFSET[8..0] is counted from the up-going edge of the VSYNC_IN pulse and
relates to HSYNC_IN pulses. Note that bit d6 of VBI_REG (reg.4) should be enabled:
VBI_REG (Reg. 4)
November-99
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ZORAN Corporation
D7
November-99
USBvision II Data Decoder
D6
EN_WIN_QUALIFIER
D5
D4
ZR36505 Data Sheet
D3
D2
D1
D0
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
VBI Window Qualifier:
To enable VBI Window Qualifier, bit d4 of VBI_REG (reg.4) should be set to '1'. This will
restrict data capture to those lines that are reported "VBI lines" by the video decoder.
Normally, the VBI lines are expected to be lines 2-21.
VBI_REG (Reg. 4)
D7
D6
D5
D4
EN_VBI_QUALIFIER
D3
D2
D1
D0
1
2
VBI QUALIFIER WINDOW (lines 2-21)
21
last
line
Note that if both bits d4 and d6 of VBI_REG (reg.4) are enabled, the data capture window
will consist of all lines that are common to the VBI wondow and the given Line Window.
VBI Type Qualifier:
To enable VBI Type Qualifier, bit d7 of VBI_REG (reg.4) should be set to '1', and the
desired VBI Type code should be defined in the DATA_TYPE_QUALIFIER[3..0] field
(bits d3-d0 of VBI_REG).
VBI_REG (Reg. 4)
D7
D6-D4
D3
D2
D1
D0
EN_TYPE_QUALIFIER
DATA_TYPE_QUALIFIER[3..0]
Refer to Table 6 for available VBI Data Type codes for this qualifier. Note that the same
code should be defined to the video decoder for specific lines in order to get any data that
will match this qualifier.
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
Raw Samples:
To enable Raw Samples, bit d5 of VBI_REG (reg.4) should be set to '1':
VBI_REG (Reg. 4)
D7
D6
D5
EN_RAW_SAMPLES
D4
D3
D2
D1
D0
When Raw Samples are enabled, up to 720 raw samples of a VBI line (or any other video
line) can be provided for S/W processing.
If the EN_RAW_SAMPLES bit is not set, raw samples are filtered out by default.
2.3 VBI and IRD (Remote Control) Data Format
During the Vertical Blank Time Interval, The VBI Data Qualifier stores the incoming VBI
data into the internal 1KByte SRAM. Soon after that, all binary samples from the IRD input
(IO_1) are added (about 8-12 bytes per video field). It is assumed that the total VBI data
and IRD data in a single video field never exceeds the 1KB boundary, and that all
accumulated data can be transfered via the Bulk port until the beginning of next Blank
Interval.
The data that is transfered to the host computer via the Bulk interface contains an additional
Field Synchronization Burst (which is produced after the VBI data and before the IRD
data), and is specified in the following diagrams:
November-99
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ZORAN Corporation
USBvision II Data Decoder
General VBI data
structure
ZR36505 Data Sheet
VBI data structure
for any line
Header Byte # 1: SDID
VBI Data for line #
N
Header Byte # 2: DC
VBI Data for line #
N+1
VBI Data for line #
N+2
Line
Header
bytes
Header Byte # 3: IDI1
VBI
Data
for
Video
field # i
Header Byte # 4: IDI2
Data Byte # 1
Data Byte # 2
VBI Data for line #
N+L-1
Field Synchronization
Burst
Line
received
data
bytes
Data Byte # n
16 bytes of 0x00
IRD Data (8-12 bytes)
VBI Data for line #
N
November-99
IRD Data for
Video field # i
VBI Data
for Video
field # i+1
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
The following tables specifies the Line Header bytes:
SDID
D7
'1'
D6
'0'
D5
'0'
D4
'0'
D3
'0'
D2
'1'
D1
'0'
D0
'1'
DC
D7
'1'
D6
'0'
D5
DC5
D4
DC4
D3
DC3
D2
DC2
D1
DC1
D0
DC0
DC[5:0] is the number of data bytes that were actually received in this line. Note that this
number may be different than the expected number of data bytes, due to noise or corruption
in the received analog signal.
DC[5:0]='000000' means that no data bytes follow the Line Header.
IDI1
D7
OP
D6
FID
D5
L8
D4
L7
D3
L6
D2
L5
D1
L4
D0
L3
L[8:3] : MSbits of Line Number (look for LSbits 2:0 in IDI2 byte).
FID : Field Identifier. '0' means FIRST field, '1' means SECOND field.
OP is Odd Parity bit. Examp.: D6:D0='0000101' ==> OP='1', IDI1=0x85.
IDI2
D7
OP
D6
L2
D5
L1
D4
L0
D3
DT3
D2
DT2
D1
DT1
D0
DT0
OP is Odd Parity bit. Examp.: D6:D0='1110000' ==> OP='0', IDI1=0x70.
L[2:0] : LSbits of Line Number (look for MSbits 8:3 in IDI1 byte).
DT[3:0] defines the VBI Data Type for the given line. The host computer should define the
Data Type per every VBI line (lines between 2-21). The video decoder needs this
information in order to look for the given data type per line (there is no auto detect).
Regardless of decoding success, the same data type code that was programmed by the host
controller will be returned in the DT[3:0] nibble.
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
The following table specifies the Data Type codes (DT[3:0]):
Table 6 - VBI DATA TYPE CODES
DT[3:0]
0000
0001
0010
0011
0100
0101
0110
0111*
1000
1001
1010
1011*
1100
1101
1110
1111*
VBI Data Type
Standard
Teletext EuroWST, CCST
European Closed Caption
Video Programming Service
Wide screen signalling bits
US Teletext (WST)
US Closed Caption (line 21)
Video Component signal
Oversampled CVBS data (do not use)
Teletext
VITC/EBU time codes (Europe)
VITC/EBU time codes (USA)
reserved (do not use)
US NABTS
MOJI (Japanese)
Japanese format switch (L20/22)
Active Video Region (do not use)
WST625
CC625
VPS
WSS
WST525
CC525
S/W mode
** intercast **
General Text
VITC625
VITC625
NABTS
Japtext
JFS
Expected
number of
Data bytes
42
2
26
14
34
2
718
42
11
11
34
35
26
718
The IRD (Remote Control) data Header byte contains two fields as specified bellow. It is
followed by 7 to 11 bytes (depends one broadcast system PAL/NTSC, and sampling
phase):
IR_HEADER
D7
D6
'0'
'1'
D5
'1'
D4
'1'
D3
D2
D1
IRD_LENGTH
D0
IRD_LENGTH contains the number of bytes for IRD data samples that follow the header.
November-99
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ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
3. Bulk Interface
The Bulk Interface in the ZR36505 is capable of transferring serial data from the 1KB buffer
to the ZR36504 at a bit rate of up to 2Mbit/sec.
The Bulk channel takes advantage of the existing interface for the audio codec. In order to
work simultaneously with the audio channel, the ZR36505 stops the data transfer from time
to time - as specified in the Bulk waveform diagram.
The ZR36505 pins for the Bulk interface are BCLK, DAT_OUT, BLK_EN, BLK_FULL,
and FS_L. The signal FS_L is monitored by the ZR36505 in order to coexist with the audio
channel (if exists).
The following parameters in the BLK_OPER_MODE register (reg. 5) must be properly
defined to match the ZR36504 setup:
BLK_OPER_REG (Reg. 5)
D7
D6-D4
D3
BLK_IO_EN
resrved
BCLK_RATE
D2
D1
D0
AUDIO_DAT
AUDIO_RATE
AUDIO_STEREO
BLK_IO_EN - This bit enables the ZR36505 Bulk control output signals. When this bit is
'0', the DAT_OUT and BLK_EN pins are constant Hi-Z.
BCLK_RATE - This bit defines the BCLK frequency, and must match the appropriate
parameter that is programmed in the AUDO_CONT register of the ZR36504(Reg.50, d7d6). BCLK_RATE='1' defines 2048KHz (= '11' in NT1004), and BCLK_RATE='0'
defines 1544KHz (= '10' in NT1004).
AUDIO_DAT - This bit defines whether or not the audio channel is active, and must match
the appropriate parameter that is programmed in the AUDO_CONT register of the
ZR36504(Reg.50, d0). AUDIO_DAT='1' define s audio active (= '1' in NT1004), and
AUDIO_DAT='0' defines that there is no audio data sharing the bus (= '0' in NT1004).
AUDIO_RATE - This bit defines the audio sampling rate, and must match the appropriate
parameter that is programmed in the AUDO_CONT register of the ZR36504(Reg.50, d5).
AUDIO_RATE='1' defines 16Ks/sec (= '1' in NT1004), and AUDIO_RATE='0' defines
8Ks/sec (= '0' in NT1004).
AUDIO_STEREO - This bit defines the audio stereo/mono mode, and must match the
appropriate parameter that is programmed in the AUDO_CONT register of the
November-99
Page 21 of 21
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
ZR36504(Reg.50, d4). AUDIO_STEREO='1' defines Stereo mode (= '1' in NT1004),
and AUDIO_STEREO ='0' defines Mono mode (= '0' in NT1004).
November-99
Page 22 of 22
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
The following waveform diagrams specify the procedure and timings for the ZR36505 Bulk
interface. Note that the output data is supposed to be sampled on the falling edge of the
BCLK clock signal. The BLK_EN output is set to '1' to indicate the beginning of a byte
sequence; it always turns to '1' before the most significant bit of the first byte, and returns to
'0' after the least significant bit of the last byte in sequence. When the BLK_FULL input
signal turns '1', the ZR36505 waits (by switching BLK_EN to '0') until the BLK_FULL
indication returns to '0'.
BCLK
BEh
BEsu
BLK_EN
Dh
DAT_OUT
Hi-Z
B1[7]
B1[6]
B1[5]
B1[4]
Bn[2]
Bn[1]
Bn[0]
Hi-Z
Dsu
If the audio channel is enabled (bit d2 of Reg.5 is '1'), the ZR36505 waits at least 16 clock
cycles after the FS_L pulse before beginning to send its own data (if bit d0 of Reg.5 is '1', it
waits for 32 clock cycles). During this time it keeps the DAT_OUT signal in the Hi-Z state,
in order not to interfere with the audio data.
1
2
3
4
16
(32 in Stereo mode)
BCLK
FS_L
BLK_EN
DAT_OUT
November-99
x
Keep Hi-Z in order not to interfere with audio data
B1[7]
B1[6]
B1[5]
Page 23 of 23
ZORAN Corporation
USBvision II Data Decoder
BFHsu
ZR36505 Data Sheet
BFLsu
BCLK
BLK_FULL
BLK_EN
DAT_OUT
Bn[1]
Bn[0]
Table 7 - BULK INTERFACE TIMINGS
Parameter
Hi-Z
Bn+1[7] Bn+1[6]
Symbol
Min
Max
Unit
Setup Time from BLK_EN High to BCLK Low
BEsu
100
-
ns
Hold Time from BCLK Low to BLK_EN Low
BEh
100
-
ns
Setup Time from DAT_IN valid to BCLK Low
Dsu
100
-
ns
Hold Time from BCLK Low to DAT_IN valid
Dh
100
-
ns
Setup Time from BLK_FULL High to BCLK High
BFHsu
80
-
ns
Hold Time from BLK_FULL Low to BCLK High
BFLsu
0
-
ns
Freq.BCLK
1544
2048
KHz
BCLK frequency
November-99
Page 24 of 24
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
4. Programmable I/O Pins
The ZR36505 has two programmable I/O pins for general purpose usage. These are IO-1
and IO-2 pins, which are Open-Drain.
Each of these pins - if used - must be connected to an external pull-up resistor to 3.3v (if not
used, it can be tied to GND). The external pull-up resistor should be in the range 1-10KΩ .
To use these pins as inputs, the host computer should write '1' to the appropriate bit in the
IO_REG register (reg. 6); these are IO_1 and IO_2 bits respectively. In this condition, the
voltage level presented on the IO-1 or IO-2 pin can be read by the host computer via the
appropriate bit ('0' represents <0.8v, '1' represents >2.0v).
To use these pins as outputs, the host computer should write the output value to the
appropriate bit in the IO_REG register; In this condition, and assuming that no external
device forces the voltage level presented on the IO-1 or IO-2 pin, the written value will be
reflected out ('0' will generate 0v, '1' will generate 3.3-5.0v).
IO_REG (Reg. 6)
D7
D6
resrved
resrved
D5
resrved
D4
resrved
D3
resrved
D2
resrved
D1
IO_2
D0
IO_1
Upon a Soft Reset operation, the IO-1 and IO-2 pins are cleared to '0'.
November-99
Page 25 of 25
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
5. Soft Reset operation
It is strongly recommended that the S/W application will perform a Soft Reset to the
ZR36505 prior to any other operation. All registers will contain their default values after this
operation (refer to table 4 for default values).
To perform a Soft Reset, the value 0x01 must be written in the SOFT_RESET register (reg.
7). There is no need to write 0x00 after writing 0x01, because this register is automatically
cleared.
SOFT_RESET (Reg. 7)
November-99
D7-D1
D0
resrved
SOFT_RESET
Page 26 of 26
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
6. Mechanical Specification
Dimensions in inches.
+.007
0.606 -.007
1
+.017
0.033 -.017
.019 x 45 Typ
+.003
0.296 -.004
0.402 +.017
-.008
24
+.005
0.099 -.006
.050 Typ
0.016+.004
-.003
24-pin 300-Mil SOIC GULL WING
November-99
Page 27 of 27
ZORAN Corporation
USBvision II Data Decoder
ZR36505 Data Sheet
http://www.zoran.com
For more information, contact Zoran’s Santa Clara office or the office
nearest you:
USA
Zoran Corporation
3112 Scott Boulevard
Santa Clara, CA 95054-3317
Tel: 408-919-4111
Fax: 408-919-4122
Japan
Zoran Japan Office
2-2-8 Roppongi, Minato-ku
Tokyo 106-0032, Japan
Tel : +81-03-5574-7081
Fax: +81-03-5574-7156
Israel
Zoran Microelectronics Ltd.
Advanced Technology Ctr.
P.O. Box 2495
Haifa, 31024 Israel
Tel : +972-4-8545-777
Fax: +972-4-8551-551
Taiwan
Zoran Taiwan Office
4F-1, No. 5, Alley 22
Lane 513, Reikuang Rd.
Taipei, Taiwan R.O.C.
Tel : +886-2-2659-9797
Fax: +886-2-2659-9595
China
Zoran China Office
Suite 2507
Electronics Science &
Tech Building
2070 Central Shennan Rd.
Shenzhen, Guangdong,
518031 P.R. China
Tel : +86-755-378-0319
Fax: +86-755-378-0852
Canada
Zoran Toronto Lab
2175 Queen St. East,
Suite 302
Toronto, Ontario
M4E 1E5 Canada
Tel : (416) 690-3356
Fax: (416) 690-336
November-99
Page 28 of 28