TI 5962-9080801MHA

 µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
D 2× Bandwidth (2 MHz) of the TL06x and
D
D
TL03x Operational Amplifiers
Low Supply Current . . . 290 µA/Ch Typ
On-chip Offset Voltage Trimming for
Improved DC Performance
D High Output Drive, Specified into 100-Ω
D
Loads
Lower Noise Floor Than Earlier
Generations of Low-Power BiFETs
description
The TLE206x series of low-power JFET-input operational amplifiers doubles the bandwidth of the earlier
generation TL06x and TL03x BiFET families without significantly increasing power consumption. Texas
Instruments Excalibur process also delivers a lower noise floor than the TL06x and TL03x. On-chip zener
trimming of offset voltage yields precision grades for dc-coupled applications. The TL206x devices are
pin-compatible with other Texas Instruments BiFETs; they can be used to double the bandwidth of TL06x and
TL03x circuits or to reduce power consumption of TL05x, TL07x, and TL08x circuits by nearly 90%.
BiFET operational amplifiers offer the inherently-higher input impedance of the JFET-input transistors, without
sacrificing the output drive associated with bipolar amplifiers. This makes them better suited for interfacing with
high-impedance sensors or low-level ac signals. They also feature inherently better ac response than bipolar
or CMOS devices having comparable power consumption. The TLE206x family features a high-output-drive
circuit capable of driving 100-Ω loads at supplies as low as ± 5 V. This makes them uniquely suited for driving
transformer loads in modems and other applications requiring good ac characteristics, low power, and high
output drive.
Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to
observe common-mode input voltage limits and output swing when operating from a single supply. DC biasing
of the input signal is required and loads should be terminated to a virtual ground node at mid-supply. Texas
Instruments TLE2426 integrated virtual ground generator is useful when operating BiFET amplifiers from single
supplies.
The TLE206x are fully specified at ±15 V and ± 5 V. For operation in low-voltage and/or single-supply systems,
Texas Instruments LinCMOS families of operational amplifiers (TLC- and TLV-prefixes) are recommended.
When moving from BiFET to CMOS amplifiers, particular attention should be paid to slew rate and bandwidth
requirements and output loading. The Texas Instruments TLV2432 and TLV2442 CMOS operational amplifiers
are excellent choices to consider.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *%' '&#)$*&'
'&%.%#. 1%##%&2/ #".)(&" +#"(*''3 ."*' "& *(*''%#-2 (-).*
&*'&3 "! %-- +%#%$*&*#'/
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061 AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
OUTLINE†
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
500 µV
—
—
1.5 mV
TLE2061ACD
—
TLE2061CD
VIOmax
AT 25°C
TA
0°C
0
C to 70
70°C
C
3 mV
500 µV
−40°C
−40
C to 85°C
85 C
1.5 mV
3 mV
−55°C
−55
C to 125
125°C
C
PLASTIC
DIP
(P)
TSSOP‡
(PW)
CERAMIC
FLAT PACK
(U)
—
—
—
—
—
TLE2061ACP
—
—
—
—
TLE2061CP
TLE2061CPWLE
—
—
—
—
—
—
TLE2061AID
—
—
TLE2061AIP
—
—
TLE2061ID
—
—
—
TLE2061IP
—
—
500 µV
—
—
TLE2061BMJG
—
—
—
1.5 mV
TLE2061AMD
TLE2061AMFK
TLE2061AMJG
—
—
TLE2061AMU
TLE2061MFK
TLE2061MJG
—
—
3 mV
TLE2061MD
TLE2061MU
† The D packages are available taped and reeled. Add R suffix to device type (e.g., TLE2061ACDR).Chips are tested at 25°C.
‡ The PW package is available left-end taped and reeled (indicated by the LE suffix on the device type (e.g., TLE2061CPWLE).
TLE2062 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
SMALL OUTLINE†
(D)
CHIP CARRIER
(FK)
CERAMIC DIP
(JG)
PLASTIC DIP
(P)
CERAMIC
FLAT PACK
(U)
0°C
to
70°C
1 mV
2 mV
4 mV
TLE2062BCD
TLE2062ACD
TLE2062CD
—
—
—
—
—
—
TLE2062BCP
TLE2062ACP
TLE2062CP
—
—
—
−40°C
to
85°C
1 mV
2 mV
4 mV
TLE2062BID
TLE2062AID
TLE2062ID
—
—
—
—
—
—
TLE2062BIP
TLE2062AIP
TLE2062IP
—
—
—
−55°C
to
125°C
1 mV
2 mV
4 mV
TLE2062BMD
TLE2062AMD
TLE2062MD
—
TLE2062AMFK
TLE2062MFK
TLE2062BMJG
TLE2062AMJG
TLE2062MJG
—
—
—
—
TLE2062AMU
TLE2062MU
† The D packages are available taped and reeled. Add R suffix to device type (e.g., TLE2062ACDR).
TLE2064 AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
PLASTIC DIP
(N)
CERAMIC
FLAT PACK
(W)
—
TLE2064ACD
TLE2064CD
—
—
TLE2064BCN
TLE2064ACN
TLE2064CN
—
2 mV
4 mV
6 mV
—
TLE2064AID
TLE2064ID
—
—
TLE2064BIN
TLE2064AIN
TLE2064IN
—
2 mV
4 mV
6 mV
—
TLE2064AMD
TLE2064MD
TLE2064BMFK
TLE2064AMFK
TLE2064MFK
TLE2064BMJ
TLE2064AMJ
TLE2064MJ
—
—
TLE2064AMW
TLE2064MW
TA
VIOmax
AT 25°C
0°C
to
70°C
2 mV
4 mV
6 mV
−40°C
to
85°C
−55°C
to
125°C
SMALL OUTLINE†
(D)
† The D packages are available taped and reeled. Add R suffix to device type, (e.g., TLE2064ACDR).
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
8
2
7
3
6
4
5
NC
VCC +
OUT
OFFSET N2
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
VCC +
NC
OUT
NC
TLE2061 AND TLE2061A
U PACKAGE
(TOP VIEW)
NC
OFFSET N1
IN−
IN+
VCC−
1
10
2
9
3
8
4
7
5
6
8
2
7
3
6
4
5
VCC +
2OUT
2IN −
2IN +
TLE2062M, TLE2062AM, TLE2062BM
FK PACKAGE
(TOP VIEW)
NC
1IN −
NC
1IN+
NC
4
NC
NC
VCC+
OUT
OFFSET N2
3 2 1 20 19
18
5
17
6
16
15
7
8
VCC −
NC
OFFSET N2
NC
4
NC
NC
IN −
NC
IN +
NC
1
14
9 10 11 12 13
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN −
4IN +
VCC −
3IN +
3IN −
3OUT
TLE2064M, TLE2064AM, TLE2064BM
FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
VCC +
NC
NC
OFFSET N1
NC
NC
NC
TLE2061M, TLE2061AM, TLE2061BM
FK PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
VCC −
1OUT
1IN −
1IN +
VCC +
2IN +
2IN −
2OUT
1IN −
1OUT
NC
4OUT
4IN −
1
NC
2OUT
NC
2IN −
NC
NC
VCC −
NC
2IN+
NC
OFFSET N1
IN −
IN +
VCC −
TLE2062, TLE2062A, TLE2062B
D, JG, OR P PACKAGE
(TOP VIEW)
1IN +
NC
VCC +
NC
2IN +
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4IN +
NC
VCC −
NC
3IN +
2IN −
2OUT
NC
3OUT
3IN −
TLE2061, TLE2061A, AND TLE2061B
D, DB, JG, P, OR PW PACKAGE
(TOP VIEW)
TLE2064, TLE2064A, TLE2064B
D, J, N, OR W PACKAGE
(TOP VIEW)
TLE2062 AND TLE2062A
U PACKAGE
(TOP VIEW)
NC
1OUT
1IN−
1IN+
VCC−
1
10
2
9
3
8
4
7
5
6
NC
VCC+
2OUT
2IN−
2IN+
NC − No internal connection
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
4
POST OFFICE BOX 655303
Q1
Q2
• DALLAS, TEXAS 75265
Q6
Q5
See Note A
R4
55 kΩ
15 pF
C1
Q3
C2
15 pF
R2
1.1 kΩ
Q8
R3
2.4 kΩ
Q7
R5
60 kΩ
Q10
Q14
Q13
Q12
Q15
C3
5.3 pF
Q11
Q9
Q16
Q22
Q21
Q20
Q17
Q19
Q18
VCC −
Q24
2.7 kΩ
R6
VCC +
Q28
43
9
1
3
Resistors
Diodes
Capacitors
TLE2061
Transistors
COMPONENT
3
2
9
42
TLE2062
Q27
3
2
9
42
Q29
R7
600 Ω
TLE2064
Q26
Q23
Q25
ACTUAL DEVICE COMPONENT COUNT
NOTES: A. OFFSET N1 AND OFFSET N2 are only availiable on the TLE2061x devices.
B. Component values are nominal.
OFFSET N2
OFFSET N1
R1
1.1 kΩ
IN −
IN +
Q4
equivalent schematic (each channel)
Q31
Q30
D1
D2
Q34
Q33
Q32
Q38
Q37
Q36
Q35
R8
R9
Q42
OUT
100 Ω
20 Ω
Q41
Q40
Q39
Template Release Date: 7−11−94
4
4
44
µ
4
4
SLOS193B − FEBRUARY 1997 − REVISED APRIL 2004
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V
Supply voltage, VCC − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −19 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 38 V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 1 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 80 mA
Total current into VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 mA
Total current out of VCC − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −80 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Package thermal impedance, θJA (see Notes 4 and 5): D package (8-pin) . . . . . . . . . . . . . . . . . . . . 97.1°C/W
D package (14-pin) . . . . . . . . . . . . . . . . . . 86.2°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . 79.7°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . 84.6°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Package thermal impedance, θJC (see Notes 4 and 5): FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6°C/W
J package . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1°C/W
JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5°C/W
U package . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7°C/W
W package . . . . . . . . . . . . . . . . . . . . . . . . . . . 10°C/W
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG, U, or W package . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC − .
2. Differential voltages are at IN+ with respect to IN −.
3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
4. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
5. The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).
recommended operating conditions
Supply voltage, VCCā±
Common-mode input voltage, VIC
VCC± = ±ā5 V
VCC± = ±ā15 V
Operating free-air temperature, TA
POST OFFICE BOX 655303
C SUFFIX
I SUFFIX
MIN
MAX
MIN
MAX
± 3.5
± 18
± 3.5
± 18
± 3.5
−1.6
4
−1.6
4
−1.6
4
−11
13
−11
13
−11
13
0
70
−40
85
−55
125
• DALLAS, TEXAS 75265
M SUFFIX
MIN
MAX
± 18
UNIT
V
V
°C
5
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061C electrical characteristics at specified free-air temperature, VCC ± = ±5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2061C
TLE2061AC
TLE2061BC
MIN
25°C
TLE2061C
Input offset voltage
TLE2061AC
VIC = 0,
RS = 50 Ω
Input offset voltage long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
0.6
0.5
Full range
VOM +
VOM −
µV/°C
25°C
0.04
µV/mo
25°C
1
AVD
Large-signal differential voltage amplification
25°C
Full range
−1.6
to
4
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
25°C
3.5
Full range
3.3
25°C
2.5
25°C
−3.7
RL = 10 kΩ
Full range
−3.3
25°C
−2.5
nA
V
V
3.7
3.1
V
2
Full range
−2
25°C
15
2
VO = ± 2.8 V,
RL = 10 kΩ
Full range
RL = 100 Ω
25°C
0.75
VO = 0 to 2 V,
Full range
0.5
25°C
0.5
Full range
0.25
−3.9
−2.7
V
80
45
V/mV
3
1012
Ω
25°C
4
pF
25°C
280
Ω
25°C
IO = 0
−2
to
6
nA
pA
2
Full range
VO = 0 to − 2 V, RL = 100 Ω
ri
3
RL = 100 Ω
RL = 100 Ω
pA
0.8
−1.6
to
4
Common-mode input voltage range
Maximum negative peak output voltage swing
1.9
2.4
Full range
Maximum positive peak output voltage swing
mV
6
Full range
Full range
RL = 10 kΩ
2.6
3.5
25°C
VICR
3.1
4
25°C
Temperature coefficient of input offset voltage
MAX
0.8
Full range
TLE2061BC
αVIO
TYP
Full range
25°C
VIO
UNIT
25°C
65
CMRR
Common-mode rejection ratio
VIC = VICRmin, RS = 50 Ω
Full range
65
75
Supply-voltage rejection ratio (∆VCC±
CC /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
25°C
kSVR
Full range
75
82
dB
93
dB
† Full range is 0°C to 70°C.
NOTE 6: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TLE2061C
TLE2061AC
TLE2061BC
TA†
MIN
25°C
ICC
Supply current
VO = 0,
No load
∆ICC
Supply-current change over operating temperature range
† Full range is 0°C to 70°C.
UNIT
TYP
MAX
280
325
Full range
350
Full range
µA
A
µA
29
TLE2061C operating characteristics at specified free-air temperature, VCC ± = ±5 V
PARAMETER
TEST CONDITIONS
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
TA†
TLE2061C
TLE2061AC
TLE2061BC
MIN
TYP
25°C
2.2
3.4
Full range
2.1
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
25°C
1.1
Equivalent input noise current
f = 1 kHz
25°C
1
THD
Total harmonic distortion
AVD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
RL = 100 Ω,
CL = 100 pF
ts
Settling time
BOM
Maximum output-swing bandwidth
RS = 20 Ω
f = 1 kHz ,
25°C
25°C
φm
Phase margin at unity gain (see Figure 3)
V/ s
V/µs
59
100
43
60
RL = 10 kΩ
CL = 100 pF
RL = 100 Ω,
CL = 100 pF
µV
V
fA/√Hz
0.025%
1.3
5
25°C
AVD = 1,
RL = 10 kΩ,
nV/√Hz
1.8
25°C
0.1%
0.01%
UNIT
MAX
25°C
25°C
10
140
MHz
µss
kHz
58°
75°
† Full range is 0°C to 70°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061C electrical characteristics at specified free-air temperature, VCC ± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2061C
TLE2061AC
TLE2061BC
MIN
25°C
TLE2061C
Input offset voltage
TLE2061AC
3.9
VIC = 0,
RS = 50 kΩ
Input offset current
IIB
Input bias current
0.3
VOM +
µV/°C
25°C
0.04
µV/mo
25°C
2
Full range
−11
to
13
25°C
13.2
Full range
25°C
RL = 600 Ω
Full range
RL = 10 kΩ
Full range
Maximum negative peak output voltage swing
25°C
RL = 600 Ω
AVD
Large-signal differential voltage amplification
−13.2
−12.5
30
Full range
20
RL = 600 Ω
25°C
25
Full range
10
VO = 0 to − 8 V, RL = 600 Ω
25°C
3
Full range
1
ri
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
IO = 0
CMRR
Common-mode rejection ratio
VIC = VICRmin, RS = 50 Ω
kSVR
Supply-voltage rejection ratio (∆VCC±
CC /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
V
13.7
13.2
V
−13.7
−13
−12
VO = 0 to 8 V,
V
12
25°C
RL = 10 kΩ
nA
13
12.5
Full range
VO = ± 10 V,
−12
to
16
nA
pA
3
−11
to
13
25°C
VOM −
4
25°C
Common-mode input voltage range
pA
1
Full range
Maximum positive peak output voltage swing
0.5
1
Full range
RL = 10 kΩ
mV
6
Full range
25°C
VICR
1.5
2.5
Full range
Input offset voltage long-term drift (see Note 4)
IIO
3
0.5
25°C
Temperature coefficient of input offset voltage
MAX
0.6
Full range
TLE2061BC
αVIO
TYP
Full range
25°C
VIO
UNIT
−13
V
230
100
V/mV
25
1012
Ω
25°C
4
pF
25°C
280
Ω
25°C
25°C
72
Full range
70
25°C
75
Full range
75
90
dB
93
dB
† Full range is 0°C to 70°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061C electrical characteristics at specified free-air temperature, VCC ± = ±15 V (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TLE2061C
TLE2061AC
TLE2061BC
TA†
MIN
25°C
ICC
Supply current
VO = 0,
No load
∆ICC
Supply-current change over operating temperature range
† Full range is 0°C to 70°C.
UNIT
TYP
MAX
290
350
Full range
375
Full range
µA
A
µA
34
TLE2061C operating characteristics at specified free-air temperature, VCC ± = ±15 V
PARAMETER
TEST CONDITIONS
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
TA†
TLE2061C
TLE2061AC
TLE2061BC
MIN
TYP
25°C
2.6
3.4
Full range
2.5
UNIT
MAX
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
25°C
1.1
µV
In
Equivalent input noise current
f = 1 kHz
25°C
1.1
fA/√Hz
THD
Total harmonic distortion
AVD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
25°C
0.025%
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
ts
Settling time
BOM
Maximum output-swing bandwidth
RS = 20 Ω
f = 1 kHz ,
25°C
100
40
60
1.5
5
25°C
0.01%
Phase margin at unity gain (see Figure 3)
70
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
nV/√Hz
2
25°C
0.1%
φm
V/ s
V/µs
25°C
25°C
10
40
MHz
µss
kHz
60°
70°
† Full range is 0°C to 70°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise
noted)
PARAMETER
TA†
TEST CONDITIONS
TLE2061I , TLE2061AI
TLE2061BI
MIN
25°C
TLE2061I
Input offset voltage
TLE2061AI
VIC = 0,
RS = 50 Ω
0.6
Input offset current
IIB
Input bias current
0.5
2.7
µV/°C
25°C
0.04
µV/mo
25°C
1
VOM −
−1.6 to 4
Full range
−1.6 to 4
25°C
3.5
Full range
3.1
25°C
2.5
Full range
25°C
−3.7
RL = 10 kΩ
Full range
−3.1
25°C
−2.5
Maximum negative peak output voltage swing
Large-signal differential voltage amplification
ri
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
−2 to 6
nA
V
V
3.7
V
3.1
2
Full range
−2
VO = ± 2.8 V,
RL = 10 kkΩ
25°C
15
Full range
2
VO = 0 to 2 V,
RL = 100 Ω
25°C
0.75
Full range
0.5
25°C
0.5
Full range
0.25
VO = 0 to − 2 V,
RL = 100 Ω
nA
pA
4
RL = 100 Ω
RL = 100 Ω
AVD
3
25°C
Maximum positive peak output voltage swing
pA
2
Full range
RL = 10 kΩ
VOM +
1.9
6
Full range
Common-mode input voltage range
mV
Full range
25°C
VICR
2.6
3.9
Full range
Input offset voltage long-term drift (see Note 4)
IIO
3.1
4.4
25°C
Temperature coefficient of input offset voltage
0.8
Full range
TLE2061BI
αVIO
MAX
Full range
25°C
VIO
UNIT
TYP
25°C
−3.9
V
−2.7
80
45
V/mV
3
1012
Ω
25°C
4
pF
IO = 0
25°C
280
Ω
25°C
65
CMRR
Common-mode rejection ratio
VIC = VICRmin,
RS = 50 Ω
Full range
65
kSVR
Supply-voltage rejection ratio (∆VCC
CC± /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
25°C
75
Full range
65
ICC
Supply current
∆ICC
Supply-current change over operating
temperature range
25°C
VO = 0,
No load
82
dB
93
280
Full range
Full range
dB
325
350
29
A
µA
µA
† Full range is − 40°C to 85°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061I operating characteristics at specified free-air temperature, VCC ± = ±5 V
PARAMETER
TEST CONDITIONS
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
TLE2061I
TLE2061AI
TLE2061BI
TA†
MIN
TYP
25°C
2.2
3.4
Full range
1.7
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
25°C
1.1
Equivalent input noise current
f = 1 kHz
25°C
1
THD
Total harmonic distortion
AVD = 2,
VO(PP) = 2 V,
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 100 Ω,
ts
Settling time
BOM
Maximum output-swing bandwidth
φm
Phase margin at unity gain (see Figure 3)
RS = 20 Ω
f = 1 kHz ,
f = 10 kHz,
RL = 10 kΩ
CL = 100 pF
CL = 100 pF
25°C
25°C
V/ s
V/µs
59
100
43
60
RL = 10 kΩ
CL = 100 pF
RL = 100 Ω,
CL = 100 pF
nV/√Hz
µV
fA/√Hz
0.025%
1.3
5
25°C
AVD = 1,
RL = 10 kΩ,
MAX
1.8
25°C
0.1%
0.01%
UNIT
25°C
25°C
10
140
MHz
µss
kHz
58°
75°
† Full range is − 40°C to 85°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061I electrical characteristics at specified free-air temperature, VCC ± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2061I, TLE2061AI
TLE2061BI
MIN
25°C
TLE2061I
0.6
Full range
Input offset voltage
TLE2061AI
0.5
Full range
αVIO
Temperature coefficient of input offset
voltage
Input offset voltage long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
0.3
Full range
VIC = 0,
RS = 50 Ω
µV/°C
25°C
0.04
µV/mo
25°C
2
VOM −
Maximum negative peak output voltage
swing
AVD
Large-signal differential voltage amplification
ri
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
4
25°C
−11 to 13
Full range
−11 to 13
25°C
13.2
13
RL = 600 Ω
12.5
Full range
12
25°C
−13.2
RL = 10 kΩ
Full range
−13
25°C
−12.5
Full range
−12
VO = ± 10 V,
RL = 10 kkΩ
25°C
30
Full range
20
VO = 0 to 8 V,
RL = 600 Ω
25°C
25
Full range
10
VO = 0 to − 8 V,
RL = 600 Ω
25°C
3
Full range
01
25°C
nA
pA
5
25°C
RL = 600 Ω
pA
3
Full range
Maximum positive peak output voltage swing
0.5
6
Full range
RL = 10 kΩ
VOM +
mV
Full range
Full range
Common-mode input voltage range
1.5
1.3
25°C
VICR
3
2.9
25°C
TLE2061BI
UNIT
MAX
4.3
25°C
VIO
TYP
−12 to 16
nA
V
V
13.7
V
13.2
−13.7
V
−13
230
100
V/mV
25
1012
Ω
25°C
4
pF
IO = 0
25°C
280
Ω
25°C
72
Full range
65
25°C
75
Full range
65
CMRR
Common-mode rejection ratio
VIC = VICRmin,
RS = 50 Ω
kSVR
Supply-voltage rejection ratio (∆VCC±
CC /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
ICC
Supply current
∆ICC
Supply-current change over operating
temperature range
25°C
VO = 0,
No load
90
dB
93
dB
290
Full range
Full range
350
375
34
A
µA
µA
† Full range is − 40°C to 85°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061I operating characteristics at specified free-air temperature, VCC ± = ±15 V
PARAMETER
TEST CONDITIONS
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
TLE2061I
TLE2061AI
TLE2061BI
TA†
MIN
TYP
25°C
2.6
3.4
Full range
2.1
UNIT
MAX
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
25°C
1.1
µV
In
Equivalent input noise current
f = 1 kHz
25°C
1.1
fA/√Hz
THD
Total harmonic distortion
AVD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
25°C
0.025%
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
ts
Settling time
BOM
Maximum output-swing bandwidth
RS = 20 Ω
f = 1 kHz ,
25°C
100
40
60
1.5
5
25°C
0.01%
Phase margin at unity gain (see Figure 3)
70
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
nV/√Hz
2
25°C
0.1%
φm
V/ s
V/µs
25°C
25°C
10
40
MHz
µss
kHz
60°
70°
† Full range is − 40°C to 85°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061M electrical characteristics at specified free-air temperature, VCC ± = ±5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2061M
TLE2061AM
TLE2061BM
MIN
25°C
TLE2061M
Input offset voltage
TLE2061AM
VIC = 0,
RS = 50 Ω
Input offset voltage long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
0.5
Full range
µV/°C
25°C
0.04
µV/mo
25°C
1
−1.6
to
4
25°C
3.5
25°C
Full range
RL = 100 Ω
Full range
RL = 10 kΩ
Full range
25°C
Large-signal differential
voltage amplification
25°C
2.5
−3.5
−2.5
RL = 100 Ω
Full range
−2
D and P
packages
−2.5
25°C
15
2
25°C
1
25°C
1
Full range
0.5
RL = 100 Ω
25°C
0.75
Full range
0.5
VO = 0 to − 2 V, RL = 100 Ω
3.1
−3.9
−3.5
V
−2.7
80
65
0.5
VO = 0 to − 2.5 V,RL = 600 Ω
VO = 0 to 2 V,
V
−2
Full range
Full range
3.6
−3
D and P
packages
FK and JG
packages
3.7
2
Full range
VO = 0 to 2.5 V, RL = 600 Ω
V
V
2
RL = 600 Ω
RL = 10 kΩ
nA
3
2.5
FK and JG
packages
25°C
−2
to
6
nA
pA
30
Full range
RL = 600 Ω
VO = ± 2.8 V,
AVD
3
−1.6
to
4
Full range
pA
15
25°C
Common-mode input voltage range
Maximum negative peak
output voltage swing
1.9
3.1
Full range
Maximum positive peak output voltage swing
mV
6
Full range
25°C
VOM −
2.6
Full range
RL = 10 kΩ
VOM +
0.6
4.6
25°C
VICR
3.1
6
25°C
Temperature coefficient of input offset voltage
MAX
0.8
Full range
TLE2061BM
αVIO
TYP
Full range
25°C
VIO
UNIT
25°C
0.5
Full range
0.25
16
V/mV
45
3
† Full range is − 55°C to 125°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted) (continued)
PARAMETER
TLE2061M
TLE2061AM
TLE2061BM
TA†
TEST CONDITIONS
MIN
ri
Input resistance
25°C
ci
Input capacitance
zo
Open-loop output impedance
Ω
25°C
4
pF
25°C
280
Ω
25°C
65
Full range
60
25°C
75
Full range
65
Common-mode rejection ratio
VIC = VICRmin,
RS = 50 Ω
kSVR
Supply-voltage rejection ratio (∆VCC ± /∆VIO)
VCC ± = ± 5 V to ± 15 V,
RS = 50 Ω
ICC
Supply current
VO = 0,
82
dB
93
dB
25°C
Supply-current change over operating
temperature range
MAX
IO = 0
CMRR
∆ICC
TYP
1012
UNIT
No load
280
Full range
325
350
Full range
µA
A
µA
39
† Full range is − 55°C to 125°C.
TLE2061M operating characteristics at specified free-air temperature, VCC± = ±5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLE2061M
TLE2061AM
TLE2061BM
MIN
SR
Slew rate at unity gain (see Figure 1)
RL = 10 kΩ,
TYP
CL = 100 pF
RS = 20 Ω
3.4
f = 10 Hz,
f = 1 kHz ,
RS = 20 Ω
43
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
Equivalent input noise current
f = 1 kHz
THD
Total harmonic distortion
AVD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
0.025%
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
1.8
B1
RL = 600 Ω,
CL = 100 pF
1.3
ts
Settling time
BOM
Maximum output-swing bandwidth
φm
Phase margin at unity gain (see Figure 3)
POST OFFICE BOX 655303
1.1
1
0.1%
5
0.01%
10
RL = 600 Ω,
RL = 10 kΩ
140
CL = 100 pF
CL = 100 pF
58°
• DALLAS, TEXAS 75265
MAX
V/
V/µs
s
59
Vn
AVD = 1,
RL = 10 kΩ,
UNIT
nV/√Hz
V
µV
fA /√Hz
MHz
µss
kHz
75°
15
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2061M ,TLE2061AM
TLE2061BM
MIN
25°C
TLE2061M
Input offset voltage
TLE2061AM
0.5
Input offset current
0.3
Input bias current
VICR
Common-mode input voltage range
6
µV/°C
25°C
0.04
µV/mo
25°C
2
pA
20
VOM +
RL = 600 Ω
VOM −
Maximum negative peak output voltage
swing
−11 to 13
−11 to 13
25°C
13
Full range
12.5
25°C
12.5
12
25°C
−13
Full range
−12.5
25°C
−12.5
Full range
−12
25°C
30
Full range
20
VO = 0 to 8 V,
RL = 600 Ω
25°C
25
Full range
7
VO = 0 to − 8 V,
RL = 600 Ω
25°C
3
Full range
1
RL = 10 kΩ
VO = ± 10 V,
RL = 10 kkΩ
Large-signal differential voltage
amplification
25°C
Full range
−12 to 16
nA
pA
40
Full range
RL = 600 Ω
AVD
4
Full range
RL = 10 kΩ
0.5
Full range
Full range
Maximum positive peak output voltage
swing
mV
1.7
25°C
IIB
1.5
3.6
Full range
VIC = 0,
RS = 50 Ω
Input offset voltage long-term drift
(see Note 4)
IIO
3
6
25°C
αVIO
0.6
Full range
TLE2061BM
Temperature coefficient of input offset
voltage
MAX
Full range
25°C
VIO
UNIT
TYP
nA
V
V
13.7
13.2
V
−13.7
−13
V
230
100
V/mV
25
ri
Input resistance
25°C
1012
Ω
ci
Input capacitance
25°C
4
pF
zo
Open-loop output impedance
280
Ω
IO = 0
25°C
25°C
72
CMRR
Common-mode rejection ratio
VIC = VICRmin,
RS = 50 Ω
Full range
65
Supply-voltage rejection ratio
(∆VCC ± /∆VIO)
VCC ± = ± 5 V to ± 15 V,
RS = 50 Ω
25°C
75
kSVR
Full range
65
90
dB
93
dB
† Full range is − 55°C to 125°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continue)
PARAMETER
TLE2061M ,TLE2061AM
TLE2061BM
TA†
TEST CONDITIONS
MIN
25°C
ICC
∆ICC
Supply current
VO = 0,
Supply-current change over operating
temperature range
No load
UNIT
TYP
MAX
290
350
Full range
375
Full range
A
µA
µA
46
† Full range is − 55°C to 125°C.
TLE2061M operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER
TEST CONDITIONS
TA†
25°C
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
THD
Total harmonic distortion
AVD = 2,
VO(PP) = 2 V,
B1
Unity-gain bandwidth (see Figure 3)
ts
Settling time
BOM
Maximum output-swing bandwidth
φm
Phase margin at unity gain (see Figure 3)
TLE2061M
TLE2061AM
TLE2061BM
MIN
TYP
2
3.4
UNIT
MAX
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
25°C
70
f = 1 kHz,
RS = 20 Ω
25°C
40
f = 0.1 Hz to 10 Hz
25°C
1.1
µV
V
f = 1 kHz
25°C
1.1
fA /√Hz
f = 10 kHz,
RL = 10 kΩ
25°C
0.025%
RL = 10 kΩ,
CL = 100 pF
25°C
2
RL = 600 Ω,
CL = 100 pF
25°C
1.5
0.1%
25°C
5
0.01%
25°C
10
Full range
V/ s
V/µs
1.8
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
25°C
40
CL = 100 pF
25°C
60°
RL = 600 Ω,
CL = 100 pF
25°C
70°
nV/√Hz
MHz
µss
kHz
† Full range is − 55°C to 125°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2061Y electrical characteristics at VCC± = ±15 V, TA = 25°C (unless otherwise noted)
TLE2061Y
PARAMETER
VIO
αVIO
Input offset voltage
IIO
IIB
Input offset current
TEST CONDITIONS
Input offset voltage long-term drift (see Note 4)
VIC = 0,
Common-mode input voltage range
VOM +
Maximum positive peak output voltage swing
VOM −
Maximum negative peak output voltage swing
MAX
0.6
3
Large-signal differential voltage amplification
UNIT
mV
µV/mo
0.04
RS = 50 Ω
2
pA
4
pA
−11
to
13
−12
to
16
V
RL = 10 kΩ
13.2
13.7
RL = 600 Ω
12.5
13.2
RL = 10 kΩ
−13.2
−13.7
RL = 600 Ω
−12.5
− 13
RL = 10 kΩ
30
230
RL = 600 Ω
VO = 0 to − 8 V, RL = 600 Ω
25
100
3
25
VO = ± 10 V,
VO = 0 to 8 V,
ri
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
CMRR
Common-mode rejection ratio
IO = 0
RS = 50 Ω,
Supply-voltage rejection ratio (∆VCC /∆VIO)
VCC ± = ± 5 V to ± 15 V,
RS = 50 Ω
kSVR
TYP
Input bias current
VICR
AVD
MIN
VIC = VICRmin
V
V
V/mV
1012
Ω
4
pF
280
Ω
72
90
dB
75
93
dB
ICC
Supply current
VO = 0,
No load
290
350
µA
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
TLE2061Y operating characteristics at VCC± = ±15 V, TA = 25°C
TLE2061Y
PARAMETER
SR
TEST CONDITIONS
Slew rate at unity gain (see Figure 1)
RL = 10 kΩ,
f = 10 Hz,
CL = 100 pF
RS = 20 Ω
f = 1 kHz ,
RS = 20 Ω
MIN
TYP
2.6
3.4
MAX
UNIT
V/µs
70
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
1.1
µV
In
Equivalent input noise current
f = 1 Hz
1.1
fA /√Hz
THD
Total harmonic distortion
AVD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 600 Ω,
CL = 100 pF
CL = 100 pF
ts
Settling time
BOM
Maximum output-swing bandwidth
φm
18
Phase margin at unity gain (see Figure 3)
POST OFFICE BOX 655303
40
0.025%
2
1.5
0.1%
5
0.01%
10
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
40
CL = 100 pF
60°
RL = 600 Ω,
CL = 100 pF
70°
• DALLAS, TEXAS 75265
nV/√Hz
MHz
µss
kHz
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2062C
TLE2062AC
TLE2062BC
MIN
25°C
TLE2062C
Input offset voltage
TLE2062AC
RS = 50 Ω
VIC = 0,
Input offset voltage long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
5.9
0.7
Full range
VOM +
VOM −
µV/°C
25°C
0.04
µV/mo
25°C
1
−1.6
to
4
Full range
−1.6
to
4
25°C
3.5
Full range
3.3
25°C
2.5
25°C
−3.7
RL = 10 kΩ
Full range
−3.3
25°C
−2.5
Large-signal differential voltage amplification
RL = 10 kΩ
−2
25°C
15
0.75
0.5
RL = 100 Ω
Full range
RL = 100 Ω
25°C
0.5
VO = 0 to − 2 V,
Full range
0.25
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
IO = 0
CMRR
Common-mode rejection ratio
VIC = VICRmin, RS = 50 Ω
kSVR
Supply-voltage rejection ratio (∆VCC ± /∆VIO)
VCC ± = ± 5 V to ± 15 V,
RS = 50 Ω
V
V
3.7
3.1
V
−3.9
−2.7
V
80
2
25°C
VO = 0 to 2 V,
ri
nA
2
Full range
Full range
−2
to
6
nA
pA
2
Full range
VO = ± 2.8 V,
AVD
3
RL = 100 Ω
RL = 100 Ω
pA
0.8
25°C
Common-mode input voltage range
Maximum negative peak output voltage swing
3
6
Full range
Full range
Maximum positive peak output voltage swing
mV
3.9
Full range
RL = 10 kΩ
4
4.9
25°C
VICR
5
0.9
25°C
Temperature coefficient of input offset voltage
MAX
1
Full range
TLE2062BC
αVIO
TYP
Full range
25°C
VIO
UNIT
45
V/mV
3
1012
Ω
25°C
4
pF
25°C
560
Ω
25°C
25°C
65
Full range
65
25°C
75
Full range
75
82
dB
93
dB
† Full range is 0°C to 70°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150 °C extrapolated
to TA = 25 °C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062C electrical characteristics at specified free-air temperature, VCC ± = ±5 V (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLE2062C
TLE2062AC
TLE2062BC
MIN
25°C
ICC
∆ICC
Supply current
Supply-current change over operating
temperature range
VO = 0,
No load
UNIT
TYP
MAX
560
620
Full range
635
Full range
µA
A
µA
26
† Full range is 0°C to 70°C.
TLE2062C operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER
TEST CONDITIONS
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
THD
Total harmonic distortion
VO(PP) = 2 V,
AVD = 2,
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 100 Ω,
Settling time
BOM
φm
Maximum output-swing bandwidth
Phase margin at unity gain (see Figure 3)
MIN
TYP
25°C
2.2
3.4
Full range
2.1
UNIT
MAX
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
25°C
59
100
f = 1 kHz,
RS = 20 Ω
25°C
43
60
f = 0.1 Hz to 10 Hz
25°C
1.1
f = 1 kHz
25°C
1
RL = 10 kΩ,
f = 10 kHz
25°C
0.025%
CL = 100 pF
25°C
1.8
CL = 100 pF
25°C
1.3
V/ s
V/µs
0.1%
25°C
5
0.01%
25°C
10
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
25°C
140
CL = 100 pF
25°C
58°
RL = 100 Ω,
CL = 100 pF
25°C
75°
† Full range is 0°C to 70°C.
20
TA†
TLE2062C
TLE2062AC
TLE2062BC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
nV/√Hz
µV
fA/√Hz
MHz
µss
kHz
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062C electrical characteristics at specified free-air temperature, VCC ± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2062C
TLE2062AC
TLE2062BC
MIN
25°C
TLE2062C
0.9
Full range
Input offset voltage
TLE2062AC
0.8
Full range
αVIO
Temperature coefficient of input offset voltage
RS = 50 Ω
VIC = 0,
Input offset voltage long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
0.5
Full range
VOM +
µV/°C
0.04
µV/mo
25°C
2
−11
to
13
25°C
13.2
25°C
RL = 600 Ω
Full range
RL = 10 kΩ
Full range
Maximum negative peak output voltage swing
25°C
Large-signal differential voltage amplification
ri
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
nA
V
V
13.7
13
12.5
13.2
V
12
−13.2
−13.7
−13
−12.5
Full range
−12
25°C
30
VO = ± 10 V,
RL = 10 kΩ
Full range
20
RL = 600 Ω
25°C
25
VO = 0 to 8 V,
Full range
10
RL = 600 Ω
25°C
3
VO = 0 to − 8 V,
Full range
1
−13
V
230
100
V/mV
25
1012
Ω
25°C
4
pF
25°C
560
Ω
25°C
IO = 0
−12
to
16
nA
pA
3
Full range
Full range
RL = 600 Ω
AVD
4
25°C
Common-mode input voltage range
pA
1
−11
to
13
25°C
VOM −
1
25°C
Full range
Maximum positive peak output voltage swing
mV
1.9
Full range
RL = 10 kΩ
2
6
Full range
25°C
VICR
4
2.9
25°C
TLE2062BC
MAX
4.9
25°C
VIO
TYP
UNIT
25°C
72
CMRR
Common-mode rejection ratio
VIC = VICRmin, RS = 50 Ω
Full range
70
kSVR
Supply-voltage rejection ratio (∆VCC ± /∆VIO)
VCC ± = ± 5 V to ± 15 V,
RS = 50 Ω
25°C
75
Full range
75
90
dB
93
dB
† Full range is 0°C to 70°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150 °C extrapolated
to TA = 25 °C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062C electrical characteristics at specified free-air temperature, VCC ± = ±15 V (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLE2062C
TLE2062AC
TLE2062BC
MIN
25°C
ICC
∆ICC
Supply current
VO = 0 V,
Supply-current change over operating
temperature range
No load
UNIT
TYP
MAX
625
690
Full range
715
Full range
µA
A
A
µA
36
† Full range is 0°C to 70°C.
TLE2062C operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER
TEST CONDITIONS
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
THD
Total harmonic distortion
VO(PP) = 2 V,
AVD = 2,
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 600 Ω,
Settling time
BOM
φm
Maximum output-swing bandwidth
Phase margin at unity gain (see Figure 3)
TLE2062C
TLE2062AC
TLE2062BC
MIN
TYP
25°C
2.6
3.4
Full range
2.5
UNIT
MAX
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
25°C
70
100
f = 1 kHz,
RS = 20 Ω
25°C
40
60
f = 0.1 Hz to 10 Hz
25°C
1.1
µV
f = 1 kHz
25°C
1.1
fA/√Hz
RL = 10 kΩ,
f = 10 kHz
25°C
0.025%
CL = 10 0 pF
25°C
2
CL = 100 pF
25°C
1.5
0.1%
25°C
5
0.01%
25°C
10
V/ s
V/µs
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
25°C
40
CL = 100 pF
25°C
60°
RL = 600 Ω,
CL = 100 pF
25°C
70°
† Full range is 0°C to 70°C.
22
TA†
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
nV/√Hz
MHz
µss
kHz
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2062I
TLE2062AI
TLE2062BI
MIN
25°C
TLE2062I
Input offset voltage
TLE2062AI
RS = 50 Ω
VIC = 0,
Input offset voltage long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
6.3
0.7
Full range
VOM +
VOM −
µV/°C
25°C
0.04
µV/mo
25°C
1
−1.6
to
4
Full range
−1.6
to
4
25°C
3.5
Full range
3.1
25°C
2.5
25°C
−3.7
RL = 10 kΩ
Full range
−3.1
25°C
−2.5
Large-signal differential voltage amplification
RL = 10 kΩ
−2
25°C
15
0.75
0.5
RL = 100 Ω
Full range
RL = 100 Ω
25°C
0.5
VO = 0 to − 2 V,
Full range
0.25
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
IO = 0
CMRR
Common-mode rejection ratio
VIC = VICRmin, RS = 50 Ω
kSVR
Supply-voltage rejection ratio (∆VCC ± /∆VIO)
VCC ± = ± 5 V to ± 15 V,
RS = 50 Ω
V
V
3.7
3.1
V
−3.9
−2.7
V
80
2
25°C
VO = 0 to 2 V,
ri
nA
2
Full range
Full range
−2
to
6
nA
pA
4
Full range
VO = ± 2.8 V,
AVD
3
RL = 100 Ω
RL = 100 Ω
pA
2
25°C
Common-mode input voltage range
Maximum negative peak output voltage swing
3
6
Full range
Full range
Maximum positive peak output voltage swing
mV
4.3
Full range
RL = 10 kΩ
4
5.3
25°C
VICR
5
0.9
25°C
Temperature coefficient of input offset voltage
MAX
1
Full range
TLE2062BI
αVIO
TYP
Full range
25°C
VIO
UNIT
45
V/mV
3
1012
Ω
25°C
4
pF
25°C
560
Ω
25°C
25°C
65
Full range
65
25°C
75
Full range
65
82
dB
93
dB
† Full range is − 40°C to 85°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150 °C extrapolated
to TA = 25 °C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062I electrical characteristics at specified free-air temperature, VCC ± = ±5 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLE2062I
TLE2062AI
TLE2062BI
MIN
25°C
ICC
∆ICC
Supply current
Supply-current change over operating
temperature range
VO = 0,
No load
UNIT
TYP
MAX
560
620
Full range
640
Full range
µA
A
µA
54
† Full range is − 40°C to 85°C.
TLE2062I operating characteristics at specified free-air temperature, VCC ± = ±5 V
PARAMETER
TEST CONDITIONS
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
THD
Total harmonic distortion
VO(PP) = 2 V,
AVD = 2,
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 100 Ω,
Settling time
BOM
φm
Maximum output-swing bandwidth
Phase margin at unity gain (see Figure 3)
MIN
TYP
25°C
2.2
3.4
Full range
1.7
UNIT
MAX
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
25°C
59
100
f = 1 kHz,
RS = 20 Ω
25°C
43
60
f = 0.1 Hz to 10 Hz
25°C
1.1
f = 1 kHz
25°C
1
RL = 10 kΩ,
f = 10 kHz
25°C
0.025%
CL = 100 pF
25°C
1.8
CL = 100 pF
25°C
1.3
V/ s
V/µs
0.1%
25°C
5
0.01%
25°C
10
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
25°C
140
CL = 100 pF
25°C
58°
RL = 100 Ω,
CL = 100 pF
25°C
75°
† Full range is − 40°C to 85°C.
24
TA†
TLE2062I
TLE2062AI
TLE2062BI
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
nV/√Hz
µV
fA/√Hz
MHz
µss
kHz
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2062I
TLE2062AI
TLE2062BI
MIN
25°C
TLE2062I
Input offset voltage
TLE2062AI
RS = 50 Ω
VIC = 0,
Input offset voltage long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
5.3
0.5
Full range
VOM +
µV/°C
25°C
0.04
µV/mo
25°C
2
−11
to
13
25°C
13.2
25°C
RL = 600 Ω
Full range
RL = 10 kΩ
Full range
Maximum negative peak output voltage swing
25°C
VO = ± 10 V,
Large-signal differential voltage amplification
RL = 10 kΩ
−13.2
−12.5
Full range
−12
25°C
30
Full range
20
25°C
25
10
RL = 600 Ω
25°C
3
VO = 0 to − 8 V,
Full range
1
Input capacitance
zo
Open-loop output impedance
IO = 0
CMRR
Common-mode rejection ratio
VIC = VICRmin, RS = 50 Ω
kSVR
Supply-voltage rejection ratio (∆VCC ± /∆VIO)
VCC ± = ± 5 V to ± 15 V,
RS = 50 Ω
V
13.7
13.2
V
−13.7
−13
Full range
ci
V
12
RL = 600 Ω
Input resistance
nA
13
12.5
VO = 0 to 8 V,
ri
−12
to
16
nA
pA
5
Full range
Full range
RL = 600 Ω
AVD
4
−11
to
13
Common-mode input voltage range
pA
3
25°C
25°C
VOM −
1
6
Full range
Full range
Maximum positive peak output voltage swing
mV
2.3
Full range
RL = 10 kΩ
2
3.3
25°C
VICR
4
0.8
25°C
Temperature coefficient of input offset voltage
MAX
0.9
Full range
TLE2062BI
αVIO
TYP
Full range
25°C
VIO
UNIT
−13
V
230
100
V/mV
25
1012
Ω
25°C
4
pF
25°C
560
Ω
25°C
25°C
72
Full range
65
25°C
75
Full range
65
90
dB
93
dB
† Full range is − 40°C to 85°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150 °C extrapolated
to TA = 25 °C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLE2062I
TLE2062AI
TLE2062BI
MIN
25°C
ICC
∆ICC
Supply current
Supply-current change over operating
temperature range
VO = 0,
No load
UNIT
TYP
MAX
625
690
Full range
720
Full range
µA
A
µA
74
† Full range is − 40°C to 85°C.
TLE2062I operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER
TEST CONDITIONS
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
THD
Total harmonic distortion
VO(PP) = 2 V,
AVD = 2,
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 600 Ω,
Settling time
BOM
φm
Maximum output-swing bandwidth
Phase margin at unity gain (see Figure 3)
MIN
TYP
25°C
2.6
3.4
Full range
2.1
UNIT
MAX
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
25°C
70
100
f = 1 kHz,
RS = 20 Ω
25°C
40
60
f = 0.1 Hz to 10 Hz
25°C
1.1
µV
f = 1 kHz
25°C
1.1
fA/√Hz
RL = 10 kΩ,
f = 10 kHz
25°C
0.025%
CL = 100 pF
25°C
2
CL = 100 pF
25°C
1.5
V/ s
V/µs
0.1%
25°C
5
0.01%
25°C
10
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
25°C
40
CL = 100 pF
25°C
60°
RL = 600 Ω,
CL = 100 pF
25°C
70°
† Full range is − 40°C to 85°C.
26
TA†
TLE2062I
TLE2062AI
TLE2062BI
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
nV/√Hz
MHz
µss
kHz
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062M electrical characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER
TEST CONDITIONS
TA†
TLE2062M
TLE2062AM
TLE2062BM
MIN
25°C
TLE2062M
Input offset voltage
TLE2062AM
RS = 50 Ω
VIC = 0,
Input offset voltage long-term drift (see Note 4)
IIO
7
Input offset current
0.7
Full range
VICR
VOM +
6
µV/°C
0.04
µV/mo
25°C
1
15
Full range
−1.6
to
4
25°C
3.5
25°C
FK and JG
packages
RL = 600 Ω
Full range
D and P
packages
RL = 100 Ω
Full range
RL = 10 kΩ
Full range
FK and JG
packages
RL = 600 Ω
Full range
D and P
packages
RL = 100 Ω
25°C
25°C
VOM −
AVD
Maximum negative peak output
voltage swing
Large-signal differential voltage
amplification
FK and JG
packages
D and P
packages
25°C
25°C
2.5
V
V
3.7
3.6
V
2
2.5
3.1
2
−3.5
−3.9
−3
−2.5
−3.5
V
−2
−2.5
−2
25°C
15
2
VO = ± 2.8 V,
RL = 10 kΩ
Full range
VO = 0 to 2.5 V,
RL = 600 Ω
Full range
VO = 0 to − 2.5 V,
RL = 600 Ω
Full range
0.5
RL = 100 Ω
25°C
0.75
VO = 0 to 2 V,
Full range
0.5
RL = 100 Ω
25°C
0.5
VO = 0 to − 2 V,
Full range
0.25
25°C
nA
3
Full range
25°C
−2
to
6
nA
pA
30
−1.6
to
4
Full range
pA
3
25°C
Common-mode input voltage range
Maximum positive peak output
voltage swing
3
25°C
Full range
Full range
RL = 10 kΩ
mV
5
Full range
Input bias current
4
6
25°C
IIB
5
0.9
25°C
Temperature coefficient of input offset voltage
MAX
1
Full range
TLE2062BM
αVIO
TYP
Full range
25°C
VIO
UNIT
1
−2.7
80
65
0.5
1
16
V/mV
45
3
† Full range is − 55°C to 125°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150 °C extrapolated
to TA = 25 °C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER
TA†
TEST CONDITIONS
TLE2062M
TLE2062AM
TLE2062BM
MIN
ri
Input resistance
25°C
ci
Input capacitance
zo
Open-loop output impedance
CMRR
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio (∆VCC ± /∆VIO)
ICC
Supply current (two amplifiers)
4
pF
560
Ω
65
Full range
60
VCC ± = ± 5 V to ± 15 V,
RS = 50 Ω
25°C
75
Full range
65
25°C
∆ICC
Supply-current change over operating
temperature range (two amplifiers)
Ω
25°C
25°C
82
dB
93
dB
560
Full range
No load
MAX
25°C
IO = 0
VIC = VICRmin
RS = 50 Ω,,
VO = 0,
TYP
1012
UNIT
620
650
Full range
µA
A
µA
A
72
† Full range is − 55°C to 125°C.
TLE2062M operating characteristics at specified free-air temperature, TA = 25°C, VCC ± = ±5 V
PARAMETER
TEST CONDITIONS
TLE2062M
TLE2062AM
TLE2062BM
MIN
SR
Slew rate at unity gain (see Figure 1)
TYP
RL = 10 kΩ,
CL = 100 pF
3.4
f = 10 Hz,
RS = 20 Ω
59
f = 1 kHz,
RS = 20 Ω
43
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
Equivalent input noise current
f = 1 kHz
THD
Total harmonic distortion
VO(PP) = 2 V,
AVD = 2,
RL = 10 kΩ,
f = 10 kHz
0.025%
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
1.8
B1
RL = 600 Ω,
CL = 100 pF
1.3
Settling time
BOM
φm
28
Maximum output-swing bandwidth
Phase margin at unity gain (see Figure 3)
POST OFFICE BOX 655303
1.1
1
0.1%
5
0.01%
10
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
140
CL = 100 pF
58°
RL = 600 Ω,
CL = 100 pF
75°
• DALLAS, TEXAS 75265
UNIT
MAX
V/µs
nV/√Hz
µV
fA/√Hz
MHz
µss
kHz
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2062M
TLE2062AM
TLE2062BM
MIN
25°C
TLE2062M
Input offset voltage
TLE2062AM
RS = 50 Ω
VIC = 0,
Input offset voltage long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
6
0.5
Full range
VOM +
µV/°C
25°C
0.04
µV/mo
25°C
2
Full range
−11
to
13
25°C
13
Full range
12.5
25°C
12.5
Full range
RL = 10 kΩ
Full range
−12.5
25°C
−12.5
Maximum negative peak output voltage swing
VO = ± 10 V,
Large-signal differential voltage amplification
RL = 10 kΩ
−13
Full range
−11
25°C
30
Full range
20
25°C
25
RL = 600 Ω
Full range
7
RL = 600 Ω
25°C
3
VO = 0 to − 8 V,
Full range
1
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
IO = 0
CMRR
Common-mode rejection ratio
VIC = VICRmin,
kSVR
Supply-voltage rejection ratio (∆VCC ± /∆VIO)
VCC ± = ± 5 V to ± 15 V,
RS = 50 Ω
V
V
13.7
13.2
V
−13.7
−13
V
230
100
V/mV
25
1012
Ω
25°C
4
pF
25°C
560
Ω
25°C
RS = 50 Ω
nA
11
VO = 0 to 8 V,
ri
−12
to
16
nA
pA
40
RL = 600 Ω
RL = 600 Ω
AVD
4
−11
to
13
Common-mode input voltage range
pA
20
25°C
25°C
VOM −
1
3
Full range
Maximum positive peak output voltage swing
mV
6
Full range
Full range
RL = 10 kΩ
2
4
25°C
VICR
4
0.8
25°C
Temperature coefficient of input offset voltage
MAX
0.9
Full range
TLE2062BM
αVIO
TYP
Full range
25°C
VIO
UNIT
25°C
72
Full range
65
25°C
75
Full range
65
90
dB
93
dB
† Full range is − 55°C to 125°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150 °C extrapolated
to TA = 25 °C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2062M
TLE2062AM
TLE2062BM
MIN
25°C
ICC
∆ICC
Supply current
Supply-current change over operating
temperature range
VO = 0,
No load
UNIT
TYP
MAX
625
690
Full range
730
Full range
µA
A
µA
97
† Full range is − 55°C to 125°C.
TLE2062M operating characteristics at specified free-air temperature, VCC ± = ±15 V
PARAMETER
TEST CONDITIONS
TA†
25°C
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
THD
Total harmonic distortion
VO(PP) = 2 V,
AVD = 2,
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 600 Ω,
Settling time
BOM
φm
Maximum output-swing bandwidth
Phase margin at unity gain (see Figure 3)
MIN
TYP
2
3.4
UNIT
MAX
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
25°C
70
f = 1 kHz,
RS = 20 Ω
25°C
40
f = 0.1 Hz to 10 Hz
25°C
1.1
µV
f = 1 kHz
25°C
1.1
fA/√Hz
RL = 10 kΩ,
f = 10 kHz
25°C
0.025%
CL = 100 pF
25°C
2
CL = 100 pF
25°C
1.5
0.1%
25°C
5
0.01%
25°C
10
Full range
V/ s
V/µs
1.8
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
25°C
40
CL = 100 pF
25°C
60°
RL = 600 Ω,
CL = 100 pF
25°C
70°
† Full range is − 55°C to 125°C.
30
TLE2062M
TLE2062AM
TLE2062BM
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
nV/√Hz
MHz
µss
kHz
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2062Y electrical characteristics at VCC± = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
αVIO
Input offset voltage
IIO
IIB
Input offset current
VICR
Common-mode input voltage range
VOM +
Maximum positive peak output voltage swing
VOM −
Maximum negative peak output voltage swing
AVD
0.9
Input offset voltage long-term drift (see Note 4)
VIC = 0,
Large-signal differential voltage amplification
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
CMRR
Common-mode rejection ratio
RS = 50 Ω
UNIT
mV
µV/mo
2
pA
4
pA
−11
to
13
−12
to
16
V
RL = 10 kΩ
RL = 600 Ω
13.2
13.7
12.5
13.2
RL = 10 kΩ
RL = 600 Ω
−13.2
−13.7
−12.5
−13
V
V
VO = ±10 V,
VO = 0 to 8 V,
RL = 10 kΩ
30
230
RL = 600 Ω
25
100
VO = 0 to − 8 V,
RL = 600 Ω
3
25
12
10
Ω
4
pF
560
Ω
72
90
dB
75
93
dB
IO = 0
VIC = VICRmin,
Supply-voltage rejection ratio (∆VCC /∆VIO)
4
0.04
Input bias current
ri
kSVR
TLE2062Y
MIN
TYP
MAX
RS = 50 Ω
VCC ± = ± 5 V to ±15 V,
RS = 50 Ω
V/mV
ICC
Supply current
VO = 0,
No load
625
690
µA
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150 °C extrapolated
to TA = 25 °C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
TLE2062Y operating characteristics at VCC± = ±15 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLE2062Y
MIN
TYP
MAX
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
Equivalent input noise current
f = 1 Hz
THD
Total harmonic distortion
VO(PP) = 2 V,
AVD = 2,
RL = 10 kΩ,
f = 10 kHz
0.025%
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
2
B1
RL = 600 Ω,
CL = 100 pF
1.5
Settling time
BOM
φm
Maximum output-swing bandwidth
Phase margin at unity gain (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
2.6
3.4
f = 10 Hz,
RS = 20 Ω
70
f = 1 kHz,
RS = 20 Ω
40
nV/√Hz
µV
1.1
fA/√Hz
0.1%
5
10
AVD = 1,
RL = 10 kΩ,
RL = 10 kΩ
40
CL = 100 pF
60°
RL = 600 Ω,
CL = 100 pF
70°
• DALLAS, TEXAS 75265
V/µs
1.1
0.01%
POST OFFICE BOX 655303
4
UNIT
MHz
µss
kHz
31
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TLE2064C
TLE2064AC
TLE2064BC
TA†
MIN
25°C
TLE2064C
VIO
Input offset voltage
Temperature coefficient of input offset voltage
IIB
VICR
RS = 50 Ω
VIC = 0,
6
µV/°C
0.04
µV/mo
Maximum positive peak output voltage swing
0.8
25°C
Full range
−1.6
to
4
Maximum negative peak output voltage swing
RL = 100 Ω
Large-signal differential voltage amplification
25°C
3.5
Full range
3.3
25°C
2.5
−2
to
6
nA
pA
2
−1.6
to
4
Full range
pA
3
Full range
Common-mode input voltage range
3.5
1
25°C
Input bias current
mV
4.4
25°C
Full range
RL = 10 kΩ
A VD
0.8
Full range
25°C
Input offset current
6
6.9
Full range
RL = 100 Ω
VOM −
1.2
25°C
RL = 10 kΩ
VOM +
7
Full range
Input offset voltage long-term drift (see Note 4)
IIO
MAX
1.2
7.9
25°C
TLE2064BC
αVIO
TYP
Full range
TLE2064AC
UNIT
nA
V
V
3.7
3.1
V
2
25°C
−3.7
Full range
−3.3
25°C
−2.5
Full range
−2
25°C
15
Full range
2
VO = ± 2.8 V,
RL = 10 kΩ
VO = 0 to 2 V,
RL = 100 Ω
25°C
0.75
Full range
0.5
VO = 0 to − 2 V,
RL = 100 Ω
25°C
0.5
Full range
0.15
−3.9
−2.7
V
80
45
V/mV
3
ri
Input resistance
25°C
1012
Ω
ci
Input capacitance
25°C
4
pF
zo
Open-loop output impedance
IO = 0
25°C
560
Ω
CMRR
Common-mode rejection ratio
VIC = VICRmin,
kSVR
Supply-voltage rejection ratio (∆VCC
CC± /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
RS = 50 Ω
25°C
65
Full range
65
25°C
75
Full range
75
82
93
dB
dB
† Full range is 0°C to 70°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064C electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TLE2064C
TLE2064AC
TLE2064BC
TA†
MIN
25°C
ICC
∆ICC
Supply current (four amplifiers)
Supply-current change over operating
temperature range (four amplifiers)
VO1/ VO2 Crosstalk attenuation
† Full range is 0°C to 70°C.
VO = 0,
No load
AVD = 1000,
f = 1 kHz
UNIT
TYP
MAX
1.12
1.3
Full range
1.3
mA
Full range
52
A
µA
25°C
120
dB
TLE2064C operating characteristics at specified free-air temperature, VCC± = ±5 V
PARAMETER
TEST CONDITIONS
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
f = 1 kHz ,
RS = 20 Ω
MIN
TYP
25°C
2.2
3.4
Full range
2.1
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
25°C
1.1
Equivalent input noise current
f = 1 kHz
25°C
1
THD
Total harmonic distortion
A VD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
25°C
0.025%
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 100 Ω,
CL = 100 pF
ts
Settling time
ε = 0.01%
BOM
Maximum output-swing bandwidth
A VD = 1,
RL = 10 kΩ
RL = 10 kΩ,
CL = 100 pF
RL = 100 Ω,
CL = 100 pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
φm
RL = 10 kΩ,
TA†
TLE2064C
TLE2064AC
TLE2064BC
CL = 100 pF
ε = 0.1%
Phase margin at unity gain (see Figure 3)
25°C
UNIT
MAX
V/ s
V/µs
59
100
43
60
nV/√Hz
µV
fA/√Hz
1.8
25°C
1.3
5
25°C
25°C
25°C
10
140
MHz
µss
kHz
58°
75°
† Full range is 0°C to 70°C.
33
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLE2064C
TLE2064AC
TLE2064BC
MIN
25°C
TLE2064C
0.9
Full range
Input offset voltage
TLE2064AC
0.9
Full range
αVIO
Temperature coefficient of input offset voltage
RS = 50 Ω
VIC = 0,
Input offset voltage long-term drift (see Note 4)
0.7
Full range
Input offset current
IIB
Input bias current
Full range
RL = 10 kΩ
VOM +
Maximum positive peak output voltage swing
25°C
13.2
Full range
RL = 10 kΩ
Full range
Maximum negative peak output voltage swing
25°C
Large-signal differential voltage amplification
ri
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
12.5
−13.2
−12.5
Full range
−12
25°C
30
20
RL = 600 Ω
25°C
25
VO = 0 to 8 V,
Full range
10
RL = 600 Ω
25°C
3
VO = 0 to − 8 V,
Full range
1
RS = 50 Ω
kSVR
Supply-voltage rejection ratio (∆VCC±
CC /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
13.7
13.2
V
−13.7
−13
V
230
100
V/mV
25
1012
Ω
25°C
4
pF
25°C
560
Ω
25°C
VIC = VICRmin,
V
−13
Full range
Common-mode rejection ratio
V
12
RL = 10 kΩ
CMRR
nA
13
VO = ± 10 V,
IO = 0
−12
to
16
nA
pA
3
−11
to
13
RL = 600 Ω
RL = 600 Ω
A VD
4
Full range
25°C
pA
1
25°C
25°C
VOM −
µV/°C
µV/mo
2
−11
to
13
Full range
2
0.04
Full range
Common-mode input voltage range
mV
6
Full range
25°C
VICR
4
4
25°C
25°C
IIO
6
4.9
25°C
TLE2064BC
MAX
6.9
25°C
VIO
TYP
UNIT
25°C
72
Full range
70
25°C
75
Full range
75
90
dB
93
dB
† Full range is 0°C to 70°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLE2064C
TLE2064AC
TLE2064BC
MIN
ICC
∆ICC
25°C
Supply current (four amplifiers)
Supply-current change over operating
temperature range (four amplifiers)
VO1/ VO2 Crosstalk attenuation
† Full range is 0°C to 70°C.
VO = 0,
AVD = 1000,
No load
f = 1 kHz
UNIT
TYP
MAX
1.25
1.4
Full range
1.5
mA
Full range
72
µA
25°C
120
dB
TLE2064C operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER
TEST CONDITIONS
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
Equivalent input noise current
f = 1 kHz
THD
Total harmonic distortion
A VD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
ts
Settling time
ε = 0.01%
BOM
Maximum output-swing bandwidth
A VD = 1,
RL = 10 kΩ
RL = 10 kΩ,
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
φm
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
f = 1 kHz ,
RS = 20 Ω
ε = 0.1%
Phase margin at unity gain (see Figure 3)
TA†
TLE2064C
TLE2064AC
TLE2064BC
MIN
TYP
25°C
2.6
3.4
Full range
2.5
25°C
UNIT
MAX
V/ s
V/µs
70
100
40
60
25°C
1.1
25°C
1
25°C
0.025%
nV/√Hz
µV
fA/√Hz
2
25°C
1.5
5
25°C
25°C
25°C
10
40
MHz
µss
kHz
50°
70°
† Full range is 0°C to 70°C.
35
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TLE2064I
TLE2064AI
TLE2064BI
TA†
MIN
25°C
TLE2064I
VIO
Input offset voltage
Temperature coefficient of input offset voltage
IIB
VICR
VIC = 0,
RS = 50 Ω
6
µV/°C
0.04
µV/mo
Maximum positive peak output voltage swing
2
25°C
Full range
−1.6
to
4
Maximum negative peak output voltage swing
RL = 100 Ω
Large-signal differential voltage amplification
25°C
3.5
Full range
3.1
25°C
2.5
−2
to
6
nA
pA
4
−1.6
to
4
Full range
pA
3
Full range
Common-mode input voltage range
3.5
1
25°C
Input bias current
mV
4.8
25°C
Full range
RL = 10 kΩ
A VD
0.8
Full range
25°C
Input offset current
6
7.3
Full range
RL = 100 Ω
VOM −
1.2
25°C
RL = 10 kΩ
VOM +
7
Full range
Input offset voltage long-term drift (see Note 4)
IIO
MAX
1.2
8.3
25°C
TLE2064BI
αVIO
TYP
Full range
TLE2064AI
UNIT
nA
V
V
3.7
3.1
V
2
25°C
−3.7
Full range
−3.1
25°C
−2.5
Full range
−2
25°C
15
Full range
2
VO = ± 2.8 V,
RL = 10 kΩ
VO = 0 to 2 V,
RL = 100 Ω
25°C
0.75
Full range
0.5
VO = 0 to − 2 V, RL = 100 Ω
25°C
0.5
Full range
0.15
−3.9
−2.7
V
80
45
V/mV
3
ri
Input resistance
25°C
1012
Ω
ci
Input capacitance
25°C
4
pF
zo
Open-loop output impedance
IO = 0
25°C
560
Ω
CMRR
Common-mode rejection ratio
VIC = VICRmin, RS = 50 Ω
25°C
65
Full range
65
kSVR
Supply-voltage rejection ratio (∆VCC
CC± /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
25°C
75
Full range
65
82
93
dB
dB
† Full range is − 40°C to 85°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064I electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TLE2064I
TLE2064AI
TLE2064BI
TA†
MIN
ICC
∆ICC
25°C
Supply current (four amplifiers)
Supply-current change over operating
temperature range (four amplifiers)
VO1/ VO2 Crosstalk attenuation
† Full range is − 40°C to 85°C.
VO = 0,
No load
AVD = 1000,
f = 1 kHz
UNIT
TYP
MAX
1.12
1.3
Full range
1.3
mA
Full range
108
µA
25°C
120
dB
TLE2064I operating characteristics at specified free-air temperature, VCC± = ±5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
TA†
TLE2064I
TLE2064AI
TLE2064BI
MIN
TYP
25°C
2.2
3.4
Full range
1.7
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
25°C
1.1
Equivalent input noise current
f = 1 kHz
25°C
1
THD
Total harmonic distortion
A VD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
25°C
0.025%
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 100 Ω,
CL = 100 pF
ts
Settling time
ε = 0.01%
BOM
Maximum output-swing bandwidth
A VD = 1,
RL = 10 kΩ
φm
Phase margin at unity gain (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
RL = 100 Ω,
CL = 100 pF
f = 1 kHz ,
f = 1 kHz ,
CL = 100 pF
ε = 0.1%
25°C
UNIT
MAX
V/ s
V/µs
59
100
43
60
nV/√Hz
µV
fA/√Hz
1.8
25°C
1.3
5
25°C
25°C
25°C
10
140
MHz
µss
kHz
58°
75°
† Full range is − 40°C to 85°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TLE2064I
TLE2064AI
TLE2064BI
TA†
MIN
25°C
TLE2064I
VIO
Input offset voltage
Temperature coefficient of input offset voltage
IIB
VICR
RS = 50 Ω
VIC = 0,
25°C
6
µV/°C
0.04
µV/mo
3
25°C
Full range
−11
to
13
25°C
13.2
Maximum positive peak output voltage swing
25°C
Full range
25°C
Full range
Maximum negative peak output voltage swing
25°C
RL = 600 Ω
Large-signal differential voltage amplification
−12
to
16
nA
V
V
13.7
13
12.5
nA
pA
5
−11
to
13
Full range
pA
4
Full range
Common-mode input voltage range
2
2
25°C
Input bias current
mV
3.3
Full range
RL = 10 kΩ
A VD
0.7
Full range
25°C
Input offset current
4
5.3
Full range
RL = 600 Ω
VOM −
0.9
25°C
RL = 10 kΩ
VOM +
6
Full range
Input offset voltage long-term drift (see Note 4)
IIO
MAX
0.9
7.3
25°C
TLE2064BI
αVIO
TYP
Full range
TLE2064AI
UNIT
13.2
V
12
−13.2
−13.7
−13
−12.5
Full range
−12
25°C
30
Full range
20
VO = ± 10 V,
RL = 10 kΩ
VO = 0 to 8 V,
RL = 600 Ω
25°C
25
Full range
10
VO = 0 to − 8 V,
RL = 600 Ω
25°C
3
Full range
1
−13
V
230
100
V/mV
25
ri
Input resistance
25°C
1012
Ω
ci
Input capacitance
25°C
4
pF
zo
Open-loop output impedance
IO = 0
25°C
560
Ω
CMRR
Common-mode rejection ratio
VIC = VICRmin,
kSVR
Supply-voltage rejection ratio (∆VCC
CC± /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
RS = 50 Ω
25°C
72
Full range
65
25°C
75
Full range
65
90
93
dB
dB
† Full range is − 40°C to 85°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TLE2064I
TLE2064AI
TLE2064BI
TA†
MIN
ICC
∆ICC
25°C
Supply current (four amplifiers)
Supply-current change over operating
temperature range (four amplifiers)
VO1/ VO2 Crosstalk attenuation
† Full range is − 40°C to 85°C.
VO = 0,
No load
AVD = 1000,
f = 1 kHz
UNIT
TYP
MAX
1.25
1.4
Full range
1.5
mA
Full range
148
µA
25°C
120
dB
TLE2064I operating characteristics at specified free-air temperature, VCC± = ± 15 V
PARAMETER
TEST CONDITIONS
CL = 100 pF
f = 10 Hz,
RS = 20 Ω,
f = 1 kHz ,
RS = 20 Ω
MIN
TYP
25°C
2.6
3.4
Full range
2.1
UNIT
MAX
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
25°C
1.1
µV
Equivalent input noise current
f = 1 kHz
25°C
1.1
fA/√Hz
THD
Total harmonic distortion
A VD = 2,
RL = 10 kΩ
f = 10 kHz,
VO(PP) = 2 V,
25°C
0.025%
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
ts
Settling time
ε = 0.01%
BOM
Maximum output-swing bandwidth
A VD = 1,
RL = 10 kΩ
RL = 10 kΩ,
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
φm
RL = 10 kΩ,
TA†
TLE2064I
TLE2064AI
TLE2064BI
ε = 0.1%
Phase margin at unity gain (see Figure 3)
25°C
V/ s
V/µs
70
100
40
60
nV/√Hz
2
25°C
1.5
5
25°C
25°C
25°C
10
40
MHz
µss
kHz
60°
70°
† Full range is − 40°C to 85°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064M electrical characteristics at specified free-air temperature, VCC± = ±5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TLE2064M
TLE2064AM
TLE2064BM
TA†
MIN
25°C
TLE2064M
Input offset voltage
TLE2064AM
RS = 50 Ω
VIC = 0,
Input offset voltage long-term drift (see Note 4)
0.8
Full range
25°C
VICR
VOM +
Maximum positive peak output
voltage swing
Maximum negative peak output
voltage swing
A VD
3
−1.6
to
4
25°C
3.5
FK and J
packages
RL = 600 Ω
Full range
D and N
packages
RL = 100 Ω
25°C
25°C
Full range
RL = 10 kΩ
Full range
FK and J
packages
RL = 600 Ω
Full range
D and N
packages
RL = 100 Ω
FK and J
packages
25°C
25°C
RL = 10 kΩ
2.5
2.5
−2.5
−2.5
2
25°C
V
3.1
−3.9
−3.5
V
−2
Full range
Full range
3.6
−3
15
VO = 0 to − 2.5 V, RL = 600 Ω
3.7
2
−3.5
−2
Full range
V
V
2
25°C
RL = 600 Ω
VO = 0 to 2.5 V,
nA
3
Full range
25°C
−2
to
6
nA
pA
30
Full range
Full range
pA
15
25°C
RL = 10 kΩ
VO = ± 2.8 V,
Large-signal differential voltage
amplification
µV/°C
µV/mo
1
−1.6
to
4
25°C
VOM −
6
Full range
Common-mode input voltage range
3.5
0.04
Full range
Input bias current
mV
5.5
Full range
Input offset current
6
8
25°C
IIB
7
9
25°C
IIO
1.2
1.2
25°C
Temperature coefficient of input offset voltage
MAX
Full range
TLE2064BM
αVIO
TYP
Full range
25°C
VIO
UNIT
1
−2.7
80
65
V/mV
0.5
1
16
0.5
† Full range is − 55°C to 125°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064M electrical characteristics at specified free-air temperature, VCC± = ± 5 V (unless
otherwise noted) continued)
PARAMETER
TLE2064M
TLE2064AM
TLE2064BM
TA†
TEST CONDITIONS
MIN
A VD
Large-signal differential voltage
amplification
ri
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
D and N
packages
VO = 0 to 2 V,
RL = 100 Ω
VO = 0 to − 2 V, RL = 100 Ω
TYP
25°C
0.75
Full range
0.25
25°C
0.4
Full range
0.15
4
pF
25°C
560
Ω
25°C
65
VIC = VICRmin, RS = 50 Ω
Full range
60
75
Supply-voltage rejection ratio (∆VCC±
CC /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
25°C
kSVR
Full range
65
ICC
Supply current (four amplifiers)
25°C
Supply-current change over operating
temperature range (four amplifiers)
VO1/ VO2 Crosstalk attenuation
† Full range is − 55°C to 125°C.
82
dB
93
dB
1.12
Full range
No load
AVD = 1000,
V/mV
3
25°C
Common-mode rejection ratio
∆ICC
45
Ω
CMRR
VO = 0,
MAX
1012
25°C
IO = 0
f = 1 kHz
UNIT
1.3
1.3
mA
Full range
144
µA
25°C
120
dB
TLE2064M operating characteristics, VCC± = ±5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLE2064M
TLE2064AM
TLE2064BM
MIN
SR
Slew rate at unity gain (see Figure 1)
TYP
MAX
RL = 10 kΩ,
CL = 100 pF
3.4
f = 10 Hz,
RS = 20 Ω
59
f = 1 kHz ,
RS = 20 Ω
43
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
Equivalent input noise current
f = 1 kHz
THD
Total harmonic distortion
A VD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
0.025%
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 600 Ω,
CL = 100 pF
1.8
B1
CL = 100 pF
1.3
Settling time
ε = 0.1%
5
ts
ε = 0.01%
10
BOM
Maximum output-swing bandwidth
A VD = 1,
RL = 10 kΩ
140
φm
Phase margin at unity gain (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
58°
RL = 600 Ω,
CL = 100 pF
75°
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
1.1
1
V/µs
nV/√Hz
µV
fA/√Hz
MHz
µss
kHz
41
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TLE2064M
TLE2064AM
TLE2064BM
TA†
MIN
25°C
TLE2064M
VIO
Input offset voltage
Temperature coefficient of input offset voltage
IIB
VICR
RS = 50 Ω
VIC = 0,
25°C
6
µV/°C
0.04
µV/mo
4
25°C
Full range
−11
to
13
Maximum positive peak output voltage swing
25°C
12.5
Full range
12
25°C
−13
25°C
RL = 600 Ω
Large-signal differential voltage amplification
12.5
Full range
Maximum negative peak output voltage swing
13
Full range
Full range
−12
to
16
nA
V
V
13.7
13.2
V
−13.7
−12.5
−13
nA
pA
40
−11
to
13
25°C
pA
20
Full range
Common-mode input voltage range
2
2
25°C
Input bias current
mV
4
25°C
Full range
RL = 10 kΩ
A VD
0.7
Full range
Input offset current
4
6
25°C
RL = 600 Ω
VOM −
0.9
Full range
RL = 10 kΩ
VOM +
6
Full range
Input offset voltage long-term drift
(see Note 4)
IIO
MAX
0.9
8
25°C
TLE2064BM
αVIO
TYP
Full range
TLE2064AM
UNIT
−13
V
−12.5
25°C
30
VO = ± 10 V,
RL = 10 kΩ
Full range
20
VO = 0 to 8 V,
RL = 600 Ω
25°C
25
Full range
7
VO = 0 to − 8 V,
RL = 600 Ω
25°C
3
Full range
1
230
100
V/mV
25
ri
Input resistance
25°C
1012
Ω
ci
Input capacitance
25°C
4
pF
zo
Open-loop output impedance
560
Ω
IO = 0
25°C
RS = 50 Ω
CMRR
Common-mode rejection ratio
VIC = VICRmin,
kSVR
Supply-voltage rejection ratio (∆VCC
CC± /∆VIO)
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
25°C
72
Full range
65
25°C
75
Full range
65
90
93
dB
dB
† Full range is − 55°C to 125°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLE2064M
TLE2064AM
TLE2064BM
MIN
ICC
∆ICC
25°C
Supply current (four amplifiers)
Supply-current change over operating
temperature range (four amplifiers)
VO1/ VO2 Crosstalk attenuation
† Full range is − 55°C to 125°C.
VO = 0,
No load
AVD = 1000,
f = 1 kHz
UNIT
TYP
MAX
1.25
1.4
Full range
1.5
mA
Full range
194
µA
25°C
120
dB
TLE2064M operating characteristics at specified free-air temperature, VCC± = ±15 V
PARAMETER
TEST CONDITIONS
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
TLE2064M
TLE2064AM
TLE2064BM
MIN
TYP
25°C
2.6
3.4
Full range
1.8
UNIT
MAX
SR
Slew rate at unity gain (see Figure 1)
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
25°C
1.1
V
µV
Equivalent input noise current
f = 1 kHz
25°C
1.1
fA/√Hz
THD
Total harmonic distortion
A VD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
25°C
0.025%
B1
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
ts
Settling time
ε = 0.01%
BOM
Maximum output-swing bandwidth
A VD = 1,
RL = 10 kΩ
RL = 10 kΩ,
CL = 100 pF
RL = 600 Ω,
CL = 100 pF
φm
RL = 10 kΩ,
TA†
RS = 20 Ω
f = 1 kHz ,
ε = 0.1%
Phase margin at unity gain (see Figure 3)
V/ s
V/µs
70
25°C
40
nV/√Hz
2
25°C
1.5
5
25°C
25°C
25°C
10
40
MHz
µss
kHz
60°
70°
† Full range is − 55°C to 125°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TLE2064Y electrical characteristics at VCC± = ±15 V, TA = 25°C (unless otherwise noted)
TLE2064Y
PARAMETER
VIO
∝VIO
Input offset voltage
IIO
IIB
Input offset current
TEST CONDITIONS
Input offset voltage long-term drift (see Note 4)
TYP
MAX
0.9
6
VOM +
Maximum positive peak output voltage swing
VOM −
Maximum negative peak output voltage swing
Large-signal differential voltage amplification
pA
4
pA
−11
to
13
−12
to
16
V
RL = 10 kΩ
13.2
13.7
RL = 600 Ω
12.5
13.2
RL = 10 kΩ
−13.2
−13.7
V
RL = 600 Ω
12.5
13
V
RL = 10 kΩ
30
230
RL = 600 Ω
RL = 600 Ω
25
100
V/mV
3
25
1012
Ω
VO = ± 10 V,
VO = 0 to 8 V,
VO = 0 to − 8 V,
ri
Input resistance
ci
Input capacitance
zo
Open-loop output impedance
CMRR
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio (∆VCC± /∆VIO)
ICC
VO1/ VO2
Supply current
IO = 0
RS = 50 Ω,
VIC = VICRmin,
VCC± = ± 5 V to ± 15 V,
RS = 50 Ω
VO = 0,
AVD = 1000,
Crosstalk attenuation
mV
2
Input bias current
Common-mode input voltage range
UNIT
µV/mo
0.04
RS = 50 Ω
VIC = 0,
VICR
A VD
MIN
V
4
pF
560
Ω
72
90
dB
75
93
dB
No load
1.25
f = 1 kHz
120
1.4
mA
dB
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
TLE2064Y operating characteristics at VCC± = ±15 V, TA = 25°C
TLE2064Y
PARAMETER
SR
TEST CONDITIONS
Slew rate at unity gain (see Figure 1)
MIN
2.6
TYP
MAX
RL = 10 kΩ,
CL = 100 pF
f = 10 Hz,
RS = 20 Ω
3.4
70
f = 1 kHz ,
RS = 20 Ω
40
UNIT
V/µs
Vn
Equivalent input noise voltage (see Figure 2)
VN(PP)
In
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
1.1
µV
Equivalent input noise current
f = 1 kHz
1.1
fA/√Hz
THD
Total harmonic distortion
A VD = 2,
VO(PP) = 2 V,
f = 10 kHz,
RL = 10 kΩ
Unity-gain bandwidth (see Figure 3)
RL = 10 kΩ,
RL = 600 Ω,
CL = 100 pF
2
B1
CL = 100 pF
1.5
Settling time
ε = 0.1%
5
ts
ε = 0.01%
10
BOM
Maximum output-swing bandwidth
A VD = 1,
RL = 10 kΩ
40
φm
Phase margin at unity gain (see Figure 3)
RL = 10 kΩ,
CL = 100 pF
60°
RL = 600 Ω,
CL = 100 pF
70°
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
nV/√Hz
0.025%
MHz
µss
kHz
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
2 kΩ
VCC +
VCC +
−
−
VO
VI
VO
+
+
VCC −
VCC −
CL
(see Note A)
RL
RS
RS
NOTE A: CL includes fixture capacitance.
Figure 2. Noise-Voltage Test Circuit
Figure 1. Slew-Rate Test Circuit
10 kΩ
VCC +
100 Ω
VI
−
VO
+
VCC −
CL
(see Note A)
RL
NOTE A: CL includes fixture capacitance.
Figure 3. Unity-Gain Bandwidth and Phase-Margin Test Circuit
typical values
Typical values presented in this data sheet represent the median (50% point) of device parametric performance.
input bias and offset current
At the picoampere bias current level typical of the TLE206x, TLE2064xA, and TLE206xB, accurate
measurement of the bias current becomes difficult. Not only does this measurement require a picoammeter,
but test socket leakages can easily exceed the actual device bias currents. To accurately measure these small
currents, Texas Instruments uses a two-step process. The socket leakage is measured using picoammeters
with bias voltages applied but with no device in the socket. The device is then inserted into the socket and a
second test that measures both the socket leakage and the device input bias current is performed. The two
measurements are then subtracted algebraically to determine the bias current of the device.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
IIB
Input bias current
IIO
VICR
Input offset current
vs Free-air temperature
Common-mode input voltage
vs Free-air temperature
VOM
Maximum peak output voltage
vs Output current
vs Supply voltage
10, 11
12, 13, 14
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
vs Load resistance
15, 16
17
AVD
Large-signal differential voltage amplification
vs Frequency
vs Free-air temperature
18
19
IOS
Short-circuit output current
vs Elasped time
vs Free-air temperature
20
21
zo
Output impedance
vs Frequency
CMRR
Common-mode rejection ratio
vs Frequency
Supply current
vs Supply voltage
vs Free-air temperature
Voltage-follower small-signal pulse response
vs Time
31, 32
Voltage-follower large-signal pulse response
vs Time
33, 34
ICC
Noise voltage (referred to input)
46
4, 5, 6
vs Common-mode input voltage
vs Free-air temperature
0.1 to 10 Hz
7
8
8
9
22, 23
24
25, 26, 27
28, 29, 30
35
Vn
THD
Equivalent input noise voltage
vs Frequency
36
Total harmonic distortion
vs Frequency
37, 38
B1
Unity-gain bandwidth
vs Supply voltage
vs Free-air temperature
39
40
φm
Phase margin
vs Supply voltage
vs Load capacitance
vs Free-air temperature
41
42
43
Phase shift
vs Frequency
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TLE2062
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
TLE2061
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
15
736 Amplifiers Tested From 3 Wafer Lots
VCC ± = ± 15 V
TA = 25°C
P Package
Percentage of Amplifiers − %
Percentage of Amplifiers − %
15
10
5
0
−4
−3
−2
−1
0
1
2
3
1836 Amplifiers Tested From 1 Wafer Lot
VCC ± = ± 15 V
TA = 25°C
P Package
10
5
0
−4
4
−3
VIO − Input Offset Voltage − mV
−2
−1
3
4
Figure 5
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
TLE2064
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
2
20
2792 Amplifiers Tested From 2 Wafer Lots
VCC ± = ± 15 V
TA = 25°C
N Package
VID = 0
TA = 25°C
IIB − Input Bias Current − nA
Percentage of Amplifiers − %
2
1
VIO − Input Offset Voltage − mV
Figure 4
15
0
10
5
1.5
1
0.5
VCC ± = ± 15 V
0
−8
−6
−4
−2
0
2
4
6
8
VIO − Input Offset Voltage − mV
0
− 20
− 15
− 10 − 5
0
5
10
15
20
VIC − Common-Mode Input Voltage − V
Figure 6
Figure 7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
INPUT BIAS CURRENT
AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
COMMON-MODE INPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
105
VCC + + 2
VCC ± = ± 15 V
VIC = 0
VIC − Common-Mode Input Voltage − V
I IB and I IO − Input Bias and Input Offset Currents − pA
TYPICAL CHARACTERISTICS†
104
ÎÎ
VCC + + 1
103
ÎÎ
ÎÎ
ÎÎ
ÎÎ
IIB
102
VIC +
VCC +
VCC − + 4
IIO
ÎÎÎ
ÎÎÎ
VCC − + 3
101
100
25
45
65
85
105
125
VIC −
VCC − + 2
− 75 − 50 − 25
TA − Free-Air Temperature − °C
ÎÎÎÎ
ÎÎÎÎ
TA = 25°C
16
14
VCC ± = ± 15 V
12
10
8
6
4
VCC± = ± 5 V
2
0
0
− 10
− 20
− 30
50
75
100 125
MAXIMUM NEGATIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOM − − Maximum Negative Peak Output Voltage − V
VOM+ − Maximum Positive Peak Output Voltage − V
MAXIMUM POSITIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
18
25
Figure 9
Figure 8
20
0
TA − Free-Air Temperature − °C
− 40
− 50
− 60
ÎÎÎÎ
ÎÎÎÎ
− 20
TA = 25°C
− 18
− 16
− 14
VCC ± = ± 15 V
− 12
− 10
−8
−6
−4
VCC± = ± 5 V
−2
0
0
5
IO − Output Current − mA
10
15
20
25
30
35
IO − Output Current − mA
Figure 10
Figure 11
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
40
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
20
RL = 10 kΩ
TA = 25°C
15
VOM − Maximum Peak Output Voltage − V
VOM − Maximum Peak Output Voltage − V
20
VOM +
10
5
0
−5
− 10
VOM −
− 15
− 20
0
2
4
6
8
10
12
14
16
18
VOM +
10
5
0
−5
− 10
VOM −
− 15
− 20
20
RL = 600 Ω
TA = 25°C
15
0
2
| VCC ± | − Supply Voltage − V
10
12
14
16
18
20
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
RL = 100 Ω
TA = 25°C
VOM +
4
2
0
−2
−4
VOM −
−6
2
4
6
8
| VCC ± | − Supply Voltage − V
10
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
VOM − Maximum Peak Output Voltage − V
8
Figure 13
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
0
6
| VCC + | − Supply Voltage − V
Figure 12
6
4
10
VCC ± = ± 5 V
RL = 10 kΩ
TA = 25°C
8
6
4
2
0
10 k
Figure 14
100 k
1M
f − Frequency − Hz
10 M
Figure 15
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS†
30
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
ÎÎÎÎ
ÎÎÎÎ
VCC ± = ± 15 V
RL = 10 kΩ
TA = 25°C
25
20
15
10
5
0
10 k
100 k
1M
10 M
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
10
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
VCC ± = ± 5 V
TA = 25°C
8
6
4
2
0
100
10
Figure 17
60°
120
Phase Shift
80°
100
ÎÎÎ
100°
AVD
120°
40
140°
20
160°
0
−20
0.1
VCC ± = ± 15 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
1
10
100
180°
1k
10 k
200°
100 k 1 M 10 M
f − Frequency − Hz
AVD− Large-Signal DIfferential Voltage Amplification − V/mV
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
Phase Shift
AVD− Large-Signal DIfferential Voltage Amplification − dB
Figure 16
60
10 k
RL − Load Resistance − Ω
f − Frequency − Hz
80
1k
LARGE-SIGNAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
400
RL = 10 kΩ
350
300
250
VCC ± = ± 15 V
200
150
100
50
VCC ± = ± 5 V
0
− 75 − 50 − 25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 19
Figure 18
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS†
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
SHORT-CIRCUIT OUTPUT CURRENT
vs
ELAPSED TIME
80
VID = − 100 mV
I OS − Short-Circuit Output Current − mA
I OS − Short-Circuit Output Current − mA
80
60
40
20
VCC ± = ± 15 V
TA = 25°C
0
VO = 0
− 20
− 40
VID = 100 mV
− 60
10
20
30
40
50
VID = − 100 mV
40
20
0
− 20
VID = 100 mV
− 40
− 60
− 80
− 75 − 50 − 25
− 80
0
VCC ± = ± 15 V
VO = 0
60
60
Figure 20
zo − Output Impedance − Ω
z o − Output Impedance − Ω
30
AVD = 10
1
ÁÁ
ÁÁ
0.01
0.001
10
100
125
35
VCC ± = ± 15 V
TA = 25°C
AVD = 100
0.1
75
TLE2062 AND TLE2064
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
10
50
Figure 21
TLE2061
OUTPUT IMPEDANCE
vs
FREQUENCY
100
25
TA − Free-Air Temperature − °C
t − Elapsed Time − s
ÁÁ
ÁÁ
0
ÎÎÎÎ
ÎÎÎÎ
AVD = 1
100
1k
VCC ± = ± 15 V
TA = 25°C
25
ÎÎÎÎ
AVD = 10
20
ÎÎÎÎ
ÎÎÎÎ
15
AVD = 100
AVD = 1
10
5
10 k
100 k
1M
0
100
1k
10 k
100 k
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 22
Figure 23
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS†
TLE2061
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
340
TA = 25°C
VO = 0
No Load
ÎÎÎÎÎ
ÎÎÎÎÎ
80
320
I CC − Supply Current − µ A
CMRR − Common-Mode Rejection Ratio − dB
100
VCC ± = ± 5 V
60
40
TA = 125°C
300
TA = 25°C
280
260
20
TA = − 55°C
240
0
10
100
1k
10 k
100 k
1M
10 M
0
2
4
f − Frequency − Hz
6
12
14
16
18
1.4
700
VO = 0
No Load
650
TA = 125°C
625
VO = 0
No Load
1.35
I CC − Supply Current − mA
675
1.3
TA = 125°C
1.25
600
TA = 25°C
1.2
TA = 25°C
1.15
575
550
1.1
TA = − 55°C
TA = − 55°C
1.05
525
1
0
2
4
6
8
10
12
14
16
18
20
0
2
|VCC ±| − Supply Voltage − V
4
6
8
10
12
14
16
18
| VCC ± | − Supply Voltage − V
Figure 26
Figure 27
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
52
20
TLE2064
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
TLE2062
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
A
xA
IICC
CC − Supply Current − µ
10
Figure 25
Figure 24
500
8
| VCC ± | − Supply Voltage − V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
20
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS†
TLE2061
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TLE2062
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
340
700
VO = 0
No Load
VCC ± = ± 15 V
300
280
VCC ± = ± 5 V
VO = 0
No Load
650
A
xA
IICC
CC − Supply Current − µ
ÎÎÎÎÎ
ÎÎÎÎÎ
320
I CC − Supply Current − µ A
675
VCC ± = ± 15 V
625
600
575
550
260
VCC ± = ± 5 V
525
240
−75
−50
−25
0
25
50
75
100
500
− 75 − 50 − 25
125
TA − Free-Air Temperature − °C
TLE2064
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
75
100
125
100
VO = 0
No Load
VO − Output Voltage − mV
I CC − Supply Current − mA
50
VOLTAGE-FOLLOWER
SMALL-SIGNAL
PULSE RESPONSE
1.4
1.3
ÎÎÎÎÎ
1.25
VCC± = ±15 V
1.2
1.15
ÎÎÎÎÎ
ÎÎÎÎÎ
1.1
50
0
VCC ± = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
See Figure 1
− 50
VCC ± = ± 5 V
1.05
1
− 75
25
Figure 29
Figure 28
1.35
0
TA − Free-Air Temperature − °C
− 50
− 25
0
25
50
75
100
125
− 100
0
TA − Free-Air Temperature − °C
Figure 30
0.5
1
1.5
t − Time − µs
2
2.5
Figure 31
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER
SMALL-SIGNAL
PULSE RESPONSE
4
100
50
VO − Output Voltage − V
VO − Output Voltage − mV
3
0
VCC ± = ± 15 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
See Figure 1
− 50
1
0
0.5
1
1.5
t − Time − µs
2
2.5
3
3
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC ± = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
See Figure 1
−1
− 100
0
2
−2
0
5
Figure 33
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
NOISE VOLTAGE
(REFERRED TO INPUT)
0.1 TO 10 Hz
15
1
VCC ± = ± 15 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
See Figure 1
VCC ± = ± 15 V
TA = 25°C
0.5
5
Noise Voltage − V
VO − Output Voltage − V
15
t − Time − µs
Figure 32
10
10
0
−5
0
− 0.5
− 10
− 15
−1
0
54
10
20
30
40
0
1
2
3
4
5
t − Time − µs
t − Time − µs
Figure 34
Figure 35
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6
7
8
9
10
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
Vn − Equivalent Input Noise Voltage − nV/ Hz
VCC ± = ± 5 V
RS = 20 Ω
TA = 25°C
See Figure 2
80
60
40
20
0.3
THD − Total Harmonic Distortion − %
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
100
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
AVD = 2
VO(PP) = 2 V
TA = 25°C
0.2
VCC ± = ± 5 V
0.1
Source Signal
0
1
10
100
1k
0
10 k
10
100
f − Frequency − Hz
1k
Figure 37
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
TOTAL HARMONIC DISTORATION
vs
FREQUENCY
2.5
0.6
AVD = 10
VO(PP) = 2 V
TA = 25°C
0.5
B1 − Unity-Gain Bandwidth − MHz
THD − Total Harmonic Distortion − %
100 k
f − Frequency − Hz
Figure 36
0.4
0.3
VCC ± = ± 5 V
0.2
Source Signal
0.1
0
10 k
RL = 10 kΩ
CL = 100 pF
TA = 25°C
See Figure 3
2
1.5
1
10
100
1k
10 k
100 k
0
2
4
6
8
10
12
14
f − Frequency − Hz
| VCC ± | − Supply Voltage − V
Figure 38
Figure 39
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
16
18
20
55
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
TYPICAL CHARACTERISTICS†
PHASE MARGIN
vs
SUPPLY VOLTAGE
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
62°
2.5
RL = 10 kΩ
CL = 100 pF
TA = 25°C
See Figure 3
VCC ± = ± 15 V
60°
φ m − Phase Margin
B1 − Unity-Gain Bandwidth − MHz
61°
2
VCC ± = ± 5 V
59°
ÁÁ
ÁÁ
1.5
58°
57°
56°
RL = 10 kΩ
CL = 100 pF
See Figure 3
1
− 75
55°
− 50
− 25
0
25
50
75
100
TA − Free-Air Temperature − °C
0
125
2
4
6
8
10
12
14
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
66°
60°
VCC ± = ± 15 V
RL = 10 kΩ
TA = 25°C
See Figure 3
φ m − Phase Margin
φ m − Phase Margin
40°
62°
20°
VCC ± = ± 15 V
60°
ÁÁ
ÁÁ
30°
RL = 10 kΩ
CL = 100 pF
See Figure 3
64°
58°
VCC ± = ± 5 V
56°
10°
0°
0
200
400
600
800
1000
54°
− 75
− 50
− 25
0
25
50
75
100
TA − Free-Air Temperature − °C
CL − Load Capacitance − pF
Figure 42
Figure 43
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
56
20
Figure 41
PHASE MARGIN
vs
LOAD CAPACITANCE
ÁÁ
ÁÁ
18
| VCC ± | − Supply Voltage − V
Figure 40
50°
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
APPLICATION INFORMATION
input characteristics
The TLE206x, TLE206xA, and TLE206xB are specified with a minimum and a maximum input voltage that if
exceeded at either input could cause the device to malfunction. Because of the extremely high input impedance
and resulting low bias current requirements, the TLE206x, TLE206xA, and TLE206xB are well suited for
low-level signal processing. However, leakage currents on printed-circuit boards and sockets can easily exceed
bias current requirements and cause degradation in system performance. It is good practice to include guard
rings around inputs (see Figure 44). These guards should be driven from a low-impedance source at the same
voltage level as the common-mode input.
+
VI
VI
VO
+
+
VO
−
−
R1
R2
VO
VI
−
R3
R4
Where
R3 + R2
R1
R4
Figure 44. Use of Guard Rings
TLE2061 input offset voltage nulling
The TLE2061 series offers external null pins that can be used to further reduce the input offset voltage. The
circuit of Figure 45 can be connected as shown if the feature is desired. When external nulling is not needed,
the null pins may be left unconnected.
IN −
−
IN +
+
OUT
N1
N2
100 kΩ
5 kΩ
VCC −
Figure 45. Input Offset Voltage Nulling
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
µ SLOS193B − FEBRUARY 1997 − REVISED MAY 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice . The Boyle macromodel (see Note 5) and the subcircuit in Figure 46 were generated
using the TLE206x typical electrical and operating characteristics at 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases).
D
D
D
D
D
D
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
3
VCC +
egnd
9
rss
92
fb
−
+
iss
din
+
rp
2
10
IN −
j1
dp
vc
j2
IN+
1
11
r2
−
53
C2
6
dc
12
hlim
−
+
VCC −
54
4
+
−
−
+
vin
+
gcm
ga
−
ro1
de
5
−
ve
OUT
.subckt TLE2062 1 2 3 4 5
c1
11 12 1.457E−12
c2
6
7 15.00E−12
dc
5 53 dx
de
54
5 dx
dlp 90 91 dx
dln 92 90 dx
dp
4
3 dx
egnd 99
0 poly (2) (3,0) (4,0) 0 .5 .5
fb
7 99 poly (5) vb vc ve vlp
+ vln 0 4.357E6 − 4E6 4E6 4E6 − 4E6
ga
6
0 11 12 188.5E−6
gcm
0
6 10 99 3.352E−9
iss
3 10 dc 51.00E−6
hlim 90
0 vlim 1k
j1
11
2 10 jx
j2
12
1 10 jx
r2
6
9 100.0E3
rd1
4 11 5.305E3
rd2
4 12 5.305E3
r01
8
5 280
r02
7 99 280
rp
3
4 113.2E3
rss 10 99 3.922E6
vb
9
0 dc 0
vc
3 53 dc 2
ve
54
4 dc 2
vlim 7
8 dc 0
vlp 91 0 dc 50
vln
0 92 dc 50
.model dx D(Is=800.0E−18)
.model jx PJF(Is=2.000E−12 Beta = 423E−6
+ Vto = − 1)
.ends
Figure 46. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
58
−
vlim
8
rd2
91
+
vip
7
C1
rd1
+ dip
90
ro2
vb
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9080701M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080701M2A
TLE2061MFKB
5962-9080701MHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080701MHA
TLE2061M
5962-9080701MPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080701MPA
TLE2061M
5962-9080702Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080702Q2A
TLE2061
AMFKB
5962-9080702QHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080702QHA
TLE2061AM
5962-9080702QPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080702QPA
TLE2061AM
5962-9080703QPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080703QPA
TLE2061BM
5962-9080801M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080801M2A
TLE2062MFKB
5962-9080801MHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080801MHA
TLE2062M
5962-9080801MPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080801MPA
TLE2062M
5962-9080802Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080802Q2A
TLE2062
AMFKB
5962-9080802QHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080802QHA
TLE2062AM
5962-9080802QPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080802QPA
TLE2062AM
5962-9080803QPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080803QPA
TLE2062BM
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9080901M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080901M2A
TLE2064
MFKB
5962-9080901MCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9080901MC
A
TLE2064MJB
5962-9080901MDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9080901MD
A
TLE2064MWB
5962-9080902M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080902M2A
TLE2064A
MFKB
5962-9080902MCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9080902MC
A
TLE2064AMJB
5962-9080902MDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9080902MD
A
TLE2064AMWB
5962-9080903Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080903Q2A
TLE2064
BMFKB
5962-9080903QCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9080903QC
A
TLE2064BMJB
TLE2061ACD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061AC
TLE2061ACDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061AC
TLE2061ACP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2061AC
TLE2061ACPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2061AC
TLE2061AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 2
2061AI
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLE2061AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2061AIP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2061AI
TLE2061AIPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2061AI
TLE2061AMFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080702Q2A
TLE2061
AMFKB
TLE2061AMJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080702QPA
TLE2061AM
TBD
Call TI
Call TI
-55 to 125
TBD
A42
N / A for Pkg Type
-55 to 125
TBD
Call TI
Call TI
0 to 70
TLE2061AMP
OBSOLETE
PDIP
P
8
TLE2061AMUB
ACTIVE
CFP
U
10
TLE2061BCP
OBSOLETE
PDIP
P
8
1
2061AI
9080702QHA
TLE2061AM
TLE2061BIP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-40 to 85
TLE2061BMJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2061CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061C
TLE2061CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061C
TLE2061CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061C
TLE2061CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061C
TLE2061CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2061CP
TLE2061CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2061CP
TLE2061CPSR
OBSOLETE
SO
PS
8
TBD
Call TI
Call TI
TLE2061ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061I
TLE2061IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061I
Addendum-Page 3
9080703QPA
TLE2061BM
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLE2061IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061I
TLE2061IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2061I
TLE2061IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2061IP
TLE2061IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2061IP
TLE2061MD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2061MDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2061MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080701M2A
TLE2061MFKB
TLE2061MJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080701MPA
TLE2061M
TLE2061MP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-55 to 125
TLE2061MUB
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2062ACD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062AC
TLE2062ACDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062AC
TLE2062ACDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062AC
TLE2062ACDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062AC
TLE2062ACP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
TLE2062AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062AI
TLE2062AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062AI
TLE2062AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062AI
Addendum-Page 4
-55 to 125
2061M
2061M
9080701MHA
TLE2061M
0 to 70
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
TLE2062AIDRG4
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
2062AI
TLE2062AIP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
TLE2062AMD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2062AMDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2062AMDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
2062AM
TLE2062AMFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080802Q2A
TLE2062
AMFKB
TLE2062AMJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2062
AMJG
TLE2062AMJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080802QPA
TLE2062AM
TLE2062AMP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-55 to 125
TLE2062AMUB
ACTIVE
CFP
U
10
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2062BCD
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
0 to 70
TLE2062BCDR
OBSOLETE
SOIC
D
8
TBD
Call TI
Call TI
0 to 70
TLE2062BCP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
0 to 70
1
-55 to 125
2062AM
2062AM
9080802QHA
TLE2062AM
TLE2062BIP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-40 to 85
TLE2062BMFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLE2062BMJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2062
BMJG
TLE2062BMJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080803QPA
TLE2062BM
TLE2062CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062C
TLE2062CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062C
TLE2062CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062C
Addendum-Page 5
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLE2062CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062C
TLE2062CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2062CP
TLE2062CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2062CP
TLE2062CPSR
OBSOLETE
SO
PS
8
TBD
Call TI
Call TI
TLE2062ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062I
TLE2062IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062I
TLE2062IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062I
TLE2062IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2062I
TLE2062IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2062IP
TLE2062IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2062IP
TLE2062MD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2062MDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2062MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080801M2A
TLE2062MFKB
TLE2062MJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2062MJG
TLE2062MJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
9080801MPA
TLE2062M
-55 to 125
2062M
TLE2062MP
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
-55 to 125
TLE2062MUB
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2064ACD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 6
2062M
9080801MHA
TLE2062M
2064AC
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLE2064ACDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2064AC
TLE2064ACDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2064AC
TLE2064ACDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2064AC
TLE2064ACN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2064ACN
TLE2064ACNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLE2064ACN
TLE2064AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2064AI
TLE2064AIDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2064AI
TLE2064AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2064AI
TLE2064AIDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2064AI
TLE2064AIN
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
TLE2064AMD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2064AMDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2064AMDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2064AMDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2064AMFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080902M2A
TLE2064A
MFKB
TLE2064AMJ
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2064AMJ
TLE2064AMJB
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9080902MC
A
TLE2064AMJB
TLE2064AMN
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
-55 to 125
Addendum-Page 7
-55 to 125
2064AM
2064AM
-55 to 125
2064AM
2064AM
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
1
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
A42
N / A for Pkg Type
Op Temp (°C)
Device Marking
(4/5)
TLE2064AMWB
ACTIVE
CFP
W
14
TLE2064BCN
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
0 to 70
TLE2064BIN
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
-40 to 85
TLE2064BMFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080903Q2A
TLE2064
BMFKB
TLE2064BMJ
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2064BMJ
TLE2064BMJB
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9080903QC
A
TLE2064BMJB
TLE2064BMN
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
-55 to 125
TLE2064CD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLE2064C
TLE2064CDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLE2064C
TLE2064CDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLE2064C
TLE2064CDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLE2064C
TLE2064CN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLE2064CN
TLE2064CNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLE2064CN
TLE2064CNSR
OBSOLETE
SO
NS
14
TBD
Call TI
Call TI
TLE2064ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLE2064I
TLE2064IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLE2064I
TLE2064IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLE2064I
TLE2064IDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLE2064I
Addendum-Page 8
-55 to 125
5962-9080902MD
A
TLE2064AMWB
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLE2064IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLE2064IN
TLE2064INE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLE2064IN
TLE2064MD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
TLE2064M
TLE2064MDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2064MDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2064MDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLE2064MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629080901M2A
TLE2064
MFKB
TLE2064MJ
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
TLE2064MJ
TLE2064MJB
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9080901MC
A
TLE2064MJB
TLE2064MN
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
-55 to 125
TLE2064MWB
ACTIVE
CFP
W
14
TBD
A42
N / A for Pkg Type
-55 to 125
1
T2064M
-55 to 125
TLE2064M
T2064M
5962-9080901MD
A
TLE2064MWB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 9
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLE2061, TLE2061A, TLE2061AM, TLE2061B, TLE2061BM, TLE2061M, TLE2062, TLE2062A, TLE2062AM, TLE2062B, TLE2062BM,
TLE2062M, TLE2064, TLE2064A, TLE2064AM, TLE2064B, TLE2064BM, TLE2064M :
• Catalog: TLE2061A, TLE2061B, TLE2061, TLE2062A, TLE2062B, TLE2062, TLE2064A, TLE2064B, TLE2064
• Military: TLE2061M, TLE2061AM, TLE2061BM, TLE2062M, TLE2062AM, TLE2062BM, TLE2064M, TLE2064AM, TLE2064BM
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 10
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLE2061CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLE2061IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLE2062ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLE2062AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLE2062AMDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLE2062CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLE2062IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLE2064ACDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLE2064AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLE2064AMDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLE2064CDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLE2064IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLE2064MDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLE2061CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLE2061IDR
SOIC
D
8
2500
340.5
338.1
20.6
TLE2062ACDR
SOIC
D
8
2500
340.5
338.1
20.6
TLE2062AIDR
SOIC
D
8
2500
340.5
338.1
20.6
TLE2062AMDR
SOIC
D
8
2500
367.0
367.0
35.0
TLE2062CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLE2062IDR
SOIC
D
8
2500
340.5
338.1
20.6
TLE2064ACDR
SOIC
D
14
2500
367.0
367.0
38.0
TLE2064AIDR
SOIC
D
14
2500
367.0
367.0
38.0
TLE2064AMDR
SOIC
D
14
2500
367.0
367.0
38.0
TLE2064CDR
SOIC
D
14
2500
367.0
367.0
38.0
TLE2064IDR
SOIC
D
14
2500
367.0
367.0
38.0
TLE2064MDR
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated