TDA7430 TDA7431 DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLER 1 STEREO (4 STEREO) INPUT + 1 MIXER INPUT INPUT ATTENUATION CONTROL IN 0.5dB STEP VOICE CANCELLER IS AVAILABLE TREBLE MIDDLE AND BASS CONTROL THREE SURROUND MODES ARE AVAILABLE: - MUSIC: 4 SELECTABLE RESPONSES - MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES 2 SPEAKER AND 2 RECORD ATTENUATORS: - 2 INDEPENDENT SPEAKERS AND 2 INDEPENDENT RECORD CONTROL IN 1dB STEP FOR BALANCE FACILITY - AVAILABILITY OF LOUDSPEAKER EQUALIZATION FIXED BY EXTERNAL COMPONENTS - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7430/7431 are volume tone (bass middle and treble) balance (Left/Right) processors with SDIP42 TQFP44 ORDERING NUMBERS: TDA7430 (TQFP44) TDA7431 (SDIP42) voice canceller for quality audio applications in car radio and Hi-Fi systems. They reproduce surround sound by using programmable phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. September 1999 LPVC R_IN2 R_IN3 R_IN4 CREF PS4 VS PS3 PS2 PS1 44 43 42 41 40 39 38 37 36 35 34 LP1 1 33 R_IN1 HP1 2 32 MIX HP2. 3 31 L_IN1 REAROUT 4 30 L_IN2 REARIN 5 29 L_IN3 VAR_L 6 28 L_IN4 BASSO_L 7 27 RECOUT_L VAR_R 8 26 RECOUT_R BASSO_R 9 25 L_OUT BASS_LO 10 24 R_OUT BASS_LI 11 23 DIG_GND SCL SDA AGND TREBLE_L TREBLE_R MIDDLE_RI MIDDLE_LI MIDDLE_LO 12 13 14 15 16 17 18 19 20 21 22 MIDDLE_RO D95AU219B VS CREF NBRO NBRIN LPVC R_IN MIX L_IN NBLIN NBLO RECOUT_L RECOUT_R L_OUT R_OUT DIG_GND SCL SDA ADDR AGND TREBLE_L TREBLE_R BASS_RI 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 BASS_RO PS4 PS3 PS2 PS1 LP LP1 HP1 HP2 VOUTREF VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI BASS_RO BASS_RI MIDDLE_LO MIDDLE_LI MIDDLE_RO MIDDLE_RI LP PIN CONNECTIONS D95AU220B 1/21 L-IN1 R-IN4 0.47µF R-IN3 0.47µF R-IN2 0.47µF R-IN1 0.47µF L-IN4 0.47µF L-IN3 0.47µF L-IN2 0.47µF 37 36 35 33 28 29 30 31 + + - 39 VS 100K VOICE ON R6 R5 MIX-IN 1µF 32 MIX 34 RHP1 LPVC 100nF 31.5dB control LPF - + + RLP1 HP2 THE SWITCHES POSITION MATCHES THE RESET CONDITION 50K 50K 50K 50K 50K 50K 50K 50K 3 HP1 2 LP1 1 31.5dB control 20 + - + - 38 SUPPLY L-R 22µF LP 44 Vref MOVIE/ MUSIC SIM 1.2nF 5 2.2µF 4 MOVIE/SIM 50K MIXING AMP MIXING AMP PS4 400Hz PS4 PS3 400Hz 41 RPS4 PS3 22nF RPS3 MUSIC 42 EFFECT CONTROL OFF PS2 4KHz PS2 PS1 90Hz LPF 9KHz 43 RPS2 PS1 RPS1 CREF 0.47µF AGND 22nF REAROUT 4.7nF REARIN 2.7K 18nF 18 5.6nF 2.7K 18nF 22nF 16 RM MIDDLE TREBLE REAR SURR 3BAND FIX RB 5.6K 100nF REAR 100nF 12 SURR FIX 3BAND BASSO-R 79dB CONTROL MUTE REC ATT MUTE REC ATT 9 30K FIX VAR 30K VAR-L VAR-R 8 VAR FIX 6 2.2µF 2.2µF 7 BASSO-L 79dB CONTROL I2 C BUS DECODER + LATCHES BASS 13 RB 10 BASS-LO 100nF BASS-LI BASS 11 5.6K 22nF 100nF 14 RM MIDDLE 17 15 TREBLE TREBLE-R SURR SURR 19 TREBLE-L OFF OFF 40 5.6nF MIDDLE-LI MIDDLE-RI 100nF BASS-RI MIDDLE-LO MIDDLE-RO 680nF BASS-RO 2/21 5.6nF - + + - 26 24 23 21 22 25 RECOUT-R R-OUT DIG GND SDA SCL L-OUT RECOUT-L D95AU221B 79dB CONTROL MUTE SPKR ATT MUTE SPKR ATT 79dB CONTROL 27 TDA7430 - TDA7431 BLOCK DIAGRAM (TDA7430) R-in 0.47µF L-in 0.47µF 50K 50K 31.5dB control 100nF + + - R5 100K VOICE ON R6 HP2 MIX-IN 1µF 36 MIX 38 RHP1 LPVC LPF - + + RLP1 8 - + - + L-R THE SWITCHES POSITION MATCHES THE RESET CONDITION 37 35 HP1 6 7 LP1 31.5dB control LP 42 3 VS 2 41 SUPPLY Vref 22µF 1 5.6nF 22 TREBLE TREBLE 5.6nF TREBLE-R SURR SURR 23 TREBLE-L OFF OFF MIXING AMP MIXING AMP PS4 400Hz RPS4 PS4 22nF VOUTREF 9 MOVIE/SIM PS3 400Hz MUSIC 24 PS3 RPS3 EFFECT CONTROL OFF PS2 4KHz RPS2 PS2 1.2nF LPF 9KHz 4 5 MOVIE/ MUSIC SIM PS1 90Hz RPS1 PS1 22nF AGND 4.7nF CREF 21 19 2.7K 18nF 22nF RM 20 MIDDLE MIDDLE 22nF 18 RM 2.7K 18nF MIDDLE-LI MIDDLE-RI MIDDLE-LO MIDDLE-RO 100nF 17 15 FIX 3BAND 5.6K 100nF FIX 100nF RB 16 SURR REAR BASS 3BAND BASSO-R 79dB CONTROL MUTE REC ATT MUTE REC ATT 11 BASSO-L 79dB CONTROL I2C BUS DECODER + LATCHES BASS REAR SURR RB 14 BASS-LO 100nF BASS-LI 5.6K 100nF BASS-RO 2.2µF 13 12 VAR FIX 10 2.2µF 34 30K FIX VAR 30K NB3 NB4 NB-RA 39 - + + - NB-LB 40 31 29 25 28 26 27 30 32 D95AU222C 79dB CONTROL MUTE SPKR ATT MUTE SPKR ATT 79dB CONTROL NB-RB 33 NB2 NB1 NB-LA NBLIN NBRIN 680nF BASS-RI VAR-L VAR-R NBLO NBRO 5.6nF RECOUT-R R-OUT ADDR DIG GND SDA SCL L-OUT RECOUT-L TDA7430 - TDA7431 BLOCK DIAGRAM (TDA7431) 3/21 TDA7430 - TDA7431 THERMAL DATA Symbol R th j-pins Description Thermal Resistance Junction-pins Value Unit 85 °C/W Ma x. ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Operating Supply Voltage T amb Operating Ambient Temperature Tstg Storage Temperature Range Value Unit 11 V -10 to 85 °C -55 to +150 °C QUICK REFERENCE DATA Symbol Min. Typ. Max. VS Supply Voltage Parameter 7 9 10.2 VCL Max. input signal handling 2 Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio V out = 1Vrms (mode = OFF) 106 SC Channel Separation f = 1KHz (2db step) 0.1 % dB 90 dB -14 +14 dB Middle Control (2db step) -14 +14 dB Bass Control (2dB step) -14 +14 dB -79 0 dB Balance Control Mute Attenuation 4/21 V Vrms THD Treble Control Unit 1dB step (LCH, RCH) 100 dB TDA7430 - TDA7431 TEST CIRCUIT (TDA7430) 2.2µF BASSO-R VAR-R 22nF PS4 22nF 2.2µF 2.2µF BASSO-L 8 9 REAROUT VAR-L 7 6 0.47µF 0.47µF R-IN4 R-IN3 REARIN 4 5 0.47µF 37 R-IN2 36 35 40 33 PS3 1µF MIX 32 R-IN1 41 4.7nF 0.47µF 31 PS2 L-IN1 42 L-IN2 100nF PS1 L-IN3 5.6nF 0.47µF 28 1 TREBLE-R L-IN4 VS 39 18 10µF TDA7430 5.6nF TREBLE-L 19 CREF 100nF 22µF 38 100nF 220nF LPVC 34 100nF 10 22nF MIDDLE-LO BASS-LO 14 100nF 18nF 11 MIDDLE-LI 15 BASS-LI 2.7K 22nF BASS-RO MIDDLE-RO MIDDLE-RI 5.6K 100nF 12 16 18nF 0.47µF 29 44 LP1 5.6nF 0.47µF 30 43 1.2nF LP 0.47µF 100nF 13 17 27 26 25 24 23 22 21 RECOUT-L RECOUT-R L-OUT R-OUT DIG-GND SCL SDA 2.7K 20 3 AGND HP2 2 BASS-RI 5.6K HP1 D95AU225B 680nF TEST CIRCUIT (TDA7431) 2.2µF BASSO-R 22nF PS4 22nF 1 2.2µF VAR-R 13 BASSO-L 12 680nF VAR-L 11 HP2 10 0.47µF 1µF R-IN MIX HP1 8 7 37 0.47µF L-IN 36 35 42 VS 10µF PS3 2 4.7nF PS2 41 3 CREF NBRO 100nF PS1 1.2nF LP 15K 220nF 5 39 NBRIN LP1 5.6nF 6 TREBLE-R 34 TDA7431 NBLIN 15K 5.6nF TREBLE-L 7.5K 220nF 22 23 220nF 33 NBLO 100nF 7.5K LPVC 100nF 38 MIDDLE-LO 14 18 BASS-LO 100nF 18nF MIDDLE-LI 15 19 BASS-LI 2.7K BASS-RO 22nF MIDDLE-RO MIDDLE-RI 2.7K D95AU224B 5.6K 100nF 16 20 18nF 220nF 40 4 5.6nF 22nF 100nF 22µF 100nF 21 17 9 32 31 30 29 28 27 26 25 VOUTREF RECOUT-L RECOUT-R L-OUT R-OUT DIG-GND SCL SDA ADDR 24 BASS-RI 5.6K AGND 5/21 TDA7430 - TDA7431 ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS Supply Voltage 7 9 10.2 V IS Supply Current 10 18 26 mA 60 80 SVR Ripple Rejection LCH / RCH out, Mode = OFF dB INPUT STAGE R IN Input Resistance V CL Clipping Level C RANGE Control Range THD = 0.3% 35 50 2 2.5 65 KΩ Vrms 31.5 dB AVMIN Min. Attenuation -1 0 1 AVMAX Max. Attenuation 31 31.5 32 dB dB ASTEP Step Resolution 0.5 1 dB VDC DC Steps adjacent att. step -3 0 3 mV AVO1 Voice Canceler Output 1 LIN = RIN, RIN = ON, Vmix = 0V FIX, 0dB attenuation 5 6 7 dB AVO2 Voice Canceler Output 2 LIN = RIN = 0V Vmix = 1Vrms FIX, 0dB attenuation -1 0 1 dB AVO3 Voice Canceler Output 3 LIN = -RIN, Vmix = 0V FIX, 0dB attenuation 5 6 7 dB RLPV Low Pass Filter Resistance 22.4 32 41.6 KΩ RMIX Input Impedance 70 100 130 KΩ dB BASS CONTROL Gb BSTEP RB Control Range +11.5 +14.0 +16.0 Step Resolution Max. Boost/cut 1 2 3 dB Internal Feedback Resistance 32 44 56 KΩ +11.5 +14.0 +16.0 dB 1 2 3 dB 17.5 25 32.5 KΩ +13.0 +14.0 +15.0 dB 1 2 3 dB -6 dB 1 1.5 dB MIDDLE CONTROL Gm M STEP RM Control Range Max. Boost/cut Step Resolution Internal Feedback Resistance TREBLE CONTROL Gt TSTEP Control Range Step Resolution Max. Boost/cut EFFECT CONTROL C RANGE SSTEP 6/21 Control Range - 21 Step Resolution 0.5 TDA7430 - TDA7431 ELECTRICAL CHARACTERISTICS (continued) SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1 Symbol Min. Typ. Max. Unit GOFF In-phase Gain (OFF) Parameter Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin → Rout Lin → Lout Test Condition -1 0 1 dB D GOFF LR In-phase Gain Difference (OFF) Mode OFF, Input signal of 1kHz, 1.4 Vp-p R in → Rout, Lin → Lout -1 0 1 dB GMOV In-phase Gain (Movie) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in → Rout, Lin → Lout 8 dB DGMOV LR In-phase Gain Difference (Movie) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) – (Lin → Lout) 0 dB GMUS In-phase Gain (Music) 7 dB D GMUS LR In-phase Gain Difference (Music) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout), (Lin → Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) - (Lin → Lout) 0 dB LMON1 Simulated L Output 1 Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin → Lou t 4.5 dB LMON2 Simulated L Output 2 Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin → Lou t –4.0 dB LMON3 Simulated L Output 3 Simulated Mode, EffectCtrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Lou t 7.0 dB R MON1 Simulated R Output 1 Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin →R out – 4.5 dB R MON2 Simulated R Output 2 Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin →R out 3.8 dB R MON3 Simulated R Output 3 Simulated Mode, EffectCtrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Rout – 20 dB RLP1 Low Pass Filter Resistance 7 10 13 R HPI High Pass Filter Resistance 42 60 78 KΩ KΩ RLPF LP Pin Impedance 7 10 13 KΩ 7/21 TDA7430 - TDA7431 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit SURROUND SOUND MATRIX PHASE R PS10 Phase Shifter 1: D1 = 0, D0 = 0 8.3 11.8 15.2 KΩ R PS11 Phase Shifter 1: D1 = 0, D0 = 1 10 14.1 18.3 KΩ R PS12 Phase Shifter 1: D1 = 1, D0 = 0 12.6 17.9 23.3 KΩ R PS13 Phase Shifter 1: D1 = 1, D0 = 1 26.4 37.3 48.85 KΩ R PS20 Phase Shifter 2: D3 = 0, D2 = 0 4 5.6 7.2 KΩ R PS21 Phase Shifter 2: D3 = 0, D2 = 1 4.8 6.8 8.7 KΩ R PS22 Phase Shifter 2: D3 = 1, D2 = 0 6 8.4 10.9 KΩ R PS23 Phase Shifter 2: D3 = 1, D2 = 1 12.9 18.3 23.7 KΩ R PS30 Phase Shifter 3: D5 = 0, D4 = 0 8.5 12.1 15.6 KΩ R PS31 Phase Shifter 3: D5 = 0, D4 = 1 10.2 14.5 18.7 KΩ R PS32 Phase Shifter 3: D5 = 1, D4 = 0 12.7 18.1 23.3 KΩ R PS33 Phase Shifter 3: D5 = 1, D4 = 1 27.4 39.1 50.75 KΩ R PS40 Phase Shifter 4: D7 = 0, D6 = 0 8.5 12.1 15.6 KΩ R PS41 Phase Shifter 4: D7 = 0, D6 = 1 10.2 14.5 18.7 KΩ R PS42 Phase Shifter 4: D7 = 1, D6 = 0 12.7 18.1 23.3 KΩ R PS43 Phase Shifter 4: D7 = 1, D6 = 1 27.4 39.1 50.75 KΩ SPEAKER & RECORD ATTENUATORS Crange Control Range SSTEP Step Resolution EA Attenuation set error 79 -0.5 Av = 0 to -20dB Av = -20 to -79dB DC Steps adjacent att. steps 1.5 -1.5 0 1.5 dB -3 0 2 dB 3 mV -3 0 AMUTE Output Mute Condition +70 100 RVEA Input Impedance 21 30 VDC dB 1 dB dB 39 KΩ AUDIO OUTPUTS NO(OFF) Output Noise (OFF) Output Mute, Flat BW = 20Hz to 20KHz 4 5 µVrms µVrms NO(MOV) Output Noise (Movie) Mode =Movie , BW = 20Hz to 20KHz 30 µVrms NO(MUS) Output Noise (Music) Mode = Music , BW = 20Hz to 20KHz, 30 mVrms N O(MON) Output Noise (Simulated) Mode = Simulated, BW = 20Hz to 20KHz 30 µVrms d Distorsion Av = 0 ; Vin = 1Vrms SC Channel Separation VOCL Clipping Level ROUT Output Resistance VOUT DC Voltage Level d = 0.3% 0.01 70 90 2 2.5 10 40 0.1 % dB Vrms 70 3.8 Ω V BUS INPUTS 8/21 V IL Input Low Voltage VIH Input High Voltage 3 IIN Input Current -5 VO Output Voltage SDA Acknowledge IO = 1.6mA 1 V +5 µA V V 0.4 TDA7430 - TDA7431 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7430/TDA7431 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an ac- knowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. 2 Figure 3: Data Validity on the I CBUS Figure 4: Timing Diagram of I2CBUS Figure 5: Acknowledge on the I2CBUS 9/21 TDA7430 - TDA7431 /TDA7431 address A subaddress bytes A sequence of data (N byte + achnowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7430 CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 MSB ACK DATA 1 to DATA n LSB B DATA MSB ACK LSB DATA ACK P D95AU226A ACK = Achnowledge S = Start P = Stop A = Address B = Auto Increment EXAMPLES No Incremental Bus The TDA7430 /TDA7431 receives a start condi- CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 tion, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition. A 0 MSB ACK 0 DATA LSB X X MSB X D3 D2 D1 D0 ACK LSB DATA ACK P D95AU306 Incremental Bus The TDA7430 /TDA7431 receive s a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 D95AU307 10/21 0 0 whereas SUBADDRESS from ”1XXX1010” to ”1XXX1111” of DATA are ignored. The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. A 0 MSB ACK 1 DATA 1 to DATA n LSB X X X D3 D2 D1 D0 ACK MSB LSB DATA ACK P TDA7430 - TDA7431 DATA BYTES Address = 80(HEX): ADDR open; 82 (HEX): need to connect supply FUNCTION SELECTION: The first byte (subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 B X X X 0 0 0 0 INPUT ATTENUATION B X X X 0 0 0 1 SURROUND & OUT & EFFECT CONTROL B X X X 0 0 1 0 PHASE RESISTOR B X X X 0 0 1 1 BASS & NATURAL BASE B X X X 0 1 0 0 MIDDLE & TREBLE B X X X 0 1 0 1 SPEAKER ATTENUATION ”L” B X X X 0 1 1 0 SPEAKER ATTENUATION ”R” B X X X 0 1 1 1 RECORD ATTENUATION ”L” B X X X 1 0 0 0 RECORD ATTENUATION”R” B X X X 1 0 0 1 INPUT MULTIPLEXER, VOICE CANCELLER & REC OUT B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 INPUT ATTENUATION SELECTION MSB D7 D6 D5 D4 D3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LSB INPUT ATTENUATION D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0.5 dB STEPS 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 4 dB STEPS 0 -4 -8 -12 -16 -20 -24 -28 D2 D1 D0 REAR SWITCH REARIN, REAROUT PIN ACTIVE NO REARIN, REAROUT PIN INPUT ATTENUATION = 0 ∼ -31.5dB D7 D6 0 1 D5 D4 D3 11/21 TDA7430 - TDA7431 SURROUND SELECTION MSB D7 LSB D6 D5 D4 D3 D2 D1 0 0 1 1 D0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SURROUND MODE SIMULATED MUSIC OFF MOVIE OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 PHASE RESISTOR SELECTION MSB D7 LSB D6 D5 0 0 1 1 0 0 1 1 12/21 0 1 0 1 D4 0 1 0 1 D3 D2 0 0 1 1 0 1 0 1 D1 0 0 1 1 D0 0 1 0 1 SURROUND PHASE RESISTOR PHASE SHIFT 1 (KΩ) 12 14 18 37 PHASE SHIFT 2 (KΩ) 6 7 8 18 PHASE SHIFT 3 (KΩ) 12 14 18 39 PHASE SHIFT 4 (KΩ) 12 14 18 39 TDA7430 - TDA7431 BASS SELECTION MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB BASS D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 NATURAL BASE NBRIN, NBRO, NBLIN, NBLO PIN ACTIVE NO NBRIN, NBRO, NBLIN, NBLO PIN LSB SPEAKER/RECORD ATT D0 0 1 0 1 0 1 0 1 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE 0 1 SPEAKER/RECORD ATT. R & L SELECTION MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 X X X X = INDIFFERENT 0,1 SPEAKER/RECORD ATTENUATION = 0dB ∼ -79dB 13/21 TDA7430 - TDA7431 MIDDLE & TREBLE SELECTION MSB D7 D6 D5 D4 LSB MIDDLE D3 D2 D1 D0 2 dB STEPS 0 0 0 0 -14 0 0 0 1 -12 0 0 1 0 -10 0 0 1 1 -8 0 1 0 0 -6 0 1 0 1 -4 0 1 1 0 -2 0 1 1 1 0 1 1 1 1 0 1 1 1 0 2 1 1 0 1 4 1 1 0 0 6 1 0 1 1 8 1 0 1 0 10 1 0 0 1 12 1 0 0 0 14 TREBLE 2 dB STEPS 0 0 0 0 -14 0 0 0 1 -12 0 0 1 0 -10 0 0 1 1 -8 0 1 0 0 -6 0 1 0 1 -4 0 1 1 0 -2 0 1 1 1 0 1 1 1 1 0 1 1 1 0 2 1 1 0 1 4 1 1 0 0 6 1 0 1 1 8 1 0 1 0 10 1 0 0 1 12 1 0 0 0 14 14/21 TDA7430 - TDA7431 VOICE CANCELLER/INPUT/RECOUT L & R SELECTION MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 VOICE CANCELLER 0 OFF 1 ON INPUT MULTIPLEXER 0 0 IN2 0 1 IN3 1 0 IN4 1 1 IN1 REC OUT ”L” 0 0 VER 1 (3BAND) 0 1 VER 2 (SURR) 1 0 VER 3 (REAR) 1 1 FIX REC OUT ”R” 0 0 VER 1 (3BAND) 0 1 VER 2 (SURR) 1 0 VER 3 (REAR) 1 1 FIX POWER ON RESET BASS & MIDDLE 2dB TREBLE 0dB SURROUND & OUT CONTROL+ EFFECT CONTROL OFF + FIX + MAX ATTENUATION SPEAKER/RECORD ATTENUATION L &R MUTE INPUT ATTENUATION + REARN SWITCH MAX ATTENUATION + ON NATURAL BASE OFF VOICE CANCELER OFF INPUT IN1 PIN: L-OUT, R-OUT, RECOUT-L, RECOUT-R VS 20µA 100Ω GND D94AU204 15/21 TDA7430 - TDA7431 PIN: HP1 PIN: HP2 LP1 VS VS 10K 20µA 5.5K 60K 60K GND HP2 GND HP1 5.5K D94AU199 D94AU198 PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4, VS PIN: VER-L, VER-R, VS 20µA 20µA SW 50K GND VREF 30K D94AU200 PIN: CREF GND Vref D95AU227 PIN: LP1 VS VS 20K 20µA 20µA 42K 10K 20K GND GND 16/21 D95AU336 HP1 D94AU211 TDA7430 - TDA7431 PIN: SCL, SDA PIN: PS1, PS2, PS3, PS4 LP VS 20µA GND D94AU205 20µA GND D95AU308 PIN: ADDR PIN: REARIN VS VS 20µA 20µA SW 50K GND GND 50K D95AU228A PIN: MIX GND Vref D95AU229 PIN: REAROUT, BASSO-L, BASSO-R VS VS 20µA 20µA 100K GND Vref D94AU123 GND D95AU230 17/21 TDA7430 - TDA7431 PIN: BASS-LI,BASS-RI, MIDDLE-LI, MIDDLE-RI, PIN: BASS-LO,BASS-RO,MIDDLE-LO,MIDDLE-RO, VS VS 20µA 20µA (*) GND 45K : Bass or 25K : MIDDLE GND BASS-LO BASS-RO,MIDDLE-LO,MIDDLE-RO BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI D95AU231A PIN: TREBLE-L, TREBLE-R D95AU232 (*) 45K : Bass 25K : MIDDLE PIN: VOUT REF VS VS 20µA 20µA 25K GND GND D95AU233A 10K GND D95AU309 PIN: NBLIN, NBRIN PIN: NBLO, NBRO VS VS 20µA VREF GND D95AU234 18/21 SW GND D95AU235A TDA7430 - TDA7431 SDIP42 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 5.08 0.20 A1 0.51 A2 3.05 3.81 4.57 0.120 B 0.38 0.46 0.56 0.0149 0.0181 0.0220 B1 0.89 1.02 1.14 0.035 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 D 36.58 36.83 37.08 1.440 E 15.24 16.00 0.60 E1 12.70 14.48 0.50 0.020 13.72 0.150 0.040 1.450 0.180 0.045 1.460 0.629 0.540 e 1.778 0.070 e1 15.24 0.60 0.570 e2 18.54 0.730 e3 1.52 0.060 L 2.54 OUTLINE AND MECHANICAL DATA MAX. 3.30 3.56 0.10 0.130 SDIP42 (0.600”) 0.140 E A2 A L A1 E1 B B1 e e1 e2 D c E 42 22 .015 0,38 Gage Plane 1 e3 21 e2 SDIP42 19/21 TDA7430 - TDA7431 mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.30 C 0.09 0.063 0.006 0.15 0.002 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.014 0.018 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 e 0.80 0.031 E 12.00 0.472 E1 10.00 0.394 E3 8.00 0.315 L 0.45 0.60 0.75 OUTLINE AND MECHANICAL DATA MAX. 0.018 0.024 L1 1.00 K 0°(min.), 3.5°(typ.), 7°(max.) 0.030 0.039 TQFP44 (10 x 10) D D1 A A2 A1 33 23 34 22 0.10mm .004 B E B E1 Seating Plane 12 44 11 1 C L e K TQFP4410 20/21 TDA7430 - TDA7431 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 21/21