STMICROELECTRONICS TDA7442

TDA7442
TDA7442D
TONE CONTROL AND SURROUND
DIGITALLY CONTROLLED AUDIO PROCESSOR
1
■
■
■
■
■
■
■
2
FEATURES
4 STEREO INPUTS
INPUT ATTENUATION CONTROL IN 0.5dB
STEP
TREBLE AND BASS CONTROL
TWO SURROUND MODE AVAILABLE WITH 4
SELECTABLE RESPONSES:
– MUSIC
– SIMULATED STEREO
TWO SPEAKER ATTENUATORS:
– 2 INDEPENDENT SPEAKER CONTROLS IN
1dB STEPS FOR BALANCE FACILITY
– INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA
SERIAL BUS
2 MONITOR OUTPUT (ONLY FOR TDA7442)
DESCRIPTION
The TDA7442/42D is volume tone (bass and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems.
It reproduces surround sound by using a program-
Figure 1. Packages
SO-28
SDIP-32
Table 1. Order Codes
Part Number
Package
TDA7442
SDIP-32
TDA7442D
SO-28
TDA7442D013TR
Tape & Reel
mable phase shifter. Control of all the functions is
accomplished by serial bus.
The AC signal setting is obtained by resistor networks and switches combined with operational
amplifiers.
Thanks to the BIPOLAR/CMOS Technology used,
Low Distortion, Low Noise and DC stepping are
obtained.
Figure 2. Pin Connections (Top views)
R_IN3
R_IN2
28
1
2
27
R-IN2
1
32
R-IN3
R_IN4
R-IN1
2
31
R-IN4
LOUT
MONITOR(L)
3
30
L-OUT
4
29
R-OUT
R_IN1
3
26
ROUT
MONITOR(R)
L_IN1
4
25
AGND
L-IN1
5
28
AGND
VS
L-IN2
6
27
VS
23
CREF
L-IN3
7
26
CREF
22
SDA
L-IN4
8
25
SDA
SCL
MUXOUT(L)
9
L_IN2
5
L_IN3
6
L_IN4
7
MUXOUTL
IN(L)
MUXOUT(R)
IN(R)
8
24
SO28
21
24
SCL
IN(L)
10
23
DIGGND
9
20
DIG-GND
10
19
TREBLE(R)
MUXOUT(R)
11
22
TREBLE-R
TREBLE(L)
N.C.
12
21
N.C.
IN(R)
13
20
TREBLE-L
11
18
BIN(R)
12
17
PS1
BOUT(R)
13
16
LP
BIN(L)
SDIP32
14
15
D98AU948
BOUT(L)
BIN(R)
14
19
PS1
BOUT(R)
15
18
LP
BIN(L)
16
17
BOUT(L)
D01AU1247
June 2004
REV. 2
1/17
TDA7442 - TDA7442D
Figure 3. Block Diagram (TDA7442)
5.6nF
100nF
5.6K
100nF
100nF
MONITOR(L)
0.47µF
3
5
IN(L)
2.2µF
MUXOUT(L)
9
31.5dB
control
10
L-IN1
6
20
BIN(L) BOUT(L)
16
17
RB
FIX
30K
L-IN2
PS1
90Hz
50K
0.47µF
TREBLE-L
19
RPS1
50K
0.47µF
PS1
OFF
7
79dB CONTROL
L-IN3
50K
0.47µF
8
-
L-IN4
+
50K
+
SURR
MUSIC/
SYMULATED
SYMULATED
VAR
+
FIX
L+R
MIXING
AMP
MUSIC
-
OFF
L-R
-
TREBLE
SPKR
ATT
24
25
I2C BUS DECODER + LATCHES
2
LOUT
BASS
+
0.47µF
30
MUTE
23
SCL
SDA
DIG GND
R-IN1
50K
0.47µF
1
LPF
9KHz
R-IN2
FIX
SURR
+
VAR
SPKR
ATT
-
R-IN3
OFF
30K
50K
29
ROUT
MUTE
31
79dB CONTROL
R-IN4
31.5dB
control
50K
4
MONITOR(R)
Vref
SUPPLY
11
13
MUXOUT(R)
18
27
28
VS
LP
IN(R)
0.47µF
BASS
32
RB
26
CREF
AGND
0.47µF
TREBLE
MIXING
AMP
EFFECT
CONTROL
50K
14
TREBLE-R
BIN(R)
13
BOUT(R)
D98AU947B
22µF
1.2nF
2.2µF
22
5.6nF
100nF
100nF
5.6K
Figure 4. Block Diagram (TDA7442D)
5.6nF
100nF
5.6K
100nF
100nF
MUXOUT(L)
0.47µF
8
31.5dB
control
4
IN(L)
2.2µF
PS1
TREBLE-L
9
17
18
L-IN1
5
RB
FIX
30K
L-IN2
PS1
90Hz
50K
0.47µF
BOUT(L)
15
RPS1
50K
0.47µF
BIN(L)
14
OFF
6
79dB CONTROL
L-IN3
50K
0.47µF
7
-
L-IN4
50K
+
MUSIC/
SYMULATED
SYMULATED
+
VAR
SURR
FIX
L+R
MIXING
AMP
MUSIC
-
OFF
L-R
+
TREBLE
SPKR
ATT
21
22
I2C BUS DECODER + LATCHES
3
LOUT
BASS
+
0.47µF
27
MUTE
20
SCL
SDA
DIG GND
R-IN1
50K
0.47µF
2
LPF
9KHz
R-IN2
FIX
VAR
1
30K
50K
OFF
SPKR
ATT
MUTE
28
79dB CONTROL
R-IN4
50K
31.5dB
control
SUPPLY
10
11
16
IN(R)
MUXOUT(R)
2.2µF
LP
24
25
VS
1.2nF
Vref
RB
23
CREF
19
12
TREBLE-R
BIN(R)
13
BOUT(R)
22µF
5.6nF
2/17
+
-
R-IN3
0.47µF
BASS
SURR
AGND
0.47µF
TREBLE
MIXING
AMP
EFFECT
CONTROL
50K
100nF
5.6K
100nF
D01AU1248
26
ROUT
TDA7442 - TDA7442D
Table 2. Quick Reference Data
Symbol
Parameter
Min.
Typ.
Max.
9
10.2
Unit
VS
Supply Voltage
7
VCL
Max. input signal handling
2
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
S/N
Signal to Noise Ratio Vout = 1Vrms (mode = OFF)
106
dB
SC
Channel Separation f = 1KHz
90
dB
V
Vrms
0.1
%
Treble Control (2db step)
-14
+14
Bass Control (2dB step)
-14
+14
dB
Balance Control 1dB step (LCH, RCH)
-79
0
dB
Mute Attenuation
dB
100
dB
Table 3. Thermal Data
Symbol
Rth j-pins
Parameter
Thermal Resistance Junction-pins
Value
Unit
85
°C/W
Value
Unit
11
V
-10 to 70
°C
-55 to +150
°C
Max.
Table 4. Absolute Maximum Ratings
Symbol
VS
Parameter
Operating Supply Voltage
Tamb
Operating Ambient Temperature
Tstg
Storage Temperature Range
Table 5. Electrical Characteristics
Refer to the test circuit Tamb = 25°C, VS = 9V, R L = 10KΩ, Vin = 1Vrms; R G = 600Ω, all controls flat (G =
0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Supply Voltage
7
9
10.2
V
Supply Current
10
18
26
mA
Ripple Rejection
60
80
SUPPLY
VS
IS
SVR
LCH / RCH out, Mode = OFF
dB
INPUT STAGE
RIN
Input Resistance
VCL
Clipping Level
CRANGE
Control Range
THD = 0.3%
35
50
2
2.5
65
KΩ
Vrms
31.5
dB
AVMIN
Min. Attenuation
-1
0
1
dB
AVMAX
Max. Attenuation
31
31.5
32
dB
ASTEP
Step Resolution
0.5
1
dB
BASS CONTROL
Gb
Control Range
±11.5
±14.0
±16.0
dB
BSTEP
Step Resolution
1
2
3
dB
Internal Feedback Resistance
32
44
56
KΩ
RB
Max. Boost/cut
3/17
TDA7442 - TDA7442D
Table 5. Electrical Characteristics (continued)
Refer to the test circuit Tamb = 25°C, VS = 9V, R L = 10KΩ, Vin = 1Vrms; R G = 600Ω, all controls flat (G =
0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
+13.0
+14.0
+15.0
dB
1
2
3
dB
-6
dB
1.5
dB
TREBLE CONTROL
Gt
Control Range
TSTEP
Step Resolution
Max. Boost/cut
EFFECT CONTROL
CRANGE
Control Range
- 21
SSTEP
Step Resolution
0.5
1
SURROUND SOUND MATRIX PHASE
RPS10
Phase Shifter 1: D1 = 0, D0 = 0
8.3
11.8
15.2
KΩ
RPS11
Phase Shifter 1: D1 = 0, D0 = 1
10
14.1
18.3
KΩ
RPS12
Phase Shifter 1: D1 = 1, D0 = 0
12.6
17.9
23.3
KΩ
RPS13
Phase Shifter 1: D1 = 1, D0 = 1
26.4
37.3
48.85
KΩ
SURROUND SOUND MATRIX
TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1
GOFF
In-phase Gain (OFF)
Mode OFF, Input signal of
-1
0
1
dB
DGOFF
LR In-phase Gain Difference
(OFF)
Mode OFF, Input signal of 1kHz,
1.4 Vp-p Rin → Rout, Lin → Lout
-1
0
1
dB
GMUS
In-phase Gain (Music)
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 Vp-p (Rin
→ Rout), (Lin → Lout)
7
dB
DGMUS
LR In-phase Gain Difference
(Music)
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 Vp-p (Rin
→ Rout) - (Lin → Lout)
0
dB
79
dB
1kHz, 1.4 Vp-p, Rin → Rout Lin →
Lout
SPEAKER ATTENUATORS
Crange
Control Range
SSTEP
Step Resolution
EA
VDC
Attenuation set error
DC Steps
AMUTE
Output Mute Condition
RVEA
Input Impedance
Av = 0 to -20dB
-0.5
1
1.5
dB
-1.5
0
1.5
dB
Av = -20 to -79dB
-3
0
2
dB
adjacent att. steps
-3
0
3
mV
+70
100
21
30
dB
39
KΩ
AUDIO OUTPUTS
NO(OFF)
Output Noise (OFF)
Output Mute, Flat
BW = 20Hz to 20KHz
4
5
µVrms
µVrms
NO(MUS)
Output Noise (Music)
Mode = Music ,
BW = 20Hz to 20KHz,
30
mVrms
Output Noise (Pseudo Stereo)
Mode = Pseudo Stereo
BW = 20Hz to 20KHz,
30
mVrms
Distorsion
Av = 0 ; Vin = 1Vrms
NO(PSEUDO)
d
SC
4/17
Channel Separation
VOCL
Clipping Level
ROUT
Output Resistance
d = 0.3%
0.01
0.1
%
70
90
dB
2
2.5
Vrms
10
30
50
Ω
TDA7442 - TDA7442D
Table 5. Electrical Characteristics (continued)
Refer to the test circuit Tamb = 25°C, VS = 9V, R L = 10KΩ, Vin = 1Vrms; R G = 600Ω, all controls flat (G =
0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol
VOUT
Parameter
Test Condition
Min.
DC Voltage Level
Typ.
Max.
3.8
Unit
V
MONITOR OUTPUTS
d
SC
Distorsion
Av = 0 ; Vin = 1Vrms
Channel Separation
VOCL
Clipping Level
ROUT
Output Resistance
VOUT
DC Voltage Level
d = 0.3%
0.01
0.1
%
70
90
dB
2
2.5
Vrms
20
50
70
4.5
Ω
V
BUS INPUTS
VIL
Input Low Voltage
VIH
Input High Voltage
IIN
Input Current
VO
Output Voltage SDA
Acknowledge
1
3
-5
IO = 1.6mA
V
V
+5
µA
0.4
V
5/17
TDA7442 - TDA7442D
3
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7442D and vice versa takes place through the 2 wires
I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
3.1 Data Validity
As shown in fig. 5, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2 Start and Stop Conditions
As shown in fig. 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
3.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
3.4 Acknowledge
The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
3.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 5. Data Validity on the I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 6. Timing Diagram of I2CBUS
SCL
I2CBUS
SDA
D99AU1032
START
STOP
Figure 7. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA
MSB
START
6/17
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
TDA7442 - TDA7442D
4
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
■
■
■
■
■
A start condition (S)
A chip address byte, containing the TDA7442D
A subaddress bytes
A sequence of data (N byte + acknowledge)
A stop condition (P)
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
0
0
A
0
MSB
ACK
DATA 1 to DATA n
LSB
DATA
B
MSB
ACK
LSB
DATA
ACK
P
D95AU226A
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
4.1 EXAMPLES
4.1.1 No Incremental Bus
The TDA7442D receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no
incremental bus), N-datas (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
0
0
A
0
MSB
ACK
0
DATA
LSB
X
X
MSB
X D3 D2 D1 D0 ACK
LSB
DATA
ACK
P
D95AU306
4.1.2 Incremental Bus
The TDA7442D receive a start conditions, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concerns the subaddress sent plus one sent
in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
0
0
A
0
MSB
ACK
1
DATA 1 to DATA n
LSB
X
X
X D3 D2 D1 D0 ACK
MSB
LSB
DATA
ACK
P
D95AU307
7/17
TDA7442 - TDA7442D
5
DATA BYTES
Address = 80(HEX)
5.1 Function Selection:
The first byte (subaddress)
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
B
X
X
X
0
0
0
D0
0
INPUT ATTENUATION
B
X
X
X
0
0
0
1
SURROUND & OUT & EFFECT
CONTROL
B
X
X
X
0
0
1
0
PHASE RESISTOR
B
X
X
X
0
0
1
1
BASS
B
X
X
X
0
1
0
0
TREBLE
B
X
X
X
0
1
0
1
SPEAKER ATTENUATION "L"
B
X
X
X
0
1
1
0
SPEAKER ATTENUATION "R"
B
X
X
X
0
1
1
1
NOT ALLOWED
B
X
X
X
1
0
0
0
NOT ALLOWED
B
X
X
X
1
0
0
1
INPUT MULTIPLEXER
B = 1 incremental bus; active
B = 0 no incremental bus;
X = indifferent 0,1
Input Attenuation Selection
MSB
D7
D6
D5
D4
D3
LSB
INPUT ATTENUATION
D2
D1
D0
0.5 dB STEPS
1
0
0
0
0
1
0
0
1
-0.5
1
0
1
0
-1
1
0
1
1
-1.5
1
1
0
0
-2
1
1
0
1
-2.5
1
1
1
0
-3
1
1
1
1
-3.5
4 dB STEPS
1
0
0
0
0
1
0
0
1
-4
1
0
1
0
-8
1
0
1
1
-12
1
1
0
0
-16
1
1
0
1
-20
1
1
1
0
-24
1
1
1
1
-28
INPUT ATTENUATION = 0 ~ -31.5dB
8/17
TDA7442 - TDA7442D
5.2 Surround Selection
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
SURROUND MODE
0
0
SIMULATED STEREO
0
1
MUSIC
1
0
OFF
OUT
0
VAR
1
FIX
EFFECT CONTROL
0
0
0
0
-6
0
0
0
1
-7
0
0
1
0
-8
0
0
1
1
-9
0
1
0
0
-10
0
1
0
1
-11
0
1
1
0
-12
0
1
1
1
-13
1
0
0
0
-14
1
0
0
1
-15
1
0
1
0
-16
1
0
1
1
-17
1
1
0
0
-18
1
1
0
1
-19
1
1
1
0
-20
1
1
1
1
-21
PHASE RESISTOR SELECTION
MSB
D7
D6
D5
D4
D3
D2
LSB
SURROUND PHASE RESISTOR
D1
D0
PHASE SHIFT 1 (KΩ)
0
0
12
0
1
14
1
0
18
1
1
37
BASS SELECTION
MSB
LSB
BASS
D7
D6
D5
D4
D3
D2
D1
D0
2 dB STEPS
X
X
X
1
0
0
0
0
-14
X
X
X
1
0
0
0
1
-12
X
X
X
1
0
0
1
0
-10
X
X
X
1
0
0
1
1
-8
X
X
X
1
0
1
0
0
-6
X
X
X
1
0
1
0
1
-4
X
X
X
1
0
1
1
0
-2
X
X
X
1
0
1
1
1
0
X
X
X
1
1
1
1
1
0
9/17
TDA7442 - TDA7442D
5.2 Surround Selection (continued)
MSB
LSB
BASS
D7
D6
D5
D4
D3
D2
D1
D0
2 dB STEPS
X
X
X
1
1
1
1
0
2
X
X
X
1
1
1
0
1
4
X
X
X
1
1
1
0
0
6
X
X
X
1
1
0
1
1
8
X
X
X
1
1
0
1
0
10
X
X
X
1
1
0
0
1
12
X
X
X
1
1
0
0
0
14
LSB
SPEAKER/ATT
D4
D3
D2
D1
D0
1 dB STEPS
X
0
0
0
0
X
0
0
1
-1
X
0
1
0
-2
X
0
1
1
-3
X
1
0
0
-4
X
1
0
1
-5
X
1
1
0
-6
X
1
1
1
SPEAKER SELECTION
MSB
D7
D6
D5
-7
8 dB STEPS
X
0
0
0
0
0
X
0
0
0
1
-8
X
0
0
1
0
-16
X
0
0
1
1
-24
X
0
1
0
0
-32
X
0
1
0
1
-40
X
0
1
1
0
-48
X
0
1
1
1
-56
X
1
0
0
0
-64
X
1
0
0
1
-72
MUTE
X
1
0
1
X
X
1
1
X
X
X = INDIFFERENT 0,1
SPEAKER ATTENUATION = 0dB ~ -79dB
TREBLE SELECTION
MSB
LSB
TREBLE
D7
D6
D5
D4
D3
D2
D1
D0
2 dB STEPS
0
0
0
0
1
1
1
0
-14
0
0
0
1
1
1
1
0
-12
0
0
1
0
1
1
1
0
-10
0
0
1
1
1
1
1
0
-8
0
1
0
0
1
1
1
0
-6
0
1
0
1
1
1
1
0
-4
10/17
TDA7442 - TDA7442D
5.2 Surround Selection (continued)
MSB
LSB
TREBLE
D7
D6
D5
D4
D3
D2
D1
D0
2 dB STEPS
0
1
1
0
1
1
1
0
-2
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
0
2
1
1
0
1
1
1
1
0
4
1
1
0
0
1
1
1
0
6
1
0
1
1
1
1
1
0
8
1
0
1
0
1
1
1
0
10
1
0
0
1
1
1
1
0
12
1
0
0
0
1
1
1
0
14
INPUT SELECTION
MSB
D7
LSB
D2
D1
D0
INPUT MULTIPLEXER
X
D6
D5
D4
D3
0
0
0
IN2
X
0
1
0
IN3
X
1
0
0
IN4
1
1
0
IN1
X
X = INDIFFERENT 0,1
SPEAKER ATTENUATION = 0dB ~ -79dB
TREBLE SELECTION
MSB
D7
D6
D5
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
INPUT SELECTION
MSB
D7
D6
D5
X
X
X
X
D4
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
D3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LSB
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TREBLE
2 dB STEPS
-14
-12
-10
-8
-6
-4
-2
0
0
2
4
6
8
10
12
14
D4
D3
D2
0
0
1
1
D1
0
1
0
1
LSB
D0
0
0
0
0
INPUT MULTIPLEXER
IN2
IN3
IN4
IN1
11/17
TDA7442 - TDA7442D
Table 6.
POWER ON RESET
BASS
2dB
TREBLE
0dB
SURROUND & OUT CONTROL+ EFFECT CONTROL
OFF + FIX + MAX ATTENUATION
SPEAKER ATTENUATION L &R
MUTE
INPUT ATTENUATION
MAX ATTENUATION
INPUT
IN1
Figure 8. PIN: TREBLE-L, TREBLE-R
Figure 11. PIN: CREF
VS
VS
20µA
20µA
20K
42K
20K
25K
D95AU336
GND
GND
Figure 12. PIN: SCL, SDA
D95AU309
20µA
Figure 9. PIN: VOUT REF
VS
20µA
GND
D94AU205
Figure 13. PIN: LP
VS
GND
20µA
D95AU233A
10K
GND
Figure 10. PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3,
R-IN3,L-IN4, R-IN4,
GND
D95AU308
Figure 14. PIN: L-OUT, R-OUT
VS
20µA
VS
20µA
50K
GND
VREF
D94AU200
GND
D95AU230
12/17
TDA7442 - TDA7442D
Figure 15. PIN: BASS-LI, BASS-RI
Figure 16. PIN: BASS-LO, BASS-RO
VS
VS
20µA
GND
20µA
45K
45K : Bass
GND
BASS-LO
BASS-RO
D98AU949
BASS-LI,BASS-RI
D98AU950
13/17
TDA7442 - TDA7442D
Figure 17. SO-28 Mechanical Data & Package Dimensions
mm
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
2.65
MAX.
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
0.5
c1
0.020
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
OUTLINE AND
MECHANICAL DATA
0.104
a1
C
14/17
inch
8 ° (max.)
SO-28
TDA7442 - TDA7442D
Figure 18. SDIP-32 Mechanical Data & Package Dimensions
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
3.556
3.759
5.080
0.14
0.147
0.2
A1
0.508
A2
3.048
3.556
4.572
0.12
0.14
0.18
B
0.356
0.457
0.584
0.014
0.018
0.023
B1
0.762
1.016
1.397
0.03
0.04
0.055
C
0.203
0.254
0.356
0.008
0.01
0.014
D
27.43
27.94
28.45
1.08
1.1
1.12
E
9.906
10.41
11.05
0.39
0.409
0.433
E1
7.620
8.890
9.398
0.3
0.35
0.37
0.020
e
1.778
0.070
eA
10.16
0.400
eB
L
12.70
2.540
3.048
3.810
SDIP-32
(Shrink Plastic Dip 32L)
0.500
0.1
0.12
0.15
E
E1
A2
A
A1
L
B
B1
e
eA
eB
D
C
32
17
1
16
SDIP32M
0123183
15/17
TDA7442 - TDA7442D
Table 7. Revision History
Date
Revision
January 2001
1
First issue.
June 2004
2
Changed the Style-sheet in compliance to the new “Corporate Technical
Pubblications Design Guide”
16/17
Description of Changes
TDA7442 - TDA7442D
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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17/17