TDA7442 TDA7442D ® TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR 4 STEREO INPUTS INPUT ATTENUATION CONTROL IN 0.5dB STEP TREBLE AND BASS CONTROL TWO SURROUND MODE AVAILABLE WITH 4 SELECTABLE RESPONSES: - MUSIC - SIMULATED STEREO TWO SPEAKER ATTENUATORS: - 2 INDEPENDENT SPEAKER CONTROLS IN 1dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS 2 MONITOR OUTPUT (ONLY FOR TDA7442) DESCRIPTION The TDA7442/42D is volume tone (bass and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems. It reproduces surround sound by using a pro- SO28 SDIP32 ORDERING NUMBER: TDA7442D (SO28) TDA7442 (SDIP32) grammable phase shifter. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the BIPOLAR/CMOS Technology used, Low Distortion, Low Noise and DC stepping are obtained. PIN CONNECTIONS R-IN2 1 32 R-IN3 R_IN3 1 28 R_IN4 R-IN1 2 31 R-IN4 R_IN2 2 27 LOUT MONITOR(L) 3 30 L-OUT R_IN1 3 26 ROUT MONITOR(R) 4 29 R-OUT L_IN1 4 25 AGND L-IN1 5 28 AGND L_IN2 5 24 VS L-IN2 6 27 VS L-IN3 7 26 CREF L-IN4 8 25 SDA MUXOUT(L) 9 24 SCL IN(L) 10 23 DIGGND MUXOUT(R) 11 22 TREBLE-R N.C. 12 21 N.C. IN(R) 13 20 TREBLE-L BIN(R) 14 19 PS1 BOUT(R) 15 18 LP BIN(L) 16 17 BOUT(L) L_IN3 L_IN4 6 23 7 22 CREF SDA MUXOUTL 8 21 SCL IN(L) 9 20 DIG-GND MUXOUT(R) 10 19 TREBLE(R) IN(R) 11 18 TREBLE(L) BIN(R) 12 17 PS1 BOUT(R) 13 16 LP BIN(L) 14 15 BOUT(L) D98AU948 SO28 January 2001 D01AU1247 SDIP32 1/16 TDA7442 - TDA7442D BLOCK DIAGRAM (TDA7442) 5.6nF 100nF 5.6K 100nF 100nF MONITOR(L) 0.47µF 3 5 IN(L) 2.2µF MUXOUT(L) 31.5dB control 9 10 L-IN1 6 20 BIN(L) BOUT(L) 16 17 RB FIX 30K L-IN2 PS1 90Hz 50K 0.47µF TREBLE-L 19 RPS1 50K 0.47µF PS1 OFF 7 79dB CONTROL L-IN3 50K 0.47µF 8 - L-IN4 + 50K + SURR MUSIC/ SYMULATED SYMULATED VAR + FIX L+R MIXING AMP MUSIC - OFF L-R - TREBLE SPKR ATT 24 25 I2C BUS DECODER + LATCHES 2 LOUT BASS + 0.47µF 30 MUTE 23 SCL SDA DIG GND R-IN1 50K 0.47µF 1 LPF 9KHz R-IN2 FIX + VAR SPKR ATT - 32 R-IN3 30K 50K 29 ROUT MUTE OFF 79dB CONTROL 31 R-IN4 31.5dB control 50K 4 MONITOR(R) Vref SUPPLY 11 13 MUXOUT(R) 18 27 28 VS LP IN(R) 0.47µF BASS SURR RB 26 CREF AGND 0.47µF TREBLE MIXING AMP EFFECT CONTROL 50K 1.2nF 2.2µF 22 14 TREBLE-R BIN(R) 13 D98AU947B BOUT(R) 22µF 5.6nF 100nF 100nF 5.6K BLOCK DIAGRAM (TDA7442D) 5.6nF 100nF 5.6K 100nF 100nF MUXOUT(L) 0.47µF 31.5dB control 4 8 IN(L) 2.2µF PS1 TREBLE-L 9 17 18 L-IN1 5 RB FIX 30K L-IN2 PS1 90Hz 50K 0.47µF BOUT(L) 15 RPS1 50K 0.47µF BIN(L) 14 OFF 6 79dB CONTROL L-IN3 50K 0.47µF 7 - L-IN4 50K + + SURR MUSIC/ SYMULATED SYMULATED VAR + FIX L+R MIXING AMP MUSIC - OFF L-R - TREBLE SPKR ATT 21 22 I2C BUS DECODER + LATCHES 3 LOUT BASS + 0.47µF 27 MUTE 20 SCL SDA DIG GND R-IN1 50K 0.47µF 2 LPF 9KHz R-IN2 FIX VAR 30K 50K SPKR ATT MUTE OFF 79dB CONTROL 28 R-IN4 50K 31.5dB control SUPPLY 10 11 16 IN(R) MUXOUT(R) 2.2µF LP 24 25 VS 1.2nF Vref RB 23 CREF 19 12 TREBLE-R BIN(R) 13 BOUT(R) 22µF 5.6nF 2/16 + - 1 R-IN3 0.47µF BASS SURR AGND 0.47µF TREBLE MIXING AMP EFFECT CONTROL 50K 100nF 5.6K 100nF D01AU1248 26 ROUT TDA7442 - TDA7442D QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. 9 10.2 VS VCL Supply Voltage 7 Max. input signal handling 2 THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N SC Signal to Noise Ratio V out = 1Vrms (mode = OFF) Channel Separation f = 1KHz 106 90 Treble Control (2db step) Unit V Vrms 0.1 % dB dB -14 +14 dB Bass Control (2dB step) -14 +14 dB Balance Control 1dB step (LCH, RCH) Mute Attenuation -79 0 dB 100 dB THERMAL DATA Symbol Rth j-pins Description Thermal Resistance Junction-pins Value 85 Max. Unit °C/W ABSOLUTE MAXIMUM RATINGS Symbol Parameter VS Tamb Operating Supply Voltage Tstg Storage Temperature Range Operating Ambient Temperature Value Unit 11 V -10 to 85 °C -55 to +150 °C 3/16 TDA7442 - TDA7442D ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS Supply Voltage 7 9 10.2 V IS SVR Supply Current 10 18 26 mA 60 80 Ripple Rejection LCH / RCH out, Mode = OFF dB INPUT STAGE RIN Input Resistance VCL Clipping Level CRANGE Control Range AVMIN AVMAX Min. Attenuation -1 0 1 dB Max. Attenuation 31 31.5 32 dB ASTEP Step Resolution 0.5 1 dB THD = 0.3% 35 50 2 2.5 65 KΩ Vrms 31.5 dB BASS CONTROL Gb Control Range +11.5 +14.0 +16.0 dB BSTEP Step Resolution 1 2 3 dB Internal Feedback Resistance 32 44 56 KΩ +13.0 +14.0 +15.0 dB 1 2 3 dB -6 dB RB Max. Boost/cut TREBLE CONTROL Gt Control Range TSTEP Step Resolution Max. Boost/cut EFFECT CONTROL CRANGE SSTEP Control Range - 21 Step Resolution 0.5 1 1.5 dB SURROUND SOUND MATRIX PHASE RPS10 Phase Shifter 1: D1 = 0, D0 = 0 8.3 11.8 15.2 KΩ RPS11 RPS12 Phase Shifter 1: D1 = 0, D0 = 1 Phase Shifter 1: D1 = 1, D0 = 0 10 12.6 14.1 17.9 18.3 23.3 KΩ KΩ RPS13 Phase Shifter 1: D1 = 1, D0 = 1 26.4 37.3 48.85 KΩ SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1 Symbol Parameter GOFF In-phase Gain (OFF) DGOFF LR In-phase Gain Difference (OFF) GMUS In-phase Gain (Music) DGMUS LR In-phase Gain Difference (Music) 4/16 Test Condition Min. Typ. Max. Unit Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin → Rout Lin → Lout Mode OFF, Input signal of 1kHz, 1.4 Vp-p Rin → Rout, Lin → Lout Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout), (Lin → Lout) -1 0 1 dB -1 0 1 dB Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) - (Lin → Lout) 7 dB 0 dB TDA7442 - TDA7442D ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit SPEAKER ATTENUATORS Crange Control Range SSTEP Step Resolution EA VDC AMUTE RVEA Attenuation set error 79 1 1.5 dB dB -1.5 0 1.5 Av = -20 to -79dB -3 0 2 dB adjacent att. steps -3 0 3 mV Output Mute Condition +70 100 Input Impedance 21 30 39 KΩ DC Steps Av = 0 to -20dB dB -0.5 dB AUDIO OUTPUTS NO(OFF) Output Noise (OFF) NO(MUS) Output Noise (Music) NO(PSEUDO) d Output Mute, Flat BW = 20Hz to 20KHz Mode = Music , BW = 20Hz to 20KHz, Output Noise (Pseudo Stereo) Mode = Pseudo Stereo BW = 20Hz to 20KHz, Distorsion Av = 0 ; Vin = 1Vrms SC VOCL Channel Separation ROUT VOUT Output Resistance Clipping Level d = 0.3% 30 µVrms µVrms mVrms 30 mVrms 4 5 0.01 0.1 % 70 90 dB 2 2.5 Vrms 10 30 DC Voltage Level 50 3.8 Ω V MONITOR OUTPUTS d Distorsion Av = 0 ; Vin = 1Vrms SC VOCL Channel Separation Clipping Level d = 0.3% ROUT VOUT Output Resistance DC Voltage Level 0.01 70 2 90 2.5 20 50 4.5 0.1 % dB Vrms 70 Ω V BUS INPUTS VIL Input Low Voltage VIH IIN Input High Voltage Input Current VO Output Voltage SDA Acknowledge 3 -5 IO = 1.6mA 1 V +5 V µA 0.4 V 5/16 TDA7442 - TDA7442D knowledge bit. The MSB is transferred first. I2C BUS INTERFACE Data transmission from microprocessor to the TDA7442D and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 4: Timing Diagram of I2CBUS SCL I2CBUS SDA D99AU1032 START STOP Figure 5: Acknowledge on the I2CBUS SCL 1 2 3 7 8 9 SDA MSB START 6/16 D99AU1033 ACKNOWLEDGMENT FROM RECEIVER TDA7442 - TDA7442D address A subaddress bytes A sequence of data (N byte + achnowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7442D SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 MSB ACK DATA 1 to DATA n LSB B DATA MSB ACK LSB DATA ACK P D95AU226A ACK = Achnowledge S = Start P = Stop A = Address B = Auto Increment EXAMPLES No Incremental Bus The TDA7442D receives a start condition, the CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition. A 0 MSB ACK 0 DATA LSB X X MSB X D3 D2 D1 D0 ACK LSB DATA ACK P D95AU306 Incremental Bus The TDA7442D receive s a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored. The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. A 0 MSB ACK 1 DATA 1 to DATA n LSB X X X D3 D2 D1 D0 ACK MSB LSB DATA ACK P D95AU307 7/16 TDA7442 - TDA7442D DATA BYTES Address = 80(HEX) FUNCTION SELECTION: The first byte (subaddress) MSB LSB SUBADDRESS D7 B D6 X D5 X D4 X D3 0 D2 0 D1 0 D0 0 B X X X 0 0 0 1 B X X X 0 0 1 0 SURROUND & OUT & EFFECT CONTROL PHASE RESISTOR B X X X 0 0 1 1 BASS B X X X 0 1 0 0 TREBLE B B X X X X X X 0 0 1 1 0 1 1 0 SPEAKER ATTENUATION "L" SPEAKER ATTENUATION "R" B X X X 0 1 1 1 NOT ALLOWED B B X X X X X X 1 1 0 0 0 0 0 1 NOT ALLOWED INPUT MULTIPLEXER INPUT ATTENUATION B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 INPUT ATTENUATION SELECTION MSB D7 D6 1 1 1 1 1 1 1 1 D5 D4 D3 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 INPUT ATTENUATION = 0 ∼ -31.5dB 8/16 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB INPUT ATTENUATION D0 0 1 0 1 0 1 0 1 0.5 dB STEPS 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 4 dB STEPS 0 -4 -8 -12 -16 -20 -24 -28 TDA7442 - TDA7442D SURROUND SELECTION MSB D7 LSB D6 D5 D4 D3 D2 D1 0 0 1 D0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SURROUND MODE SIMULATED STEREO MUSIC OFF OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 PHASE RESISTOR SELECTION MSB D7 LSB D6 D5 D4 D3 D2 D1 0 0 1 1 D0 0 1 0 1 SURROUND PHASE RESISTOR PHASE SHIFT 1 (KΩ) 12 14 18 37 9/16 TDA7442 - TDA7442D BASS SELECTION MSB D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB BASS D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 LSB SPEAKER/ATT D0 0 1 0 1 0 1 0 1 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE SPEAKER SELECTION MSB D7 X X X X X X X X D6 D5 D4 D3 X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 X X 1 1 0 1 1 X X X X = INDIFFERENT 0,1 SPEAKER ATTENUATION = 0dB ∼ -79dB 10/16 TDA7442 - TDA7442D TREBLE SELECTION MSB LSB TREBLE D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 2 dB STEPS -14 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 0 -12 -10 0 0 1 1 1 1 1 0 -8 0 0 1 1 0 0 0 1 1 1 1 1 1 1 0 0 -6 -4 0 1 1 0 1 1 1 0 -2 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 2 4 1 1 1 0 0 1 0 1 1 1 1 1 1 1 0 0 6 8 1 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0 10 12 1 0 0 0 1 1 1 0 14 D5 D4 D3 D2 0 0 D1 0 1 D0 0 0 INPUT MULTIPLEXER IN2 IN3 X 1 0 0 IN4 X 1 1 0 IN1 INPUT SELECTION MSB D7 X X LSB D6 POWER ON RESET BASS TREBLE 2dB 0dB SURROUND & OUT CONTROL+ EFFECT CONTROL SPEAKER ATTENUATION L &R INPUT ATTENUATION OFF + FIX + MAX ATTENUATION MUTE MAX ATTENUATION INPUT IN1 11/16 TDA7442 - TDA7442D PIN: TREBLE-L, TREBLE-R PIN: VOUT REF VS VS 20µA 20µA 25K GND GND D95AU233A 10K GND D95AU309 PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4, PIN: CREF VS VS 20µA 20K 20µA 42K 50K GND VREF 20K D95AU336 D94AU200 PIN: SCL, SDA GND PIN: LP VS 20µA GND D94AU205 20µA GND D95AU308 12/16 TDA7442 - TDA7442D PIN: BASS-LI, BASS-RI PIN: L-OUT, R-OUT VS VS 20µA 20µA GND 45K : Bass BASS-LO GND BASS-RO D98AU949 D95AU230 PIN: BASS-LO, BASS-RO VS 20µA 45K GND BASS-LI,BASS-RI D98AU950 13/16 TDA7442 - TDA7442D mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S 14/16 OUTLINE AND MECHANICAL DATA 8 ° (max.) SO28 TDA7442 - TDA7442D mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 3.556 3.759 5.080 0.14 0.147 0.2 A1 0.508 A2 3.048 3.556 4.572 0.12 0.14 0.18 B 0.356 0.457 0.584 0.014 0.018 0.023 B1 0.762 1.016 1.397 0.03 0.04 0.055 C 0.203 0.254 0.356 0.008 0.01 0.014 D 27.43 27.94 28.45 1.08 1.1 1.12 E 9.906 10.41 11.05 0.39 0.409 0.433 E1 7.620 8.890 9.398 0.3 0.35 0.37 0.020 e 1.778 0.070 eA 10.16 0.400 eB L 12.70 2.540 3.048 3.810 SDIP32 (Shrink Plastic Dip 32L) 0.500 0.1 0.12 0.15 E E1 A2 A A1 L B B1 e eA eB D C 32 17 1 16 SDIP32M 0123183 15/16 TDA7442 - TDA7442D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 16/16