Revised November 1999 74ABT573 Octal D-Type Latch with 3-STATE Outputs General Description Features The ABT573 is an octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. ■ Inputs and outputs on opposite sides of package allow easy interface with microprocessors This device is functionally identical to the ABT373 but has broadside pinouts. ■ Functionally identical to ABT373 ■ Useful as input or output port for microprocessors ■ 3-STATE outputs for bus interfacing ■ Output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching, noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High impedance glitch-free bus loading during entire power up and power down ■ Nondestructive hot insertion capability Ordering Code: Order Number 74ABT573CSC 74ABT573CSJ Package Number M20B M20D Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT573CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT573CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT573CPC N20A 20-Lead Plastic Dual-In-Line (PDIP), JEDEC MS-01, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation DS011548 Descriptions D0–D7 Data Inputs LE Latch Enable Input (Active HIGH) OE 3-STATE Output Enable Input (Active LOW) O0–O7 3-STATE Latch Outputs www.fairchildsemi.com 74ABT573 Octal D-Type Latch with 3-STATE Outputs January 1993 74ABT573 Functional Description Function Table The ABT573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs OE LE D O L H H H L H L L L L X O0 H X X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial O0 = Value stored from previous clock cycle Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Voltage Applied to Any Output in the Disabled or −0.5V to +5.5V Power-Off State −0.5V to VCC in the HIGH State Current Applied to Output in LOW State (Max) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Twice the rated IOL (mA) −500 mA DC Latchup Source Current Over Voltage Latchup (I/O) Note 2: Either voltage limit or current limit is sufficient to protect inputs. 10V DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage VOL Output LOW Voltage 0.55 IIH Input HIGH Current 1 2.5 2.0 1 IBVI Input HIGH Current 7 Breakdown Test IIL −1 Input LOW Current −1 VID Input Leakage Test IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX VCC V 4.75 Conditions Recognized HIGH Signal Recognized LOW Signal Min V Min V Min µA Max µA Max µA Max V 0.0 IIN = −18 mA IOH = −3 mA IOH = −32 mA IOL = 64 mA VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 µA All Other Pins Grounded 10 µA 0 − 5.5V VOUT = 2.7V; OE = 2.0V 0 − 5.5V VOUT = 0.5V; OE = 2.0V −10 µA −275 mA Max VOUT = 0.0V Output HIGH Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max OE = VCC ICCT Additional ICC/Input 2.5 mA −100 All Others at VCC or GND Outputs Enabled Outputs 3-STATE 2.5 mA Outputs 3-STATE 2.5 mA VI = VCC − 2.1V Max Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 4) 0.12 MHz Max Outputs Open OE = GND, LE = V CC (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed but not tested. 3 www.fairchildsemi.com 74ABT573 Absolute Maximum Ratings(Note 1) 74ABT573 DC Electrical Characteristics Symbol Parameter Min Typ Max Units VCC 0.7 1.0 Conditions CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL V 5.0 TA = 25°C (Note 5) VOLV Quiet Output Minimum Dynamic VOL −1.5 −1.2 V 5.0 TA = 25°C (Note 5) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 6) VIHD Minimum HIGH Level Dynamic Input Voltage 2.2 1.8 V 5.0 TA = 25°C (Note 7) VILD Maximum LOW Level Dynamic Input Voltage V 5.0 TA = 25°C (Note 7) 1.0 0.7 Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP Package) Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 1.9 2.7 4.5 1.9 4.5 tPHL Dn to On 1.9 2.8 4.5 1.9 4.5 tPLH Propagation Delay 2.0 3.1 5.0 2.0 5.0 tPHL LE to On 2.0 3.0 5.0 2.0 5.0 tPZH Output Enable Time 1.5 3.1 5.3 1.5 5.3 1.5 3.1 5.3 1.5 5.3 tPZL tPHZ Output Disable Time 2.0 3.6 5.4 2.0 5.4 tPLZ Time 2.0 3.4 5.4 2.0 5.4 Units ns ns ns ns AC Operating Requirements (SOIC and SSOP Package) Symbol Parameter Min TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF Typ Max Min fTOGGLE Max Toggle Frequency 100 tS(H) Set Time, HIGH 1.5 1.5 tS(L) or LOW Dn to LE 1.5 1.5 tH(H) Hold Time, HIGH 1.0 1.0 or LOW Dn to LE 1.0 1.0 tW(H) Pulse Width, 3.0 3.0 www.fairchildsemi.com 4 Max MHz tH(L) LE HIGH Units ns ns ns 74ABT573 Extended AC Electrical Characteristics (SOIC Package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V CL = 50 pF CL = 250 pF CL = 250 pF 8 Outputs Switching (Note 9) 8 Outputs Switching Parameter (Note 8) (Note 10) Min Max Min Max Min Max tPLH Propagation Delay 1.5 5.2 2.0 6.8 2.0 9.0 tPHL Dn to On 1.5 5.2 2.0 6.8 2.0 9.0 tPLH Propagation Delay 1.5 5.5 2.0 7.5 2.0 9.5 tPHL LE to On 1.5 5.5 2.0 7.5 2.0 9.5 tPZH Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5 1.5 6.2 2.0 8.0 2.0 10.5 1.0 5.5 1.0 5.5 tPZL tPHZ Output Disable Time tPLZ Units (Note 11) ns ns ns (Note 11) ns Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Skew (Note 12) (SOIC Package) Symbol Parameter TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V CL = 50 pF CL = 250 pF 8 Outputs Switching 8 Outputs Switching (Note 12) (Note 13) Max Max Units tOSHL (Note 14) Pin to Pin Skew, HL Transitions 1.0 1.5 ns tOSLH (Note 14) Pin to Pin Skew, LH Transitions 1.0 1.5 ns tPS (Note 15) Duty Cycle, LH–HL Skew 1.4 3.5 ns tOST (Note 14) Pin to Pin Skew, LH/HL Transitions 1.5 3.9 ns tPV (Note 16) Device to Device Skew LH/HL Transitions 2.0 4.0 ns Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Conditions Symbol Parameter Typ Units (TA = 25°C) CIN Input Capacitance 5 pF VCC = 0V COUT (Note 17) Output Capacitance 9 pF VCC = 5.0V Note 17: COUT is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012. 5 www.fairchildsemi.com 74ABT573 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables. AC Loading *Includes jig and probe capacitance FIGURE 1. Test Load FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT573 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 7 www.fairchildsemi.com 74ABT573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 8 74ABT573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 9 www.fairchildsemi.com 74ABT573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 10 74ABT573 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line (PDIP), JEDEC MS-01, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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