Revised November 1999 74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs General Description Features The ABT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Current sinking capability is 64 mA on both the A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver. Transmit (active HIGH) enables data from A Ports to B Ports; Receive (active LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition. ■ Bidirectional non-inverting buffers ■ A and B output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching, noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High impedance glitch-free bus loading during entire power up and power down cycle ■ Non-destructive hot insertion capability ■ Disable time is less than enable time to avoid bus contention Ordering Code: Order Number 74ABT245CSC 74ABT245CSJ Package Number M20B M20D Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT245CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT245CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ABT245CPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation DS010945 Description OE Output Enable Input (Active LOW) T/R Transmit/Receive Input A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs www.fairchildsemi.com 74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs September 1991 74ABT245 Logic Symbol Truth Table Inputs OE L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH Z State H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram www.fairchildsemi.com 2 Output T/R Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Voltage Applied to Any Output in the Disabled or Power-off State −0.5V to 5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −500 mA DC Latchup Source Current Over Voltage Latchup (I/O) 10V Note 2: Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage Recognized LOW Signal Min IIN = −18 mA (OE, T/R) 2.5 V Min IOH = −3 mA (An, Bn) V Min IOH = −32 mA (An, Bn) V Min IOL = 64 mA (A n, Bn) µA Max 7 µA Max VIN = 7.0V (OE, T/R) µA Max VIN = 5.5V (An, Bn) µA Max V 0.0 Output LOW Voltage 0.55 IIH Input HIGH Current 1 1 IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) 100 IIL Input LOW Current −1 −1 Input Leakage Test Conditions Recognized HIGH Signal 2.0 VOL VID VCC V 4.75 VIN = 2.7V (OE, T/R) VIN = VCC (OE, T/R) VIN = 0.5V (OE, T/R) VIN = 0.0V (OE, T/R) IID = 1.9 µA (OE, T/R) All Other Pins Grounded IIH + IOZH Output Leakage Current 10 µA 0 − 5.5V VOUT = 2.7V (An, Bn); OE = 2.0V IIL + I OZL Output Leakage Current −10 µA 0 − 5.5V VOUT = 0.5V (An, Bn); OE = 2.0V IOS Output Short-Circuit Current −275 mA Max VOUT = 0.0V (An, Bn) ICEX Output HIGH Leakage Current 50 µA Max VOUT = V CC (An, Bn) IZZ Bus Drainage Test 100 µA 0.0 −100 VOUT = 5.5V (An, Bn); All Others GND ICCH Power Supply Current 50 µA Max ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max OE = V CC, T/R = GND or VCC; ICCT Additional Outputs Enabled 2.5 mA I CC/Input Outputs 3-STATE 2.5 mA Outputs 3-STATE 50 µA No Load 0.1 mA/ All Outputs HIGH All Other GND or VCC VI = V CC − 2.1V Max OE, T/R V I = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND. ICCD Dynamic ICC MHz Max Outputs Open OE = GND, T/R = GND or VCC One Bit Toggling, 50% Duty Cycle 3 www.fairchildsemi.com 74ABT245 Absolute Maximum Ratings(Note 1) 74ABT245 DC Electrical Characteristics (SOIC package) Symbol Parameter Min Typ Max Units VCC 0.7 1.0 Conditions CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL V 5.0 TA = 25°C (Note 3) VOLV Quiet Output Minimum Dynamic VOL −1.3 −1.0 V 5.0 TA = 25°C (Note 3) VOHV Minimum HIGH Level Dynamic Output Voltage 2.7 3.1 V 5.0 TA = 25°C (Note 5) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.7 V 5.0 TA = 25°C (Note 4) VILD Maximum LOW Level Dynamic Input Voltage V 5.0 TA = 25°C (Note 4) 0.9 0.6 Note 3: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 4: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ILD), 0V to threshold (VIHD ). Guaranteed, but not tested. Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP package) Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = −40°C to +85°C VCC = +5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min tPLH Propagation Delay 1.0 2.1 3.6 1.0 4.8 1.0 3.6 tPHL Data to Outputs 1.0 2.4 3.6 1.0 4.8 1.0 3.6 Units Max tPZH Output Enable 1.5 3.2 6.0 1.0 6.7 1.5 6.0 tPZL Time 1.5 3.7 6.0 2.0 7.5 1.5 6.0 tPHZ Output Disable 1.0 3.6 6.1 1.7 7.4 1.0 6.1 tPLZ Time 1.0 3.3 5.6 1.7 6.5 1.0 5.6 ns ns ns Extended AC Electrical Characteristics (SOIC package) Symbol −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 8 Outputs Switching 1 Output Switching 8 Outputs Switching Parameter (Note 6) Min Typ (Note 7) (Note 8) Max Min Max Min Max fTOGGLE Max Toggle Frequency tPLH Propagation Delay 1.5 5.0 1.5 6.0 2.5 8.5 tPHL Data to Outputs 1.5 5.0 1.5 6.0 2.5 8.5 tPZH Output Enable Time 1.5 6.5 2.5 7.5 2.5 9.5 1.5 6.5 2.5 7.5 2.5 11.0 1.0 6.5 1.0 5.6 tPZL tPHZ Output Disable Time tPLZ Units 100 MHz (Note 9) (Note 9) ns ns ns Note 6: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 7: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 8: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 9: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and have been excluded from the datasheet. www.fairchildsemi.com 4 74ABT245 Skew (SOIC package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 8 Outputs Switching 8 Outputs Switching (Note 12) (Note 13) Max Max 1.3 2.3 ns 1.0 1.8 ns 2.0 3.5 ns 2.0 3.5 ns 2.0 3.5 ns Parameter tOSHL Pin to Pin Skew (Note 10) HL Transitions tOSLH Pin to Pin Skew (Note 10) LH Transitions tPS Duty Cycle (Note 14) LH–HL Skew tOST Pin to Pin Skew (Note 10) LH/HL Transitions tPV Device to Device Skew (Note 11) LH/HL Transitions Units Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (t OSLH), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW (tOST). The specification is guaranteed but not tested. Note 11: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 13: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Capacitance Conditions Symbol Parameter Typ Units TA = 25°C CIN Input Capacitance 5.0 pF V CC = 0V (OE, T/R) CI/O (Note 15) I/O Capacitance 11.0 pF V CC = 5.0V (An, Bn) Note 15: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74ABT245 AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT245 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 7 www.fairchildsemi.com 74ABT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 8 74ABT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 9 www.fairchildsemi.com 74ABT245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 10 74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com