Revised March 2005
74ABT245
Octal Bi-Directional Transceiver with 3-STATE Outputs
General Description
Features
The ABT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented
applications. Current sinking capability is 64 mA on both
the A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional
transceiver. Transmit (active HIGH) enables data from A
Ports to B Ports; Receive (active LOW) enables data from
B Ports to A Ports. The Output Enable input, when HIGH,
disables both A and B ports by placing them in a HIGH Z
condition.
■ Bidirectional non-inverting buffers
■ A and B output sink capability of 64 mA, source
capability of 32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and 250 pF
loads
■ Guaranteed simultaneous switching, noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance glitch-free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
■ Disable time is less than enable time to avoid bus
contention
Ordering Code:
Order Number
Package
Package Description
Number
74ABT245CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ABT245CSJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT245CMSA
MSA20
74ABT245CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT245CMTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ABT245CPC
N20A
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS010945
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74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs
September 1991
74ABT245
Connection Diagram
Logic Symbol
Pin Descriptions
Pin Names
Truth Table
Description
Inputs
OE
Output Enable Input (Active LOW)
T/R
Transmit/Receive Input
A0–A7
Side A Inputs or 3-STATE Outputs
B0–B7
Side B Inputs or 3-STATE Outputs
OE
T/R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
HIGH Z State
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Logic Diagram
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2
Output
Recommended Operating
Conditions
65qC to 150qC
55qC to 125qC
55qC to 150qC
0.5V to 7.0V
0.5V to 7.0V
30 mA to 5.0 mA
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
40qC to 85qC
4.5V to 5.5V
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate ('V/'t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Voltage Applied to Any Output
in the Disabled or
0.5V to 5.5V
0.5V to VCC
Power-off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
500 mA
DC Latchup Source Current
Over Voltage Latchup (I/O)
10V
Note 3: Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
Conditions
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
1.2
V
Min
IIN
VOH
Output HIGH Voltage
2.5
V
Min
IOH
2.0
V
Min
IOH
32 mA (An, Bn)
V
Min
IOL
64 mA (A n, Bn)
PA
Max
VIN
2.7V (OE, T/R)
VIN
VCC (OE, T/R)
7
PA
Max
VIN
7.0V (OE, T/R)
PA
Max
VIN
5.5V (An, Bn)
VIN
0.5V (OE, T/R)
VOL
Output LOW Voltage
IIH
Input HIGH Current
2.0
V
0.55
1
1
IBVI
Input HIGH Current Breakdown Test
IBVIT
Input HIGH Current Breakdown Test (I/O)
100
IIL
Input LOW Current
1
1
4.75
Recognized HIGH Signal
Recognized LOW Signal
PA
Max
V
0.0
18 mA (OE, T/R)
3 mA (An, Bn)
VIN
0.0V (OE, T/R)
IID
1.9 PA (OE, T/R)
VID
Input Leakage Test
IIH IOZH
Output Leakage Current
10
PA
0 5.5V VOUT
2.7V (An, Bn); OE
2.0V
IIL I OZL
Output Leakage Current
10
PA
0 5.5V VOUT
0.5V (An, Bn); OE
2.0V
IOS
Output Short-Circuit Current
275
mA
Max
VOUT
0.0V (An, Bn)
ICEX
Output HIGH Leakage Current
50
PA
Max
VOUT
V CC (An, Bn)
IZZ
Bus Drainage Test
100
PA
0.0
VOUT
5.5V (An, Bn);
All Other Pins Grounded
100
All Others GND
ICCH
Power Supply Current
50
PA
Max
ICCL
Power Supply Current
30
mA
Max
All Outputs LOW
ICCZ
Power Supply Current
50
PA
Max
OE
All Outputs HIGH
V CC, T/R
GND or VCC;
All Other GND or VCC
ICCT
Additional
Outputs Enabled
2.5
mA
I CC/Input
Outputs 3-STATE
2.5
mA
Outputs 3-STATE
50
PA
VI
Max
V CC 2.1V
OE, T/R V I
VCC 2.1V
Data Input VI
V CC 2.1V
All Others at VCC or GND.
ICCD
Dynamic ICC
No Load
0.1
mA/
MHz
3
Max
Outputs Open
OE
GND, T/R
GND or VCC
One Bit Toggling, 50% Duty Cycle
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74ABT245
Absolute Maximum Ratings(Note 2)
74ABT245
DC Electrical Characteristics
(SOIC package)
Symbol
Parameter
Min
Conditions
Typ
Max
Units
VCC
0.7
1.0
V
5.0
TA
25qC (Note 4)
CL
50 pF, RL
VOLP
Quiet Output Maximum Dynamic VOL
VOLV
Quiet Output Minimum Dynamic VOL
1.3
1.0
V
5.0
TA
25qC (Note 4)
VOHV
Minimum HIGH Level Dynamic Output Voltage
2.7
3.1
V
5.0
TA
25qC (Note 6)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.7
V
5.0
TA
25qC (Note 5)
VILD
Maximum LOW Level Dynamic Input Voltage
V
5.0
TA
25qC (Note 5)
0.9
0.6
500:
Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ).
Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package)
25qC
TA
Symbol
Parameter
CL
TA
5V
VCC
55qC to 125qC
VCC
50 pF
CL
40qC to 85qC
TA
4.5V–5.5V
VCC
50 pF
4.5V–5.5V
CL
50 pF
Min
Typ
Max
Min
Max
Min
tPLH
Propagation Delay
1.0
2.1
3.6
1.0
4.8
1.0
3.6
tPHL
Data to Outputs
1.0
2.4
3.6
1.0
4.8
1.0
3.6
Units
Max
tPZH
Output Enable
1.5
3.2
6.0
1.0
6.7
1.5
6.0
tPZL
Time
1.5
3.7
6.0
2.0
7.5
1.5
6.0
tPHZ
Output Disable
1.0
3.6
6.1
1.7
7.4
1.0
6.1
tPLZ
Time
1.0
3.3
5.6
1.7
6.5
1.0
5.6
ns
ns
ns
Extended AC Electrical Characteristics
(SOIC package)
40qC to 85qC
VCC
Symbol
CL
Parameter
TA
4.5V–5.5V
50 pF
CL
8 Outputs Switching
Typ
4.5V–5.5V
TA
40qC to 85qC
VCC
250 pF
1 Output Switching
(Note 7)
Min
40qC to 85qC
VCC
CL
4.5V–5.5V
250 pF
(Note 8)
(Note 9)
Max
Min
Max
Min
Max
fTOGGLE
Max Toggle Frequency
tPLH
Propagation Delay
1.5
5.0
1.5
6.0
2.5
8.5
tPHL
Data to Outputs
1.5
5.0
1.5
6.0
2.5
8.5
tPZH
Output Enable Time
1.5
6.5
2.5
7.5
2.5
9.5
1.5
6.5
2.5
7.5
2.5
11.0
1.0
6.5
1.0
5.6
tPZL
tPHZ
Output Disable Time
tPLZ
Units
8 Outputs Switching
100
MHz
(Note 10)
(Note 10)
ns
ns
ns
Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only.
Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10: The 3-STATE delays are dominated by the RC network (500:, 250 pF) on the output and have been excluded from the datasheet.
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4
74ABT245
Skew
(SOIC package)
40qC to 85qC
TA
VCC
Symbol
CL
Parameter
tOSHL
Pin to Pin Skew
(Note 11)
HL Transitions
tOSLH
Pin to Pin Skew
(Note 11)
LH Transitions
tPS
Duty Cycle
(Note 15)
LH–HL Skew
tOST
Pin to Pin Skew
(Note 11)
LH/HL Transitions
tPV
Device to Device Skew
(Note 12)
LH/HL Transitions
TA
4.5V–5.5V
40qC to 85qC
VCC
50 pF
CL
4.5V–5.5V
250 pF
Units
8 Outputs Switching
8 Outputs Switching
(Note 13)
(Note 14)
Max
Max
1.3
2.3
ns
1.0
1.8
ns
2.0
3.5
ns
2.0
3.5
ns
2.0
3.5
ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or
HIGH-to-LOW (tOST). The specification is guaranteed but not tested.
Note 12: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 14: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Conditions
Symbol
Parameter
Typ
Units
TA
CIN
Input Capacitance
5.0
pF
V CC
0V (OE, T/R)
CI/O (Note 16)
I/O Capacitance
11.0
pF
V CC
5.0V (An, Bn)
Note 16: CI/O is measured at frequency f
25qC
1 MHz, per MIL-STD-883, Method 3012.
5
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74ABT245
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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74ABT245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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74ABT245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
74ABT245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
9
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74ABT245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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10
74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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