Revised January 1999 74ABT543 Octal Registered Transceiver with 3-STATE Outputs ■ Separate controls for data flow in each direction General Description The ABT543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed latchup protection Features ■ Back-to-back registers for storage ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Bidirectional data path ■ Nondestructive hot insertion capability ■ A and B outputs have current sourcing capability of 32 mA and current sinking capability of 64 mA Ordering Code: Order Number Package Number 74ABT543CSC M24B Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ABT543CMSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT543CMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Assignment for SOIC, SSOP and TSSOP © 1999 Fairchild Semiconductor Corporation Pin Names DS011508.prf Description OEAB, OEBA Output Enable Inputs LEAB, LEBA Latch Enable Inputs CEAB, CEBA Chip Enable Inputs A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs www.fairchildsemi.com 74ABT543 Octal Registered Transceiver with 3-STATE Outputs November 1992 74ABT543 Functional Description Data I/O Control Table The ABT543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be low in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Inputs Output Buffers Latched HIGH Z — H X X X H X Latched L L X Transparent — X X H — HIGH Z L X L — Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram www.fairchildsemi.com Latch Status CEAB LEAB OEAB 2 Over Voltage Latchup (I/O) −65°C to +150°C Storage Temperature Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C −0.5V to +7.0V Free Air Ambient Temperature Input Voltage (Note 2) −0.5V to +7.0V Supply Voltage Input Current (Note 2) −30 mA to +5.0 mA −0.5V to +5.5V −0.5V to VCC in the HIGH State +4.5V to +5.5V Data Input 50 mV/ns Enable Input 20 mV/ns Clock Input 100 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) Voltage Applied to Any Output in the Disable or Power-Off State 10V Recommended Operating Conditions VCC Pin Potential to Ground Pin −500 mA DC Latchup Source Current twice the rated IOL (mA) Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage V IIN = −18 mA (Non I/O Pins) VOH Output HIGH Voltage VOL Output LOW Voltage VID Input Leakage Test IIH Input HIGH Current −1.2 2.5 IOH = −3 mA, (An, Bn) 2.0 IOH = −32 mA, (An, Bn) 0.55 4.75 V Min IOL = 64 mA, (An, Bn) V 0.0 IID = 1.9 µA, (Non-I/O Pins) µA Max All Other Pins Grounded 1 IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current VIN = 2.7V (Non-I/O Pins) (Note 3) VIN = VCC (Non-I/O Pins) 1 7 µA Max VIN = 7.0V (Non-I/O Pins) 100 µA Max VIN = 5.5V (An, Bn) −1 µA Max VIN = 0.5V (Non-I/O Pins) (Note 3) Breakdown Test (I/O) IIL Input LOW Current −1 VIN = 0.0V (Non-I/O Pins) IIH + IOZH Output Leakage Current 10 µA 0V–5.5V VOUT = 2.7V (An, Bn); IIL + IOZL Output Leakage Current −10 µA 0V–5.5V VOUT = 0.5V (An, Bn); −275 mA OEAB or CEAB = 2V OEAB or CEAB = 2V −100 Max VOUT = 0V (An, Bn) µA Max VOUT = VCC (An, Bn) µA 0.0V VOUT = 5.5V (An, Bn); 50 µA Max All Outputs HIGH Power Supply Current 30 mA Max All Outputs LOW Power Supply Current 50 µA Max Outputs 3-STATE Additional ICC/Input 2.5 mA Max IOS Output Short-Circuit Current ICEX Output HIGH Leakage Current 50 IZZ Bus Drainage Test 100 ICCLH Power Supply Current ICCL ICCZ ICCT All Others GND All Others at VCC or GND VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load (Note 5) Outputs Open, CEAB 0.18 mA/MHz Max and OEAB = GND, CEBA = VCC, One Bit Toggling, 50% Duty Cycle, (Note 4) Note 3: Guaranteed but not tested. Note 4: For 8-bit toggling. ICCD < 1.4 mA/MHz. Note 5: Guaranteed, but not tested. 3 www.fairchildsemi.com 74ABT543 Absolute Maximum Ratings(Note 1) 74ABT543 DC Electrical Characteristics (SOIC Package) Conditions Symbol Parameter Min Typ Max Units VCC CL = 50 pF, 0.7 1.0 V 5.0 TA = 25°C (Note 6) RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL −1.2 −0.8 V 5.0 TA = 25°C (Note 6) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 7) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.7 V 5.0 TA = 25°C (Note 8) VILD Maximum LOW Level Dynamic Input Voltage V 5.0 TA = 25°C (Note 8) 0.7 0.9 Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 7: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 8: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP Packages) Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 1.5 3.1 4.8 1.5 4.8 tPHL An to Bn or Bn to An 1.5 4.8 1.5 4.8 tPLH Propagation Delay tPHL tPZH tPZL LEAB to Bn, LEBA to An 1.6 OEBA or OEAB to An or Bn 1.6 3.4 5.3 1.6 5.3 5.3 1.6 5.3 Units ns ns Enable Time LEAB to Bn, LEBA to An 1.5 OEBA or OEAB to An or Bn 1.5 tPHZ Disable Time 2.0 tPLZ CEBA or CEAB to An or Bn 2.0 3.6 4.0 5.8 1.5 5.8 5.8 1.5 5.8 6.5 2.0 6.5 6.5 2.0 6.5 ns ns AC Operating Requirements (SOIC and SSOP Packages) Symbol Parameter TA = +25°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Max Min tS(H) Setup Time, HIGH or LOW 1.5 1.5 tS(L) An or Bn to LEBA or LEAB 1.5 1.5 tH(H) Hold Time, HIGH or LOW 1.0 1.0 tH(L) An or Bn to LEBA or LEAB 1.0 1.0 tS(H) Setup Time, HIGH or LOW 1.5 1.5 tS(L) An or Bn to CEAB or CEBA 1.5 1.5 tH(H) Hold Time, HIGH or LOW 1.3 1.3 tH(L) An or Bn to CEAB or CEBA 1.3 1.3 tW(L) Pulse Width, LOW 3.0 3.0 www.fairchildsemi.com 4 Units Max ns ns ns ns ns 74ABT543 Extended AC Electrical Characteristics (SOIC Package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 8 Outputs Switching 1 Output Switching 8 Outputs Switching Parameter (Note 9) Min Typ (Note 10) Units (Note 11) Max Min Max Min Max fTOGGLE Max Toggle Frequency tPLH Propagation Delay 1.5 6.2 2.0 7.5 2.5 10.0 tPHL An to Bn or Bn to An 1.5 6.2 2.0 7.5 2.5 10.0 tPLH Propagation Delay 1.5 6.5 2.0 8.0 2.5 10.5 tPHL LEAB to Bn, LEBA to An 1.5 6.5 2.0 8.0 2.5 10.5 tPZH Output Enable Time tPZL OEBA or OEAB to An or Bn 1.5 7.5 2.0 8.5 2.5 11.0 CEBA or CEAB to An or Bn 1.5 7.5 2.0 8.5 2.5 11.0 OEBA or OEAB to An or Bn 1.5 8.5 CEBA or CEAB to An or Bn 1.5 8.5 tPHZ 100 MHz ns ns ns Output Disable Time tPLZ (Note 12) (Note 12) ns Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 12: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet Skew (SOIC Package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 8 Outputs Switching 8 Outputs Switching (Note 13) (Note 14) Max Max 1.0 2.0 ns 1.3 2.0 ns 2.0 4.0 ns 2.0 4.0 ns 2.5 4.5 ns Parameter tOSHL Pin to Pin Skew (Note 15) HL Transitions tOSLH Pin to Pin Skew (Note 15) LH Transitions tPS Duty Cycle (Note 16) LH–HL Skew tOST Pin to Pin Skew (Note 15) LH/HL Transitions tPV Device to Device Skew (Note 17) LH/HL Transitions Units Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 14: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 15: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 17: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. 5 www.fairchildsemi.com 74ABT543 Capacitance Symbol Parameter Conditions: TA = 25°C Typ Units CIN Input Capacitance 5.0 pF VCC = 0V (non I/O pins) CI/O (Note 18) Output Capacitance 11.0 pF VCC = 5.0V (An, Bn) Note 18: CI/O is measured at frequency, f = 1 MHz, PER MLT-STD-883B, METHOD 3012. AC Loading FIGURE 2. VM = 1.5V Input Pulse Requirements *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude Rep. Rate 3V 1 MHz tW tr tf 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT543 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24 7 www.fairchildsemi.com 74ABT543 Octal Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.