FAIRCHILD 74ACTQ533MTC

Revised November 1999
74ACTQ533
Quiet Series Octal Transparent Latch
with 3-STATE Outputs
General Description
Features
The ACTQ533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high impedance state.
■ ICC and IOZ reduced by 50%
The ACTQ533 utilizes Fairchild Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch up immunity
■ Eight latches in a single package
■ Outputs source/sink 24 mA
■ Inverted version of the ACTQ373
■ 4 kV minimum ESD immunity
Ordering Code:
Order Number
74ACTQ533SC
74ACTQ533MTC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ533PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
Description
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O0–O7
3-STATE Latch Outputs
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010630
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74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs
January 1990
74ACTQ533
Truth Table
Inputs
Outputs
LE
OE
Dn
X
H
X
Z
H
L
L
H
H
L
H
L
L
L
X
O0
On
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Functional Description
The ACTQ533 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs at setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Recommended Operating
Conditions
− 0.5V to + 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = − 0.5V
− 20 mA
VI = VCC + 0.5V
+ 20 mA
DC Input Voltage (VI)
Supply Voltage (VCC)
−0.5V to VCC + 0.5V
0V to VCC
Output Voltage (VO)
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
DC Output Diode Current (IOK)
VO = − 0.5V
− 20 mA
VO = VCC + 0.5V
DC Output Voltage (VO)
4.5V to 5.5V
Input Voltage (VI)
125 mV/ns
VIN from 0.8V to 2.0V
+ 20 mA
VCC @ 4.5V, 5.5V
− 0.5V to VCC + 0.5V
DC Output Source
± 50 mA
or Sink Current (IO)
DC VCC or Ground Current
± 50 mA
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
− 65°C to + 150°C
DC Latchup Source
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
± 300 mA
or Sink Current
Junction Temperature (TJ)
PDIP
140°C
DC Electrical Characteristics
Symbol
Parameter
VCC
TA = +25°C
(V)
Typ
TA = −40°C to +85°C
Guaranteed Limits
VIH
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
VIL
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
VOH
Units
V
V
V
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
VIN = VIL or VIH
VOL
4.5
3.86
3.76
5.5
4.86
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
±0.1
±1.0
V
IOH = −24 mA
IOH = −24 mA (Note 2)
V
IOUT = 50 µA
VIN = VIL or VIH
IIN
Maximum Input
Leakage Current
IOZ
Maximum 3-STATE
Leakage Current
ICCT
Maximum
±0.25
5.5
±2.5
V
IOL = 24 mA
IOL = 24 mA (Note 2)
µA
µA
VI = VCC, GND
VI = VIL, VIH
VO = VCC, GND
1.5
mA
VI = VCC − 2.1V
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 3)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent
40.0
µA
ICC/Input
Supply Current
VOLP
Quiet Output
Maximum Dynamic VOL
VOLV
Quiet Output
Minimum Dynamic VOL
VIHD
Minimum HIGH Level
Dynamic Input Voltage
5.5
0.6
5.5
4.0
5.0
1.1
1.5
V
5.0
−0.6
−1.2
V
5.0
1.9
2.2
V
3
VIN = VCC
or GND
Figures 1, 2
(Note 4)(Note 5)
Figures 1, 2
(Note 4)(Note 5)
(Note 4)(Note 6)
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74ACTQ533
Absolute Maximum Ratings(Note 1)
74ACTQ533
DC Electrical Characteristics
Symbol
TA = +25°C
VCC
Parameter
(V)
Typ
5.0
1.2
Maximum LOW Level
VILD
(Continued)
Dynamic Input Voltage
TA = −40°C to +85°C
Units
Conditions
Guaranteed Limits
0.8
V
(Note 4)(Note 6)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD),
f = 1 MHz.
AC Electrical Characteristics
Symbol
Parameter
VCC
TA = + 25°C
(V)
CL = 50 pF
TA = − 40°C to + 85°C
CL = 50 pF
Units
(Note 7)
Min
Typ
Max
Min
Max
5.0
2.0
6.0
8.0
2.0
8.5
ns
5.0
2.5
7.0
9.0
2.5
9.5
ns
tPHL
Propagation Delay
tPLH
Dn to On
tPHL
Propagation Delay
tPLH
LE to On
tPZL, tPZH
Output Enable Time
5.0
2.0
7.0
9.0
2.0
9.5
ns
tPHZ, tPLZ
Output Disable Time
5.0
1.0
8.0
10.0
1.0
10.5
ns
tOSHL
Output to Output Skew
tOSLH
Dn to On(Note 8)
0.5
1.0
1.0
ns
5.0
Note 7: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
Symbol
tS
Parameter
Setup Time, HIGH or LOW
Dn to LE
tH
Hold Time, HIGH or LOW
Dn to LE
tW
LE Pulse Width, HIGH
V CC
TA = + 25°C
(V)
CL = 50 pF
TA = − 40°C to + 85°C
CL = 50 pF
Typ
Guaranteed Minimum
5.0
0
3.0
3.0
ns
5.0
0
1.5
1.5
ns
5.0
2.0
4.0
4.0
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
VCC = OPEN
CPD
Power Dissipation Capacitance
40
pF
VCC = 5.0V
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Units
(Note 9)
4
Conditions
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/V OHV:
Tektronics Model 7854 Oscillo-
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
• Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
scope
Procedure:
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
VILD and VIHD:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the
correct voltage.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with a digital volt meter.
• Next decrease the input HIGH voltage level on the VIH
until the output begins to oscillate or steps out a min of 2
ns. Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input HIGH voltage level at
which oscillation occurs is defined as VIHD.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 10: VOHV and VOLP are measured with respect to ground reference.
Note 11: Input pulses have the following characteristics:
f = 1 MHz, t r = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 2. Simultaneous Switching Test Circuit
5
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74ACTQ533
FACT Noise Characteristics
74ACTQ533
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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74ACTQ533
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Package Number MTC20
7
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74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
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user.
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