FAIRCHILD 74LCX11M_08

74LCX11
Low Voltage Triple 3-Input AND Gate with 5V
Tolerant Inputs
Features
General Description
■ 5V tolerant inputs
The LCX11 is a triple 3-input AND gate with buffered
outputs. LCX devices are designed for low voltage (2.5V
or 3.3V) operation with the added capability of interfacing to a 5V signal environment.
■ 2.3V–3.6V VCC specifications provided
■ 6.0ns tPD max. (VCC = 3.3V), 10µA ICC max.
■ Power down high impedance inputs and outputs
■ ±24mA output drive (VCC = 3.0V)
■ Implements proprietary noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
The 74LCX11 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
■ ESD performance:
– Human body model > 2000V
– Machine model > 200V
■ Leadless DQFN package
Ordering Information
Order Number
74LCX11M
74LCX11SJ
Package
Number
M14A
M14D
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX11BQX(1)
MLP14A
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX11MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
February 2008
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
Connection Diagrams
Logic Symbol
Pin Assignments for SOIC, SOP, and TSSOP
IEEE/IEC
(Top View)
Pad Assignments for DQFN
Logic Diagram
(Top Through View)
Pin Description
Pin Names
Description
An, Bn, Cn
Inputs
On
Outputs
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
VI
VO
Parameter
Rating
Supply Voltage
–0.5V to +7.0V
DC Input Voltage
–0.5V to +7.0V
DC Output Voltage, Output in HIGH or LOW
IIK
DC Input Diode Current, VI < GND
IOK
DC Output Diode Current
State(2)
–0.5V to VCC + 0.5V
–50mA
VO < GND
–50mA
VO > VCC
+50mA
IO
DC Output Source/Sink Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature
±50mA
±100mA
±100mA
–65°C to +150°C
Note:
2. IO Absolute Maximum Rating must be observed.
Recommended Operating Conditions(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
Parameter
Min.
Max.
Units
Operating
2.0
3.6
V
Data Retention
1.5
3.6
Supply Voltage
VI
Input Voltage
0
5.5
V
VO
Output Voltage, HIGH or LOW State
0
VCC
V
VCC = 3.0V–3.6V
±24
mA
VCC = 2.7V–3.0V
±12
VCC = 2.3V–2.7V
±8
IOH / IOL
TA
∆t / ∆V
Output Current
Free-Air Operating Temperature
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
–40
85
°C
0
10
ns / V
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
3
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
Absolute Maximum Ratings
TA = –40°C to +85°C
Symbol
VIH
VIL
VOH
VOL
II
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Leakage Current
IOFF
Power-Off Leakage Current
ICC
Quiescent Supply Current
∆ICC
Increase in ICC per Input
VCC (V)
Conditions
Min.
2.3–2.7
1.7
2.7–3.6
2.0
Max.
V
2.3–2.7
0.7
2.7–3.6
0.8
IOH = –100µA
2.3–3.6
V
VCC – 0.2
2.3
IOH = –8mA
1.8
2.7
IOH = –12mA
2.2
3.0
IOH = –18mA
2.4
IOH = –24mA
2.2
V
IOL = 100µA
0.2
2.3
IOL = 8mA
0.6
2.7
IOL = 12mA
0.4
3.0
IOL = 16mA
0.4
IOL = 24mA
0.55
0 ≤ VI ≤ 5.5V
2.3–3.6
2.3–3.6
0
2.3–3.6
2.3–3.6
Units
V
±5.0
µA
VI or VO = 5.5V
10
µA
VI = VCC or GND
10
µA
3.6V ≤ VI ≤ 5.5V
±10
VIH = VCC – 0.6V
500
µA
AC Electrical Characteristics
TA = –40°C to +85°C, RL = 500Ω
VCC = 3.3V ± 0.3V,
CL = 50pF
Symbol
tPHL, tPLH
Parameter
Propagation Delay
tOSHL, tOSLH Output to Output
Skew(4)
VCC = 2.7V,
CL = 50pF
VCC = 2.5V ± 0.2V,
CL = 30pF
Min.
Max.
Min.
Max.
Min.
Max.
Units
1.5
6.0
1.5
7.0
1.5
7.2
ns
1.0
ns
Note:
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
4
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
DC Electrical Characteristics
TA = 25°C
Symbol
Parameter
VCC (V)
VOLP
Quiet Output Dynamic Peak VOL
3.3
VOLV
Quiet Output Dynamic Valley VOL
Conditions
Typical
Unit
CL = 50pF, VIH = 3.3V, VIL = 0V
0.8
V
2.5
CL = 30pF, VIH = 2.5V, VIL = 0V
0.6
3.3
CL = 50pF, VIH = 3.3V, VIL = 0V
–0.8
2.5
CL = 30pF, VIH = 2.5V, VIL = 0V
–0.6
V
Capacitance
Symbol
Parameter
Conditions
Typical
Units
Input Capacitance
VCC = Open, VI = 0V or VCC
7
pF
COUT
Output Capacitance
VCC = 3.3V, VI = 0V or VCC
8
pF
CPD
Power Dissipation Capacitance
VCC = 3.3V, VI = 0V or VCC, f = 10MHz
25
pF
CIN
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
5
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
Dynamic Switching Characteristics
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH, tPHZ
GND
Figure 1. AC Test Circuit (CL includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
VCC
Symbol
3.3V ± 0.3V
2.7V
2.5V ± 0.2V
Vmi
1.5V
1.5V
VCC / 2
Vmo
1.5V
1.5V
VCC / 2
Vx
VOL + 0.3V
VOL + 0.3V
VOL + 0.15V
Vy
VOH – 0.3V
VOH – 0.3V
VOH – 0.15V
Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
6
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
AC Loading and Waveforms (Generic for LCX Family)
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
Schematic Diagram (Generic for LCX Family)
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
7
Tape Format for DQFN
Package Designator
Tape Section
Number of Cavities
Cavity Status
Cover Tape Status
BQX
Leader (Start End)
125 (Typ.)
Empty
Sealed
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (Typ.)
Empty
Sealed
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
12mm
13.0 (330.0)
0.059 (1.50)
0.512 (13.00)
0.795 (20.20)
2.165 (55.00)
0.488 (12.4)
0.724 (18.4)
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
8
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
Tape and Reel Specification
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
Physical Dimensions
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
PIN ONE
INDICATOR
1
1.70
7
0.51
0.35
1.27
0.25
1.27
LAND PATTERN RECOMMENDATION
M
C B A
(0.33)
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.10
C
0.25
0.19
0.10 C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50 X 45°
0.25
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
9
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
Physical Dimensions (Continued)
Figure 4. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
10
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
Physical Dimensions (Continued)
Figure 5. 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
11
0.65
0.43 TYP
1.65
6.10
0.45
12.00° TOP
& BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
1.00
R0.09min
Figure 6. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
12
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
Physical Dimensions (Continued)
ACEx®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
PDP-SPM™
Power220®
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Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
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QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
FPS™
FRFET®
Global Power ResourceSM
Green FPS™
Green FPS™e-Series™
GTO™
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IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
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FACT®
FAST®
FastvCore™
FlashWriter® *
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SyncFET™
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UniFET™
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* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
©1995 Fairchild Semiconductor Corporation
74LCX11 Rev. 1.6.0
www.fairchildsemi.com
13
74LCX11 — Low Voltage Triple 3-Input AND Gate with 5V Tolerant Inputs
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