74LCX574 OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : fMAX = 150 MHz (MIN.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LCX574 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 8 bit D-Type flip-flops are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74LCX574M 74LCX574MTR 74LCX574TTR outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The Output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS September 2001 1/10 74LCX574 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 D0 to D7 10 20 Q0 to Q7 CK GND VCC TRUTH TABLE 3-State Outputs Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10 INPUT NAME AND FUNCTION 3-State Output Enable Input (Active LOW) Data Inputs OUTPUT OE CK D H X Q X Z L X NO CHANGE L L L L H H X : Don’t Care Z : High Impedance 74LCX574 ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (OFF State) VO DC Output Voltage (High or Low State) (note 1) -0.5 to +7.0 V -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 50 mA IOK DC Output Diode Current (note 2) - 50 mA IO DC Output Current ± 50 mA ICC DC Supply Current per Supply Pin ± 100 mA IGND DC Ground Current per Supply Pin ± 100 mA Tstg Storage Temperature -65 to +150 °C TL Lead Temperature (10 sec) 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND RECOMMENDED OPERATING CONDITIONS Symbol V CC Parameter Supply Voltage (note 1) Value Unit 2.0 to 3.6 V 0 to 5.5 V VI Input Voltage VO Output Voltage (OFF State) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V ± 24 mA ± 12 mA IOH, IOL IOH, IOL Top dt/dv High or Low Level Output Current (V CC = 3.0 to 3.6V) High or Low Level Output Current (V CC = 2.7V) Operating Temperature Input Rise and Fall Time (note 2) -55 to 125 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V 3/10 74LCX574 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Ioff IOZ ICC ∆ICC Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input Min. Max. 2.0 -55 to 125 °C Min. Unit Max. 2.0 V 2.7 to 3.6 0.8 0.8 2.7 to 3.6 I O=-100 µA VCC-0.2 VCC-0.2 2.7 IO=-12 mA 2.2 2.2 IO=-18 mA 2.4 2.4 IO=-24 mA 2.2 V V 2.2 2.7 to 3.6 IO=100 µA 0.2 0.2 2.7 IO=12 mA 0.4 0.4 IO=16 mA 0.4 0.4 IO=24 mA 0.55 0.55 2.7 to 3.6 VI = 0 to 5.5V ±5 ±5 µA 0 V I or VO = 5.5V 10 10 µA 2.7 to 3.6 V I = VIH or VIL VO = 0 to VCC ±5 ±5 µA 2.7 to 3.6 VI = VCC or GND VI or VO= 3.6 to 5.5V 10 10 ± 10 ± 10 2.7 to 3.6 VIH = VCC - 0.6V 500 500 3.0 II -40 to 85 °C VCC (V) 3.0 VOL Value V µA µA DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP V OLV Parameter Dynamic Low Level Quiet Output (note 1) TA = 25 °C VCC (V) 3.3 Value Min. CL = 50pF VIL = 0V, V IH = 3.3V Typ. 0.8 -0.8 Unit Max. V 1) Number of outputs defined as ”n”. Measured with ”n-1” outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 4/10 74LCX574 AC ELECTRICAL CHARACTERISTICS Test Conditi on Symbol Parameter tPLH tPHL Propagation Delay Time tPZL tPZH Output Enable Time to HIGH and LOW level Output Disable Time from HIGH to LOW level Set-Up Time, HIGH or LOW level (Dn to CK) Hold Time, HIGH or LOW level (Dn to CK) CK Pulse Width, HIGH or LOW tPLZ tPHZ tS th tW fMAX tOSLH tOSHL Clock Pulse Frequency Output To Output Skew Time (note1, 2) VCC (V) 2.7 3.0 to 3.6 2.7 CL (pF) RL (Ω) Value ts = t r (ns) 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 2.7 3.0 to 3.6 50 500 3.0 to 3.6 50 3.0 to 3.6 50 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 -55 to 125 °C Min. Max. Min. Max. 1.5 1.5 1.5 9.5 8.5 9.5 1.5 1.5 1.5 9.5 8.5 9.5 1.5 8.5 1.5 8.5 1.5 8.5 1.5 8.5 1.5 7.5 1.5 7.5 Unit ns ns ns 2.5 2.5 2.5 2.5 1.5 1.5 1.5 1.5 2.5 3.3 3.3 3.3 3.3 ns 500 2.5 165 150 MHz 500 2.5 2.7 3.0 to 3.6 -40 to 85 °C 1.0 ns ns 1.0 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter Value TA = 25 °C VCC (V) Min. Typ. Unit Max. Input Capacitance 3.3 VIN = 0 to VCC 6 pF C OUT Output Capacitance 3.3 VIN = 0 to VCC 12 pF CPD Power Dissipation Capacitance (note 1) 3.3 fIN = 10MHz V IN = 0 or VCC 25 CIN pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per flip-flop) 5/10 74LCX574 TEST CIRCUIT TEST tPLH, tPHL SWITCH Open tPZL, tPLZ 6V tPZH, tPHZ GND C L = 50 pF or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES, MAXIMUM CK FREQUENCY (f=1MHz; 50% duty cycle) 6/10 74LCX574 WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3 : PULSE WIDTH (f=1MHz; 50% duty cycle) 7/10 74LCX574 SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A a1 MAX. MIN. TYP. 2.65 0.1 0.104 0.2 a2 MAX. 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 M S 0.75 0.029 8° (max.) PO13L 8/10 74LCX574 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.0256 BSC 0.60 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 9/10 74LCX574 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. 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