ETC 74LCXH16244MEAX

Revised June 2002
74LCXH16244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
General Description
Features
The LCXH16244 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
■ 5V tolerant control inputs and outputs
The LCXH16244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
■ Power down high impedance inputs and outputs
The LCXH16244 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCXH16244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining CMOS low power dissipation.
■ 2.3V–3.6V VCC specifications provided
■ 4.5 ns tPD max (VCC = 3.0V), 20 µA ICC max
■ Bushold on inputs eliminates the need for external
pull-up/pull-down resistors
■ ±24 mA output drive (VCC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
Package Number
Package Description
74LCXH16244G
(Note 1)(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LCXH16244MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCXH16244MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500248
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74LCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold
September 2000
74LCXH16244
Connection Diagrams
Pin Descriptions
Pin Assignment for SSOP and TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
I0–I15
Inputs
O0–O15
Outputs
NC
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
O0
NC
OE1
OE2
NC
I0
B
O2
O1
NC
NC
I1
I2
C
O4
O3
VCC
VCC
I3
I4
D
O6
O5
GND
GND
I5
I6
E
O8
O7
GND
GND
I7
I8
F
O10
O9
GND
GND
I9
I10
I12
G
O12
O11
VCC
VCC
I11
H
O14
O13
NC
NC
I13
I14
J
O15
NC
OE4
OE3
NC
I15
Truth Tables
Inputs
OE1
Pin Assignment for FBGA
Outputs
I0–I3
L
L
L
L
H
H
H
X
Z
Inputs
OE2
Outputs
I4–I7
L
L
L
H
H
H
X
Z
Outputs
OE3
I8–I11
L
L
L
L
H
H
H
X
Z
I12–I15
O12–O15
Inputs
OE4
2
O8–O11
Outputs
L
L
L
L
H
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
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O4–O7
L
Inputs
(Top Thru View)
O0–O3
Z
X = Immaterial
Z = High Impedance
3-STATE outputs are controlled by an Output Enable (OEn)
input for each nibble. When OEn is LOW, the outputs are in
2-state mode. When OEn is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
The LCXH16244 contains sixteen non-inverting buffers
with 3-STATE standard outputs. The device is nibble
(4 bits) controlled with each nibble functioning identically,
but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The
Logic Diagram
3
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74LCXH16244
Functional Description
74LCXH16244
Absolute Maximum Ratings(Note 3)
Symbol
Parameter
VCC
Supply Voltage
VI
DC Input Voltage
Value
Units
V
−0.5 to +7.0
OE
I0 - I15
VO
Conditions
−0.5 to +7.0
V
−0.5 to VCC + 0.5
−0.5 to +7.0
DC Output Voltage
Output in 3-STATE
−0.5 to VCC + 0.5
Output in HIGH or LOW State (Note 4)
IIK
DC Input Diode Current
−50
VI < GND
IOK
DC Output Diode Current
−50
VO < GND
+50
VO > VCC
V
mA
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current per Supply Pin
±100
mA
IGND
DC Ground Current per Ground Pin
±100
mA
TSTG
Storage Temperature
−65 to +150
°C
Recommended Operating Conditions (Note 5)
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH/IOL
Output Current
TA
Free-Air Operating Temperature
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
Min
Max
Operating
2.0
3.6
Data Retention
1.5
3.6
0
VCC
HIGH or LOW State
0
VCC
3-STATE
0
5.5
VCC = 3.0V − 3.6V
±24
VCC = 2.7V − 3.0V
±12
VCC = 2.3V − 2.7V
±8
Units
V
V
V
mA
−40
85
°C
0
10
ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
VIH
Parameter
Conditions
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
VOH
HIGH Level Output Voltage
VCC
TA = −40°C to +85°C
(V)
Min
2.3 − 2.7
1.7
2.7 − 3.6
2.0
2.3 − 2.7
VOL
LOW Level Output Voltage
Input Leakage Current
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0.8
IOH = −8 mA
2.3
1.8
2.7
2.2
IOH = −18 mA
3.0
2.4
IOH = −24 mA
3.0
2.2
IOL = 100 µA
2.3 − 3.6
0.2
IOL = 8 mA
2.3
0.6
IOL = 12 mA
2.7
0.4
IOL = 16 mA
3.0
0.4
V
3.0
0.55
Data
VI = VCC or GND
2.3 − 3.6
±5.0
Control
0 ≤ VI ≤ 5.5
2.3 − 3.6
±5.0
4
V
VCC − 0.2
IOH = −12 mA
IOL = 24 mA
II
2.3 − 3.6
Units
V
0.7
2.7 − 3.6
IOH = −100 µA
Max
V
µA
Symbol
(Continued)
Parameter
VCC
Conditions
TA = −40°C to +85°C
(V)
II(HOLD)
Bushold Input Minimum
VIN = 0.7V
Drive Hold Current
VIN = 1.7V
2.3
VIN = 0.8V
3.0
VIN = 2.0V
II(OD)
Bushold Input Over-Drive
(Note 6)
Current to Change State
(Note 7)
2.7
(Note 6)
3.6
(Note 7)
0 ≤ VO ≤ 5.5V
IOZ
3-STATE Output Leakage
IOFF
Power-Off Leakage Current
VO = 5.5V
ICC
Quiescent Supply Current
∆ICC
Increase in ICC per Input
Min
Units
Max
45
−45
µA
75
−75
300
−300
µA
450
−450
2.3 − 3.6
±5.0
µA
0
10
µA
VI = VCC or GND
2.3 − 3.6
20
µA
VIH = VCC −0.6V
2.3 − 3.6
500
µA
VI = VIH or VIL
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500 Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V
CL = 50 pF
CL = 50 pF
CL = 30 pF
Min
Max
Min
Max
Min
tPHL
Propagation Delay
1.0
4.5
1.0
5.2
1.0
5.4
tPLH
Data to Output
1.0
4.5
1.0
5.2
1.0
5.4
tPZL
Output Enable Time
1.0
5.5
1.0
6.3
1.0
7.2
1.0
5.5
1.0
6.3
1.0
7.2
Output Disable Time
1.0
5.4
1.0
5.7
1.0
6.5
5.4
1.0
5.7
1.0
6.5
tPZH
tPLZ
tPHZ
tOSHL
1.0
Output to Output Skew (Note 8)
Max
1.0
ns
ns
ns
ns
1.0
tOSLH
Units
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
VCC
TA = 25°C
(V)
Typical
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
0.8
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
0.6
CL = 50 pF, VIH = 3.3V, VIL = 0V
3.3
−0.8
CL = 30 pF, VIH = 2.5V, VIL = 0V
2.5
−0.6
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Conditions
Units
V
V
Capacitance
Typical
Units
CIN
Symbol
Input Capacitance
Parameter
VCC = Open, VI = 0V or VCC
Conditions
7
pF
COUT
Output Capacitance
VCC = 3.3V, VI = 0V or VCC
8
pF
CPD
Power Dissipation Capacitance
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
20
pF
5
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74LCXH16244
DC Electrical Characteristics
74LCXH16244
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
CL
VI
6V for VCC = 3.3V, 2.7V
50 pF
VCC * 2 for VCC = 2.5V
30 pF
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
Symbol
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VCC
3.3V ± 0.3V
2.7V
2.5V ± 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL + 0.3V
VOL + 0.3V
VOL + 0.15V
Vy
VOH − 0.3V
VOH − 0.3V
VOH − 0.15V
6
74LCXH16244
Schematic Diagram Generic for LCXH Family
7
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74LCXH16244
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
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8
74LCXH16244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
9
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74LCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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