74LVC245A; 74LVCH245A Octal bus transceiver; 3-state Rev. 05 — 25 August 2009 Product data sheet 1. General description The 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features n n n n n n n n n 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Inputs accept voltages up to 5.5 V High-impedance when VCC = 0 V Bushold on all data inputs (74LVCH245A only) Complies with JEDEC standard no. 8-1A ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Specified from −40 °C to +85 °C and −40 °C to +125 °C 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74LVC245AD Temperature range Name Description Version −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm −40 °C to +125 °C DHVQFN20 SOT764-1 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm −40 °C to +125 °C DHXQFN20U plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm 74LVCH245AD 74LVC245ADB 74LVCH245ADB 74LVC245APW 74LVCH245APW 74LVC245ABQ 74LVCH245ABQ 74LVC245ABX 74LVCH245ABX SOT1045-1 4. Functional diagram 1 DIR OE 2 B0 3 19 3EN1 3EN2 1 14 18 3 17 13 4 16 5 15 6 14 7 13 8 12 A6 12 A7 B7 11 9 Logic diagram Fig 2. IEC logic symbol 74LVC_LVCH245A_5 Product data sheet 11 mna175 mna174 Fig 1. 2 A5 B6 9 G3 2 B5 8 15 A4 B4 7 1 16 A3 B3 6 17 A2 B2 5 18 A1 B1 4 19 A0 © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 2 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state 5. Pinning information 5.1 Pinning 1 terminal 1 index area 74LVC245A 74LVCH245A 20 VCC DIR 74LVC245A 74LVCH245A A0 2 19 OE A1 3 18 B0 A2 4 17 B1 DIR 1 20 VCC A0 2 19 OE A1 3 18 B0 A3 5 16 B2 A2 4 17 B1 A4 6 15 B3 A3 5 16 B2 A5 7 14 B4 A4 6 15 B3 A6 8 A5 7 14 B4 A6 8 13 B5 A7 9 A7 9 12 B6 GND 10 11 B7 GND(1) 13 B5 B7 11 GND 10 12 B6 001aak293 Transparent top view 001aak292 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for DHVQFN20 and DHXQFN20U 5.2 Pin description Table 2. Pin description Symbol Pin Description DIR 1 direction control A0 to A7 2, 3, 4, 5, 6, 7, 8, 9 data input/output GND 10 ground (0 V) B0 to B7 18, 17, 16, 15, 14, 13, 12, 11 data input/output OE 19 output enable input (active LOW) VCC 20 supply voltage 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 3 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state 6. Functional description Table 3. Function selection[1] Inputs Inputs/outputs OE DIR An Bn L L An = Bn inputs L H inputs Bn = An H X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit −0.5 +6.5 V −50 - mA −0.5 +6.5 V - ±50 mA output HIGH or LOW [2] −0.5 VCC + 0.5 V output 3-state [2] −0.5 +6.5 V - ±50 mA VO > VCC or VO < 0 V IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 500 mW Tamb = −40 °C to +125 °C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO20 packages: above 70 °C derate linearly with 8 mW/K. For (T)SSOP20 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN20 and DHXQFN20U packages: above 60 °C derate linearly with 4.5 mW/K. 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 4 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage maximum speed performance 2.7 - 3.6 V functional 1.2 - 3.6 V VI input voltage 0 - 5.5 V VO output voltage output HIGH or LOW 0 - VCC V output 3-state 0 - 5.5 V Tamb ambient temperature in free air −40 - +125 °C ∆t/∆V input transition rise and fall rate VCC = 1.2 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max HIGH-level input voltage VCC = 1.2 V VCC - - VCC - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VIL LOW-level input voltage VCC = 1.2 V - - 0 - 0 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VOH HIGH-level output VI = VIH or VIL voltage IO = −100 µA; VCC = 2.7 V to 3.6 V VCC − 0.2 VCC - VCC − 0.3 - V VIH VOL LOW-level output voltage IO = −12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = −18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = −24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 µA; VCC = 2.7 V to 3.6 V - 0 0.20 - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.40 - 0.6 V VI = VIH or VIL IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V [2] - ±0.1 ±5 - ±20 µA [2][3] - ±0.1 ±5 - ±20 µA II input leakage current VI = 5.5 V or GND; VCC = 3.6 V IOZ OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V IOFF power-off leakage VI or VO = 5.5 V; VCC = 0.0 V current - ±0.1 ±10 - ±20 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V - 0.1 10 - 40 µA ∆ICC additional supply current per input pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V - 5 500 - 5000 µA 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 5 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max CI input capacitance - 4.0 - - - pF CI/O input/output capacitance - 10 - - - pF IBHL bus hold LOW current VCC = 3.0 V; VI = 0.8 V [4][5] 75 - - 60 - µA IBHH bus hold HIGH current VCC = 3.0 V; VI = 2.0 V [4][5] −75 - - −60 - µA IBHLO bus hold LOW overdrive current VCC = 3.6 V [4][6] 500 - - 500 - µA IBHHO bus hold HIGH overdrive current VCC = 3.6 V [4][6] −500 - - −500 - µA [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. [3] For I/O ports the parameter IOZ includes the input leakage current. [4] Valid for data inputs of bus hold parts only (74LVCH245A). Note that control inputs do not have a bus hold circuit. [5] The specified sustaining current at the data input holds the input below the specified VI level. [6] The specified overdrive current at the data input forces the data input to the opposite input state. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter tpd propagation delay −40 °C to +85 °C Conditions An to Bn; see Figure 5 Max Min Max - 17.0 - - - VCC = 1.2 V [3] VCC = 3.0 V to 3.6 V enable time Typ[2] [1] VCC = 2.7 V ten OE to An or Bn; see Figure 6 1.5 3.4 7.3 1.5 9.5 ns 2.9 6.3 1.5 8.0 ns - 22.0 - - - ns [1] VCC = 2.7 V [3] VCC = 3.0 V to 3.6 V disable time OE to An or Bn; see Figure 6 1.5 5.0 9.5 1.5 12.0 ns 1.5 4.0 8.5 1.5 11.0 ns - 12.0 - - - ns [1] VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(o) output skew time 1.5 3.6 8.0 1.5 10.0 ns [3] 1.7 3.4 7.0 1.7 9.0 ns [4] - - 1.0 - 1.5 ns 74LVC_LVCH245A_5 Product data sheet ns 1.5 VCC = 1.2 V tdis −40 °C to +125 °C Unit Min © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 6 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter CPD [1] power dissipation capacitance −40 °C to +85 °C Conditions per buffer; VI = GND to VCC; VCC = 3.3 V −40 °C to +125 °C Unit Min Typ[2] Max Min Max - 15 - - - [5] pF tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [2] Typical values are measured at Tamb = 25 °C. [3] Typical values are measured at Tamb = 25 °C and VCC = 3.3 V. [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [5] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs. 11. AC waveforms VI An, Bn input VM VM GND tPLH tPHL VOH Bn, An output VM VM VOL mna176 See Table 8 for measurement points VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Input (An, Bn) to output (Bn, An) propagation delays and output transition times 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 7 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state VI OE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PHZ VOH t PZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mna367 See Table 8 for measurement points VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.1 V VOH − 0.1 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 8 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VEXT VCC VI RL VO G DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2.5 ns 50 pF 500 Ω[1] open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND [1] The circuit performs better when RL = 1 kΩ. 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 9 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.016 0.394 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT163-1 (SO20) 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 10 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Package outline SOT339-1 (SSOP20) 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 11 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 10. Package outline SOT360-1 (TSSOP20) 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 12 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 0.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 11. Package outline SOT764-1 (DHVQFN20) 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 13 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state DHXQFN20U: plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm B D SOT1045-1 A A E A1 detail X terminal 1 index area terminal 1 index area e1 L1 v w b e 2 M M C C A B C y y1 C 9 L 10 1 Eh e 20 11 19 12 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D Dh E Eh e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.30 0.18 4.6 4.4 3.35 3.05 2.6 2.4 1.35 1.05 0.5 3.5 0.45 0.25 0.13 0.05 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC SOT1045-1 --- JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-01 09-08-04 Fig 12. Package outline SOT1045-1 (DHXQFN20U) 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 14 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC_LVCH245A_5 20090825 - 74LVC_LVCH245A_4 Modifications: 74LVC_LVCH245A_4 Modifications: 74LVC_LVCH245A_3 • Product data sheet New SOT1045-1 package outline drawing (DHXQFN20U package). 20090703 Product data sheet - 74LVC_LVCH245A_3 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Added type number 74LVC245ABX and 74LVCH245ABX (DHXQFN20U package) 20030507 Product specification - 74LVC245A_74LVCH245A_2 74LVC245A_74LVCH245A_2 20020620 Product specification - 74LVC245A_74LVCH245A_1 74LVC245A_74LVCH245A_1 19971219 Product specification - - 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 15 of 17 74LVC245A; 74LVCH245A NXP Semiconductors Octal bus transceiver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC_LVCH245A_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 25 August 2009 16 of 17 NXP Semiconductors 74LVC245A; 74LVCH245A Octal bus transceiver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 August 2009 Document identifier: 74LVC_LVCH245A_5