Revised June 2001 74LVQ241 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The LVQ241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. ■ Ideal for low power/low noise 3.3V applications ■ Implements patented EMI reduction circuitry ■ Available in SOIC JEDEC, SOIC EIAJ and QSOP packages ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Improved latch-up immunity ■ Guaranteed incident wave switching into 75Ω ■ 4 kV minimum ESD immunity Ordering Code: Order Number Package Number 74LVQ241SC 74LVQ241SJ 74LVQ241QSC Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Diagram Connection Diagram IEEE/IEC Truth Tables Inputs OE1 Pin Descriptions Pin Names OE1, OE2 Description 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs Outputs In (Pins 12, 14, 16, 18) L L L L H H H X Inputs Z Outputs OE2 In L X Z H H H H L L (Pins 3, 5, 7, 9) H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance © 2001 Fairchild Semiconductor Corporation DS011355 www.fairchildsemi.com 74LVQ241 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs February 1992 74LVQ241 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) 2.0V to 3.6V VI = −0.5V −20 mA Input Voltage (VI) 0V to VCC VI = VCC + 0.5V +20 mA Output Voltage (VO) 0V to VCC DC Input Voltage (VI) −0.5V to VCC + 0.5V Minimum Input Edge Rate ∆V/∆t VO = −0.5V −20 mA VIN 0.8V to 2.0V VO = VCC + 0.5V +20 mA VCC @ 3.0V DC Output Voltage (VO) 125 mV/ns −0.5V to VCC + 0.5V DC Output Source Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditions for actual device operation ±50 mA or Sink Current (IO) DC VCC or Ground Current ±400 mA (ICC or IGND ) Storage Temperature (TSTG) −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) −65°C to +150°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Latch-Up Source or ±300 mA Sink Current DC Electrical Characteristics Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN Maximum Input Leakage Current TA = +25°C VCC TA = −40°C to +85°C Units (V) Typ 3.0 1.5 2.0 2.0 V 3.0 1.5 0.8 0.8 V 3.0 2.99 2.9 2.9 V 3.0 2.58 2.48 V 0.1 0.1 V 3.0 0.36 0.44 V 3.6 ±0.1 ±1.0 µA 3.0 Conditions Guaranteed Limits 0.002 VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND IOLD Minimum Dynamic 3.6 36 mA VOLD = 0.8V Max (Note 5) IOHD Output Current (Note 4) 3.6 −25 mA VOHD = 2.0V Min (Note 5) ICC Maximum Quiescent Supply Current IOZ 3.6 4.0 40.0 µA 3.6 ±0.25 ±2.5 µA VI (OE) = VIL, VIH Maximum 3-STATE Leakage Current VIN = VCC or GND VI = VCC, GND VO = VCC, GND VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level VILD Maximum Low Level Dynamic Input Voltage Dynamic Input Voltage 3.3 0.4 0.8 V (Note 6)(Note 7) 3.3 −0.4 −0.8 V (Note 6)(Note 7) 3.3 1.6 2.0 V (Note 6)(Note 8) 3.3 1.6 0.8 V (Note 6)(Note 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V. One output @ GND. Note 8: Max number of Data Inputs (n) switching. n−1 Inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 TA = +25°C Symbol Parameter tPHL Propagation Delay tPLH Data to Output tPZL Output Enable Time tPZH Output Disable Time tPHZ tPLZ tOSHL Output to Output tOSLH Skew Data to Output (Note 9) TA = −40°C to +85°C CL = 50 pF VCC CL = 50 pF (V) Min Typ Max Min Max 2.7 2.0 7.8 12.7 2.0 14.0 3.3 ± 0.3 2.0 6.5 9.0 2.0 9.5 2.7 2.5 9.6 18.3 2.5 19.0 3.3 ± 0.3 2.5 8.0 13.0 2.5 13.5 2.7 1.0 10.2 20.4 1.0 21.0 3.3 ± 0.3 1.0 8.5 14.5 1.0 15.0 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 Units ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = Open Conditions CPD (Note 10) Power Dissipation Capacitance 70 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 74LVQ241 AC Electrical Characteristics 74LVQ241 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 4 74LVQ241 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74LVQ241 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6