SN54LVTH16374,, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com FEATURES • • • • • • • • • • • Members of the Texas Instruments Widebus™ Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) SCBS145Q – MAY 1992 – REVISED DECEMBER 2006 SN54LVTH16374 . . . WD PACKAGE SN74LVTH16374 . . . DGG OR DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2CLK DESCRIPTION/ORDERING INFORMATION The 'LVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1992–2006, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. SN54LVTH16374,, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCBS145Q – MAY 1992 – REVISED DECEMBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. ORDERING INFORMATION PACKAGE (1) TA FBGA – GRD FBGA – ZRD (Pb-free) ORDERABLE PART NUMBER Reel of 1000 Tube of 25 SSOP – DL –40°C to 85°C Reel of 1000 TSSOP – DGG VFBGA – GQL VFBGA – ZQL (Pb-free) –55°C to 125°C (1) 2 CFP – WD Reel of 2000 Reel of 1000 Tube SN74LVTH16374GRDR SN74LVTH16374ZRDR TOP-SIDE MARKING LL374 SN74LVTH16374DL 74LVTH16374DLG4 SN74LVTH16374DLR LVTH16374 74LVTH16374DLRG4 SN74LVTH16374DGGR 74LVTH16374DGGRG4 SN74LVTH16374KR SN74LVTH16374ZQLR SNJ54LVTH16374WD LVTH16374 LL374 SNJ54LVTH16374WD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Submit Documentation Feedback SN54LVTH16374,, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCBS145Q – MAY 1992 – REVISED DECEMBER 2006 GQL OR ZQL PACKAGE (TOP VIEW) TERMINAL ASSIGNMENTS (1) (56-Ball GQL/ZQL Package) 1 2 3 4 5 6 A B C D E F G H J K abc 1 2 3 4 5 6 A 1OE NC NC NC NC 1CLK B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 VCC VCC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 VCC VCC 2D6 2D5 J 2Q7 2Q8 GND GND 2D8 2D7 K 2OE NC NC NC NC 2CLK (1) abc NC – No internal connection GRD OR ZRD PACKAGE (TOP VIEW) 1 2 3 4 5 6 TERMINAL ASSIGNMENTS (1) (54-Ball GRD/ZRD Package) A B C D E F G 1 2 3 4 5 6 A 1Q1 NC 1OE 1CLK NC 1D1 B 1Q3 1Q2 NC NC 1D2 1D3 C 1Q5 1Q4 VCC VCC 1D4 1D5 D 1Q7 1Q6 GND GND 1D6 1D7 E 2Q1 1Q8 GND GND 1D8 2D1 F 2Q3 2Q2 GND GND 2D2 2D3 G 2Q5 2Q4 VCC VCC 2D4 2D5 H 2Q7 2Q6 NC NC 2D6 2D7 J 2Q8 NC 2OE 2CLK NC 2D8 H J (1) NC – No internal connection FUNCTION TABLE (EACH FLIP-FLOP) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z Submit Documentation Feedback 3 SN54LVTH16374,, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCBS145Q – MAY 1992 – REVISED DECEMBER 2006 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1CLK 1D1 1 2OE 48 2CLK C1 47 2 1D 1Q1 24 25 C1 2D1 36 To Seven Other Channels 13 1D 2Q1 To Seven Other Channels Pin numbers shown are for the DGG, DL, and WD packages. Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 V VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high state (2) state (2) SN54LVTH16374 96 SN74LVTH16374 128 SN54LVTH16374 48 SN74LVTH16374 64 IO Current into any output in the low state IO Current into any output in the high state (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA θJA Package thermal impedance (4) Tstg Storage temperature range DGG package 70 DL package 63 GQL/ZQL package 42 GRD/ZRD package (1) (2) (3) (4) 4 UNIT mA mA °C/W 36 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback www.ti.com SN54LVTH16374,, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS145Q – MAY 1992 – REVISED DECEMBER 2006 Recommended Operating Conditions (1) SN54LVTH16374 SN74LVTH16374 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 0.8 VI Input voltage 5.5 5.5 V IOH High-level output current –24 –32 mA IOL Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate 10 10 ns/V ∆t/∆VCC Power-up ramp rate 200 TA Operating free-air temperature –55 (1) 2 Outputs enabled 2 V –40 V µs/V 200 125 V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 5 SN54LVTH16374,, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCBS145Q – MAY 1992 – REVISED DECEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 2.7 V, VOH VCC = 3 V VCC = 2.7 V VOL VCC = 3 V MIN TYP (1) II = –18 mA VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC = 2.7 V, SN54LVTH16374 IOH = –8 mA IOH = –24 mA SN74LVTH16374 MAX MIN TYP (1) –1.2 II Data inputs VCC – 0.2 VCC – 0.2 2.4 2.4 IOH = –32 mA Ioff 2 IOL = 100 µA 0.2 0.2 IOL = 24 mA 0.5 0.5 IOL = 16 mA 0.4 0.4 IOL = 32 mA 0.5 0.5 IOL = 48 mA 0.55 II(hold) 10 VCC = 3.6 V, VI = VCC or GND ±1 ±1 1 1 Data inputs VCC = 3 V VI = VCC VI = 0 –5 –5 ±100 VI or VO = 0 to 4.5 V VI = 2 V µA 75 75 –75 –75 µA µA VCC = 3.6 V, (2) VI = 0 to 3.6 V IOZH VCC = 3.6 V, VO = 3 V IOZL VCC = 3.6 V, VO = 0.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care IOZPD ICC VCC = 3.6 V, IO = 0, VI = VCC or GND ∆ICC (4) VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND CI VI = 3 V or 0 3 3 pF Co VO = 3 V or 0 9 9 pF (1) (2) (3) (4) 6 10 VI = 0.8 V V 0.55 VI = 5.5 V VCC = 0, V V 2 VCC = 0 or 3.6 V, VCC = 3.6 V UNIT –1.2 IOL = 64 mA Control inputs MAX 500 5 5 µA –5 –5 µA ±100 (3) ±100 µA VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care ±100 (3) ±100 µA Outputs high 0.19 0.19 5 5 0.19 0.19 0.2 0.2 Outputs low Outputs disabled All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. On products compliant to MIL-PRF-38535, this parameter is not production tested. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Submit Documentation Feedback mA mA SN54LVTH16374,, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCBS145Q – MAY 1992 – REVISED DECEMBER 2006 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH16374 VCC = 3.3 V ± 0.3 V MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ SN74LVTH16374 VCC = 2.7 V MAX MIN 160 MAX VCC = 3.3 V ± 0.3 V MIN 160 VCC = 2.7 V MAX MIN MAX 160 3 3 3 High or low 2.9 3.3 High or low 0.8 0.2 UNIT 160 MHz 3 ns 1.8 2 ns 0.8 0.1 ns Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH16374 PARAMETER TO (OUTPUT) VCC = 3.3 V ± 0.3 V SN74LVTH16374 VCC = 2.7 V MIN TYP (1) VCC = 2.7 V MIN fmax 160 160 tPLH 1.4 5.6 6.2 1.9 3 4.5 5.2 1.7 4.8 5 2.1 2.9 4 4.2 tPZH tPZL tPHZ tPLZ CLK Q OE Q OE Q MAX VCC = 3.3 V ± 0.3 V MIN MAX tPHL (1) FROM (INPUT) MAX 160 MIN MAX 160 MHz 1 5.6 6.4 1.5 2.8 4.5 5.4 1.4 5.5 6.2 1.5 2.8 4.4 5 1 6.4 6.9 2.4 3.5 5 5.4 1.7 5 5.2 2 3.2 4.6 4.8 tsk(LH) 0.5 tsk(HL) 0.5 UNIT ns ns ns ns All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback 7 SN54LVTH16374,, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS www.ti.com SCBS145Q – MAY 1992 – REVISED DECEMBER 2006 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V Timing Input LOAD CIRCUIT 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL Output Waveform 1 S1 at 6 V (see Note B) tPLH 1.5 V 1.5 V 1.5 V VOL tPZL tPLZ 3V 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZH VOH Output 2.7 V Output Control VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9564701QXA ACTIVE CFP WD 48 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVTH16374DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH16374DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH16374DL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH16374DLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH16374DLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH16374GQLR ACTIVE BGA MI CROSTA R JUNI OR GQL 56 1000 TBD SNPB Level-1-240C-UNLIM SN74LVTH16374GRDR ACTIVE BGA MI CROSTA R JUNI OR GRD 54 1000 TBD SNPB Level-1-240C-UNLIM SN74LVTH16374ZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74LVTH16374ZRDR ACTIVE BGA MI CROSTA R JUNI OR ZRD 54 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SNJ54LVTH16374WD ACTIVE WD 48 A42 SNPB N / A for Pkg Type 1 TBD TBD A42 SNPB MSL Peak Temp (3) 74LVTH16374DGGRG4 CFP 1 Lead/Ball Finish N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.075 (1,91) 0.009 (0,23) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.250 (6,35) 0.390 (9,91) 0.370 (9,40) 0.370 (9,40) 0.250 (6,35) 48 1 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 25 24 NO. OF LEADS** 48 56 A MAX 0.640 (16,26) 0.740 (18,80) A MIN 0.610 (15,49) 0.710 (18,03) 4040176 / D 10/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO -146AA GDFP1-F56 and JEDEC MO -146AB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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