Preliminary Revised August 2001 74VCX32373 Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary) General Description Features The VCX32373 contains thirty-two non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. ■ 1.65V–3.6V VCC supply operation The 74VCX32373 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. ■ Power-off high impedance inputs and outputs The 74VCX32373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ Static Drive (IOH/IOL) ■ 3.6V tolerant inputs and outputs ■ tPD (In to On) 3.0 ns max for 3.0V to 3.6V VCC 3.4 ns max for 2.3V to 2.7V VCC 6.8 ns max for 1.65V to 1.95V VCC ■ Support live insertion and withdrawal (Note 1) ±24 mA @ 3.0V VCC ±18 mA @ 2.3V VCC ±6 mA @ 1.65V VCC ■ Uses patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 300 mA ■ ESD performance: Human body model > 2000V Machine model > 200V ■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Ordering Number Package Number 74VCX32373GX (Note 2) BGA96A Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] Note 2: BGA package available in Tape and Reel only. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS500567 www.fairchildsemi.com 74VCX32373 Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary) February 2001 74VCX32373 Preliminary Connection Diagram Pin Descriptions Pin Assignment for FBGA Pin Names Description OEn Output Enable Input (Active LOW) LEn Latch Enable Input I0–I31 Inputs O0–O31 Outputs FBGA Pin Assignments (Top Thru View) 1 2 3 4 5 6 A O1 O0 OE1 LE1 I0 I1 B O3 O2 GND GND I2 I3 C O5 O4 VCC VCC I4 I5 D O7 O6 GND GND I6 I7 E O9 O8 GND GND I8 I9 F O11 O10 VCC VCC I10 I11 G O13 O12 GND GND I12 I13 H O14 O15 OE2 LE2 I15 I14 J O17 O16 OE3 LE3 I16 I17 K O19 O18 GND GND I18 I19 L O21 O20 VCC VCC I20 I21 M O23 O22 GND GND I22 I23 N O25 O24 GND GND I24 I25 P O27 O26 VCC VCC I26 I27 R O29 O28 GND GND I28 I29 T O30 O31 OE4 LE4 I31 I30 Truth Tables Inputs Outputs Outputs LE1 OE1 I0–I7 O0–O7 LE3 OE3 I16–I23 O16–O23 X H X Z X H X Z H L L L H L L L H L H H H L H H L X O0 L L X L Inputs H L X Inputs Outputs LE2 OE2 I8–I15 O8–O15 Inputs O0 Outputs LE4 OE4 I24–I31 O24–O31 Z X H X Z X H X H L L L H L L L H L H H H L H H L L X O0 L L X O0 = HIGH Voltage Level = LOW Voltage Level = Immaterial (HIGH or LOW, inputs may not float) www.fairchildsemi.com Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of Latch Enable 2 Preliminary The 74VCX32373 contains thirty-two edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 32-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3STATE outputs are controlled by the Output Enable (OEn) input. When OEn is LOW the standard outputs are in the 2state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74VCX32373 Functional Description 74VCX32373 Preliminary Absolute Maximum Ratings(Note 3) Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Recommended Operating Conditions (Note 5) Power Supply Output Voltage (VO) Operating −0.5V to +4.6V Outputs 3-STATED Outputs Active (Note 4) DC Input Diode Current (IIK) VI < 0V 1.65V to 3.6V Data Retention Only −0.5V to VCC +0.5V −50 mA Output Voltage (VO) DC Output Diode Current (IOK) Output in Active States VO < 0V −50 mA Output in “OFF” State VO > VCC +50 mA Output Current in IOH/IOL DC Output Source/Sink Current ±50 mA (IOH/IOL) Storage Temperature Range (TSTG) 0V to VCC 0.0V to 3.6V VCC = 3.0V to 3.6V ±24 mA VCC = 2.3V to 2.7V ±18 mA VCC = 1.65V to 2.3V DC VCC or GND Current per Supply Pin (ICC or GND) 1.2V to 3.6V −0.3V to +3.6V Input Voltage ±100 mA ±6 mA Free Air Operating Temperature (TA) −65°C to +150 °C −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused inputs must be held HIGH or LOW. DC Electrical Characteristics (2.7V < VCC ≤ 3.6V) Symbol Parameter Conditions VCC (V) VIH HIGH Level Input Voltage 2.7–3.6 VIL LOW Level Input Voltage 2.7–3.6 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage Min Max Units 0.8 V 2.0 V IOH = −100 µA 2.7–3.6 VCC − 0.2 V IOH = −12 mA 2.7 2.2 V IOH = −18 mA 3.0 2.4 V IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.7–3.6 0.2 V IOL = 12 mA 2.7 0.4 V IOL = 18 mA 3.0 0.4 V IOL = 24 mA 3.0 0.55 V 2.7–3.6 ±5.0 µA 2.7–3.6 ±10 µA II Input Leakage Current 0 ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V VI = VIH or VIL V IOFF Power-OFF Leakage Current 0 ≤ (VI, VO) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current VI = VCC or GND 2.7–3.6 20 µA VCC ≤ (VI, VO) ≤ 3.6V (Note 6) 2.7–3.6 ±20 µA VIH = VCC − 0.6V 2.7–3.6 750 µA ∆ICC Increase in ICC per Input Note 6: Outputs disabled or 3-STATE only. www.fairchildsemi.com 4 Preliminary Symbol Parameter VCC Conditions (V) VIH HIGH Level Input Voltage 2.3 − 2.7 VIL LOW Level Input Voltage 2.3 − 2.7 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage IOH = −100 µA Min Max Units 0.7 V 1.6 V 2.3 − 2.7 VCC − 0.2 V IOH = −6 mA 2.3 2.0 V IOH = −12 mA 2.3 1.8 V IOH = −18 mA 2.3 1.7 IOL = 100 µA 2.3 − 2.7 0.2 V IOL = 12 mA 2.3 0.4 V IOL = 18 mA 2.3 0.6 V 2.3 − 2.7 ±5.0 µA 2.3 − 2.7 ±10 µA II Input Leakage Current 0 ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V VI = V IH or VIL V IOFF Power-OFF Leakage Current 0 ≤ (VI, VO) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current VI = V CC or GND 2.3 − 2.7 20 µA VCC ≤ (VI, VO) ≤ 3.6V (Note 7) 2.3 − 2.7 ±20 µA Max Units Note 7: Outputs disabled or 3-STATE only. DC Electrical Characteristics (1.65V ≤ VCC < 2.3V) Symbol Parameter Conditions VCC (V) VIH HIGH Level Input Voltage 1.65 - 2.3 VIL LOW Level Input Voltage 1.65 - 2.3 VOH HIGH Level Output Voltage IOH = −100 µA Min 0.65 × VCC 1.65 - 2.3 VCC − 0.2 IOH = −6 mA 1.65 1.25 IOL = 100 µA 1.65 - 2.3 VOL LOW Level Output Voltage II Input Leakage Current 0 ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V IOL = 6 mA VI = V IH or VIL V 0.35 × V CC V V V 0.2 V 1.65 0.3 V 1.65 - 2.3 ±5.0 µA 1.65 - 2.3 ±10 µA IOFF Power-OFF Leakage Current 0 ≤ (VI, VO) ≤ 3.6V 0 10 µA ICC Quiescent Supply Current VI = V CC or GND 1.65 - 2.3 20 µA VCC ≤ (VI, VO) ≤ 3.6V (Note 8) 1.65 − 2.3 ±20 µA Note 8: Outputs disabled or 3-STATE only. 5 www.fairchildsemi.com 74VCX32373 DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V) 74VCX32373 Preliminary AC Electrical Characteristics (Note 9) T A = −40°C to +85°C, CL = 30 pF, RL = 500Ω Symbol Parameter V CC = 3.3V ± 0.3V V CC = 2.5V ± 0.2V V CC = 1.8V ± 0.15V Min Max Min Max Min Max Units tPHL, tPLH Propagation Delay In to On 0.8 3.0 1.0 3.4 1.5 6.8 tPHL, tPLH Propagation Delay LE to On 0.8 3.0 1.0 3.9 1.5 7.8 ns ns tPZL, tPZH Output Enable Time 0.8 3.5 1.0 4.6 1.5 9.2 ns tPLZ, tPHZ Output Disable Time 0.8 3.5 1.0 3.8 1.5 6.8 ns tS Setup Time 1.5 1.5 2.5 ns tH Hold Time 1.0 1.0 1.0 ns tW Pulse Width 1.5 1.5 4.0 ns Note 9: For CL = 50PF, add approximately 300 ps to the AC maximum specification. Dynamic Switching Characteristics Symbol VOLP VOLV VOHV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Quiet Output Dynamic Valley VOH Conditions CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V VCC TA = +25°C (V) Typical 1.8 0.25 2.5 0.6 3.3 0.8 1.8 −0.25 2.5 −0.6 3.3 −0.8 1.8 1.5 2.5 1.9 3.3 2.2 Units V V V Capacitance Symbol Parameter Conditions TA = +25°C Typical Units CIN Input Capacitance VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC 6 pF COUT Output Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 7 pF CPD Power Dissipation Capacitance VI = 0V or VCC, f = 10 MHz, 20 pF VCC = 1.8V, 2.5V or 3.3V www.fairchildsemi.com 6 Preliminary 74VCX32373 AC Loading and Waveforms TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V; VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V tPZH, tPHZ GND FIGURE 1. AC Test Circuit FIGURE 3. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms Symbol VCC 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VX VOL +0.3V VOL +0.15V VOL +0.15V VY VOH −0.3V VOH −0.15V VOH −0.15V 7 www.fairchildsemi.com 74VCX32373 Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary) Preliminary Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8