Revised April 1999 74VHC373 Octal D-Type Latch with 3-STATE Outputs General Description The VHC373 is an advanced high speed CMOS octal Dtype latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is LATCHED. When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: tPD = 5.0 ns (typ) @ VCC = 5V ■ High Noise Immunity: VNIH = VNIL = 28% VCC (Min) ■ Power Down Protection is provided on all inputs ■ Low Noise: VOLP = 0.6V (typ) ■ Low Power Dissipation: ICC = 4 µA (Max) @ TA = 25°C ■ Pin and Function Compatible with 74HC373 Ordering Code: Order Number Package Number 74VHC373M 74VHC373SJ 74VHC373MTC 74VHC373N M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D7 © 1999 Fairchild Semiconductor Corporation Description Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Outputs DS011555.prf www.fairchildsemi.com 74VHC373 Octal D-Type Latch with 3-STATE Outputs February 1993 74VHC373 Functional Description Truth Table The VHC373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs LE OE Dn On Z X H X H L L L H L H H L L X O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to + 7.0V DC Input Voltage (VIN) −0.5V to + 7.0V Recommended Operating Conditions (Note 2) 2.0V to + 5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) 0V to + 5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC /GND Current (ICC ) ±75 mA VCC = 3.3V ± 0.3V −65°C to +150°C Storage Temperature (TSTG) 0 ∼ 100 ns/V VCC = 5.0 ± 0.5V Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C 0 ∼ 20 ns/V Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH HIGH Level Input Voltage VIL VOL IOZ TA = +25°C Min Typ TA = −40°C to +85°C Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage VOH VCC (V) Parameter Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 Conditions V 3.0 − 5.5 HIGH Level Units V VIN = VIH V IOH = −50 µA or VIL 4.4 0.0 0.1 IOH = −4 mA V LOW Level 2.0 Output Voltage 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 IOH = −8 mA VIN = VIH 0.1 V IOL = 50 µA or VIL IOL = 4 mA 3.0 0.36 0.44 4.5 0.36 0.44 5.5 ±0.25 ±2.5 µA VIN = VIH or VIL 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5 or GND 5.5 4.0 40.0 µA VIN = VCC or GND 3-STATE Output V IOL = 8 mA VOUT = VCC or GND Off-State Current IIN Input Leakage Current ICC Quiescent Supply Current Noise Characteristics Symbol Parameter TA = +25°C VCC (V) Typ Limits Units Conditions VOLP (Note 3) Quiet Output Maximum Dynamic VOL 5.0 0.6 0.9 V CL = 50 pF VOLV (Note 3) Quiet Output Minimum Dynamic VOL 5.0 −0.6 −0.9 V CL = 50 pF VIHD (Note 3) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF VILD (Note 3) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF Note 3: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC373 Absolute Maximum Ratings(Note 1) 74VHC373 AC Electrical Characteristics Symbol VCC (V) Parameter tPLH Propagation Delay tPHL Time (LE to On) TA = +25°C Min 3.3 ± 0.3 5.0 ± 0.5 tPLH Propagation Delay tPHL Time (D to On) 3.3 ± 0.3 5.0 ± 0.5 tPZL 3-STATE tPZH Output 3.3 ± 0.3 5.0 ± 0.5 Enable Time TA = −40°C to +85°C Typ Max Min Max 7.0 11.0 1.0 13.0 9.5 14.5 1.0 16.5 4.9 7.2 1.0 8.5 6.4 9.2 1.0 10.5 7.3 11.4 1.0 13.5 9.8 14.9 1.0 17.0 5.0 7.2 1.0 8.5 6.5 9.2 1.0 10.5 7.3 11.4 1.0 13.5 9.8 14.9 1.0 17.0 5.5 8.1 1.0 9.5 7.0 10.1 1.0 11.5 tPLZ 3-STATE Output 3.3 ± 0.3 9.5 13.2 1.0 15.0 tPHZ Disable Time 5.0 ± 0.5 6.5 9.2 1.0 10.5 tOSLH Output to 3.3 ± 0.3 1.5 1.5 tOSHL Output Skew 5.0 ± 0.5 1.0 1.0 CIN Input Capacitance 10 10 COUT Output Capacitance CPD Power Dissipation Units Conditions CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF RL = 1 kΩ ns CL = 15 pF ns CL = 50 pF RL = 1 kΩ ns CL = 50 pF CL = 50 pF (Note 4) ns CL = 50 pF CL = 50 pF pF VCC = Open 6 pF VCC = 5.0V 27 pF (Note 5) 4 CL = 15 pF CL = 50 pF Capacitance Note 4: Parameter guaranteed by design. tOSLH = |tPLH max − t PLH min |; tOSHL = |tPHL max − tPHL min| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD • VCC • fIN + ICC/8 (per Latch). The total CPD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) = 14 + 13n. AC Operating Requirements Symbol tW(H) tS tH Parameter Minimum Pulse Width (LE) Minimum Set-Up Time Minimum Hold Time www.fairchildsemi.com TA = +25°C VCC (V) Min Typ TA = −40°C to +85°C Max Min 3.3 ± 0.3 5.0 5.0 5.0 ± 0.5 5.0 5.0 3.3 ± 0.3 4.0 4.0 5.0 ± 0.5 4.0 4.0 3.3 ± 0.3 1.0 1.0 5.0 ± 0.5 1.0 1.0 4 Max Units ns ns ns 74VHC373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74VHC373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC373 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)