Revised October 1999 74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in a high impedance state. ■ Input and output interface capability to systems at 5V VCC The LVTH373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT373 and LVTH373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373). ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ Functionally compatible with the 74 series 373 Ordering Code: Order Number 74LVT373WM 74LVT373SJ 74LVT373MTC Package Number M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74LVTH373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Logic Symbols IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS012015 www.fairchildsemi.com 74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs September 1999 74LVT373 • 74LVTH373 Connection Diagram Pin Descriptions Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Latch Outputs Truth Table Inputs Outputs LE OE Dn On Z X H X H L L L H L H H L L X O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description ing the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. The LVT373 and LVTH373 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preced- Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE V −0.5 to +7.0 Output in HIGH or LOW State (Note 2) V V V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage IOH HIGH Level Output Current IOL LOW Level Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Units 2.7 3.6 V 0 5.5 V −32 mA 64 mA −40 85 °C 0 10 ns/V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed. 3 www.fairchildsemi.com 74LVT373 • 74LVTH373 Absolute Maximum Ratings(Note 1) 74LVT373 • 74LVTH373 DC Electrical Characteristics Symbol T A = −40°C to +85°C VCC (V) Parameter Min Typ Max Units −1.2 V Conditions (Note 3) Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA 2.7 2.4 V IOH = −8 mA 3.0 2.0 V IOH = −32 mA VOL II(HOLD) 2.7 II = −18 mA VIK Output LOW Voltage Bushold Input Minimum Drive 2.0 VO ≤ 0.1V or VO ≥ VCC − 0.1V 2.7 0.2 V IOL = 100 µA 2.7 0.5 V IOL = 24 mA 3.0 0.4 V IOL = 16 mA 3.0 0.5 V IOL = 32 mA 3.0 0.55 V IOL = 64 mA VI = 0.8V 3.0 (Note 4) II(OD) V 0.8 75 µA −75 µA VI = 2.0V 500 µA (Note 5) 3.0 (Note 4) Bushold Input Over-Drive Current to Change State µA (Note 6) II Input Current 3.6 10 µA VI = 5.5V Control Pins 3.6 ±1 µA VI = 0V or VCC Data Pins 3.6 −5 µA VI = 0V 1 µA VI = VCC 0 ±100 µA 0V ≤ VI or VO ≤ 5.5V 0–1.5V ±100 µA IOFF Power Off Leakage Current IPU/PD Power up/down 3-STATE −500 VO = 0.5V to 3.0V VI = GND or VCC Output Current IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.0V IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < V O ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ V O ≤ 5.5V, Outputs Disabled ∆ICC Increase in Power Supply Current 3.6 0.2 mA (Note 7) One Input at VCC − 0.6V Other Inputs at VCC or GND Note 3: All typical values are at VCC = 3.3V, TA = 25°C. Note 4: Applies to Bushold versions only (74LVTH373). Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 8) TA = 25°C VCC (V) Min Typ Max Units Conditions CL = 50 pF RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 9) Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. www.fairchildsemi.com 4 TA = −40°C to +85°C CL = 50 pF, RL = 500Ω Symbol Parameter VCC = 3.3V ±0.3V Typ (Note 10) Min Units VCC = 2.7V Max Min Max tPHL Propagation Delay 1.5 4.5 1.5 5.0 tPLH Dn to On 1.5 4.5 1.5 4.9 tPHL Propagation Delay 1.7 4.6 1.7 4.9 tPLH LE to On 1.7 4.5 1.7 5.0 tPZL Output Enable Time 1.3 4.8 1.3 5.9 1.3 4.8 1.3 5.5 tPZH tPLZ Output Disable Time tPHZ 1.9 4.6 1.9 4.9 1.9 4.6 1.9 4.9 ns ns ns ns tW LE Pulse Width 3.0 3.0 tS Setup Time, Dn to LE 1.1 1.0 ns ns tH Hold Time, Dn to LE 1.4 1.4 ns Note 10: All typical values are at VCC = 3.3V, TA = 25°C. Capacitance (Note 11) Typical Units CIN Symbol Input Capacitance Parameter VCC = OPEN, VI = 0V or VCC Conditions 3 pF COUT Output Capacitance VCC = 3.0V, VO= 0V or VCC 5 pF Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVT373 • 74LVTH373 AC Electrical Characteristics 74LVT373 • 74LVTH373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com 74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)