Revised March 2005 74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in a high impedance state. The LVTH373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. ■ Input and output interface capability to systems at 5V VCC These octal latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT373 and LVTH373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink 32 mA/64 mA ■ Functionally compatible with the 74 series 373 ■ ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number Package Package Description Number 74LVT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVT373SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVT373MTC MTC20 74LVTH373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH373SJ 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH373MTCX_NL (Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbols IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS012015 www.fairchildsemi.com 74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs September 1999 74LVT373 • 74LVTH373 Connection Diagram Pin Descriptions Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Latch Outputs Truth Table Inputs H L Z X O0 Outputs LE OE Dn On X H X Z H L L L H L H H L L X O0 HIGH Voltage Level LOW Voltage Level High Impedance Immaterial Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description ing the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. The LVT373 and LVTH373 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preced- Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Conditions Units V V Output in 3-STATE V Output in HIGH or LOW State (Note 3) V VI GND mA VO GND mA 64 VO ! VCC Output at HIGH State 128 VO ! VCC Output at LOW State r64 r128 65 to 150 mA mA mA qC Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V HIGH Level Output Current 32 mA LOW Level Output Current 64 mA VCC Supply Voltage VI Input Voltage IOH IOL TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V Units 40 85 qC 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. 3 www.fairchildsemi.com 74LVT373 • 74LVTH373 Absolute Maximum Ratings(Note 2) 74LVT373 • 74LVTH373 DC Electrical Characteristics Symbol 40qC to 85qC TA VCC (V) Parameter Min Typ Max Units 1.2 V Conditions (Note 4) Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC 0.2 V IOH 100 PA 2.7 2.4 V IOH 8 mA 3.0 2.0 V IOH 32 mA VOL II(HOLD) 2.7 18 mA VIK Output LOW Voltage 2.0 (Note 5) II 0.2 V IOL 100 PA 2.7 0.5 V IOL 24 mA 3.0 0.4 V IOL 16 mA 3.0 0.5 V IOL 32 mA 3.0 0.55 V IOL PA VI 0.8V 2.0V 75 64 mA 3.0 Bushold Input Over-Drive Current to Change State 3.0 PA (Note 7) Input Current 3.6 10 PA VI 5.5V 3.6 r1 PA VI 0V or VCC 5 PA VI 0V 1 PA VI VCC 0 r100 PA 0V d VI or VO d 5.5V 0–1.5V r100 PA 75 PA VI 500 PA (Note 6) 500 Data Pins IPU/PD VO t VCC 0.1V Bushold Input Minimum Drive Control Pins IOFF VO d 0.1V or 2.7 (Note 5) II(OD) V 0.8 II 3.6 Power Off Leakage Current Power up/down 3-STATE Output Current VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC V O d 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ Power Supply Current 3.6 0.19 mA VCC d V O d 5.5V, Outputs Disabled 'ICC Increase in Power Supply Current 3.6 0.2 mA (Note 8) One Input at VCC 0.6V Other Inputs at VCC or GND Note 4: All typical values are at VCC 3.3V, TA 25qC. Note 5: Applies to Bushold versions only (74LVTH373). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 9) TA VCC (V) Min 25qC Typ Units Conditions CL Max 50 pF, RL VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 10) Note 9: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. www.fairchildsemi.com 4 500: 40qC to 85qC TA CL Symbol Parameter 50 pF, RL Typ (Note 11) Min 500: 3.3V r0.3V VCC VCC Max Units 2.7V Min Max tPHL Propagation Delay 1.5 4.5 1.5 5.0 tPLH Dn to On 1.5 4.5 1.5 4.9 tPHL Propagation Delay 1.7 4.6 1.7 4.9 tPLH LE to On 1.7 4.5 1.7 5.0 tPZL Output Enable Time 1.3 4.8 1.3 5.9 1.3 4.8 1.3 5.5 tPZH tPLZ Output Disable Time tPHZ 1.9 4.6 1.9 4.9 1.9 4.6 1.9 4.9 ns ns ns ns tW LE Pulse Width 3.0 3.0 ns tS Setup Time, Dn to LE 1.1 1.0 ns tH Hold Time, Dn to LE 1.4 1.4 ns Note 11: All typical values are at VCC 3.3V, T A 25qC. Capacitance (Note 12) Symbol Parameter Conditions CIN Input Capacitance VCC OPEN, VI COUT Output Capacitance VCC 3.0V, VO 0V or VCC Note 12: Capacitance is measured at frequency f 0V or VCC Typical Units 3 pF 5 pF 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVT373 • 74LVTH373 AC Electrical Characteristics 74LVT373 • 74LVTH373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 74LVT373 • 74LVTH373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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