INTEL 80960JD-50

A
PRELIMINARY
80960JD
EMBEDDED 32-BIT MICROPROCESSOR
■
Pin/Code Compatible with all 80960Jx
Processors
■
High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
Two-Way Set Associative Instruction Cache
— 80960JD - 4 Kbyte
— Programmable Cache Locking
Mechanism
Direct Mapped Data Cache
— 80960JD - 2 Kbyte
— Write Through Operation
On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
■
■
■
■
■ High Bandwidth Burst Bus
■
■
■
■
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
New Instructions
— Conditional Add, Subtract and Select
— Processor Management
High-Speed Interrupt Controller
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
Two On-Chip Timers
— Independent 32-Bit Counting
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
Halt Mode for Low Power
■ IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
■ Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)
132
PIN 1
99
A
A80960JD
i
i960
®
XXXXXXXXA2
M
© 19xx
i
NG80960JD
XXXXXXXXA2
M
© 19xx
33
66
Figure 1. 80960JD Microprocessor
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272596-002
A
80960JD
80960JD
EMBEDDED 32-BIT MICROPROCESSOR
1.0 PURPOSE ..................................................................................................................................................1
2.0 80960JD OVERVIEW ................................................................................................................................. 1
2.1 80960 Processor Core ........................................................................................................................2
2.2 Burst Bus ............................................................................................................................................2
2.3 Timer Unit ...........................................................................................................................................3
2.4 Priority Interrupt Controller .................................................................................................................3
2.5 Instruction Set Summary ....................................................................................................................3
2.6 Faults and Debugging .........................................................................................................................3
2.7 Low Power Operation .........................................................................................................................4
2.8 Test Features ......................................................................................................................................4
2.9 Memory-Mapped Control Registers ....................................................................................................4
2.10 Data Types and Memory Addressing Modes ....................................................................................4
3.0 PACKAGE INFORMATION ........................................................................................................................6
3.1 Pin Descriptions .................................................................................................................................. 6
3.1.1 Functional Pin Definitions ........................................................................................................6
3.1.2 80960Jx 132-Lead PGA Pinout .............................................................................................13
3.1.3 80960Jx PQFP Pinout ...........................................................................................................17
3.2 Package Thermal Specifications ......................................................................................................20
3.3 Thermal Management Accessories ..................................................................................................22
4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................23
4.1 Absolute Maximum Ratings ..............................................................................................................23
4.2 Operating Conditions ........................................................................................................................23
4.3 Connection Recommendations .........................................................................................................24
4.4 DC Specifications .............................................................................................................................24
4.5 AC Specifications ..............................................................................................................................26
4.5.1 AC Test Conditions and Derating Curves ...............................................................................33
4.5.2 AC Timing Waveforms ............................................................................................................34
5.0 BUS FUNCTIONAL WAVEFORMS .........................................................................................................42
6.0 DEVICE IDENTIFICATION .......................................................................................................................56
7.0 REVISION HISTORY ...............................................................................................................................56
PRELIMINARY
ii
80960JD
A
FIGURES
Figure 1.
80960JD Microprocessor ...........................................................................................................0
Figure 2.
80960JD Block Diagram ............................................................................................................2
Figure 3.
132-Lead Pin Grid Array Bottom View - Pins Facing Up .......................................................... 13
Figure 4.
132-Lead Pin Grid Array Top View - Pins Facing Down ........................................................... 14
Figure 5.
132-Lead PQFP - Top View ..................................................................................................... 17
Figure 6.
50 MHz Maximum Allowable Ambient Temperature ................................................................ 21
Figure 7.
40 MHz Maximum Allowable Ambient Temperature ................................................................ 22
Figure 8.
AC Test Load ............................................................................................................................ 33
Figure 9.
Output Delay or Hold vs. Load Capacitance ............................................................................ 33
Figure 10.
Rise and Fall Time Derating ..................................................................................................... 34
Figure 11.
CLKIN Waveform ..................................................................................................................... 34
Figure 12.
Output Delay Waveform for TOV1 ............................................................................................. 35
Figure 13.
Output Float Waveform for TOF ................................................................................................ 35
Figure 14.
Input Setup and Hold Waveform for TIS1 and TIH1 ................................................................... 36
Figure 15.
Input Setup and Hold Waveform for TIS2 and TIH2 ................................................................... 36
Figure 16.
Input Setup and Hold Waveform for TIS3 and TIH3 ................................................................... 37
Figure 17.
Input Setup and Hold Waveform for TIS4 and TIH4 ................................................................... 37
Figure 18.
Relative Timings Waveform for TLXL and T LXA ......................................................................... 38
Figure 19.
DT/R and DEN Timings Waveform .......................................................................................... 38
Figure 20.
TCK Waveform ......................................................................................................................... 39
Figure 21.
Input Setup and Hold Waveforms for T BSIS1 and T BSIH1 ......................................................... 39
Figure 22.
Output Delay and Output Float Waveform for TBSOV1 and TBSOF1 .......................................... 40
Figure 23.
Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 .......................................... 40
Figure 24.
Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ........................................................... 41
Figure 25.
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ............................... 42
Figure 26.
Burst Read and Write Transactions Without Wait States, 32-Bit Bus ...................................... 43
Figure 27.
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................ 44
Figure 28.
Burst Read and Write Transactions Without Wait States, 8-Bit Bus ........................................ 45
Figure 29.
Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus ................................................................................... 46
Figure 30.
Bus Transactions Generated by Double Word Read Bus Request,
Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian ........................... 47
Figure 31.
HOLD/HOLDA Waveform For Bus Arbitration .......................................................................... 48
Figure 32.
Cold Reset Waveform .............................................................................................................. 49
Figure 33.
Warm Reset Waveform ............................................................................................................ 50
Figure 34.
Entering the ONCE State ......................................................................................................... 51
Figure 35.
Summary of Aligned and Unaligned Accesses (32-Bit Bus) .................................................... 54
Figure 36.
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ................................ 55
iii
PRELIMINARY
A
80960JD
TABLES
Table 1.
80960Jx Instruction Set ................................................................................................................ 5
Table 2.
Pin Description Nomenclature ...................................................................................................... 6
Table 3.
Pin Description — External Bus Signals ...................................................................................... 7
Table 4.
Pin Description — Processor Control Signals, Test Signals and Power ..................................... 10
Table 5.
Pin Description — Interrupt Unit Signals .................................................................................... 12
Table 6.
132-Lead PGA Pinout — In Signal Order ................................................................................... 15
Table 7.
132-Lead PGA Pinout — In Pin Order ....................................................................................... 16
Table 8.
132-Lead PQFP Pinout — In Signal Order ................................................................................ 18
Table 9.
132-Lead PQFP Pinout — In Pin Order ..................................................................................... 19
Table 10.
132-Lead PGA Package Thermal Characteristics ...................................................................... 20
Table 11.
132-Lead PQFP Package Thermal Characteristics ................................................................... 21
Table 12.
80960JD Operating Conditions .................................................................................................. 23
Table 13.
80960JD DC Characteristics ...................................................................................................... 24
Table 14.
80960JD ICC Characteristics ...................................................................................................... 25
Table 15.
80960JD AC Characteristics (50 MHz) ...................................................................................... 26
Table 16.
Note Definitions for Table 15, 80960JD AC Characteristics (50 MHz) ...................................... 28
Table 17.
80960JD AC Characteristics (40 MHz) ...................................................................................... 28
Table 18.
80960JD AC Characteristics (33 MHz) ...................................................................................... 31
Table 19.
Natural Boundaries for Load and Store Accesses ..................................................................... 52
Table 20.
Summary of Byte Load and Store Accesses .............................................................................. 52
Table 21.
Summary of Short Word Load and Store Accesses ................................................................... 52
Table 22.
Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) .................................................. 53
Table 23.
80960JD Die and Stepping Reference ....................................................................................... 56
Table 24.
Data Sheet Version -001 to -002 Revision History ..................................................................... 56
PRELIMINARY
iv
A
1.0
PURPOSE
This document contains advance information for the
80960JD microprocessor,
including
electrical
characteristics and package pinout information.
Detailed functional descriptions — other than
parametric performance — are published in the
i960® Jx Microprocessor User’s Guide (272483).
Throughout this data sheet, references to “80960Jx”
indicate features which apply to all of the following:
• 80960JA — 5V, 2 Kbyte instruction cache, 1 Kbyte
data cache
• 80960JF — 5V, 4 Kbyte instruction cache, 2 Kbyte
data cache
• 80960JD — 5V, 4 Kbyte instruction cache, 2 Kbyte
data cache and clock doubling
• 80L960JA — 3.3 V version of the 80960JA
• 80L960JF — 3.3 V version of the 80960JF
2.0
80960JD OVERVIEW
The 80960JD offers high performance to costsensitive 32-bit embedded applications. The
80960JD is object code compatible with the 80960
Core Architecture and is capable of sustained
execution at the rate of one instruction per clock.
This processor’s features include generous
instruction cache, data cache and data RAM. It also
boasts a fast interrupt mechanism, dual programmable timer units and new instructions.
The 80960JD’s clock doubler operates the processor
core at twice the bus clock rate to improve execution
performance without increasing the complexity of
board designs.
Memory subsystems for cost-sensitive embedded
applications often impose substantial wait state
penalties. The 80960JD integrates considerable
storage resources on-chip to decouple CPU
execution from the external bus.
The 80960JD rapidly allocates and deallocates local
register sets during context switches. The processor
needs to flush a register set to the stack only when it
saves more than seven sets to its local register
cache.
A 32-bit multiplexed burst bus provides a high-speed
interface to system memory and I/O. A full
complement of control signals simplifies the
connection of the 80960JD to external components.
The user programs physical and logical memory
PRELIMINARY
80960JD
attributes through memory-mapped control registers
(MMRs) — an extension not found on the i960 Kx,
Sx or Cx processors. Physical and logical configuration registers enable the processor to operate with
all combinations of bus width and data object
alignment. The processor supports a homogeneous
byte ordering model.
This processor integrates two important peripherals:
a timer unit and an interrupt controller. These and
other hardware resources are programmed through
memory-mapped control registers, an extension to
the familiar 80960 architecture.
The timer unit (TU) offers two independent 32-bit
timers for use as real-time system clocks and
general-purpose system timing. These operate in
either single-shot or auto-reload mode and can
generate interrupts.
The interrupt controller unit (ICU) provides a flexible
means for requesting interrupts. The ICU provides
full programmability of up to 240 interrupt sources
into 31 priority levels. The ICU takes advantage of a
cached priority table and optional routine caching to
minimize interrupt latency. Clock doubling reduces
interrupt latency by 40% compared to the
80960JA/JF. Local registers may be dedicated to
high-priority interrupts to further reduce latency.
Acting independently from the core, the ICU
compares the priorities of posted interrupts with the
current process priority, off-loading this task from the
core. The ICU also supports the integrated timer
interrupts.
The 80960JD features a Halt mode designed to
support applications where low power consumption
is critical. The halt instruction shuts down instruction
execution, resulting in a power savings of up to 90
percent.
The 80960JD’s testability features, including ONCE
(On-Circuit Emulation) mode and Boundary Scan
(JTAG), provide a powerful environment for design
debug and fault diagnosis.
The Solutions960® program features a wide variety
of development tools which support the i960
processor family. Many of these tools are developed
by partner companies; some are developed by Intel,
such as profile-driven optimizing compilers. For more
information on these products, contact your local
Intel representative.
1
A
80960JD
CLKIN
32-bit buses
address / data
PLL, Clocks,
Power Mgmt
Bus
Control Unit
4 KByte Instruction Cache
Two-Way Set Associative
TAP
Instruction Sequencer
Constants
32-bit Address
32-bit Data
DEST
SRC2
DEST
SRC2
SRC1
SRC1
effective
address
Memory
Interface
Unit
DEST
Execution
and
Address
Generation
Unit
SRC1
Multiply
Divide
Unit
Register File
SRC2 DEST
Address/
Data Bus
32
Control
Programmable
Interrupt Controller
Global / Local
SRC1
21
Two 32-Bit
Timers
8-Set
Local Register Cache
128
Control
Bus Request
Queues
Boundary Scan
Controller
5
Physical Region
Configuration
Interrupt
Port
9
Memory-Mapped
Register Interface
1 Kbyte
Data RAM
2 Kbyte Direct
Mapped Data
Cache
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Figure 2. 80960JD Block Diagram
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the
80960 Core Architecture. Intel designed this
processor core as a very high performance device
that is also cost-effective. Factors that contribute to
the core’s performance include:
• Core operates at twice the bus speed (80960JD
only)
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline
break latency
• Register and resource scoreboarding allow
overlapped instruction execution
2
• 128-bit register bus speeds local register caching
• 4 Kbyte two-way set associative, integrated
instruction cache
• 2 Kbyte direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait
state program data
2.2
Burst Bus
A 32-bit high-performance bus controller interfaces
the 80960JD to external memory and peripherals.
The BCU fetches instructions and transfers data at
the rate of up to four 32-bit words per six clock
cycles. The external address/data bus is multiplexed.
PRELIMINARY
A
Users may configure the 80960JD’s bus controller to
match an application’s fundamental memory organization. Physical bus width is register-programmed for
up to eight regions. Byte ordering and data caching
are programmed through a group of logical memory
templates and a defaults register.
The BCU’s features include:
• Multiplexed external bus to minimize pin count
• 32-, 16- and 8-bit bus widths to simplify I/O
interfaces
• External ready control for address-to-data, data-todata and data-to-next-address wait state types
• Support for big or little endian byte ordering to
facilitate the porting of existing program code
• Unaligned bus accesses performed transparently
• Three-deep load/store queue to decouple the bus
from the core
Upon reset, the 80960JD conducts an internal self
test. Then, before executing its first instruction, it
performs an external bus confidence test by
performing a checksum on the first words of the
initialization boot record (IBR).
80960JD
inputs. The interrupt unit (IU) also accepts interrupts
from the two on-chip timer channels and a single
Non-Maskable Interrupt (NMI) pin. Interrupts are
serviced according to their priority levels relative to
the current process priority.
Low interrupt latency is critical to many embedded
applications. As part of its highly flexible interrupt
mechanism,
the
80960JD
exploits
several
techniques to minimize latency:
• Interrupt vectors and interrupt handler routines can
be reserved on-chip
• Register frames for high-priority interrupt handlers
can be cached on-chip
• The interrupt stack can be placed in cacheable
memory space
• Interrupt microcode executes at twice the bus
frequency
2.5
Instruction Set Summary
The 80960Jx adds several new instructions to the
i960 core architecture. The new instructions are:
• Conditional Move
The user may examine the contents of the caches at
any time by executing special cache control instructions.
• Conditional Add
• Conditional Subtract
• Byte Swap
2.3
Timer Unit
The timer unit (TU) contains two independent 32-bit
timers which are capable of counting at several clock
rates and generating interrupts. Each is programmed
by use of the TU registers. These memory-mapped
registers are addressable on 32-bit boundaries. The
timers have a single-shot mode and auto-reload
capabilities for continuous operation. Each timer has
an independent interrupt request to the 80960JD’s
interrupt controller. The TU can generate a fault
when unauthorized writes from user mode are
detected. Clock prescaling is supported.
2.4
Priority Interrupt Controller
A programmable interrupt controller manages up to
240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may
be configured for individual edge- or level-triggered
PRELIMINARY
• Halt
• Cache Control
• Interrupt Control
Table 1 identifies the instructions that the 80960Jx
supports. Refer to i960® Jx Microprocessor User’s
Guide (272483) for a detailed description of each
instruction.
2.6
Faults and Debugging
The 80960Jx employs a comprehensive fault model.
The processor responds to faults by making implicit
calls to a fault handling routine. Specific information
collected for each fault allows the fault handler to
diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. In
software, the 80960Jx may be configured to detect
as many as seven different trace event types. Alter3
A
80960JD
natively, mark and fmark instructions can generate
trace events explicitly in the instruction stream.
Hardware breakpoint registers are also available to
trap on execution and data addresses.
2.7
Low Power Operation
Intel fabricates the 80960Jx using an advanced submicron manufacturing process. The processor’s submicron topology provides the circuit density for
optimal cache size and high operating speeds while
dissipating modest power. The processor also uses
dynamic power management to turn off clocks to
unused circuits.
Users may program the 80960Jx to enter Halt mode
for maximum power savings. In Halt mode, the
processor core stops completely while the integrated
peripherals continue to function, reducing overall
power requirements up to 90 percent. Processor
execution resumes from internally or externally
generated interrupts.
2.8
Test Features
The 80960Jx incorporates numerous features which
enhance the user’s ability to test both the processor
and the system to which it is attached. These
features include ONCE (On-Circuit Emulation) mode
and Boundary Scan (JTAG).
The 80960Jx provides testability features compatible
with IEEE Standard Test Access Port and Boundary
Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ,
forces the processor to float all its output pins
(ONCE mode). ONCE mode can also be initiated at
reset without using the boundary scan mechanism.
ONCE mode is useful for board-level testing. This
feature allows a mounted 80960JD to electrically
“remove” itself from a circuit board. This allows for
system-level testing where a remote tester — such
as an in-circuit emulator — can exercise the
processor system.
The provided test logic does not interfere with
component or circuit board behavior and ensures
that components function correctly, connections
4
between various components are correct, and
various components interact correctly on the printed
circuit board.
The JTAG Boundary Scan feature is an attractive
alternative to conventional “bed-of-nails” testing. It
can examine connections which might otherwise be
inaccessible to a test system.
2.9
Memory-Mapped Control
Registers
The 80960JD, though compliant with i960 series
processor core, has the added advantage of
memory-mapped, internal control registers not found
on the i960 Kx, Sx or Cx processors. These give
software the interface to easily read and modify
internal control registers.
Each of these registers is accessed as a memorymapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The
processor ensures that these accesses do not
generate external bus cycles.
2.10 Data Types and Memory
Addressing Modes
As with all i960 family processors, the 80960Jx
instruction set supports several data types and
formats:
• Bit
• Bit fields
• Integer (8-, 16-, 32-, 64-bit)
• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
• Triple word (96 bits)
• Quad word (128 bits)
The 80960Jx provides a full set of addressing modes
for C and assembly programming:
• Two Absolute modes
• Five Register Indirect modes
• Index with displacement
• IP with displacement
PRELIMINARY
A
80960JD
Table 1. 80960Jx Instruction Set
Data Movement
Arithmetic
Logical
Bit, Bit Field and Byte
Load
Add
And
Set Bit
Store
Subtract
Not And
Clear Bit
Move
Multiply
And Not
Not Bit
*Conditional Select
Divide
Or
Alter Bit
Load Address
Remainder
Exclusive Or
Scan For Bit
Modulo
Not Or
Span Over Bit
Shift
Or Not
Extract
Extended Shift
Nor
Modify
Extended Multiply
Exclusive Nor
Scan Byte for Equal
Extended Divide
Not
*Byte Swap
Add with Carry
Nand
Subtract with Carry
*Conditional Add
*Conditional Subtract
Rotate
Comparison
Branch
Call/Return
Fault
Compare
Unconditional Branch
Call
Conditional Fault
Conditional Compare
Conditional Branch
Call Extended
Synchronize Faults
Compare and
Increment
Compare and Branch
Call System
Return
Compare and
Decrement
Branch and Link
Test Condition Code
Check Bit
Processor
Management
Debug
Atomic
Modify Trace Controls
Flush Local Registers
Atomic Add
Mark
Modify Arithmetic
Controls
Atomic Modify
Force Mark
Modify Process
Controls
*Halt
System Control
*Cache Control
*Interrupt Control
NOTE:
Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB implementations.
PRELIMINARY
5
A
80960JD
3.0
PACKAGE INFORMATION
The 80960JD is offered in several speed and
package types. The 132-pin Pin Grid Array (PGA)
device will be specified for operation at
Vcc = 5.0 V ± 5% over a case temperature range of
0° to 85°C:
• A80960JD-50 (50 MHz core, 25 MHz bus)
The 132-pin Pin Grid Array (PGA) device will be
specified for operation at Vc c = 5.0 V ± 5% over a
case temperature range of 0° to 100°C:
Table 2. Pin Description Nomenclature
Symbol
I
O
Pin can be either an input or output.
Pin must be connected as described.
S
Synchronous. Inputs must meet setup
and hold times relative to CLKIN for
proper operation.
S(E) Edge sensitive input
S(L) Level sensitive input
A (...)
R (...)
For complete package specifications and information, refer to Intel’s Packaging Handbook
(240800).
Section 3.1.1, Functional Pin Definitions
describes pin function; Section 3.1.2, 80960Jx 132Lead PGA Pinout and Section 3.1.3, 80960Jx
PQFP Pinout define the signal and pin locations for
the supported package types.
3.1.1
Functional Pin Definitions
While the processor’s RESET pin is
asserted, the pin:
R(1) is driven to VCC
R(0) is driven to VSS
R(Q) is a valid output
R(X) is driven to unknown state
R(H) is pulled up to VCC
Pin Descriptions
This section describes the pins for the 80960JD in
the 132-pin ceramic Pin Grid Array (PGA) package
and 132-lead Plastic Quad Flatpack Package
(PQFP).
Asynchronous. Inputs may be
asynchronous relative to CLKIN.
A(E) Edge sensitive input
A(L) Level sensitive input
• NG80960JD-40 (40 MHz core, 20 MHz bus)
3.1
Output pin only.
–
• A80960JD-40 (40 MHz core, 20 MHz bus)
• NG80960JD-33 (33.33 MHz core, 16.67 MHz bus)
Input pin only.
I/O
• A80960JD-33 (33.33 MHz core, 16.67 MHz bus)
The 132-pin Plastic Quad Flatpack (PQFP) devices
will be specified for operation at Vcc = 5.0 V ± 5%
over a case temperature range of 0° to 100°C:
Description
H (...)
While the processor is in the hold state,
the pin:
H(1) is driven to VCC
H(0) is driven to VSS
H(Q) Maintains previous state or
continues to be a valid output
H(Z) Floats
P (...)
While the processor is halted, the pin:
P(1) is driven to VCC
P(0) is driven to VSS
P(Q) Maintains previous state or
continues to be a valid output
Table 2 presents the legend for interpreting the pin
descriptions which follow. Pins associated with the
bus interface are described in Table 3. Pins
associated with basic control and test functions are
described in Table 4. Pins associated with the
Interrupt Unit are described in Table 5.
6
PRELIMINARY
A
80960JD
Table 3. Pin Description — External Bus Signals (Sheet 1 of 4)
NAME
AD31:0
TYPE
DESCRIPTION
I/O
S(L)
R(X)
H(Z)
P(Q)
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (Ta) cycle, bits 31:2 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, read or write
data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.
SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies the
number of data transfers during the bus transaction.
AD1
0
0
1
1
AD0
0
1
0
1
Bus Transfers
1 Transfer
2 Transfers
3 Transfers
4 Transfers
When the processor enters Halt mode, if the previous bus operation was a:
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are
driven with the value of A3:2 from the last data cycle.
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ALE
O
R(0)
H(Z)
P(0)
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a Ta cycle and deasserted before the beginning of the Td state. It is
active HIGH and floats to a high impedance state during a hold cycle (T h).
ALE
O
R(1)
H(Z)
P(1)
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the
inverted version of ALE. This signal gives the 80960JD a high degree of compatibility
with existing 80960Kx systems.
ADS
O
R(1)
H(Z)
P(1)
ADDRESS STROBE indicates a valid address and the start of a new bus access.
The processor asserts ADS for the entire Ta cycle. External bus control logic typically
samples ADS at the end of the cycle.
A3:2
O
R(X)
H(Z)
P(Q)
ADDRESS3:2 comprise a partial demultiplexed address bus.
32-bit memory accesses: the processor asserts address bits A3:2 during Ta. The
partial word address increments with each assertion of RDYRCV during a burst.
16-bit memory accesses: the processor asserts address bits A3:1 during Ta with A1
driven on the BE1 pin. The partial short word address increments with each assertion
of RDYRCV during a burst.
8-bit memory accesses: the processor asserts address bits A3:0 during Ta , with A1:0
driven on BE1:0. The partial byte address increments with each assertion of
RDYRCV during a burst.
PRELIMINARY
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Table 3. Pin Description — External Bus Signals (Sheet 2 of 4)
NAME
BE3:0
TYPE
O
R(1)
H(Z)
P(1)
DESCRIPTION
BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
32-bit bus:
BE3
BE2
BE1
BE0
enables data on AD31:24
enables data on AD23:16
enables data on AD15:8
enables data on AD7:0
16-bit bus:
BE3
BE2
BE1
BE0
becomes Byte High Enable (enables data on AD15:8)
is not used (state is high)
becomes Address Bit 1 (A1)
becomes Byte Low Enable (enables data on AD7:0)
8-bit bus:
BE3
BE2
BE1
BE0
is not used (state is high)
is not used (state is high)
becomes Address Bit 1 (A1)
becomes Address Bit 0 (A0)
The processor asserts byte enables, byte high enable and byte low enable during Ta.
Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last Td cycle.
For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A3:2 described above.
WIDTH/
HLTD1:0
O
R(0)
H(Z)
P(1)
WIDTH/HALTED signals denote the physical memory attributes for a bus transaction:
WIDTH/HLTD1
0
0
1
1
WIDTH/HLTD0
0
1
0
1
8 Bits Wide
16 Bits Wide
32 Bits Wide
Processor Halted
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.
D/C
W/R
8
O
R(X)
H(Z)
P(Q)
O
R(0)
H(Z)
P(Q)
DATA/CODE indicates that a bus access is a data access (1) or an instruction access
(0). D/C has the same timing as W/R.
0 = instruction access
1 = data access
WRITE/READ specifies, during a Ta cycle, whether the operation is a write (1) or read
(0). It is latched on-chip and remains valid during Td cycles.
0 = read
1 = write
PRELIMINARY
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80960JD
Table 3. Pin Description — External Bus Signals (Sheet 3 of 4)
NAME
DT/R
DEN
TYPE
DESCRIPTION
O
R(0)
H(Z)
P(Q)
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
address/data bus. It is low during Ta and Tw /Td cycles for a read; it is high during Ta
and Tw /Td cycles for a write. DT/R never changes state when DEN is asserted.
O
R(1)
H(Z)
P(1)
DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted
at the start of the first data cycle in a bus access and deasserted at the end of the last
data cycle. DEN is used with DT/R to provide control for data transceivers connected
to the data bus.
0 = receive
1 = transmit
0 = data cycle
1 = not data cycle
BLAST
O
R(1)
H(Z)
P(1)
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses. BLAST remains active as long as
wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final
data transfer in a bus cycle.
0 = last data transfer
1 = not last data transfer
RDYRCV
I
S(L)
READY/RECOVER indicates that data on AD lines can be sampled or removed. If
RDYRCV is not asserted during a Td cycle, the Td cycle is extended to the next cycle
by inserting a wait state (Tw).
0 = sample data
1 = don’t sample data
The RDYRCV pin has another function during the recovery (Tr) state. The processor
continues to insert additional recovery states until it samples the pin HIGH. This
function gives slow external devices more time to float their buffers before the
processor begins to drive address again.
0 = insert wait states
1 = recovery complete
LOCK/
ONCE
I/O
S(L)
R(H)
H(Z)
P(1)
BUS LOCK indicates that an atomic read-modify-write operation is in progress. The
LOCK output is asserted in the first clock of an atomic operation and deasserted in
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK. This prevents external agents from accessing memory involved in
semaphore operations.
0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress
ONCE MODE: The processor samples the ONCE input during reset. If it is asserted
LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the
processor stops all clocks and floats all output pins. The pin has a weak internal
pullup which is active during reset to ensure normal operation when the pin is left
unconnected.
0 = ONCE mode enabled
1 = ONCE mode not enabled
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Table 3. Pin Description — External Bus Signals (Sheet 4 of 4)
NAME
HOLD
TYPE
I
S(L)
DESCRIPTION
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the Th state. When
HOLD is deasserted, the processor deasserts HOLDA and enters either the Ti or Ta
state, resuming control of the address/data and control lines.
0 = no hold request
1 = hold request
HOLDA
BSTAT
O
R(Q)
H(1)
P(Q)
HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
relinquished control of the bus. The processor can grant HOLD requests and enter
the Th state during reset and while halted as well as during regular operation.
O
R(0)
H(Q)
P(0)
BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see i960 ® Jx Microprocessor User’s Guide (272483). Arbitration
logic can examine this signal to determine when an external bus master should
acquire/relinquish the bus.
0 = hold not acknowledged
1 = hold acknowledged
0 = no potential stall
1 = potential stall
Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 1 of 2)
TYPE
DESCRIPTION
CLKIN
NAME
I
CLOCK INPUT provides the processor’s fundamental time base; both the processor
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.
RESET
I
A(L)
RESET initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.
During reset, the input pins are ignored with the exception of LOCK/ONCE, STEST
and HOLD.
The RESET pin has an internal synchronizer. To ensure predictable processor initialization during power up, RESET must be asserted a minimum of 10,000 CLKIN
cycles with VCC and CLKIN stable. On a warm reset, RESET should be asserted for
a minimum of 15 cycles.
STEST
I
S(L)
SELF TEST enables or disables the processor’s internal self-test feature at initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.
0 = self test disabled
1 = self test enabled
10
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Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 2 of 2)
NAME
FAIL
TYPE
O
R(0)
H(Q)
P(1)
DESCRIPTION
FAIL indicates a failure of the processor’s built-in self-test performed during initialization. FAIL is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:
• When self-test passes, the processor deasserts FAIL and begins operation from
user code.
• When self-test fails, the processor asserts FAIL and then stops executing.
0 = self test failed
1 = self test passed
TCK
I
TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TDI
I
S(L)
TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising edge
of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
TDO
O
R(Q)
HQ)
P(Q)
TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. TDO does not float during ONCE mode.
TRST
I
A(L)
TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor between this pin and VSS. If TAP is not used, this
pin must be connected to VSS ; however, no resistor is required. See Section 4.3,
Connection Recommendations (pg. 24).
TMS
I
S(L)
TEST MODE SELECT is sampled at the rising edge of TCK to select the operation
of the test logic for IEEE 1149.1 Boundary Scan testing.
VCC
–
POWER pins intended for external connection to a VCC board plane.
VCCPLL
–
PLL POWER is a separate VCC supply pin for the phase lock loop clock generator. It
is intended for external connection to the VCC board plane. In noisy environments,
add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on
timing relationships.
VSS
–
GROUND pins intended for external connection to a VS S board plane.
NC
–
NO CONNECT pins. Do not make any system connections to these pins.
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Table 5. Pin Description — Interrupt Unit Signals
NAME
TYPE
XINT7:0
I
A(E/L)
DESCRIPTION
EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0
pins can be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs
can be programmed to be level (low) or edge (falling) sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins
are level sensitive in this mode.
Mixed Mode:
The XINT7:5 pins act as dedicated sources and the XINT4:0 pins
act as the five most significant bits of a vectored source. The least
significant bits of the vectored source are set to 0102 internally.
Unused external interrupt pins should be connected to VCC.
NMI
12
I
A(E)
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source and is falling edge-triggered. If NMI is
unused, it should be connected to VCC.
PRELIMINARY
A
3.1.2
80960JD
80960Jx 132-Lead PGA Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P
P
AD25
AD22 AD19
AD18 V CC
V CC
V CC
VCC
V CC
VCC
VCC
AD13 AD11
AD6
AD27
AD26 AD24
AD20
VSS
VSS
V SS
V SS
V SS
V SS
AD10 AD7
AD3
AD30
AD29
NC
AD23 AD21
AD17
AD16
AD12
AD9
BE2
BE3
VCC
N
N
VSS
M
M
AD15 AD14
AD8
AD4
AD0
AD28
AD5
AD1
V CC
VSS
AD31
AD2
V SS
V CC
VCC
VSS
BE1
NC
V SS
V CC
VCC
VSS
BE0
VCC
V SS
ALE
VCC
V SS BSTAT
VCC
V SS
DEN
VCC
VSS
DT/R
L
L
K
K
J
J
H
H
VCCPLL V SS
CLKIN
G
G
NC
V SS
V CC
RDYRCV V SS
V CC
RESET V SS
V CC
V SS
V CC
F
F
E
E
D
D
TDI
C
C
LOCK/ HOLDA BLAST
ONCE
A3
A2
FAIL
NC
NC
TDO
NC
VSS
V SS
VSS
NC
NC
VCC
VCC
V CC
4
5
6
7
8
HOLD XINT1 XINT0 TRST STEST
NC
B
B
W/R
D/C
WIDTH/
HLTD0
XINT6 XINT4 XINT3 TCK
NC
V CC
NMI
TMS
9
10
V SS
A
A
ADS
1
WIDTH/ ALE
HLTD1
2
3
XINT7 XINT5 XINT2
11
12
13
14
Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing Up
PRELIMINARY
13
A
80960JD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
TMS
NC
NC
VCC
VCC
V CC
VCC
CLKIN
V CC
V CC
V CC
AD0
AD3
AD6
XINT2
TCK
STEST
V SS
V SS
V SS
V SS
V SS
VSS
V SS
AD1
AD4
AD7
AD11
XINT5
XINT3 TRST
TDI
V CCPLL
NC
AD2
AD5
AD8
AD10
AD13
XINT7
XINT4 XINT0
AD9
V SS
V CC
NMI
XINT6 XINT1
AD12
V SS
V CC
AD14
V SS
V CC
AD15
VSS
V CC
AD16
VSS
VCC
AD17
V SS
VCC
14
14
13
13
12
12
RESET RDYRCV NC
11
11
10
10
9
9
V CC
V SS
HOLD
V CC
V SS
NC
V CC
V SS
NC
V CC
V SS
FAIL
NC
NC
A2
AD21
VSS
V CC
NC
TDO
A3
AD23
AD20
AD18
A80960JD
i
8
7
6
8
M
7
© 19xx
6
XXXXXXXX A2
5
5
4
4
3
3
ALE
WIDTH/ BLAST DT/R
HLTD0
DEN
BSTAT
ALE
BE0
BE1
AD31
AD28
NC
AD24 AD19
2
2
WIDTH/ D/C
HLTD1
HOLDA
VSS
V SS
V SS
V SS
V SS
V SS
V SS
BE3
AD29
AD26 AD22
VCC
VCC
V CC
V CC
VCC
BE2
AD30
AD27
AD25
L
M
N
P
1
1
ADS
W/R
LOCK/
ONCE
VCC
V CC
A
B
C
D
E
F
G
H
J
K
Figure 4. 132-Lead Pin Grid Array Top View - Pins Facing Down
14
PRELIMINARY
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80960JD
Table 6. 132-Lead PGA Pinout — In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
B9
A2
C5
AD31
K3
TDI
D12
VSS
A3
C4
ADS
A1
TDO
B4
VSS
D2
AD0
M14
ALE
G3
TMS
A14
VSS
D13
AD1
L13
ALE
A3
TRST
C12
VSS
E2
AD2
K12
BE0
H3
VCC
A6
VSS
E13
AD3
N14
BE1
J3
VCC
A7
VSS
F2
AD4
M13
BE2
L1
VCC
A8
VSS
F13
AD5
L12
BE3
L2
VCC
A9
VSS
G2
AD6
P14
BLAST
C3
VCC
D1
VSS
G13
AD7
N13
BSTAT
F3
VCC
D14
VSS
H2
AD8
M12
CLKIN
H14
VCC
E1
VSS
H13
AD9
M11
D/C
B2
VCC
E14
VSS
J2
AD10
N12
DEN
E3
VCC
F1
VSS
J13
AD11
P13
DT/R
D3
VCC
F14
VSS
K2
AD12
M10
FAIL
C6
VCC
G1
VSS
K13
AD13
P12
HOLD
C9
VCC
G14
VSS
N5
AD14
M9
HOLDA
C2
VCC
H1
VSS
N6
AD15
M8
LOCK/ONCE
C1
VCC
J1
VSS
N7
AD16
M7
NC
A4
VCC
J14
VSS
N8
AD17
M6
NC
A5
VCC
K1
VSS
N9
AD18
P4
NC
B5
VCC
K14
VSS
N10
AD19
P3
NC
B14
VCC
L14
VSS
N11
AD20
N4
NC
C7
VCC
P5
W/R
B1
AD21
M5
NC
C8
VCC
P6
WIDTH/HLTD0
B3
AD22
P2
NC
C14
VCC
P7
WIDTH/HLTD1
A2
AD23
M4
NC
G12
VCC
P8
XINT0
C11
AD24
N3
NC
J12
VCC
P9
XINT1
C10
AD25
P1
NC
M3
VCC
P10
XINT2
A13
AD26
N2
NMI
A10
VCC
P11
XINT3
B12
AD27
N1
RDYRCV
F12
VCCPLL
H12
XINT4
B11
AD28
L3
RESET
E12
VSS
B6
XINT5
A12
AD29
M2
STEST
C13
VSS
B7
XINT6
B10
AD30
M1
TCK
B13
VSS
B8
XINT7
A11
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
PRELIMINARY
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80960JD
Table 7. 132-Lead PGA Pinout — In Pin Order
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
A1
ADS
C6
FAIL
H1
VCC
M10
AD12
A2
WIDTH/HLTD1
C7
NC
H2
VSS
M11
AD9
A3
ALE
C8
NC
H3
BE0
M12
AD8
A4
NC
C9
HOLD
H12
VCCPLL
M13
AD4
A5
NC
C10
XINT1
H13
VSS
M14
AD0
A6
VCC
C11
XINT0
H14
CLKIN
N1
AD27
A7
VCC
C12
TRST
J1
VCC
N2
AD26
A8
VCC
C13
STEST
J2
VSS
N3
AD24
AD20
A9
VCC
C14
NC
J3
BE1
N4
A10
NMI
D1
VCC
J12
NC
N5
VSS
A11
XINT7
D2
VS S
J13
VSS
N6
VSS
A12
XINT5
D3
DT/R
J14
VCC
N7
VSS
A13
XINT2
D12
TDI
K1
VCC
N8
VSS
A14
TMS
D13
VS S
K2
VSS
N9
VSS
B1
W/R
D14
VCC
K3
AD31
N10
VSS
B2
D/C
E1
VCC
K12
AD2
N11
VSS
B3
WIDTH/HLTD0
E2
VS S
K13
VSS
N12
AD10
B4
TDO
E3
DEN
K14
VCC
N13
AD7
B5
NC
E12
RESET
L1
BE2
N14
AD3
B6
VSS
E13
VS S
L2
BE3
P1
AD25
B7
VSS
E14
VCC
L3
AD28
P2
AD22
B8
VSS
F1
VCC
L12
AD5
P3
AD19
B9
VSS
F2
VS S
L13
AD1
P4
AD18
B10
XINT6
F3
BSTAT
L14
VCC
P5
VCC
B11
XINT4
F12
RDYRCV
M1
AD30
P6
VCC
B12
XINT3
F13
VS S
M2
AD29
P7
VCC
B13
TCK
F14
VCC
M3
NC
P8
VCC
B14
NC
G1
VCC
M4
AD23
P9
VCC
C1
LOCK/ONCE
G2
VS S
M5
AD21
P10
VCC
C2
HOLDA
G3
ALE
M6
AD17
P11
VCC
C3
BLAST
G12
NC
M7
AD16
P12
AD13
C4
A3
G13
VS S
M8
AD15
P13
AD11
C5
A2
G14
VCC
M9
AD14
P14
AD6
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
16
PRELIMINARY
A
3.1.3
80960JD
80960Jx PQFP Pinout
100
101
103
102
AD8
AD7
AD6
AD5
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
AD4
VCC (I/O)
VSS (I/O)
AD3
AD2
AD1
AD0
VCC (I/O)
V SS (I/O)
V CC (Core)
VSS (Core)
V (Core)
CC
VSS (Core)
CLKIN
V SS (CLK)
VCCPLL
V CC (CLK)
NC
NC
124
125
126
127
128
129
A3
130
V CC (I/O)
VSS(I/O)
WIDTH/HLTD1
V CC(Core)
V SS (Core)
WIDTH/HLTD0
A2
131
NC
NC
NC
FAIL
ALE
TDO
132
VCC (Core)
V SS (Core)
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V CC (Core)
VSS (Core)
RESET
NC
NC
STEST
V CC (I/O)
TDI
V SS(I/O)
RDYRCV
TRST
TCK
TMS
HOLD
XINT0
XINT1
XINT2
XINT3
V CC (I/O)
VSS (I/O)
XINT4
XINT5
XINT6
XINT7
NMI
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
A
i960
i
23
24
25
26
27
28
29
30
31
32
33
®
NG80960JX
XXXXXXXX A2
M
© 19xx
70
69
68
67
AD9
V CC (I/O)
V SS (I/O)
AD10
AD11
V CC (I/O)
V SS (I/O)
V CC (Core)
V SS (Core)
AD12
AD13
AD14
AD15
V CC (I/O)
V SS (I/O)
AD16
AD17
AD18
AD19
V CC (I/O)
V SS (I/O)
AD20
AD21
AD22
AD23
V CC (Core)
V SS (Core)
V CC (I/O)
V SS (I/O)
AD24
AD25
AD26
NC
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
AD27
VCC (I/O)
VSS (I/O)
AD28
AD29
AD30
AD31
VCC (Core)
VSS (Core)
VCC (I/O)
VSS (I/O)
BE3
BE2
BE1
BE0
BSTAT
LOCK/ONCE
VCC (I/O)
VSS (I/O)
VCC (Core)
VSS (Core)
ALE
HOLDA
DEN
DT/R
VCC (I/O)
VSS (I/O)
VCC (Core)
VSS (Core)
W/R
ADS
D/C
BLAST
Figure 5. 132-Lead PQFP - Top View
PRELIMINARY
17
A
80960JD
Table 8. 132-Lead PQFP Pinout — In Signal Order
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
10
AD31
60
ALE
24
VCC (Core)
47
VSS (I/O)
AD30
61
ADS
36
VCC (Core)
59
VSS (I/O)
27
AD29
62
A3
33
VCC (Core)
74
VSS (I/O)
40
AD28
63
A2
32
VCC (Core)
92
VSS (I/O)
48
AD27
66
BE3
55
VCC (Core)
113
VSS (I/O)
56
AD26
68
BE2
54
VCC (Core)
115
VSS (I/O)
64
AD25
69
BE1
53
VCC (Core)
123
VSS (I/O)
71
AD24
70
BE0
52
VCC (I/O)
9
VSS (I/O)
79
AD23
75
WIDTH/HLTD1
28
VCC (I/O)
26
VSS (I/O)
85
AD22
76
WIDTH/HLTD0
31
VCC (I/O)
41
VSS (I/O)
93
AD21
77
D/C
35
VCC (I/O)
49
VSS (I/O)
97
AD20
78
W/R
37
VCC (I/O)
57
VSS (I/O)
106
AD19
81
DT/R
42
VCC (I/O)
65
VSS (I/O)
112
AD18
82
DEN
43
VCC (I/O)
72
VSS (I/O)
131
AD17
83
BLAST
34
VCC (I/O)
80
NC
18
AD16
84
RDYRCV
132
VCC (I/O)
86
NC
19
AD15
87
LOCK/ONCE
50
VCC (I/O)
94
NC
20
AD14
88
HOLD
4
VCC (I/O)
98
NC
21
AD13
89
HOLDA
44
VCC (I/O)
105
NC
22
AD12
90
BSTAT
51
VCC (I/O)
111
NC
67
AD11
95
CLKIN
117
VCC (I/O)
129
NC
121
AD10
96
RESET
125
VCCPLL
119
NC
122
AD9
99
STEST
128
VSS (CLK)
118
NC
126
AD8
100
FAIL
23
VSS (Core)
17
NC
127
AD7
101
TCK
2
VSS (Core)
30
XINT7
14
AD6
102
TDI
130
VSS (Core)
38
XINT6
13
AD5
103
TDO
25
VSS (Core)
46
XINT5
12
AD4
104
TRST
1
VSS (Core)
58
XINT4
11
AD3
107
TMS
3
VSS (Core)
73
XINT3
8
AD2
108
VCC (CLK)
120
VSS (Core)
91
XINT2
7
AD1
109
VCC (Core)
16
VSS (Core)
114
XINT1
6
AD0
110
VCC (Core)
29
VSS (Core)
116
XINT0
5
ALE
45
VCC (Core)
39
VSS (Core)
124
NMI
15
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
18
PRELIMINARY
A
80960JD
Table 9. 132-Lead PQFP Pinout — In Pin Order
Pin
Signal
Pin
Signal
Pin
1
2
Signal
Pin
Signal
TRST
34
BLAST
67
NC
100
AD8
TCK
35
D/C
68
AD26
101
AD7
3
TMS
36
ADS
69
AD25
102
AD6
4
HOLD
37
W/R
70
AD24
103
AD5
5
XINT0
38
VSS (Core)
71
VSS (I/O)
104
AD4
6
XINT1
39
VCC (Core)
72
VCC (I/O)
105
VCC (I/O)
7
XINT2
40
VSS (I/O)
73
VSS (Core)
106
VSS (I/O)
8
XINT3
41
VCC (I/O)
74
VCC (Core)
107
AD3
9
VCC (I/O)
42
DT/R
75
AD23
108
AD2
10
VSS (I/O)
43
DEN
76
AD22
109
AD1
11
XINT4
44
HOLDA
77
AD21
110
AD0
12
XINT5
45
ALE
78
AD20
111
VCC (I/O)
13
XINT6
46
VSS (Core)
79
VSS (I/O)
112
VSS (I/O)
14
XINT7
47
VCC (Core)
80
VCC (I/O)
113
VCC (Core)
15
NMI
48
VSS (I/O)
81
AD19
114
VSS (Core)
16
VCC (Core)
49
VCC (I/O)
82
AD18
115
VCC (Core)
17
VSS (Core)
50
LOCK/ONCE
83
AD17
116
VSS (Core)
18
NC
51
BSTAT
84
AD16
117
CLKIN
19
NC
52
BE0
85
VSS (I/O)
118
VSS (CLK)
20
NC
53
BE1
86
VCC (I/O)
119
VCCPLL
21
NC
54
BE2
87
AD15
120
VCC (CLK)
22
NC
55
BE3
88
AD14
121
NC
23
FAIL
56
VSS (I/O)
89
AD13
122
NC
24
ALE
57
VCC (I/O)
90
AD12
123
VCC (Core)
25
TDO
58
VSS (Core)
91
VSS (Core)
124
VSS (Core)
26
VCC (I/O)
59
VCC (Core)
92
VCC (Core)
125
RESET
27
VSS (I/O)
60
AD31
93
VSS (I/O)
126
NC
28
WIDTH/HLTD1
61
AD30
94
VCC (I/O)
127
NC
29
VCC (Core)
62
AD29
95
AD11
128
STEST
30
VSS (Core)
63
AD28
96
AD10
129
VCC (I/O)
31
WIDTH/HLTD0
64
VSS (I/O)
97
VSS (I/O)
130
TDI
32
A2
65
VCC (I/O)
98
VCC (I/O)
131
VSS (I/O)
33
A3
66
AD27
99
AD9
132
RDYRCV
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
PRELIMINARY
19
A
80960JD
3.2
Package Thermal Specifications
The 80960JD is specified for operation when T C
(case temperature) is within the range of 0°C to 85°C
for the (PGA) 80960JD-50, or 0°C to 100°C for the
(PQFP and PGA) 80960JD-40 and 80960JD-33.
Case temperature may be measured in any
environment to determine whether the 80960JD is
within specified operating range. The case temperature should be measured at the center of the top
surface, opposite the pins.
θCA is the thermal resistance from case to ambient.
Use the following equation to calculate TA, the
maximum ambient temperature to conform to a
particular case temperature:
TA = TC - P (θCA)
Junction temperature (TJ) is commonly used in
reliability calculations. TJ can be calculated from θJC
(thermal resistance from junction to case) using the
following equation:
TJ = TC + P (θJC )
Similarly, if TA is known, the corresponding case
temperature (TC ) can be calculated as follows:
TC = TA + P (θCA)
Compute P by multiplying ICC from Table 14 and
VCC . Values for θJC and θCA are given in Table 10 for
the PGA package and Table 11 for the PQFP
package. For high speed operation, the processor’s
θJA may be significantly reduced by adding a
heatsink and/or by increasing airflow.
Figure 6 shows the maximum ambient temperature
(TA) permitted without exceeding TC for the
80960JD-50 in a PGA package. Figure 7 illustrates
this for the 80960JD-40 in PGA and PQFP
packages. The curves are based on minimum ICC
(hot) and maximum VCC of +5.25 V, with a T CASE of
+85°C for the 80960JD-50, or a TCASE of +100°C for
the 80960JD-40.
Table 10. 132-Lead PGA Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
(0)
θJC (Junction-to-Case)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
1000
(5.08)
3
3
3
3
3
3
θCA (Case-to-Ambient) (No Heatsink)
18
15
12
11
11
11
θCA (Case-to-Ambient) (Omnidirectional Heatsink)
15
12
9
8
8
8
θCA (Case-to-Ambient) (Unidirectional Heatsink)
14
11
8
7
7
7
θJA
θCA
θJC
θJ-PIN
θJ-CAP
NOTES:
1.
2.
3.
4.
5.
20
This table applies to a PGA device plugged into a socket or soldered directly into a board.
θJA = θJC + θCA
θJ-CAP = 4°C/W (approx.)
θJ-PIN = 4°C/W (inner pins) (approx.)
θJ-PIN = 8°C/W (outer pins) (approx.)
PRELIMINARY
A
80960JD
Table 11. 132-Lead PQFP Package Thermal Characteristics
Thermal Resistance — °C/Watt
Airflow — ft./min (m/sec)
Parameter
0
(0)
θJC (Junction-to-Case)
θCA (Case-to-Ambient -No Heatsink)
50
(0.25)
100
(0.50)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
6
7
7
7
7
7
7
23
20
18
14
10
9
8
θJA
θCA
θJC
θJB
θJL
NOTES:
1.
2.
3.
4.
This table applies to a PQFP device soldered directly into board.
θJA = θJC + θCA
θJL = 18°C/W (approx.)
θJB = 18°C/W (approx.)
65
60
TEMPERATURE (oC)
55
50
45
40
35
30
0
100
PGA with no heatsink
200
300
400
500
AIRFLOW (ft/min)
PGA with omnidirectional heatsink
600
700
800
PGA with unidirectional heatsink
Figure 6. 50 MHz Maximum Allowable Ambient Temperature
PRELIMINARY
21
A
80960JD
85
80
TEMPERATURE (oC)
75
70
65
60
55
50
45
40
0
PQFP
50
100
PGA with no heatsink
200
300
400
AIRFLOW (ft/min)
500
PGA with omnidirectional heatsink
600
700
800
PGA with unidirectional heatsink
Figure 7. 40 MHz Maximum Allowable Ambient Temperature
3.3
Thermal Management
Accessories
The following is a list of suggested sources for
80960JD thermal solutions. This is neither an
endorsement or a warranty of the performance of
any of the listed products and/or companies.
2. Wakefield Engineering
60 Audubon Road
Wakefield, MA 01880
(617) 245-5900
3. Aavid Thermal Technologies, Inc.
One Kool Path
Laconia, NH 03247-0400
(603) 528-3400
Heatsinks
1. Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993
(214) 243-4321 FAX: (214) 241-4656
22
PRELIMINARY
A
80960JD
4.0
ELECTRICAL SPECIFICATIONS
4.1
Absolute Maximum Ratings
Parameter
Maximum Rating
Storage Temperature .............................. –65° C to +150° C
Case Temperature Under Bias ............... –65° C to +110° C
Supply Voltage wrt. V SS .............................. –0.5V to + 4.6V
Voltage on Other Pins wrt. V SS ........... –0.5V to V CC + 0.5V
4.2
NOTICE: This data sheet contains preliminary information
on new products in production. The specifications are
subject to change without notice.
WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only. Operation
beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
Operating Conditions
Table 12. 80960JD Operating Conditions
Symbol
VCC
Parameter
Min
Max
Units
4.75
4.75
4.75
5.25
5.25
5.25
V
8
8
8
25
20
16.67
MHz
A80960JD-50 (132 PGA)
A80960JD-40 (132 PGA)
A80960JD-33 (132 PGA)
0
0
0
85
100
100
°C
NG80960JD-40 (132 PQFP)
NG80960JD-33 (132 PQFP)
0
0
100
100
Supply Voltage
80960JD-50
80960JD-40
80960JD-33
fCLKIN
Input Clock Frequency
80960JD-50
80960JD-40
80960JD-33
TC
Notes
Operating Case Temperature
PRELIMINARY
23
A
80960JD
4.3
Connection Recommendations
For clean on-chip power distribution, VCC and VSS
pins separately feed the device’s functional units.
Power and ground connections must be made to all
80960JD power and ground pins. On the circuit
board, every VCC pin should connect to a power
plane and every VSS pin should connect to a ground
plane. Place liberal decoupling capacitance near the
80960JD, since the processor can cause transient
power surges.
4.4
Pay special attention to the Test Reset (TRST) pin. It
is essential that the JTAG Boundary Scan Test
Access Port (TAP) controller initializes to a known
state whether it will be used or not. If the JTAG
Boundary Scan function will be used, connect a
pulldown resistor between the TRST pin and VS S. If
the JTAG Boundary Scan function will not be used
(even for board-level testing), connect the TRST pin
to VSS. Also, do not connect the TDI, TDO, and TCK
pins if the TAP Controller will not be used.
Pins identified as NC must not be connected in
the system.
DC Specifications
Table 13. 80960JD DC Characteristics
Max
Units
VIL
Symbol
Input Low Voltage
Parameter
-0.3
0.8
V
2.0
VCC + 0.3
V
0.45
V
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Min
Typ
V
2.4
VOLP
Output Ground Bounce
CIN
Input Capacitance
PGA
PQFP
12
10
pF
I/O or Output Capacitance
PGA
PQFP
12
10
pF
CLKIN Capacitance
PGA
PQFP
12
10
pF
CCLK
IOL = 5 mA
IOH = -1 mA
IOH = -200 µA
VCC - 0.5
COUT
Notes
< 0.8
V
(1,2)
fCLKIN = fMIN (2)
fCLKIN = fMIN (2)
fCLKIN = fMIN (2)
NOTES:
1. Typical is measured with VCC = 5.0V and temperature = 25 °C.
2. Not tested.
24
PRELIMINARY
A
80960JD
Table 14. 80960JD ICC Characteristics
Symbol
Parameter
Max
Units
±1
µA
0 ≤ VIN ≤ VCC
-250
µA
VIN = 0.45V (1)
±1
µA
0.4 ≤ VOUT ≤ VCC
80960JD-50
640
mA
(2,3)
80960JD-40
530
80960JD-33
450
ILI1
Input Leakage Current for
each pin except TCK, TDI,
TRST and TMS
ILI2
Input Leakage Current for
TCK, TDI, TRST and TMS
ILO
Output Leakage Current
ICC Active
(Power Supply)
ICC Active
(Thermal)
ICC Test
(Power modes)
Typ
-140
Notes
(2,3)
(2,3)
80960JD-50
525
80960JD-40
430
(2,4)
80960JD-33
365
(2,4)
mA
(2,4)
Reset mode
80960JD-50
510
80960JD-40
430
(5)
80960JD-33
370
(5)
80960JD-50
48
(5)
80960JD-40
41
(5)
80960JD-33
36
(5)
10
(5)
mA
(5)
Halt mode
ONCE mode
NOTES:
1. These pins have internal pullup devices. Typical leakage current is not tested.
2. Measured with device operating and outputs loaded to the test condition in Figure 8, AC Test Load (pg.
33).
3. ICC Active (Power Supply) value is provided for selecting your system’s power supply. It is measured
using one of the worst case instruction mixes with VCC = 5.25V. This parameter is characterized but not
tested.
4. I CC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured
with VCC = 5.0V and temperature = 25° C. This parameter is characterized but not tested.
5. I CC Test (Power modes) refers to the ICC values that are tested when the 80960JD is in Reset mode,
Halt mode or ONCE mode with VCC = 5.25V.
PRELIMINARY
25
A
80960JD
4.5
AC Specifications
The 80960JD AC timings are based upon device characterization.
Table 15. 80960JD AC Characteristics (50 MHz) (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
Notes
INPUT CLOCK TIMINGS
TF
CLKIN Frequency
TC
CLKIN Period
8
25
MHz
40
125
ns
± 250
ps
(1, 2)
ns
Measured at 1.5 V (1)
TCS
CLKIN Period Stability
TCH
CLKIN High Time
16
TCL
CLKIN Low Time
16
TCR
CLKIN Rise Time
TCF
CLKIN Fall Time
ns
Measured at 1.5 V (1)
25
ns
0.8 V to 2.0 V (1)
5
ns
2.0 V to 0.8 V (1)
(3)
SYNCHRONOUS OUTPUT TIMINGS
TOV1
Output Valid Delay, Except
ALE/ALE Inactive and DT/R
TOV2
Output Valid Delay, DT/R
TOF
Output Float Delay
3.5
17
ns
0.5TC + 3.5
0.5TC + 17
ns
3.5
15
ns
(4)
SYNCHRONOUS INPUT TIMINGS
TIS1
Input Setup to CLKIN —
AD31:0, NMI, XINT7:0
8
ns
(5)
TIH1
Input Hold from CLKIN —
AD31:0, NMI, XINT7:0
2
ns
(5)
TIS2
Input Setup to CLKIN —
RDYRCV and HOLD
9
ns
(6)
TIH2
Input Hold from CLKIN —
RDYRCV and HOLD
1
ns
(6)
TIS3
Input Setup to CLKIN —
RESET
8
ns
(7)
TIH3
Input Hold from CLKIN —
RESET
2
ns
(7)
TIS4
Input Setup to RESET —
ONCE, STEST
8
ns
(8)
TIH4
Input Hold from RESET —
ONCE, STEST
2
ns
(8)
NOTE:
26
See Table 16 on page 28 for note definitions for this table.
PRELIMINARY
A
80960JD
Table 15. 80960JD AC Characteristics (50 MHz) (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
Notes
RELATIVE OUTPUT TIMINGS
(9)
TLXL
ALE/ALE Width
TLXA
Address Hold from ALE/ALE
Inactive
TDXD
DT/R Valid to DEN Active
0.5TC - 7.5
ns
Equal Loading (9)
Equal Loading (9)
BOUNDARY SCAN TEST SIGNAL TIMINGS
TBSF
TCK Frequency
TBSCH
TCK High Time
15
0.5T F
TBSCL
TCK Low Time
15
TBSCR
TCK Rise Time
MHz
ns
Measured at 1.5 V (1)
ns
Measured at 1.5 V (1)
5
ns
0.8 V to 2.0 V (1)
5
ns
2.0 V to 0.8 V (1)
TBSCF
TCK Fall Time
TBSIS1
Input Setup to TCK — TDI, TMS
4
ns
TBSIH1
Input Hold from TCK — TDI,
TMS
6
ns
TBSOV1
TDO Valid Delay
3
TBSOF1
TDO Float Delay
3
30
ns
(1,10)
TBSOV2
All Outputs (Non-Test) Valid
Delay
3
30
ns
(1,10)
TBSOF2
All Outputs (Non-Test) Float
Delay
3
30
ns
(1,10)
TBSIS2
Input Setup to TCK — All Inputs
(Non-Test)
4
ns
TBSIH2
Input Hold from TCK — All
Inputs (Non-Test)
6
ns
NOTE:
30
ns
(1,10)
See Table 16 on page 28 for note definitions for this table.
PRELIMINARY
27
A
80960JD
Table 16. Note Definitions for Table 15, 80960JD AC Characteristics (50 MHz) (pg. 26)
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 1 of 3)
Symbol
Parameter
Min
Max
Units
20
MHz
Notes
INPUT CLOCK TIMINGS
TF
CLKIN Frequency
8
TC
CLKIN Period
TCS
CLKIN Period Stability
50
TCH
CLKIN High Time
TCL
CLKIN Low Time
TCR
CLKIN Rise Time
TCF
CLKIN Fall Time
TOV1
Output Valid Delay, Except ALE/ALE
Inactive and DT/R
125
ns
±250
ps
(1, 2)
20
ns
Measured at
1.5 V (1)
20
ns
Measured at
1.5 V (1)
7
ns
0.8 V to 2.0
V (1)
7
ns
2.0 V to 0.8
V (1)
18
ns
(3)
SYNCHRONOUS OUTPUT TIMINGS
28
3.5
PRELIMINARY
A
80960JD
Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 2 of 3)
Symbol
Parameter
Min
Max
Units
Notes
0.5TC + 3.5
0.5T C + 18
ns
3.5
16
ns
(4)
TOV2
Output Valid Delay, DT/R
TO F
Output Float Delay
TIS1
Input Setup to CLKIN — AD31:0, NMI,
XINT7:0
8
ns
(5)
TIH1
Input Hold from CLKIN — AD31:0, NMI,
XINT7:0
2
ns
(5)
TIS2
Input Setup to CLKIN — RDYRCV and
HOLD
9
ns
(6)
TIH2
Input Hold from CLKIN — RDYRCV and
HOLD
1
ns
(6)
TIS3
Input Setup to CLKIN — RESET
8
ns
(7)
TIH3
Input Hold from CLKIN — RESET
2
ns
(7)
TIS4
Input Setup to RESET — ONCE, STEST
8
ns
(8 )
TIH4
Input Hold from RESET — ONCE,
STEST
2
ns
(8)
TLXL
ALE/ALE Width
TLXA
Address Hold from ALE/ALE Inactive
TDXD
DT/R Valid to DEN Active
SYNCHRONOUS INPUT TIMINGS
RELATIVE OUTPUT TIMINGS
(9)
0.5TC - 7.5
ns
Equal
Loading (9)
Equal
Loading (9)
BOUNDARY SCAN TEST SIGNAL TIMINGS
TBSF
TCK Frequency
TBSCH
TCK High Time
15
ns
Measured at
1.5 V (1)
TBSCL
TCK Low Time
15
ns
Measured at
1.5 V (1)
TBSCR
TCK Rise Time
5
ns
0.8 V to 2.0
V (1)
TBSCF
TCK Fall Time
5
ns
2.0 V to 0.8
V (1)
TBSIS1
Input Setup to TCK — TDI, TMS
4
TBSIH1
Input Hold from TCK — TDI, TMS
6
TBSOV1
TDO Valid Delay
3
30
ns
(1, 10)
TBSOF1
TDO Float Delay
3
30
ns
(1, 10)
PRELIMINARY
0.5TF
MHz
ns
ns
29
A
80960JD
Table 17. 80960JD AC Characteristics (40 MHz) (Sheet 3 of 3)
Symbol
Parameter
Min
Max
Units
Notes
TBSOV2
All Outputs (Non-Test) Valid Delay
3
30
ns
(1, 10)
TBSOF2
All Outputs (Non-Test) Float Delay
3
30
ns
(1, 10)
TBSIS2
Input Setup to TCK — All Inputs (NonTest)
4
ns
TBSIH2
Input Hold from TCK — All Inputs (NonTest)
6
ns
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
30
PRELIMINARY
A
80960JD
Table 18. 80960JD AC Characteristics (33 MHz) (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
Notes
INPUT CLOCK TIMINGS
TF
CLKIN Frequency
8
16.67
MHz
TC
CLKIN Period
60
TCS
CLKIN Period Stability
TCH
CLKIN High Time
TCL
CLKIN Low Time
TCR
CLKIN Rise Time
8
ns
0.8 V to 2.0 V (1)
TCF
CLKIN Fall Time
8
ns
2.0 V to 0.8 V (1)
TOV1
Output Valid Delay, Except
ALE/ALE Inactive and DT/R
(3)
TOV2
Output Valid Delay, DT/R
TO F
Output Float Delay
TIS1
Input Setup to CLKIN — AD31:0,
NMI, XINT7:0
TIH1
125
ns
± 250
ps
(1, 2)
24
ns
Measured at 1.5 V (1)
24
ns
Measured at 1.5 V (1)
SYNCHRONOUS OUTPUT TIMINGS
3.5
19
ns
0.5TC +
3.5
0.5T C + 19
ns
3.5
18
ns
(4)
8
ns
(5)
Input Hold from CLKIN — AD31:0,
NMI, XINT7:0
2
ns
(5)
TIS2
Input Setup to CLKIN — RDYRCV
and HOLD
9
ns
(6)
TIH2
Input Hold from CLKIN —
RDYRCV and HOLD
1
ns
(6)
TIS3
Input Setup to CLKIN — RESET
8
ns
(7)
TIH3
Input Hold from CLKIN — RESET
2
ns
(7)
TIS4
Input Setup to RESET — ONCE,
STEST
8
ns
(8)
TIH4
Input Hold from RESET — ONCE,
STEST
2
ns
(8)
TLXL
ALE/ALE Width
TLXA
Address Hold from ALE/ALE Inactive
TDXD
DT/R Valid to DEN Active
SYNCHRONOUS INPUT TIMINGS
RELATIVE OUTPUT TIMINGS
PRELIMINARY
(9)
0.5TC - 8
ns
Equal Loading (9)
Equal Loading (9)
31
A
80960JD
Table 18. 80960JD AC Characteristics (33 MHz) (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
Notes
BOUNDARY SCAN TEST SIGNAL TIMINGS
TBSF
TCK Frequency
0.5TF
MHz
TBSCH
TCK High Time
15
ns
Measured at 1.5 V (1)
TBSCL
TCK Low Time
15
ns
Measured at 1.5 V (1)
TBSCR
TCK Rise Time
5
ns
0.8 V to 2.0 V (1)
TBSCF
TCK Fall Time
5
ns
2.0 V to 0.8 V (1)
TBSIS1
Input Setup to TCK — TDI, TMS
4
ns
TBSIH1
Input Hold from TCK — TDI, TMS
6
ns
TBSOV1
TDO Valid Delay
3
30
ns
(1, 10)
TBSOF1
TDO Float Delay
3
30
ns
(1, 10)
TBSOV2
All Outputs (Non-Test) Valid Delay
3
30
ns
(1, 10)
TBSOF2
All Outputs (Non-Test) Float Delay
3
30
ns
(1, 10)
TBSIS2
Input Setup to TCK — All Inputs
(Non-Test)
4
ns
TBSIH2
Input Hold from TCK — All Inputs
(Non-Test)
6
ns
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at
a particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
32
PRELIMINARY
A
4.5.1
80960JD
AC Test Conditions and Derating Curves
The AC Specifications in Section 4.5, AC Specifications are tested with the 50 pF load indicated in Figure 8.
Figure 9 shows how timings vary with load capacitance; Figure 10 shows how output rise and fall times vary
with load capacitance.
Output Pin
CL
CL = 50 pF for all signals
Figure 8. AC Test Load
AC Derating Curves
Output Valid Delay (ns) @ 1.5V
nom +6
nom +4
nom +2
nom
High-to-Low Transitions
Low-to-High Transitions
nom -2
50
100
150
C L (pF)
Figure 9. Output Delay or Hold vs. Load Capacitance
PRELIMINARY
33
A
80960JD
10
2.0V to 0.8V Transitions
Time (ns)
8
0.8V to 2.0V Transitions
6
4
2
50
100
150
CL (pF)
Figure 10. Rise and Fall Time Derating
4.5.2
AC Timing Waveforms
TCR
TCF
2.0V
1.5V
0.8V
TCH
TCL
TC
Figure 11. CLKIN Waveform
34
PRELIMINARY
A
80960JD
1.5V
CLKIN
1.5V
TOV1
AD31:0,
ALE (active),
ALE (active),
ADS, A3:2,
BE3:0,
WIDTH/HLTD1:0,
D/C, W/R, DEN,
BLAST, LOCK,
HOLDA, BSTAT, FAIL
1.5V
Figure 12. Output Delay Waveform for TOV1
1.5V
CLKIN
1.5V
TOF
AD31:0,
ALE, ALE
ADS, A3:2,
BE3:0,
WIDTH/HLTD1:0,
D/C, W/R, DT/R,
DEN, BLAST, LOCK
Figure 13. Output Float Waveform for TO F
PRELIMINARY
35
A
80960JD
CLKIN
1.5V
1.5V
1.5V
TIH1
TIS1
AD31:0
Valid
1.5V
NMI
XINT7:0
Figure 14. Input Setup and Hold Waveform for TIS1 and TIH1
CLKIN
1.5V
1.5V
1.5V
TIH2
TIS2
HOLD,
RDYRCV
1.5V
Valid
1.5V
Figure 15. Input Setup and Hold Waveform for TIS2 and TIH2
36
PRELIMINARY
A
80960JD
CLKIN
1.5V
1.5V
TIH3
TIS3
RESET
Figure 16. Input Setup and Hold Waveform for TIS3 and TIH3
RESET
TIH4
TIS4
ONCE,
STEST
Valid
Figure 17. Input Setup and Hold Waveform for TIS4 and TIH4
PRELIMINARY
37
A
80960JD
Ta
Tw /T d
1.5V
CLKIN
1.5V
1.5V
TLXL
ALE
ALE
1.5V
Valid
1.5V
T LXA
AD31:0
1.5V
1.5V
Valid
Figure 18. Relative Timings Waveform for TLXL and T LXA
Ta
CLKIN
Tw /Td
1.5V
1.5V
1.5V
TOV2
Valid
DT/R
T DXD
DEN
TOV1
Figure 19. DT/R and DEN Timings Waveform
38
PRELIMINARY
A
80960JD
TBSCR
TBSCF
2.0V
1.5V
0.8V
TBSCH
TBSCL
Figure 20. TCK Waveform
TCK
1.5V
1.5V
TBSIS1
TMS
TDI
1.5V
1.5V
TBSIH1
Valid
1.5V
Figure 21. Input Setup and Hold Waveforms for TBSIS1 and TBSIH1
PRELIMINARY
39
A
80960JD
TCK
1.5V
1.5V
TBSOV1
TDO
1.5V
T BSOF1
Valid
1.5V
Figure 22. Output Delay and Output Float Waveform for TBSOV1 AND TBSOF1
TCK
1.5V
1.5V
TBSOF2
TBSOV2
Non-Test
Outputs
1.5V
1.5V
Valid
Figure 23. Output Delay and Output Float Waveform for T BSOV2 and TBSOF2
40
PRELIMINARY
A
80960JD
TCK
1.5V
1.5V
TBSIS2
Non-Test
Inputs
1.5V
1.5V
TBSIH2
Valid
1.5V
Figure 24. Input Setup and Hold Waveform for TBSIS2 and TBSIH2
PRELIMINARY
41
A
80960JD
5.0
BUS FUNCTIONAL WAVEFORMS
Figures 25 through 30 illustrate typical 80960JD bus transactions. Figure 31 depicts the bus arbitration
sequence. Figure 32 illustrates the processor reset sequence from the time power is applied to the device.
Figure 33 illustrates the processor reset sequence when the processor is in operation. Figure 34 illustrates the
processor ONCE sequence from the time power is applied to the device. Figures 35 and 36 also show
accesses on 32-bit buses. Tables 19 through 22 summarize all possible combinations of bus accesses across
8-, 16-, and 32-bit buses according to data alignment.
Ta
Td
Tr
Ti
Ti
Ta
Td
Tr
Ti
Ti
CLKIN
AD31:0
D
In
ADDR
Invalid
ADDR
DATA Out
ALE
ADS
A3:2
BE3:0
WIDTH1:0
10
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF030A
Figure 25. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
42
PRELIMINARY
A
80960JD
Ta
Td
Td
Tr
Ta
Td
Td
Td
Td
Tr
CLKIN
AD31:0
ADDR
D
In
D
In
ADDR
DATA DATA DATA
Out
Out
Out
DATA
Out
ALE
ADS
A3:2
00 or 10
01 or 11
00
01
10
11
BE3:0
WIDTH1:0
10
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
Figure 26. Burst Read and Write Transactions Without Wait States, 32-Bit Bus
PRELIMINARY
43
A
80960JD
Ta
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
Td
Tr
CLKIN
AD31:0
DATA
Out
ADDR
DATA
Out
DATA
Out
01
10
DATA
Out
ALE
ADS
A3:2
00
11
BE3:0
WIDTH1:0
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF032A
Figure 27. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
44
PRELIMINARY
A
80960JD
Ta
Td
Td
Tr
Ta
Td
Td
Td
Td
Tr
CLKIN
AD31:0
D
In
D
In
ADDR
DATA
ADDR DATA
Out
Out
DATA
Out
DATA
Out
ALE
ADS
A3:2
BE1/A1
BE0/A0
WIDTH1:0
00,01,10 or 11
00 or 10
01 or
11
00
00,01,10 or 11
00
01
10
11
00
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF033A
Figure 28. Burst Read and Write Transactions Without Wait States, 8-Bit Bus
PRELIMINARY
45
A
80960JD
Ta
Tw
Td
Td
Tr
Tr
Ta
Tw
Td
Td
Tr
CLKIN
AD31:0
D
In
ADDR
D
In
DATA
Out
ADDR
DATA
Out
ALE
ADS
00,01,10, or 11
A3:2
BE1/A1
0
00,01,10, or 11
1
0
1
BE3/BHE
BE0/BLE
WIDTH1:0
01
01
D/C
W/R
BLAST
DT/R
DEN
F_JF034A
RDYRCV
Figure 29. Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus
46
PRELIMINARY
A
80960JD
Ta
Td
Tr
Ta
Td
Tr
Ta
Td
Tr
Ta
Td
Tr
CLKIN
AD31:0
D
In
A
D
In
A
D
In
A
D
In
A
ALE
ADS
A3:2
00
00
BE3:0
1101
0011
WIDTH1:0
01
0000
10
1110
10
D/C
Valid
W/R
BLAST
DT/R
DEN
RDYRCV
Figure 30. Bus Transactions Generated by Double Word Read Bus Request,
Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian
PRELIMINARY
47
A
80960JD
Th
Th
T i or Ta
∼
Ti or Tr
∼
Valid
∼
∼
Valid
∼
Outputs:
AD31:0,
ALE, ALE,
ADS, A3:2,
BE3:0,
WIDTH/HLTD1:0,
D/C, W/R,
DT/R, DEN,
BLAST, LOCK
∼
∼
CLKIN
∼
HOLD
(Note)
∼
HOLDA
NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the
same edge in which it recognizes HOLD if the last state was Ti or the last Tr of a bus transaction. Similarly,
the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
Figure 31. HOLD/HOLDA Waveform For Bus Arbitration
48
PRELIMINARY
∼
∼
∼∼ ∼
∼ ∼
∼ ∼ ∼ ∼ ∼
∼∼
∼∼
∼ ∼
∼∼
∼∼
∼∼∼∼∼ ∼
∼
∼
∼
Idle (Note 2)
V and CLKIN stable to RESET High, minimum
CC
10,000 CLKIN periods, for PLL stabilization.
Valid
(Input)
(Output)
Built-in self-test, approximately First
207,000 CLKIN periods
Bus
Activity
(if selected)
Valid Output (Note 3)
Valid Input (Note 3)
(Note 1)
3. Since the bus is idle, hold requests are honored during reset and built-in self-test.
2. If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure.
Notes:
1. The processor asser ts FAIL during built-in self-test. If self- test passes, the FAIL pin is deasserted.The processor also asser ts FAIL
dur ing the bus confidence test. If the bus confidence test passes, FAIL is deasserted and the processor begins user program execution.
RESET
STEST
LOCK/
ONCE
HO LDA
HOLD
AD31:0, A3:2,D/C
FAIL
ALE, ADS,
BE3:0, DEN,
BLAST
ALE,W/R, DT/R
WIDTH/HLTD1:0
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
V CC
∼
∼ ∼
∼
∼∼ ∼
∼ ∼∼ ∼
∼∼
∼ ∼ ∼ ∼ ∼ ∼∼
∼∼
∼∼
∼∼
∼ ∼∼
∼
∼
∼
∼
∼ ∼ ∼
∼
∼ ∼
∼
∼∼
∼ ∼
PRELIMINARY
∼∼ ∼
∼∼
∼
CLKIN
A
80960JD
Figure 32. Cold Reset Waveform
49
RESET
STEST
LOCK/ONCE
HOLDA
HOLD
AD31:0, A3:2, D/C
FAIL
ALE, W/R,DT /R, BSTAT,
WIDTH/HLTD1:0
Minimum RESET Low Time
15 CLKIN Cycles
Maximum RESET Low to Reset State
4 CLKIN Cycles
∼ ∼
∼
∼
ALE, ADS, BE3:0,
DEN, BLAST
∼∼
Valid
∼
∼
∼ ∼
∼∼
∼∼
∼∼∼ ∼
∼ ∼∼∼
∼ ∼
∼ ∼∼∼
∼∼
∼ ∼∼ ∼∼
∼
∼
∼
∼
∼
∼∼
∼∼
∼∼
∼ ∼
∼ ∼
∼ ∼
∼ ∼∼ ∼∼ ∼
∼
∼
∼∼ ∼
∼
∼
∼
50
RESET High to First Bus
Activity, 46 CLKIN Cycles
∼∼
CLKIN
80960JD
A
Figure 33. Warm Reset Waveform
PRELIMINARY
VCC
NOTES:
∼
∼
∼ ∼
∼
∼ ∼∼ ∼ ∼ ∼ ∼ ∼ ∼
∼ ∼ ∼∼
∼∼ ∼∼
∼∼
∼
∼ ∼∼ ∼∼ ∼
∼∼
∼ ∼∼ ∼
∼ ∼
∼∼
∼ ∼
∼∼
∼∼
∼∼
∼ ∼∼ ∼∼ ∼
∼ ∼
∼
∼
∼ ∼
∼
V CC and CLKIN stable to RESET High,
minimum 10,000 CLKIN periods, for PLL
stabilization.
(Note 1)
(Input)
2. The ONCE input may be removed after the processor enters ONCE Mode.
1. ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising edge of RESET.
RESET
STEST
LOCK/
ONCE
HOLDA
HOLD
AD31:0, A3:2,
D/C
FAIL
ALE,W/R,
DT/R, WIDT H/HLTD1:0
CLKIN
ALE, ADS,
BE3:0, DEN, BLAST
∼
∼
∼
∼
∼
∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼∼ ∼
∼ ∼∼ ∼∼
PRELIMINARY
∼
∼∼
∼ ∼
∼
∼
CLKIN may not be allowed to float.
It must be driven high or low or continue to run.
A
80960JD
Figure 34. Entering the ONCE State
51
A
80960JD
Table 19. Natural Boundaries for Load and Store Accesses
Data Width
Natural Boundary (Bytes)
Byte
1
Short Word
2
Word
4
Double Word
8
Triple Word
16
Quad Word
16
Table 20. Summary of Byte Load and Store Accesses
Address Offset from
Natural Boundary
(in Bytes)
+0 (aligned)
Accesses on 8-Bit Bus
(WIDTH1:0=00)
• byte access
Accesses on 16 Bit Bus
(WIDTH1:0=01)
Accesses on 32 Bit Bus
(WIDTH1:0=10)
• byte access
• byte access
Table 21. Summary of Short Word Load and Store Accesses
Address Offset from
Natural Boundary
(in Bytes)
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit Bus
(WIDTH1:0=01)
Accesses on 32 Bit Bus
(WIDTH1:0=10)
+0 (aligned)
• burst of 2 bytes
• short-word access
• short-word access
+1
• 2 byte accesses
• 2 byte accesses
• 2 byte accesses
52
PRELIMINARY
A
80960JD
Table 22. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)
Address Offset
from Natural
Boundary in Bytes
Accesses on 8-Bit Bus
(WIDTH1:0=00)
Accesses on 16 Bit Bus
(WIDTH1:0=01)
Accesses on 32 Bit
Bus (WIDTH1:0=10)
+0 (aligned)
(n =1, 2, 3, 4)
• n burst(s) of 4 bytes
• case n=1:
burst of 2 short words
• case n=2:
burst of 4 short words
• case n=3:
burst of 4 short words
burst of 2 short words
• case n=4:
2 bursts of 4 short words
• burst of n word(s)
+1 (n =1, 2, 3, 4)
+5 (n = 2, 3, 4)
+9 (n = 3, 4)
+13 (n = 3, 4)
•
•
•
•
•
•
•
•
•
•
•
•
+2 (n =1, 2, 3, 4)
+6 (n = 2, 3, 4)
+10 (n = 3, 4)
+14 (n = 3, 4)
• burst of 2 bytes
• n-1 burst(s) of 4 bytes
• burst of 2 bytes
• short-word access
• n-1 burst(s) of 2 short words
• short-word access
• short-word access
• n-1 word access(es)
• short-word access
+3 (n =1, 2, 3, 4)
+7 (n = 2, 3, 4)
+11 (n = 3, 4)
+15 (n = 3, 4)
•
•
•
•
•
•
•
•
•
•
•
•
+4 (n = 2, 3, 4)
+8 (n = 3, 4)
+12 (n = 3, 4)
• n burst(s) of 4 bytes
byte access
burst of 2 bytes
n-1 burst(s) of 4 bytes
byte access
byte access
n-1 burst(s) of 4 bytes
burst of 2 bytes
byte access
PRELIMINARY
byte access
short-word access
n-1 burst(s) of 2 short words
byte access
byte access
n-1 burst(s) of 2 short words
short-word access
byte access
• n burst(s) of 2 short words
byte access
short-word access
n-1 word access(es)
byte access
byte access
n-1 word access(es)
short-word access
byte access
• n word access(es)
53
A
80960JD
0
4
8
12
16
20
24
Word Offset 0
1
2
3
4
5
6
Byte Offset
Short Access (Aligned)
Byte, Byte Accesses
Short-Word
Load/Store
Short Access (Aligned)
Byte, Byte Accesses
Word Access (Aligned)
Byte, Short, Byte, Accesses
Word
Load/Store
Short, Short Accesses
Byte, Short, Byte Accesses
One Double-Word Burst (Aligned)
Byte, Short, Word, Byte Accesses
Short, Word, Short Accesses
Double-Word
Load/Store
Byte, Word, Short, Byte Accesses
Word, Word Accesses
One Double-Word
Burst (Aligned)
Figure 35. Summary of Aligned and Unaligned Accesses (32-Bit Bus)
54
PRELIMINARY
A
80960JD
0
4
8
12
16
20
24
1
2
3
4
5
6
Byte Offset
0
Word Offset
One Three-Word
Burst (Aligned)
Byte, Short, Word,
Word, Byte Accesses
Triple-Word
Load/Store
Short, Word, Word,
Short Accesses
Byte, Word, Word,
Short, Byte Accesses
Word, Word,
Word Accesses
Word, Word,
Word Accesses
Word,
Word,
Word
Accesses
One Four-Word
Burst (Aligned)
Byte, Short, Word, Word,
Word, Byte Accesses
Quad-Word
Load/Store
Short, Word, Word, Word,
Short Accesses
Byte, Word, Word, Word,
Short, Byte Accesses
Word, Word, Word,
Word Accesses
Word,
Word,
Word,
Word,
Accesses
Figure 36. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
PRELIMINARY
55
A
80960JD
6.0
DEVICE IDENTIFICATION
80960JD processors may be identified electrically according to device type and stepping (see Table 23). The
32-bit identifier is accessible in three ways:
• Upon reset, the identifier is placed into the g0 register.
• The identifier may be accessed from supervisor mode at any time by reading the DEVICEID register at
address FF008710H.
• The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the IDCODE
instruction.
The device and stepping letter is also printed on the top side of the product package.
Table 23. 80960JD Die and Stepping Reference
Device and
Stepping
Version
Number
Part Number
Manufacturer
X
Complete ID
(Hex)
80960JD A, A2
0000
1000 1000 0010 0000
0000 0001 001
1
08820013
NOTE: This data sheet applies to the 80960JD A and 80960JD A2 steppings.
7.0
REVISION HISTORY
This data sheet supersedes revision 272596-001. Table 24 indicates significant changes since the previous
revision.
Table 24. Data Sheet Version -001 to -002 Revision History (Sheet 1 of 2)
Table 13, 80960JD DC Characteristics (pg. 24) Removed Icc characteristics. Added VOLP (output
ground bounce) specification
56
Table 14, 80960JD ICC Characteristics (pg.
25)
New table for comprehensible Icc characteristics.
Added Icc’s for reset mode. Halt Icc for: 80960JD-50
(max) improved from 56 mA to 48 mA, 80960JD-40
(max) improved from 44 mA to 41mA. ONCE Icc
Improved from 30 mA to 10 mA.
Section 4.5, AC Specifications (pg. 26)
Grouped AC Specifications tables by frequency. Added
40 MHz and 33 MHz AC specifications.
Table 15, 80960JD AC Characteristics (50
MHz) (pg. 26) Section INPUT CLOCK
TIMINGS
TCS (max) improved from ±0.1% to ±250 ps
Table 15, 80960JD AC Characteristics (50
MHz) (pg. 26) Section SYNCHRONOUS
OUTPUT TIMINGS
Tov1 (min) improved from 3.0 ns to 3.5 ns. Tov2 (min)
improved from 0.45T C + 3.0 ns to 0.5TC + 3.5 ns. ToF
(min) improved from 3.0 ns to 3.5 ns. ToF (max)
improved from 17 ns to 15 ns.
PRELIMINARY
A
80960JD
Table 24. Data Sheet Version -001 to -002 Revision History (Sheet 2 of 2)
57
Table 15, 80960JD AC Characteristics (50
MHz) (pg. 26) Section SYNCHRONOUS
INPUT TIMINGS
TIS2 (min) improved from 10 ns to 9 ns
Table 15, 80960JD AC Characteristics (50
MHz) (pg. 26) Section RELATIVE OUTPUT
TIMINGS
TLXL , TLXA, and TDXD (min) improved from .45TC - 3 ns
to .5TC - 7.5 ns.
Table 15, 80960JD AC Characteristics (50
MHz) (pg. 26) Section BOUNDARY SCAN
TEST SIGNAL TIMINGS
TBSF (max) improved from 8 MHz to .5TF. TBSIS1 (min)
improved from 8 ns to 4 ns. TBSIH1 (min) improved from
10 ns to 6 ns. TBSIS2 (min) improved from 8 ns to 4 ns.
TBSIH2 (min) improved from 10 ns to 6 ns.
PRELIMINARY